Commit | Line | Data |
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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
6f392d54 CW |
37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
38 | { | |
39 | drm_i915_private_t *dev_priv = dev->dev_private; | |
40 | u32 seqno; | |
41 | ||
42 | seqno = dev_priv->next_seqno; | |
43 | ||
44 | /* reserve 0 for non-seqno */ | |
45 | if (++dev_priv->next_seqno == 0) | |
46 | dev_priv->next_seqno = 1; | |
47 | ||
48 | return seqno; | |
49 | } | |
50 | ||
8187a2b7 | 51 | static void |
78501eac | 52 | render_ring_flush(struct intel_ring_buffer *ring, |
ab6f8e32 CW |
53 | u32 invalidate_domains, |
54 | u32 flush_domains) | |
62fdfeaf | 55 | { |
78501eac | 56 | struct drm_device *dev = ring->dev; |
6f392d54 CW |
57 | drm_i915_private_t *dev_priv = dev->dev_private; |
58 | u32 cmd; | |
59 | ||
62fdfeaf EA |
60 | #if WATCH_EXEC |
61 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
62 | invalidate_domains, flush_domains); | |
63 | #endif | |
6f392d54 CW |
64 | |
65 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, | |
62fdfeaf EA |
66 | invalidate_domains, flush_domains); |
67 | ||
62fdfeaf EA |
68 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
69 | /* | |
70 | * read/write caches: | |
71 | * | |
72 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
73 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
74 | * also flushed at 2d versus 3d pipeline switches. | |
75 | * | |
76 | * read-only caches: | |
77 | * | |
78 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
79 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
80 | * | |
81 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
82 | * | |
83 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
84 | * invalidated when MI_EXE_FLUSH is set. | |
85 | * | |
86 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
87 | * invalidated with every MI_FLUSH. | |
88 | * | |
89 | * TLBs: | |
90 | * | |
91 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
92 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
93 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
94 | * are flushed at any MI_FLUSH. | |
95 | */ | |
96 | ||
97 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
98 | if ((invalidate_domains|flush_domains) & | |
99 | I915_GEM_DOMAIN_RENDER) | |
100 | cmd &= ~MI_NO_WRITE_FLUSH; | |
a6c45cf0 | 101 | if (INTEL_INFO(dev)->gen < 4) { |
62fdfeaf EA |
102 | /* |
103 | * On the 965, the sampler cache always gets flushed | |
104 | * and this bit is reserved. | |
105 | */ | |
106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
107 | cmd |= MI_READ_FLUSH; | |
108 | } | |
109 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
110 | cmd |= MI_EXE_FLUSH; | |
111 | ||
112 | #if WATCH_EXEC | |
113 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
114 | #endif | |
e1f99ce6 CW |
115 | if (intel_ring_begin(ring, 2) == 0) { |
116 | intel_ring_emit(ring, cmd); | |
117 | intel_ring_emit(ring, MI_NOOP); | |
118 | intel_ring_advance(ring); | |
119 | } | |
62fdfeaf | 120 | } |
8187a2b7 ZN |
121 | } |
122 | ||
78501eac | 123 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 124 | u32 value) |
d46eefa2 | 125 | { |
78501eac | 126 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 127 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
128 | } |
129 | ||
78501eac | 130 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 131 | { |
78501eac CW |
132 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
133 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 134 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
135 | |
136 | return I915_READ(acthd_reg); | |
137 | } | |
138 | ||
78501eac | 139 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 140 | { |
78501eac CW |
141 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
142 | struct drm_i915_gem_object *obj_priv = to_intel_bo(ring->gem_object); | |
8187a2b7 | 143 | u32 head; |
8187a2b7 ZN |
144 | |
145 | /* Stop the ring if it's running. */ | |
7f2ab699 | 146 | I915_WRITE_CTL(ring, 0); |
570ef608 | 147 | I915_WRITE_HEAD(ring, 0); |
78501eac | 148 | ring->write_tail(ring, 0); |
8187a2b7 ZN |
149 | |
150 | /* Initialize the ring. */ | |
6c0e1c55 | 151 | I915_WRITE_START(ring, obj_priv->gtt_offset); |
570ef608 | 152 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
153 | |
154 | /* G45 ring initialization fails to reset head to zero */ | |
155 | if (head != 0) { | |
156 | DRM_ERROR("%s head not reset to zero " | |
157 | "ctl %08x head %08x tail %08x start %08x\n", | |
158 | ring->name, | |
7f2ab699 | 159 | I915_READ_CTL(ring), |
570ef608 | 160 | I915_READ_HEAD(ring), |
870e86dd | 161 | I915_READ_TAIL(ring), |
6c0e1c55 | 162 | I915_READ_START(ring)); |
8187a2b7 | 163 | |
570ef608 | 164 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 ZN |
165 | |
166 | DRM_ERROR("%s head forced to zero " | |
167 | "ctl %08x head %08x tail %08x start %08x\n", | |
168 | ring->name, | |
7f2ab699 | 169 | I915_READ_CTL(ring), |
570ef608 | 170 | I915_READ_HEAD(ring), |
870e86dd | 171 | I915_READ_TAIL(ring), |
6c0e1c55 | 172 | I915_READ_START(ring)); |
8187a2b7 ZN |
173 | } |
174 | ||
7f2ab699 | 175 | I915_WRITE_CTL(ring, |
8187a2b7 ZN |
176 | ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES) |
177 | | RING_NO_REPORT | RING_VALID); | |
178 | ||
570ef608 | 179 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
180 | /* If the head is still not zero, the ring is dead */ |
181 | if (head != 0) { | |
182 | DRM_ERROR("%s initialization failed " | |
183 | "ctl %08x head %08x tail %08x start %08x\n", | |
184 | ring->name, | |
7f2ab699 | 185 | I915_READ_CTL(ring), |
570ef608 | 186 | I915_READ_HEAD(ring), |
870e86dd | 187 | I915_READ_TAIL(ring), |
6c0e1c55 | 188 | I915_READ_START(ring)); |
8187a2b7 ZN |
189 | return -EIO; |
190 | } | |
191 | ||
78501eac CW |
192 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
193 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 194 | else { |
570ef608 | 195 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 196 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
8187a2b7 ZN |
197 | ring->space = ring->head - (ring->tail + 8); |
198 | if (ring->space < 0) | |
199 | ring->space += ring->size; | |
200 | } | |
201 | return 0; | |
202 | } | |
203 | ||
78501eac | 204 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 205 | { |
78501eac CW |
206 | struct drm_device *dev = ring->dev; |
207 | int ret = init_ring_common(ring); | |
a69ffdbf | 208 | |
a6c45cf0 | 209 | if (INTEL_INFO(dev)->gen > 3) { |
78501eac CW |
210 | drm_i915_private_t *dev_priv = dev->dev_private; |
211 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; | |
a69ffdbf ZW |
212 | if (IS_GEN6(dev)) |
213 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; | |
214 | I915_WRITE(MI_MODE, mode); | |
8187a2b7 | 215 | } |
78501eac | 216 | |
8187a2b7 ZN |
217 | return ret; |
218 | } | |
219 | ||
78501eac | 220 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
8187a2b7 | 221 | do { \ |
78501eac | 222 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
ca76482e | 223 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
78501eac CW |
224 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
225 | intel_ring_emit(ring__, 0); \ | |
226 | intel_ring_emit(ring__, 0); \ | |
8187a2b7 | 227 | } while (0) |
62fdfeaf EA |
228 | |
229 | /** | |
230 | * Creates a new sequence number, emitting a write of it to the status page | |
231 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
232 | * | |
233 | * Must be called with struct_lock held. | |
234 | * | |
235 | * Returned sequence numbers are nonzero on success. | |
236 | */ | |
8187a2b7 | 237 | static u32 |
78501eac | 238 | render_ring_add_request(struct intel_ring_buffer *ring, |
ab6f8e32 | 239 | u32 flush_domains) |
62fdfeaf | 240 | { |
78501eac | 241 | struct drm_device *dev = ring->dev; |
62fdfeaf | 242 | drm_i915_private_t *dev_priv = dev->dev_private; |
6f392d54 CW |
243 | u32 seqno; |
244 | ||
245 | seqno = i915_gem_get_seqno(dev); | |
ca76482e ZW |
246 | |
247 | if (IS_GEN6(dev)) { | |
e1f99ce6 CW |
248 | if (intel_ring_begin(ring, 6) == 0) { |
249 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 3); | |
250 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE | | |
251 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH | | |
252 | PIPE_CONTROL_NOTIFY); | |
253 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
254 | intel_ring_emit(ring, seqno); | |
255 | intel_ring_emit(ring, 0); | |
256 | intel_ring_emit(ring, 0); | |
257 | intel_ring_advance(ring); | |
258 | } | |
ca76482e | 259 | } else if (HAS_PIPE_CONTROL(dev)) { |
62fdfeaf EA |
260 | u32 scratch_addr = dev_priv->seqno_gfx_addr + 128; |
261 | ||
262 | /* | |
263 | * Workaround qword write incoherence by flushing the | |
264 | * PIPE_NOTIFY buffers out to memory before requesting | |
265 | * an interrupt. | |
266 | */ | |
e1f99ce6 CW |
267 | if (intel_ring_begin(ring, 32) == 0) { |
268 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
269 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); | |
270 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
271 | intel_ring_emit(ring, seqno); | |
272 | intel_ring_emit(ring, 0); | |
273 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
274 | scratch_addr += 128; /* write to separate cachelines */ | |
275 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
276 | scratch_addr += 128; | |
277 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
278 | scratch_addr += 128; | |
279 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
280 | scratch_addr += 128; | |
281 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
282 | scratch_addr += 128; | |
283 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
284 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
285 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | | |
286 | PIPE_CONTROL_NOTIFY); | |
287 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
288 | intel_ring_emit(ring, seqno); | |
289 | intel_ring_emit(ring, 0); | |
290 | intel_ring_advance(ring); | |
291 | } | |
62fdfeaf | 292 | } else { |
e1f99ce6 CW |
293 | if (intel_ring_begin(ring, 4) == 0) { |
294 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
295 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
296 | intel_ring_emit(ring, seqno); | |
62fdfeaf | 297 | |
e1f99ce6 CW |
298 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
299 | intel_ring_advance(ring); | |
300 | } | |
62fdfeaf EA |
301 | } |
302 | return seqno; | |
303 | } | |
304 | ||
8187a2b7 | 305 | static u32 |
78501eac | 306 | render_ring_get_seqno(struct intel_ring_buffer *ring) |
8187a2b7 | 307 | { |
78501eac | 308 | struct drm_device *dev = ring->dev; |
8187a2b7 ZN |
309 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
310 | if (HAS_PIPE_CONTROL(dev)) | |
311 | return ((volatile u32 *)(dev_priv->seqno_page))[0]; | |
312 | else | |
313 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
314 | } | |
315 | ||
316 | static void | |
78501eac | 317 | render_ring_get_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 318 | { |
78501eac | 319 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
320 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
321 | unsigned long irqflags; | |
322 | ||
323 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 | 324 | if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) { |
62fdfeaf EA |
325 | if (HAS_PCH_SPLIT(dev)) |
326 | ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
327 | else | |
328 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
329 | } | |
330 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
331 | } | |
332 | ||
8187a2b7 | 333 | static void |
78501eac | 334 | render_ring_put_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 335 | { |
78501eac | 336 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
337 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
338 | unsigned long irqflags; | |
339 | ||
340 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 ZN |
341 | BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0); |
342 | if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) { | |
62fdfeaf EA |
343 | if (HAS_PCH_SPLIT(dev)) |
344 | ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
345 | else | |
346 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
347 | } | |
348 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
349 | } | |
350 | ||
78501eac | 351 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 352 | { |
78501eac CW |
353 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
354 | u32 mmio = IS_GEN6(ring->dev) ? | |
355 | RING_HWS_PGA_GEN6(ring->mmio_base) : | |
356 | RING_HWS_PGA(ring->mmio_base); | |
357 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); | |
358 | POSTING_READ(mmio); | |
8187a2b7 ZN |
359 | } |
360 | ||
ab6f8e32 | 361 | static void |
78501eac CW |
362 | bsd_ring_flush(struct intel_ring_buffer *ring, |
363 | u32 invalidate_domains, | |
364 | u32 flush_domains) | |
d1b851fc | 365 | { |
e1f99ce6 CW |
366 | if (intel_ring_begin(ring, 2) == 0) { |
367 | intel_ring_emit(ring, MI_FLUSH); | |
368 | intel_ring_emit(ring, MI_NOOP); | |
369 | intel_ring_advance(ring); | |
370 | } | |
d1b851fc ZN |
371 | } |
372 | ||
373 | static u32 | |
78501eac | 374 | ring_add_request(struct intel_ring_buffer *ring, |
549f7365 | 375 | u32 flush_domains) |
d1b851fc ZN |
376 | { |
377 | u32 seqno; | |
6f392d54 | 378 | |
78501eac | 379 | seqno = i915_gem_get_seqno(ring->dev); |
6f392d54 | 380 | |
e1f99ce6 CW |
381 | if (intel_ring_begin(ring, 4) == 0) { |
382 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
383 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
384 | intel_ring_emit(ring, seqno); | |
385 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
386 | intel_ring_advance(ring); | |
387 | } | |
d1b851fc ZN |
388 | |
389 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
390 | ||
391 | return seqno; | |
392 | } | |
393 | ||
d1b851fc | 394 | static void |
78501eac | 395 | bsd_ring_get_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
396 | { |
397 | /* do nothing */ | |
398 | } | |
399 | static void | |
78501eac | 400 | bsd_ring_put_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
401 | { |
402 | /* do nothing */ | |
403 | } | |
404 | ||
405 | static u32 | |
78501eac | 406 | ring_status_page_get_seqno(struct intel_ring_buffer *ring) |
d1b851fc ZN |
407 | { |
408 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
409 | } | |
410 | ||
411 | static int | |
78501eac CW |
412 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
413 | struct drm_i915_gem_execbuffer2 *exec, | |
414 | struct drm_clip_rect *cliprects, | |
415 | uint64_t exec_offset) | |
d1b851fc ZN |
416 | { |
417 | uint32_t exec_start; | |
e1f99ce6 | 418 | int ret; |
78501eac | 419 | |
d1b851fc | 420 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
78501eac | 421 | |
e1f99ce6 CW |
422 | ret = intel_ring_begin(ring, 2); |
423 | if (ret) | |
424 | return ret; | |
425 | ||
78501eac CW |
426 | intel_ring_emit(ring, |
427 | MI_BATCH_BUFFER_START | | |
428 | (2 << 6) | | |
429 | MI_BATCH_NON_SECURE_I965); | |
430 | intel_ring_emit(ring, exec_start); | |
431 | intel_ring_advance(ring); | |
432 | ||
d1b851fc ZN |
433 | return 0; |
434 | } | |
435 | ||
8187a2b7 | 436 | static int |
78501eac CW |
437 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
438 | struct drm_i915_gem_execbuffer2 *exec, | |
439 | struct drm_clip_rect *cliprects, | |
440 | uint64_t exec_offset) | |
62fdfeaf | 441 | { |
78501eac | 442 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
443 | drm_i915_private_t *dev_priv = dev->dev_private; |
444 | int nbox = exec->num_cliprects; | |
62fdfeaf | 445 | uint32_t exec_start, exec_len; |
e1f99ce6 | 446 | int i, count, ret; |
78501eac | 447 | |
62fdfeaf EA |
448 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
449 | exec_len = (uint32_t) exec->batch_len; | |
450 | ||
6f392d54 | 451 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
62fdfeaf EA |
452 | |
453 | count = nbox ? nbox : 1; | |
62fdfeaf EA |
454 | for (i = 0; i < count; i++) { |
455 | if (i < nbox) { | |
e1f99ce6 CW |
456 | ret = i915_emit_box(dev, cliprects, i, |
457 | exec->DR1, exec->DR4); | |
62fdfeaf EA |
458 | if (ret) |
459 | return ret; | |
460 | } | |
461 | ||
462 | if (IS_I830(dev) || IS_845G(dev)) { | |
e1f99ce6 CW |
463 | ret = intel_ring_begin(ring, 4); |
464 | if (ret) | |
465 | return ret; | |
466 | ||
78501eac CW |
467 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
468 | intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE); | |
469 | intel_ring_emit(ring, exec_start + exec_len - 4); | |
470 | intel_ring_emit(ring, 0); | |
62fdfeaf | 471 | } else { |
e1f99ce6 CW |
472 | ret = intel_ring_begin(ring, 2); |
473 | if (ret) | |
474 | return ret; | |
475 | ||
a6c45cf0 | 476 | if (INTEL_INFO(dev)->gen >= 4) { |
78501eac | 477 | intel_ring_emit(ring, |
8187a2b7 ZN |
478 | MI_BATCH_BUFFER_START | (2 << 6) |
479 | | MI_BATCH_NON_SECURE_I965); | |
78501eac | 480 | intel_ring_emit(ring, exec_start); |
62fdfeaf | 481 | } else { |
78501eac | 482 | intel_ring_emit(ring, MI_BATCH_BUFFER_START |
8187a2b7 | 483 | | (2 << 6)); |
78501eac | 484 | intel_ring_emit(ring, exec_start | |
8187a2b7 | 485 | MI_BATCH_NON_SECURE); |
62fdfeaf | 486 | } |
62fdfeaf | 487 | } |
78501eac | 488 | intel_ring_advance(ring); |
62fdfeaf EA |
489 | } |
490 | ||
f00a3ddf | 491 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
492 | if (intel_ring_begin(ring, 2) == 0) { |
493 | intel_ring_emit(ring, MI_FLUSH | | |
494 | MI_NO_WRITE_FLUSH | | |
495 | MI_INVALIDATE_ISP ); | |
496 | intel_ring_emit(ring, MI_NOOP); | |
497 | intel_ring_advance(ring); | |
498 | } | |
1cafd347 | 499 | } |
62fdfeaf | 500 | /* XXX breadcrumb */ |
1cafd347 | 501 | |
62fdfeaf EA |
502 | return 0; |
503 | } | |
504 | ||
78501eac | 505 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 506 | { |
78501eac | 507 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
62fdfeaf EA |
508 | struct drm_gem_object *obj; |
509 | struct drm_i915_gem_object *obj_priv; | |
510 | ||
8187a2b7 ZN |
511 | obj = ring->status_page.obj; |
512 | if (obj == NULL) | |
62fdfeaf | 513 | return; |
62fdfeaf EA |
514 | obj_priv = to_intel_bo(obj); |
515 | ||
516 | kunmap(obj_priv->pages[0]); | |
517 | i915_gem_object_unpin(obj); | |
518 | drm_gem_object_unreference(obj); | |
8187a2b7 | 519 | ring->status_page.obj = NULL; |
62fdfeaf EA |
520 | |
521 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
522 | } |
523 | ||
78501eac | 524 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 525 | { |
78501eac | 526 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
527 | drm_i915_private_t *dev_priv = dev->dev_private; |
528 | struct drm_gem_object *obj; | |
529 | struct drm_i915_gem_object *obj_priv; | |
530 | int ret; | |
531 | ||
62fdfeaf EA |
532 | obj = i915_gem_alloc_object(dev, 4096); |
533 | if (obj == NULL) { | |
534 | DRM_ERROR("Failed to allocate status page\n"); | |
535 | ret = -ENOMEM; | |
536 | goto err; | |
537 | } | |
538 | obj_priv = to_intel_bo(obj); | |
539 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
540 | ||
541 | ret = i915_gem_object_pin(obj, 4096); | |
542 | if (ret != 0) { | |
62fdfeaf EA |
543 | goto err_unref; |
544 | } | |
545 | ||
8187a2b7 ZN |
546 | ring->status_page.gfx_addr = obj_priv->gtt_offset; |
547 | ring->status_page.page_addr = kmap(obj_priv->pages[0]); | |
548 | if (ring->status_page.page_addr == NULL) { | |
62fdfeaf | 549 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
550 | goto err_unpin; |
551 | } | |
8187a2b7 ZN |
552 | ring->status_page.obj = obj; |
553 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 554 | |
78501eac | 555 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
556 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
557 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
558 | |
559 | return 0; | |
560 | ||
561 | err_unpin: | |
562 | i915_gem_object_unpin(obj); | |
563 | err_unref: | |
564 | drm_gem_object_unreference(obj); | |
565 | err: | |
8187a2b7 | 566 | return ret; |
62fdfeaf EA |
567 | } |
568 | ||
8187a2b7 | 569 | int intel_init_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 570 | struct intel_ring_buffer *ring) |
62fdfeaf | 571 | { |
870e86dd | 572 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 ZN |
573 | struct drm_i915_gem_object *obj_priv; |
574 | struct drm_gem_object *obj; | |
dd785e35 CW |
575 | int ret; |
576 | ||
8187a2b7 | 577 | ring->dev = dev; |
23bc5982 CW |
578 | INIT_LIST_HEAD(&ring->active_list); |
579 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 | 580 | INIT_LIST_HEAD(&ring->gpu_write_list); |
62fdfeaf | 581 | |
8187a2b7 | 582 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 583 | ret = init_status_page(ring); |
8187a2b7 ZN |
584 | if (ret) |
585 | return ret; | |
586 | } | |
62fdfeaf | 587 | |
8187a2b7 | 588 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
589 | if (obj == NULL) { |
590 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 591 | ret = -ENOMEM; |
dd785e35 | 592 | goto err_hws; |
62fdfeaf | 593 | } |
62fdfeaf | 594 | |
8187a2b7 ZN |
595 | ring->gem_object = obj; |
596 | ||
a9db5c8f | 597 | ret = i915_gem_object_pin(obj, PAGE_SIZE); |
dd785e35 CW |
598 | if (ret) |
599 | goto err_unref; | |
62fdfeaf | 600 | |
8187a2b7 ZN |
601 | obj_priv = to_intel_bo(obj); |
602 | ring->map.size = ring->size; | |
62fdfeaf | 603 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
62fdfeaf EA |
604 | ring->map.type = 0; |
605 | ring->map.flags = 0; | |
606 | ring->map.mtrr = 0; | |
607 | ||
608 | drm_core_ioremap_wc(&ring->map, dev); | |
609 | if (ring->map.handle == NULL) { | |
610 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 611 | ret = -EINVAL; |
dd785e35 | 612 | goto err_unpin; |
62fdfeaf EA |
613 | } |
614 | ||
8187a2b7 | 615 | ring->virtual_start = ring->map.handle; |
78501eac | 616 | ret = ring->init(ring); |
dd785e35 CW |
617 | if (ret) |
618 | goto err_unmap; | |
62fdfeaf | 619 | |
62fdfeaf EA |
620 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
621 | i915_kernel_lost_context(dev); | |
622 | else { | |
570ef608 | 623 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 624 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
62fdfeaf EA |
625 | ring->space = ring->head - (ring->tail + 8); |
626 | if (ring->space < 0) | |
8187a2b7 | 627 | ring->space += ring->size; |
62fdfeaf | 628 | } |
8187a2b7 | 629 | return ret; |
dd785e35 CW |
630 | |
631 | err_unmap: | |
632 | drm_core_ioremapfree(&ring->map, dev); | |
633 | err_unpin: | |
634 | i915_gem_object_unpin(obj); | |
635 | err_unref: | |
636 | drm_gem_object_unreference(obj); | |
637 | ring->gem_object = NULL; | |
638 | err_hws: | |
78501eac | 639 | cleanup_status_page(ring); |
8187a2b7 | 640 | return ret; |
62fdfeaf EA |
641 | } |
642 | ||
78501eac | 643 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 644 | { |
8187a2b7 | 645 | if (ring->gem_object == NULL) |
62fdfeaf EA |
646 | return; |
647 | ||
78501eac | 648 | drm_core_ioremapfree(&ring->map, ring->dev); |
62fdfeaf | 649 | |
8187a2b7 ZN |
650 | i915_gem_object_unpin(ring->gem_object); |
651 | drm_gem_object_unreference(ring->gem_object); | |
652 | ring->gem_object = NULL; | |
78501eac CW |
653 | |
654 | cleanup_status_page(ring); | |
62fdfeaf EA |
655 | } |
656 | ||
78501eac | 657 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 658 | { |
8187a2b7 | 659 | unsigned int *virt; |
62fdfeaf | 660 | int rem; |
8187a2b7 | 661 | rem = ring->size - ring->tail; |
62fdfeaf | 662 | |
8187a2b7 | 663 | if (ring->space < rem) { |
78501eac | 664 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
665 | if (ret) |
666 | return ret; | |
667 | } | |
62fdfeaf | 668 | |
8187a2b7 | 669 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
670 | rem /= 8; |
671 | while (rem--) { | |
62fdfeaf | 672 | *virt++ = MI_NOOP; |
1741dd4a CW |
673 | *virt++ = MI_NOOP; |
674 | } | |
62fdfeaf | 675 | |
8187a2b7 | 676 | ring->tail = 0; |
43ed340a | 677 | ring->space = ring->head - 8; |
62fdfeaf EA |
678 | |
679 | return 0; | |
680 | } | |
681 | ||
78501eac | 682 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 683 | { |
78501eac | 684 | struct drm_device *dev = ring->dev; |
570ef608 | 685 | drm_i915_private_t *dev_priv = dev->dev_private; |
78501eac | 686 | unsigned long end; |
62fdfeaf EA |
687 | |
688 | trace_i915_ring_wait_begin (dev); | |
8187a2b7 ZN |
689 | end = jiffies + 3 * HZ; |
690 | do { | |
570ef608 | 691 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
62fdfeaf EA |
692 | ring->space = ring->head - (ring->tail + 8); |
693 | if (ring->space < 0) | |
8187a2b7 | 694 | ring->space += ring->size; |
62fdfeaf | 695 | if (ring->space >= n) { |
78501eac | 696 | trace_i915_ring_wait_end(dev); |
62fdfeaf EA |
697 | return 0; |
698 | } | |
699 | ||
700 | if (dev->primary->master) { | |
701 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
702 | if (master_priv->sarea_priv) | |
703 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
704 | } | |
d1b851fc | 705 | |
e60a0b10 | 706 | msleep(1); |
8187a2b7 ZN |
707 | } while (!time_after(jiffies, end)); |
708 | trace_i915_ring_wait_end (dev); | |
709 | return -EBUSY; | |
710 | } | |
62fdfeaf | 711 | |
e1f99ce6 CW |
712 | int intel_ring_begin(struct intel_ring_buffer *ring, |
713 | int num_dwords) | |
8187a2b7 | 714 | { |
be26a10b | 715 | int n = 4*num_dwords; |
e1f99ce6 | 716 | int ret; |
78501eac | 717 | |
e1f99ce6 CW |
718 | if (unlikely(ring->tail + n > ring->size)) { |
719 | ret = intel_wrap_ring_buffer(ring); | |
720 | if (unlikely(ret)) | |
721 | return ret; | |
722 | } | |
78501eac | 723 | |
e1f99ce6 CW |
724 | if (unlikely(ring->space < n)) { |
725 | ret = intel_wait_ring_buffer(ring, n); | |
726 | if (unlikely(ret)) | |
727 | return ret; | |
728 | } | |
d97ed339 CW |
729 | |
730 | ring->space -= n; | |
e1f99ce6 | 731 | return 0; |
8187a2b7 | 732 | } |
62fdfeaf | 733 | |
78501eac | 734 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 735 | { |
d97ed339 | 736 | ring->tail &= ring->size - 1; |
78501eac | 737 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 738 | } |
62fdfeaf | 739 | |
e070868e | 740 | static const struct intel_ring_buffer render_ring = { |
8187a2b7 | 741 | .name = "render ring", |
9220434a | 742 | .id = RING_RENDER, |
333e9fe9 | 743 | .mmio_base = RENDER_RING_BASE, |
8187a2b7 | 744 | .size = 32 * PAGE_SIZE, |
8187a2b7 | 745 | .init = init_render_ring, |
297b0c5b | 746 | .write_tail = ring_write_tail, |
8187a2b7 ZN |
747 | .flush = render_ring_flush, |
748 | .add_request = render_ring_add_request, | |
f787a5f5 | 749 | .get_seqno = render_ring_get_seqno, |
8187a2b7 ZN |
750 | .user_irq_get = render_ring_get_user_irq, |
751 | .user_irq_put = render_ring_put_user_irq, | |
78501eac | 752 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
8187a2b7 | 753 | }; |
d1b851fc ZN |
754 | |
755 | /* ring buffer for bit-stream decoder */ | |
756 | ||
e070868e | 757 | static const struct intel_ring_buffer bsd_ring = { |
d1b851fc | 758 | .name = "bsd ring", |
9220434a | 759 | .id = RING_BSD, |
333e9fe9 | 760 | .mmio_base = BSD_RING_BASE, |
d1b851fc | 761 | .size = 32 * PAGE_SIZE, |
78501eac | 762 | .init = init_ring_common, |
297b0c5b | 763 | .write_tail = ring_write_tail, |
d1b851fc | 764 | .flush = bsd_ring_flush, |
549f7365 CW |
765 | .add_request = ring_add_request, |
766 | .get_seqno = ring_status_page_get_seqno, | |
d1b851fc ZN |
767 | .user_irq_get = bsd_ring_get_user_irq, |
768 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 769 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
d1b851fc | 770 | }; |
5c1143bb | 771 | |
881f47b6 | 772 | |
78501eac | 773 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 774 | u32 value) |
881f47b6 | 775 | { |
78501eac | 776 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
777 | |
778 | /* Every tail move must follow the sequence below */ | |
779 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
780 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
781 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
782 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
783 | ||
784 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
785 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
786 | 50)) | |
787 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
788 | ||
870e86dd | 789 | I915_WRITE_TAIL(ring, value); |
881f47b6 XH |
790 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
791 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
792 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
793 | } | |
794 | ||
78501eac | 795 | static void gen6_ring_flush(struct intel_ring_buffer *ring, |
549f7365 CW |
796 | u32 invalidate_domains, |
797 | u32 flush_domains) | |
881f47b6 | 798 | { |
e1f99ce6 CW |
799 | if (intel_ring_begin(ring, 4) == 0) { |
800 | intel_ring_emit(ring, MI_FLUSH_DW); | |
801 | intel_ring_emit(ring, 0); | |
802 | intel_ring_emit(ring, 0); | |
803 | intel_ring_emit(ring, 0); | |
804 | intel_ring_advance(ring); | |
805 | } | |
881f47b6 XH |
806 | } |
807 | ||
808 | static int | |
78501eac CW |
809 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
810 | struct drm_i915_gem_execbuffer2 *exec, | |
811 | struct drm_clip_rect *cliprects, | |
812 | uint64_t exec_offset) | |
881f47b6 XH |
813 | { |
814 | uint32_t exec_start; | |
e1f99ce6 | 815 | int ret; |
ab6f8e32 | 816 | |
881f47b6 | 817 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
ab6f8e32 | 818 | |
e1f99ce6 CW |
819 | ret = intel_ring_begin(ring, 2); |
820 | if (ret) | |
821 | return ret; | |
822 | ||
78501eac | 823 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
ab6f8e32 | 824 | /* bit0-7 is the length on GEN6+ */ |
78501eac CW |
825 | intel_ring_emit(ring, exec_start); |
826 | intel_ring_advance(ring); | |
ab6f8e32 | 827 | |
881f47b6 XH |
828 | return 0; |
829 | } | |
830 | ||
831 | /* ring buffer for Video Codec for Gen6+ */ | |
e070868e | 832 | static const struct intel_ring_buffer gen6_bsd_ring = { |
881f47b6 XH |
833 | .name = "gen6 bsd ring", |
834 | .id = RING_BSD, | |
333e9fe9 | 835 | .mmio_base = GEN6_BSD_RING_BASE, |
881f47b6 | 836 | .size = 32 * PAGE_SIZE, |
78501eac | 837 | .init = init_ring_common, |
297b0c5b | 838 | .write_tail = gen6_bsd_ring_write_tail, |
549f7365 CW |
839 | .flush = gen6_ring_flush, |
840 | .add_request = ring_add_request, | |
841 | .get_seqno = ring_status_page_get_seqno, | |
881f47b6 XH |
842 | .user_irq_get = bsd_ring_get_user_irq, |
843 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 844 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
549f7365 CW |
845 | }; |
846 | ||
847 | /* Blitter support (SandyBridge+) */ | |
848 | ||
849 | static void | |
78501eac | 850 | blt_ring_get_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
851 | { |
852 | /* do nothing */ | |
853 | } | |
854 | static void | |
78501eac | 855 | blt_ring_put_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
856 | { |
857 | /* do nothing */ | |
858 | } | |
859 | ||
860 | static const struct intel_ring_buffer gen6_blt_ring = { | |
861 | .name = "blt ring", | |
862 | .id = RING_BLT, | |
863 | .mmio_base = BLT_RING_BASE, | |
864 | .size = 32 * PAGE_SIZE, | |
865 | .init = init_ring_common, | |
297b0c5b | 866 | .write_tail = ring_write_tail, |
549f7365 CW |
867 | .flush = gen6_ring_flush, |
868 | .add_request = ring_add_request, | |
869 | .get_seqno = ring_status_page_get_seqno, | |
870 | .user_irq_get = blt_ring_get_user_irq, | |
871 | .user_irq_put = blt_ring_put_user_irq, | |
78501eac | 872 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
881f47b6 XH |
873 | }; |
874 | ||
5c1143bb XH |
875 | int intel_init_render_ring_buffer(struct drm_device *dev) |
876 | { | |
877 | drm_i915_private_t *dev_priv = dev->dev_private; | |
878 | ||
879 | dev_priv->render_ring = render_ring; | |
880 | ||
881 | if (!I915_NEED_GFX_HWS(dev)) { | |
882 | dev_priv->render_ring.status_page.page_addr | |
883 | = dev_priv->status_page_dmah->vaddr; | |
884 | memset(dev_priv->render_ring.status_page.page_addr, | |
885 | 0, PAGE_SIZE); | |
886 | } | |
887 | ||
888 | return intel_init_ring_buffer(dev, &dev_priv->render_ring); | |
889 | } | |
890 | ||
891 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
892 | { | |
893 | drm_i915_private_t *dev_priv = dev->dev_private; | |
894 | ||
881f47b6 XH |
895 | if (IS_GEN6(dev)) |
896 | dev_priv->bsd_ring = gen6_bsd_ring; | |
897 | else | |
898 | dev_priv->bsd_ring = bsd_ring; | |
5c1143bb XH |
899 | |
900 | return intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
901 | } | |
549f7365 CW |
902 | |
903 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
904 | { | |
905 | drm_i915_private_t *dev_priv = dev->dev_private; | |
906 | ||
907 | dev_priv->blt_ring = gen6_blt_ring; | |
908 | ||
909 | return intel_init_ring_buffer(dev, &dev_priv->blt_ring); | |
910 | } |