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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
ebd0fd4b DG |
50 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
51 | { | |
52 | if (ringbuf->last_retired_head != -1) { | |
53 | ringbuf->head = ringbuf->last_retired_head; | |
54 | ringbuf->last_retired_head = -1; | |
55 | } | |
56 | ||
57 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
58 | ringbuf->tail, ringbuf->size); | |
59 | } | |
60 | ||
117897f4 | 61 | bool intel_engine_stopped(struct intel_engine_cs *engine) |
09246732 | 62 | { |
c033666a | 63 | struct drm_i915_private *dev_priv = engine->i915; |
666796da | 64 | return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine); |
88b4aa87 | 65 | } |
09246732 | 66 | |
0bc40be8 | 67 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
88b4aa87 | 68 | { |
0bc40be8 | 69 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 70 | ringbuf->tail &= ringbuf->size - 1; |
117897f4 | 71 | if (intel_engine_stopped(engine)) |
09246732 | 72 | return; |
0bc40be8 | 73 | engine->write_tail(engine, ringbuf->tail); |
09246732 CW |
74 | } |
75 | ||
b72f3acb | 76 | static int |
a84c3ae1 | 77 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
78 | u32 invalidate_domains, |
79 | u32 flush_domains) | |
80 | { | |
4a570db5 | 81 | struct intel_engine_cs *engine = req->engine; |
46f0f8d1 CW |
82 | u32 cmd; |
83 | int ret; | |
84 | ||
85 | cmd = MI_FLUSH; | |
31b14c9f | 86 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
87 | cmd |= MI_NO_WRITE_FLUSH; |
88 | ||
89 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
90 | cmd |= MI_READ_FLUSH; | |
91 | ||
5fb9de1a | 92 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
93 | if (ret) |
94 | return ret; | |
95 | ||
e2f80391 TU |
96 | intel_ring_emit(engine, cmd); |
97 | intel_ring_emit(engine, MI_NOOP); | |
98 | intel_ring_advance(engine); | |
46f0f8d1 CW |
99 | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static int | |
a84c3ae1 | 104 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
105 | u32 invalidate_domains, |
106 | u32 flush_domains) | |
62fdfeaf | 107 | { |
4a570db5 | 108 | struct intel_engine_cs *engine = req->engine; |
6f392d54 | 109 | u32 cmd; |
b72f3acb | 110 | int ret; |
6f392d54 | 111 | |
36d527de CW |
112 | /* |
113 | * read/write caches: | |
114 | * | |
115 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
116 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
117 | * also flushed at 2d versus 3d pipeline switches. | |
118 | * | |
119 | * read-only caches: | |
120 | * | |
121 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
122 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
123 | * | |
124 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
125 | * | |
126 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
127 | * invalidated when MI_EXE_FLUSH is set. | |
128 | * | |
129 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
130 | * invalidated with every MI_FLUSH. | |
131 | * | |
132 | * TLBs: | |
133 | * | |
134 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
135 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
136 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
137 | * are flushed at any MI_FLUSH. | |
138 | */ | |
139 | ||
140 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 141 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 142 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
143 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
144 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 145 | |
36d527de | 146 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
c033666a | 147 | (IS_G4X(req->i915) || IS_GEN5(req->i915))) |
36d527de | 148 | cmd |= MI_INVALIDATE_ISP; |
70eac33e | 149 | |
5fb9de1a | 150 | ret = intel_ring_begin(req, 2); |
36d527de CW |
151 | if (ret) |
152 | return ret; | |
b72f3acb | 153 | |
e2f80391 TU |
154 | intel_ring_emit(engine, cmd); |
155 | intel_ring_emit(engine, MI_NOOP); | |
156 | intel_ring_advance(engine); | |
b72f3acb CW |
157 | |
158 | return 0; | |
8187a2b7 ZN |
159 | } |
160 | ||
8d315287 JB |
161 | /** |
162 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
163 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
164 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
165 | * | |
166 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
167 | * produced by non-pipelined state commands), software needs to first | |
168 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
169 | * 0. | |
170 | * | |
171 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
172 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
173 | * | |
174 | * And the workaround for these two requires this workaround first: | |
175 | * | |
176 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
177 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
178 | * flushes. | |
179 | * | |
180 | * And this last workaround is tricky because of the requirements on | |
181 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
182 | * volume 2 part 1: | |
183 | * | |
184 | * "1 of the following must also be set: | |
185 | * - Render Target Cache Flush Enable ([12] of DW1) | |
186 | * - Depth Cache Flush Enable ([0] of DW1) | |
187 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
188 | * - Depth Stall ([13] of DW1) | |
189 | * - Post-Sync Operation ([13] of DW1) | |
190 | * - Notify Enable ([8] of DW1)" | |
191 | * | |
192 | * The cache flushes require the workaround flush that triggered this | |
193 | * one, so we can't use it. Depth stall would trigger the same. | |
194 | * Post-sync nonzero is what triggered this second workaround, so we | |
195 | * can't use that one either. Notify enable is IRQs, which aren't | |
196 | * really our business. That leaves only stall at scoreboard. | |
197 | */ | |
198 | static int | |
f2cf1fcc | 199 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 200 | { |
4a570db5 | 201 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 202 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
203 | int ret; |
204 | ||
5fb9de1a | 205 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
206 | if (ret) |
207 | return ret; | |
208 | ||
e2f80391 TU |
209 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
210 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
8d315287 | 211 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
212 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
213 | intel_ring_emit(engine, 0); /* low dword */ | |
214 | intel_ring_emit(engine, 0); /* high dword */ | |
215 | intel_ring_emit(engine, MI_NOOP); | |
216 | intel_ring_advance(engine); | |
8d315287 | 217 | |
5fb9de1a | 218 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
219 | if (ret) |
220 | return ret; | |
221 | ||
e2f80391 TU |
222 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
223 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); | |
224 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
225 | intel_ring_emit(engine, 0); | |
226 | intel_ring_emit(engine, 0); | |
227 | intel_ring_emit(engine, MI_NOOP); | |
228 | intel_ring_advance(engine); | |
8d315287 JB |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static int | |
a84c3ae1 JH |
234 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
235 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 236 | { |
4a570db5 | 237 | struct intel_engine_cs *engine = req->engine; |
8d315287 | 238 | u32 flags = 0; |
e2f80391 | 239 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
240 | int ret; |
241 | ||
b3111509 | 242 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 243 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
244 | if (ret) |
245 | return ret; | |
246 | ||
8d315287 JB |
247 | /* Just flush everything. Experiments have shown that reducing the |
248 | * number of bits based on the write domains has little performance | |
249 | * impact. | |
250 | */ | |
7d54a904 CW |
251 | if (flush_domains) { |
252 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
253 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
254 | /* | |
255 | * Ensure that any following seqno writes only happen | |
256 | * when the render cache is indeed flushed. | |
257 | */ | |
97f209bc | 258 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
259 | } |
260 | if (invalidate_domains) { | |
261 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
262 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
263 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
264 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
265 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
266 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
267 | /* | |
268 | * TLB invalidate requires a post-sync write. | |
269 | */ | |
3ac78313 | 270 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 271 | } |
8d315287 | 272 | |
5fb9de1a | 273 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
274 | if (ret) |
275 | return ret; | |
276 | ||
e2f80391 TU |
277 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
278 | intel_ring_emit(engine, flags); | |
279 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
280 | intel_ring_emit(engine, 0); | |
281 | intel_ring_advance(engine); | |
8d315287 JB |
282 | |
283 | return 0; | |
284 | } | |
285 | ||
f3987631 | 286 | static int |
f2cf1fcc | 287 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 288 | { |
4a570db5 | 289 | struct intel_engine_cs *engine = req->engine; |
f3987631 PZ |
290 | int ret; |
291 | ||
5fb9de1a | 292 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
293 | if (ret) |
294 | return ret; | |
295 | ||
e2f80391 TU |
296 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
297 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
f3987631 | 298 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
299 | intel_ring_emit(engine, 0); |
300 | intel_ring_emit(engine, 0); | |
301 | intel_ring_advance(engine); | |
f3987631 PZ |
302 | |
303 | return 0; | |
304 | } | |
305 | ||
4772eaeb | 306 | static int |
a84c3ae1 | 307 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
308 | u32 invalidate_domains, u32 flush_domains) |
309 | { | |
4a570db5 | 310 | struct intel_engine_cs *engine = req->engine; |
4772eaeb | 311 | u32 flags = 0; |
e2f80391 | 312 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
313 | int ret; |
314 | ||
f3987631 PZ |
315 | /* |
316 | * Ensure that any following seqno writes only happen when the render | |
317 | * cache is indeed flushed. | |
318 | * | |
319 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
320 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
321 | * don't try to be clever and just set it unconditionally. | |
322 | */ | |
323 | flags |= PIPE_CONTROL_CS_STALL; | |
324 | ||
4772eaeb PZ |
325 | /* Just flush everything. Experiments have shown that reducing the |
326 | * number of bits based on the write domains has little performance | |
327 | * impact. | |
328 | */ | |
329 | if (flush_domains) { | |
330 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
331 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 332 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 333 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
334 | } |
335 | if (invalidate_domains) { | |
336 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
337 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
338 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
339 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
340 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
341 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 342 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
343 | /* |
344 | * TLB invalidate requires a post-sync write. | |
345 | */ | |
346 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 347 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 348 | |
add284a3 CW |
349 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
350 | ||
f3987631 PZ |
351 | /* Workaround: we must issue a pipe_control with CS-stall bit |
352 | * set before a pipe_control command that has the state cache | |
353 | * invalidate bit set. */ | |
f2cf1fcc | 354 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
355 | } |
356 | ||
5fb9de1a | 357 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
358 | if (ret) |
359 | return ret; | |
360 | ||
e2f80391 TU |
361 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
362 | intel_ring_emit(engine, flags); | |
363 | intel_ring_emit(engine, scratch_addr); | |
364 | intel_ring_emit(engine, 0); | |
365 | intel_ring_advance(engine); | |
4772eaeb PZ |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
884ceace | 370 | static int |
f2cf1fcc | 371 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
372 | u32 flags, u32 scratch_addr) |
373 | { | |
4a570db5 | 374 | struct intel_engine_cs *engine = req->engine; |
884ceace KG |
375 | int ret; |
376 | ||
5fb9de1a | 377 | ret = intel_ring_begin(req, 6); |
884ceace KG |
378 | if (ret) |
379 | return ret; | |
380 | ||
e2f80391 TU |
381 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
382 | intel_ring_emit(engine, flags); | |
383 | intel_ring_emit(engine, scratch_addr); | |
384 | intel_ring_emit(engine, 0); | |
385 | intel_ring_emit(engine, 0); | |
386 | intel_ring_emit(engine, 0); | |
387 | intel_ring_advance(engine); | |
884ceace KG |
388 | |
389 | return 0; | |
390 | } | |
391 | ||
a5f3d68e | 392 | static int |
a84c3ae1 | 393 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
394 | u32 invalidate_domains, u32 flush_domains) |
395 | { | |
396 | u32 flags = 0; | |
4a570db5 | 397 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 398 | int ret; |
a5f3d68e BW |
399 | |
400 | flags |= PIPE_CONTROL_CS_STALL; | |
401 | ||
402 | if (flush_domains) { | |
403 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
404 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 405 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 406 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
407 | } |
408 | if (invalidate_domains) { | |
409 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
410 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
411 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
412 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
413 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
414 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
415 | flags |= PIPE_CONTROL_QW_WRITE; | |
416 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
417 | |
418 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 419 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
420 | PIPE_CONTROL_CS_STALL | |
421 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
422 | 0); | |
423 | if (ret) | |
424 | return ret; | |
a5f3d68e BW |
425 | } |
426 | ||
f2cf1fcc | 427 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
428 | } |
429 | ||
0bc40be8 | 430 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 431 | u32 value) |
d46eefa2 | 432 | { |
c033666a | 433 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 434 | I915_WRITE_TAIL(engine, value); |
d46eefa2 XH |
435 | } |
436 | ||
0bc40be8 | 437 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 438 | { |
c033666a | 439 | struct drm_i915_private *dev_priv = engine->i915; |
50877445 | 440 | u64 acthd; |
8187a2b7 | 441 | |
c033666a | 442 | if (INTEL_GEN(dev_priv) >= 8) |
0bc40be8 TU |
443 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), |
444 | RING_ACTHD_UDW(engine->mmio_base)); | |
c033666a | 445 | else if (INTEL_GEN(dev_priv) >= 4) |
0bc40be8 | 446 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); |
50877445 CW |
447 | else |
448 | acthd = I915_READ(ACTHD); | |
449 | ||
450 | return acthd; | |
8187a2b7 ZN |
451 | } |
452 | ||
0bc40be8 | 453 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 454 | { |
c033666a | 455 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
456 | u32 addr; |
457 | ||
458 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 459 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
460 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
461 | I915_WRITE(HWS_PGA, addr); | |
462 | } | |
463 | ||
0bc40be8 | 464 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 465 | { |
c033666a | 466 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 467 | i915_reg_t mmio; |
af75f269 DL |
468 | |
469 | /* The ring status page addresses are no longer next to the rest of | |
470 | * the ring registers as of gen7. | |
471 | */ | |
c033666a | 472 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 473 | switch (engine->id) { |
af75f269 DL |
474 | case RCS: |
475 | mmio = RENDER_HWS_PGA_GEN7; | |
476 | break; | |
477 | case BCS: | |
478 | mmio = BLT_HWS_PGA_GEN7; | |
479 | break; | |
480 | /* | |
481 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
482 | * gcc switch check warning | |
483 | */ | |
484 | case VCS2: | |
485 | case VCS: | |
486 | mmio = BSD_HWS_PGA_GEN7; | |
487 | break; | |
488 | case VECS: | |
489 | mmio = VEBOX_HWS_PGA_GEN7; | |
490 | break; | |
491 | } | |
c033666a | 492 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 493 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
494 | } else { |
495 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 496 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
497 | } |
498 | ||
0bc40be8 | 499 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
500 | POSTING_READ(mmio); |
501 | ||
502 | /* | |
503 | * Flush the TLB for this page | |
504 | * | |
505 | * FIXME: These two bits have disappeared on gen8, so a question | |
506 | * arises: do we still need this and if so how should we go about | |
507 | * invalidating the TLB? | |
508 | */ | |
ac657f64 | 509 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 510 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
511 | |
512 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 513 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
514 | |
515 | I915_WRITE(reg, | |
516 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
517 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
518 | if (intel_wait_for_register(dev_priv, |
519 | reg, INSTPM_SYNC_FLUSH, 0, | |
520 | 1000)) | |
af75f269 | 521 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 522 | engine->name); |
af75f269 DL |
523 | } |
524 | } | |
525 | ||
0bc40be8 | 526 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 527 | { |
c033666a | 528 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 529 | |
c033666a | 530 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 | 531 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
532 | if (intel_wait_for_register(dev_priv, |
533 | RING_MI_MODE(engine->mmio_base), | |
534 | MODE_IDLE, | |
535 | MODE_IDLE, | |
536 | 1000)) { | |
0bc40be8 TU |
537 | DRM_ERROR("%s : timed out trying to stop ring\n", |
538 | engine->name); | |
9bec9b13 CW |
539 | /* Sometimes we observe that the idle flag is not |
540 | * set even though the ring is empty. So double | |
541 | * check before giving up. | |
542 | */ | |
0bc40be8 | 543 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 544 | return false; |
9991ae78 CW |
545 | } |
546 | } | |
b7884eb4 | 547 | |
0bc40be8 TU |
548 | I915_WRITE_CTL(engine, 0); |
549 | I915_WRITE_HEAD(engine, 0); | |
550 | engine->write_tail(engine, 0); | |
8187a2b7 | 551 | |
c033666a | 552 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 TU |
553 | (void)I915_READ_CTL(engine); |
554 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 555 | } |
a51435a3 | 556 | |
0bc40be8 | 557 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 558 | } |
8187a2b7 | 559 | |
fc0768ce TE |
560 | void intel_engine_init_hangcheck(struct intel_engine_cs *engine) |
561 | { | |
562 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); | |
563 | } | |
564 | ||
0bc40be8 | 565 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 566 | { |
c033666a | 567 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 568 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 569 | struct drm_i915_gem_object *obj = ringbuf->obj; |
9991ae78 CW |
570 | int ret = 0; |
571 | ||
59bad947 | 572 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 573 | |
0bc40be8 | 574 | if (!stop_ring(engine)) { |
9991ae78 | 575 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
576 | DRM_DEBUG_KMS("%s head not reset to zero " |
577 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
578 | engine->name, |
579 | I915_READ_CTL(engine), | |
580 | I915_READ_HEAD(engine), | |
581 | I915_READ_TAIL(engine), | |
582 | I915_READ_START(engine)); | |
8187a2b7 | 583 | |
0bc40be8 | 584 | if (!stop_ring(engine)) { |
6fd0d56e CW |
585 | DRM_ERROR("failed to set %s head to zero " |
586 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
587 | engine->name, |
588 | I915_READ_CTL(engine), | |
589 | I915_READ_HEAD(engine), | |
590 | I915_READ_TAIL(engine), | |
591 | I915_READ_START(engine)); | |
9991ae78 CW |
592 | ret = -EIO; |
593 | goto out; | |
6fd0d56e | 594 | } |
8187a2b7 ZN |
595 | } |
596 | ||
c033666a | 597 | if (I915_NEED_GFX_HWS(dev_priv)) |
0bc40be8 | 598 | intel_ring_setup_status_page(engine); |
9991ae78 | 599 | else |
0bc40be8 | 600 | ring_setup_phys_status_page(engine); |
9991ae78 | 601 | |
ece4a17d | 602 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 603 | I915_READ_HEAD(engine); |
ece4a17d | 604 | |
0d8957c8 DV |
605 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
606 | * registers with the above sequence (the readback of the HEAD registers | |
607 | * also enforces ordering), otherwise the hw might lose the new ring | |
608 | * register values. */ | |
0bc40be8 | 609 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
610 | |
611 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 612 | if (I915_READ_HEAD(engine)) |
95468892 | 613 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
614 | engine->name, I915_READ_HEAD(engine)); |
615 | I915_WRITE_HEAD(engine, 0); | |
616 | (void)I915_READ_HEAD(engine); | |
95468892 | 617 | |
0bc40be8 | 618 | I915_WRITE_CTL(engine, |
93b0a4e0 | 619 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 620 | | RING_VALID); |
8187a2b7 | 621 | |
8187a2b7 | 622 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
623 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
624 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
625 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 626 | DRM_ERROR("%s initialization failed " |
48e48a0b | 627 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
628 | engine->name, |
629 | I915_READ_CTL(engine), | |
630 | I915_READ_CTL(engine) & RING_VALID, | |
631 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
632 | I915_READ_START(engine), | |
633 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
634 | ret = -EIO; |
635 | goto out; | |
8187a2b7 ZN |
636 | } |
637 | ||
ebd0fd4b | 638 | ringbuf->last_retired_head = -1; |
0bc40be8 TU |
639 | ringbuf->head = I915_READ_HEAD(engine); |
640 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
ebd0fd4b | 641 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 642 | |
fc0768ce | 643 | intel_engine_init_hangcheck(engine); |
50f018df | 644 | |
b7884eb4 | 645 | out: |
59bad947 | 646 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
647 | |
648 | return ret; | |
8187a2b7 ZN |
649 | } |
650 | ||
f8291952 | 651 | void intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 652 | { |
0bc40be8 | 653 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
654 | return; |
655 | ||
f8291952 | 656 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
0bc40be8 TU |
657 | drm_gem_object_unreference(&engine->scratch.obj->base); |
658 | engine->scratch.obj = NULL; | |
9b1136d5 OM |
659 | } |
660 | ||
f8291952 | 661 | int intel_init_pipe_control(struct intel_engine_cs *engine) |
c6df541c | 662 | { |
f8291952 | 663 | struct drm_i915_gem_object *obj; |
c6df541c CW |
664 | int ret; |
665 | ||
0bc40be8 | 666 | WARN_ON(engine->scratch.obj); |
c6df541c | 667 | |
f8291952 CW |
668 | obj = i915_gem_object_create(engine->i915->dev, 4096); |
669 | if (IS_ERR(obj)) { | |
670 | DRM_ERROR("Failed to allocate scratch page\n"); | |
671 | ret = PTR_ERR(obj); | |
c6df541c CW |
672 | goto err; |
673 | } | |
e4ffd173 | 674 | |
f8291952 | 675 | ret = i915_gem_obj_ggtt_pin(obj, 4096, PIN_HIGH); |
a9cc726c DV |
676 | if (ret) |
677 | goto err_unref; | |
c6df541c | 678 | |
f8291952 CW |
679 | engine->scratch.obj = obj; |
680 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
2b1086cc | 681 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 682 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
683 | return 0; |
684 | ||
c6df541c | 685 | err_unref: |
0bc40be8 | 686 | drm_gem_object_unreference(&engine->scratch.obj->base); |
c6df541c | 687 | err: |
c6df541c CW |
688 | return ret; |
689 | } | |
690 | ||
e2be4faf | 691 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 692 | { |
4a570db5 | 693 | struct intel_engine_cs *engine = req->engine; |
c033666a CW |
694 | struct i915_workarounds *w = &req->i915->workarounds; |
695 | int ret, i; | |
888b5995 | 696 | |
02235808 | 697 | if (w->count == 0) |
7225342a | 698 | return 0; |
888b5995 | 699 | |
e2f80391 | 700 | engine->gpu_caches_dirty = true; |
4866d729 | 701 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
702 | if (ret) |
703 | return ret; | |
888b5995 | 704 | |
5fb9de1a | 705 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
706 | if (ret) |
707 | return ret; | |
708 | ||
e2f80391 | 709 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 710 | for (i = 0; i < w->count; i++) { |
e2f80391 TU |
711 | intel_ring_emit_reg(engine, w->reg[i].addr); |
712 | intel_ring_emit(engine, w->reg[i].value); | |
7225342a | 713 | } |
e2f80391 | 714 | intel_ring_emit(engine, MI_NOOP); |
7225342a | 715 | |
e2f80391 | 716 | intel_ring_advance(engine); |
7225342a | 717 | |
e2f80391 | 718 | engine->gpu_caches_dirty = true; |
4866d729 | 719 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
720 | if (ret) |
721 | return ret; | |
888b5995 | 722 | |
7225342a | 723 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 724 | |
7225342a | 725 | return 0; |
86d7f238 AS |
726 | } |
727 | ||
8753181e | 728 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
729 | { |
730 | int ret; | |
731 | ||
e2be4faf | 732 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
733 | if (ret != 0) |
734 | return ret; | |
735 | ||
be01363f | 736 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 737 | if (ret) |
e26e1b97 | 738 | return ret; |
8f0e2b9d | 739 | |
e26e1b97 | 740 | return 0; |
8f0e2b9d DV |
741 | } |
742 | ||
7225342a | 743 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
744 | i915_reg_t addr, |
745 | const u32 mask, const u32 val) | |
7225342a MK |
746 | { |
747 | const u32 idx = dev_priv->workarounds.count; | |
748 | ||
749 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
750 | return -ENOSPC; | |
751 | ||
752 | dev_priv->workarounds.reg[idx].addr = addr; | |
753 | dev_priv->workarounds.reg[idx].value = val; | |
754 | dev_priv->workarounds.reg[idx].mask = mask; | |
755 | ||
756 | dev_priv->workarounds.count++; | |
757 | ||
758 | return 0; | |
86d7f238 AS |
759 | } |
760 | ||
ca5a0fbd | 761 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 762 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
763 | if (r) \ |
764 | return r; \ | |
ca5a0fbd | 765 | } while (0) |
7225342a MK |
766 | |
767 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 768 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
769 | |
770 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 771 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 772 | |
98533251 | 773 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 774 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 775 | |
cf4b0de6 DL |
776 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
777 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 778 | |
cf4b0de6 | 779 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 780 | |
0bc40be8 TU |
781 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
782 | i915_reg_t reg) | |
33136b06 | 783 | { |
c033666a | 784 | struct drm_i915_private *dev_priv = engine->i915; |
33136b06 | 785 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 786 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
787 | |
788 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
789 | return -EINVAL; | |
790 | ||
0bc40be8 | 791 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 792 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 793 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
794 | |
795 | return 0; | |
796 | } | |
797 | ||
0bc40be8 | 798 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 799 | { |
c033666a | 800 | struct drm_i915_private *dev_priv = engine->i915; |
68c6198b AS |
801 | |
802 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 803 | |
717d84d6 AS |
804 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
805 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
806 | ||
d0581194 AS |
807 | /* WaDisablePartialInstShootdown:bdw,chv */ |
808 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
809 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
810 | ||
a340af58 AS |
811 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
812 | * workaround for for a possible hang in the unlikely event a TLB | |
813 | * invalidation occurs during a PSD flush. | |
814 | */ | |
815 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 816 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 817 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 818 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
819 | HDC_FORCE_NON_COHERENT); |
820 | ||
6def8fdd AS |
821 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
822 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
823 | * polygons in the same 8x4 pixel/sample area to be processed without | |
824 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
825 | * buffer." | |
826 | * | |
827 | * This optimization is off by default for BDW and CHV; turn it on. | |
828 | */ | |
829 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
830 | ||
48404636 AS |
831 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
832 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
833 | ||
7eebcde6 AS |
834 | /* |
835 | * BSpec recommends 8x4 when MSAA is used, | |
836 | * however in practice 16x4 seems fastest. | |
837 | * | |
838 | * Note that PS/WM thread counts depend on the WIZ hashing | |
839 | * disable bit, which we don't touch here, but it's good | |
840 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
841 | */ | |
842 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
843 | GEN6_WIZ_HASHING_MASK, | |
844 | GEN6_WIZ_HASHING_16x4); | |
845 | ||
e9a64ada AS |
846 | return 0; |
847 | } | |
848 | ||
0bc40be8 | 849 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 850 | { |
c033666a | 851 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 852 | int ret; |
86d7f238 | 853 | |
0bc40be8 | 854 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
855 | if (ret) |
856 | return ret; | |
857 | ||
101b376d | 858 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 859 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 860 | |
101b376d | 861 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
862 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
863 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 864 | |
7225342a MK |
865 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
866 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 867 | |
7225342a | 868 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
869 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
870 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 871 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
c033666a | 872 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 873 | |
86d7f238 AS |
874 | return 0; |
875 | } | |
876 | ||
0bc40be8 | 877 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 878 | { |
c033666a | 879 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 880 | int ret; |
00e1e623 | 881 | |
0bc40be8 | 882 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
883 | if (ret) |
884 | return ret; | |
885 | ||
00e1e623 | 886 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 887 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 888 | |
d60de81d KG |
889 | /* Improve HiZ throughput on CHV. */ |
890 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
891 | ||
7225342a MK |
892 | return 0; |
893 | } | |
894 | ||
0bc40be8 | 895 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 896 | { |
c033666a | 897 | struct drm_i915_private *dev_priv = engine->i915; |
e0f3fa09 | 898 | int ret; |
ab0dfafe | 899 | |
a8ab5ed5 TG |
900 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
901 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
902 | ||
e5f81d65 | 903 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
904 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
905 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
906 | ||
e5f81d65 | 907 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
908 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
909 | ECOCHK_DIS_TLB); | |
910 | ||
e5f81d65 MK |
911 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
912 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 913 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 914 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
915 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
916 | ||
e5f81d65 | 917 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
918 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
919 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
920 | ||
e87a005d | 921 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
c033666a CW |
922 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
923 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
a86eb582 DL |
924 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
925 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 926 | |
e87a005d | 927 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
928 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
929 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
183c6dac DL |
930 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
931 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
932 | /* |
933 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
934 | * but we do that in per ctx batchbuffer as there is an issue | |
935 | * with this register not getting restored on ctx restore | |
936 | */ | |
183c6dac DL |
937 | } |
938 | ||
e5f81d65 MK |
939 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
940 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
941 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
942 | GEN9_ENABLE_YV12_BUGFIX | | |
943 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 944 | |
e5f81d65 MK |
945 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
946 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
947 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
948 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 949 | |
e5f81d65 | 950 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
951 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
952 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
953 | ||
5a2ae95e | 954 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
c033666a CW |
955 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || |
956 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
38a39a7b BW |
957 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
958 | PIXEL_MASK_CAMMING_DISABLE); | |
959 | ||
5b0e3659 MK |
960 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
961 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
962 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
963 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 964 | |
bbaefe72 MK |
965 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
966 | * both tied to WaForceContextSaveRestoreNonCoherent | |
967 | * in some hsds for skl. We keep the tie for all gen9. The | |
968 | * documentation is a bit hazy and so we want to get common behaviour, | |
969 | * even though there is no clear evidence we would need both on kbl/bxt. | |
970 | * This area has been source of system hangs so we play it safe | |
971 | * and mimic the skl regardless of what bspec says. | |
972 | * | |
973 | * Use Force Non-Coherent whenever executing a 3D context. This | |
974 | * is a workaround for a possible hang in the unlikely event | |
975 | * a TLB invalidation occurs during a PSD flush. | |
976 | */ | |
977 | ||
978 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
979 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
980 | HDC_FORCE_NON_COHERENT); | |
981 | ||
982 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
983 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
984 | BDW_DISABLE_HDC_INVALIDATION); | |
985 | ||
e5f81d65 MK |
986 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
987 | if (IS_SKYLAKE(dev_priv) || | |
988 | IS_KABYLAKE(dev_priv) || | |
989 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
990 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
991 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 992 | |
e5f81d65 | 993 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
994 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
995 | ||
e5f81d65 | 996 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
997 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
998 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
999 | ||
6bb62855 | 1000 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
1001 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
1002 | if (ret) | |
1003 | return ret; | |
1004 | ||
e5f81d65 | 1005 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 1006 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
1007 | if (ret) |
1008 | return ret; | |
1009 | ||
e5f81d65 | 1010 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 1011 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
1012 | if (ret) |
1013 | return ret; | |
1014 | ||
3b106531 HN |
1015 | return 0; |
1016 | } | |
1017 | ||
0bc40be8 | 1018 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 1019 | { |
c033666a | 1020 | struct drm_i915_private *dev_priv = engine->i915; |
b7668791 DL |
1021 | u8 vals[3] = { 0, 0, 0 }; |
1022 | unsigned int i; | |
1023 | ||
1024 | for (i = 0; i < 3; i++) { | |
1025 | u8 ss; | |
1026 | ||
1027 | /* | |
1028 | * Only consider slices where one, and only one, subslice has 7 | |
1029 | * EUs | |
1030 | */ | |
a4d8a0fe | 1031 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1032 | continue; |
1033 | ||
1034 | /* | |
1035 | * subslice_7eu[i] != 0 (because of the check above) and | |
1036 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1037 | * | |
1038 | * -> 0 <= ss <= 3; | |
1039 | */ | |
1040 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1041 | vals[i] = 3 - ss; | |
1042 | } | |
1043 | ||
1044 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1045 | return 0; | |
1046 | ||
1047 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1048 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1049 | GEN9_IZ_HASHING_MASK(2) | | |
1050 | GEN9_IZ_HASHING_MASK(1) | | |
1051 | GEN9_IZ_HASHING_MASK(0), | |
1052 | GEN9_IZ_HASHING(2, vals[2]) | | |
1053 | GEN9_IZ_HASHING(1, vals[1]) | | |
1054 | GEN9_IZ_HASHING(0, vals[0])); | |
1055 | ||
1056 | return 0; | |
1057 | } | |
1058 | ||
0bc40be8 | 1059 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1060 | { |
c033666a | 1061 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1062 | int ret; |
d0bbbc4f | 1063 | |
0bc40be8 | 1064 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1065 | if (ret) |
1066 | return ret; | |
8d205494 | 1067 | |
a78536e7 AS |
1068 | /* |
1069 | * Actual WA is to disable percontext preemption granularity control | |
1070 | * until D0 which is the default case so this is equivalent to | |
1071 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1072 | */ | |
c033666a | 1073 | if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) { |
a78536e7 AS |
1074 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
1075 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1076 | } | |
1077 | ||
71dce58c | 1078 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) { |
9c4cbf82 MK |
1079 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1080 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1081 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1082 | } | |
1083 | ||
1084 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1085 | * involving this register should also be added to WA batch as required. | |
1086 | */ | |
c033666a | 1087 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1088 | /* WaDisableLSQCROPERFforOCL:skl */ |
1089 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1090 | GEN8_LQSC_RO_PERF_DIS); | |
1091 | ||
1092 | /* WaEnableGapsTsvCreditFix:skl */ | |
c033666a | 1093 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1094 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1095 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1096 | } | |
1097 | ||
d0bbbc4f | 1098 | /* WaDisablePowerCompilerClockGating:skl */ |
c033666a | 1099 | if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1100 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1101 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1102 | ||
e87a005d | 1103 | /* WaBarrierPerformanceFixDisable:skl */ |
c033666a | 1104 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0)) |
5b6fd12a VS |
1105 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1106 | HDC_FENCE_DEST_SLM_DISABLE | | |
1107 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1108 | ||
9bd9dfb4 | 1109 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
c033666a | 1110 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1111 | WA_SET_BIT_MASKED( |
1112 | GEN7_HALF_SLICE_CHICKEN1, | |
1113 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1114 | |
eee8efb0 MK |
1115 | /* WaDisableGafsUnitClkGating:skl */ |
1116 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1117 | ||
6107497e | 1118 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1119 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1120 | if (ret) |
1121 | return ret; | |
1122 | ||
0bc40be8 | 1123 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1124 | } |
1125 | ||
0bc40be8 | 1126 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1127 | { |
c033666a | 1128 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1129 | int ret; |
dfb601e6 | 1130 | |
0bc40be8 | 1131 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1132 | if (ret) |
1133 | return ret; | |
cae0437f | 1134 | |
9c4cbf82 MK |
1135 | /* WaStoreMultiplePTEenable:bxt */ |
1136 | /* This is a requirement according to Hardware specification */ | |
c033666a | 1137 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1138 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1139 | ||
1140 | /* WaSetClckGatingDisableMedia:bxt */ | |
c033666a | 1141 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1142 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1143 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1144 | } | |
1145 | ||
dfb601e6 NH |
1146 | /* WaDisableThreadStallDopClockGating:bxt */ |
1147 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1148 | STALL_DOP_GATING_DISABLE); | |
1149 | ||
780f0aeb | 1150 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
1151 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
1152 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
1153 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
1154 | } | |
1155 | ||
983b4b9d | 1156 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
c033666a | 1157 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1158 | WA_SET_BIT_MASKED( |
1159 | GEN7_HALF_SLICE_CHICKEN1, | |
1160 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1161 | } | |
1162 | ||
2c8580e4 AS |
1163 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1164 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1165 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1166 | /* WaDisableLSQCROPERFforOCL:bxt */ |
c033666a | 1167 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
0bc40be8 | 1168 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1169 | if (ret) |
1170 | return ret; | |
a786d53a | 1171 | |
0bc40be8 | 1172 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1173 | if (ret) |
1174 | return ret; | |
2c8580e4 AS |
1175 | } |
1176 | ||
050fc465 | 1177 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
c033666a | 1178 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
36579cb6 ID |
1179 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
1180 | L3_HIGH_PRIO_CREDITS(2)); | |
050fc465 | 1181 | |
ad2bdb44 MK |
1182 | /* WaInsertDummyPushConstPs:bxt */ |
1183 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
1184 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1185 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1186 | ||
cae0437f NH |
1187 | return 0; |
1188 | } | |
1189 | ||
e5f81d65 MK |
1190 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1191 | { | |
e587f6cb | 1192 | struct drm_i915_private *dev_priv = engine->i915; |
e5f81d65 MK |
1193 | int ret; |
1194 | ||
1195 | ret = gen9_init_workarounds(engine); | |
1196 | if (ret) | |
1197 | return ret; | |
1198 | ||
e587f6cb MK |
1199 | /* WaEnableGapsTsvCreditFix:kbl */ |
1200 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1201 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1202 | ||
c0b730d5 MK |
1203 | /* WaDisableDynamicCreditSharing:kbl */ |
1204 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1205 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1206 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1207 | ||
8401d42f MK |
1208 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1209 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1210 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1211 | HDC_FENCE_DEST_SLM_DISABLE); | |
1212 | ||
fe905819 MK |
1213 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1214 | * involving this register should also be added to WA batch as required. | |
1215 | */ | |
1216 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1217 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1218 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1219 | GEN8_LQSC_RO_PERF_DIS); | |
1220 | ||
ad2bdb44 MK |
1221 | /* WaInsertDummyPushConstPs:kbl */ |
1222 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1223 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1224 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1225 | ||
4de5d7cc MK |
1226 | /* WaDisableGafsUnitClkGating:kbl */ |
1227 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1228 | ||
954337aa MK |
1229 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1230 | WA_SET_BIT_MASKED( | |
1231 | GEN7_HALF_SLICE_CHICKEN1, | |
1232 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1233 | ||
fe905819 MK |
1234 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1235 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1236 | if (ret) | |
1237 | return ret; | |
1238 | ||
e5f81d65 MK |
1239 | return 0; |
1240 | } | |
1241 | ||
0bc40be8 | 1242 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1243 | { |
c033666a | 1244 | struct drm_i915_private *dev_priv = engine->i915; |
7225342a | 1245 | |
0bc40be8 | 1246 | WARN_ON(engine->id != RCS); |
7225342a MK |
1247 | |
1248 | dev_priv->workarounds.count = 0; | |
33136b06 | 1249 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a | 1250 | |
c033666a | 1251 | if (IS_BROADWELL(dev_priv)) |
0bc40be8 | 1252 | return bdw_init_workarounds(engine); |
7225342a | 1253 | |
c033666a | 1254 | if (IS_CHERRYVIEW(dev_priv)) |
0bc40be8 | 1255 | return chv_init_workarounds(engine); |
00e1e623 | 1256 | |
c033666a | 1257 | if (IS_SKYLAKE(dev_priv)) |
0bc40be8 | 1258 | return skl_init_workarounds(engine); |
cae0437f | 1259 | |
c033666a | 1260 | if (IS_BROXTON(dev_priv)) |
0bc40be8 | 1261 | return bxt_init_workarounds(engine); |
3b106531 | 1262 | |
e5f81d65 MK |
1263 | if (IS_KABYLAKE(dev_priv)) |
1264 | return kbl_init_workarounds(engine); | |
1265 | ||
00e1e623 VS |
1266 | return 0; |
1267 | } | |
1268 | ||
0bc40be8 | 1269 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1270 | { |
c033666a | 1271 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 1272 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1273 | if (ret) |
1274 | return ret; | |
a69ffdbf | 1275 | |
61a563a2 | 1276 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 1277 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 1278 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1279 | |
1280 | /* We need to disable the AsyncFlip performance optimisations in order | |
1281 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1282 | * programmed to '1' on all products. | |
8693a824 | 1283 | * |
2441f877 | 1284 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1285 | */ |
ac657f64 | 1286 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
1287 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1288 | ||
f05bb0c7 | 1289 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1290 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 1291 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 1292 | I915_WRITE(GFX_MODE, |
aa83e30d | 1293 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1294 | |
01fa0302 | 1295 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 1296 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 1297 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 1298 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1299 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1300 | |
c033666a | 1301 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
1302 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1303 | * "If this bit is set, STCunit will have LRA as replacement | |
1304 | * policy. [...] This bit must be reset. LRA replacement | |
1305 | * policy is not supported." | |
1306 | */ | |
1307 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1308 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1309 | } |
1310 | ||
ac657f64 | 1311 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 1312 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1313 | |
c033666a CW |
1314 | if (HAS_L3_DPF(dev_priv)) |
1315 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv)); | |
15b9f80e | 1316 | |
0bc40be8 | 1317 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1318 | } |
1319 | ||
0bc40be8 | 1320 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1321 | { |
c033666a | 1322 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a BW |
1323 | |
1324 | if (dev_priv->semaphore_obj) { | |
1325 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1326 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1327 | dev_priv->semaphore_obj = NULL; | |
1328 | } | |
b45305fc | 1329 | |
0bc40be8 | 1330 | intel_fini_pipe_control(engine); |
c6df541c CW |
1331 | } |
1332 | ||
f7169687 | 1333 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1334 | unsigned int num_dwords) |
1335 | { | |
1336 | #define MBOX_UPDATE_DWORDS 8 | |
4a570db5 | 1337 | struct intel_engine_cs *signaller = signaller_req->engine; |
c033666a | 1338 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1339 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1340 | enum intel_engine_id id; |
1341 | int ret, num_rings; | |
3e78998a | 1342 | |
c033666a | 1343 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1344 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1345 | #undef MBOX_UPDATE_DWORDS | |
1346 | ||
5fb9de1a | 1347 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1348 | if (ret) |
1349 | return ret; | |
1350 | ||
c3232b18 | 1351 | for_each_engine_id(waiter, dev_priv, id) { |
c3232b18 | 1352 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1353 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1354 | continue; | |
1355 | ||
1356 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); | |
1357 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1358 | PIPE_CONTROL_QW_WRITE | | |
f9a4ea35 | 1359 | PIPE_CONTROL_CS_STALL); |
3e78998a BW |
1360 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
1361 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
1b7744e7 | 1362 | intel_ring_emit(signaller, signaller_req->seqno); |
3e78998a BW |
1363 | intel_ring_emit(signaller, 0); |
1364 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
215a7e32 | 1365 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1366 | intel_ring_emit(signaller, 0); |
1367 | } | |
1368 | ||
1369 | return 0; | |
1370 | } | |
1371 | ||
f7169687 | 1372 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1373 | unsigned int num_dwords) |
1374 | { | |
1375 | #define MBOX_UPDATE_DWORDS 6 | |
4a570db5 | 1376 | struct intel_engine_cs *signaller = signaller_req->engine; |
c033666a | 1377 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1378 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1379 | enum intel_engine_id id; |
1380 | int ret, num_rings; | |
3e78998a | 1381 | |
c033666a | 1382 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1383 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1384 | #undef MBOX_UPDATE_DWORDS | |
1385 | ||
5fb9de1a | 1386 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1387 | if (ret) |
1388 | return ret; | |
1389 | ||
c3232b18 | 1390 | for_each_engine_id(waiter, dev_priv, id) { |
c3232b18 | 1391 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1392 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1393 | continue; | |
1394 | ||
1395 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | | |
1396 | MI_FLUSH_DW_OP_STOREDW); | |
1397 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1398 | MI_FLUSH_DW_USE_GTT); | |
1399 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
1b7744e7 | 1400 | intel_ring_emit(signaller, signaller_req->seqno); |
3e78998a | 1401 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
215a7e32 | 1402 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1403 | intel_ring_emit(signaller, 0); |
1404 | } | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
f7169687 | 1409 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1410 | unsigned int num_dwords) |
1ec14ad3 | 1411 | { |
4a570db5 | 1412 | struct intel_engine_cs *signaller = signaller_req->engine; |
c033666a | 1413 | struct drm_i915_private *dev_priv = signaller_req->i915; |
a4872ba6 | 1414 | struct intel_engine_cs *useless; |
c3232b18 DG |
1415 | enum intel_engine_id id; |
1416 | int ret, num_rings; | |
78325f2d | 1417 | |
a1444b79 | 1418 | #define MBOX_UPDATE_DWORDS 3 |
c033666a | 1419 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
a1444b79 BW |
1420 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
1421 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1422 | |
5fb9de1a | 1423 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1424 | if (ret) |
1425 | return ret; | |
024a43e1 | 1426 | |
c3232b18 DG |
1427 | for_each_engine_id(useless, dev_priv, id) { |
1428 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1429 | |
1430 | if (i915_mmio_reg_valid(mbox_reg)) { | |
78325f2d | 1431 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1432 | intel_ring_emit_reg(signaller, mbox_reg); |
1b7744e7 | 1433 | intel_ring_emit(signaller, signaller_req->seqno); |
78325f2d BW |
1434 | } |
1435 | } | |
024a43e1 | 1436 | |
a1444b79 BW |
1437 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1438 | if (num_rings % 2 == 0) | |
1439 | intel_ring_emit(signaller, MI_NOOP); | |
1440 | ||
024a43e1 | 1441 | return 0; |
1ec14ad3 CW |
1442 | } |
1443 | ||
c8c99b0f BW |
1444 | /** |
1445 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1446 | * |
1447 | * @request - request to write to the ring | |
c8c99b0f BW |
1448 | * |
1449 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1450 | * This acts like a signal in the canonical semaphore. | |
1451 | */ | |
1ec14ad3 | 1452 | static int |
ee044a88 | 1453 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1454 | { |
4a570db5 | 1455 | struct intel_engine_cs *engine = req->engine; |
024a43e1 | 1456 | int ret; |
52ed2325 | 1457 | |
e2f80391 TU |
1458 | if (engine->semaphore.signal) |
1459 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1460 | else |
5fb9de1a | 1461 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1462 | |
1ec14ad3 CW |
1463 | if (ret) |
1464 | return ret; | |
1465 | ||
e2f80391 TU |
1466 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1467 | intel_ring_emit(engine, | |
1468 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1b7744e7 | 1469 | intel_ring_emit(engine, req->seqno); |
e2f80391 TU |
1470 | intel_ring_emit(engine, MI_USER_INTERRUPT); |
1471 | __intel_ring_advance(engine); | |
1ec14ad3 | 1472 | |
1ec14ad3 CW |
1473 | return 0; |
1474 | } | |
1475 | ||
a58c01aa CW |
1476 | static int |
1477 | gen8_render_add_request(struct drm_i915_gem_request *req) | |
1478 | { | |
1479 | struct intel_engine_cs *engine = req->engine; | |
1480 | int ret; | |
1481 | ||
1482 | if (engine->semaphore.signal) | |
1483 | ret = engine->semaphore.signal(req, 8); | |
1484 | else | |
1485 | ret = intel_ring_begin(req, 8); | |
1486 | if (ret) | |
1487 | return ret; | |
1488 | ||
1489 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); | |
1490 | intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1491 | PIPE_CONTROL_CS_STALL | | |
1492 | PIPE_CONTROL_QW_WRITE)); | |
1493 | intel_ring_emit(engine, intel_hws_seqno_address(req->engine)); | |
1494 | intel_ring_emit(engine, 0); | |
1495 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1496 | /* We're thrashing one dword of HWS. */ | |
1497 | intel_ring_emit(engine, 0); | |
1498 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1499 | intel_ring_emit(engine, MI_NOOP); | |
1500 | __intel_ring_advance(engine); | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
c033666a | 1505 | static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv, |
f72b3435 MK |
1506 | u32 seqno) |
1507 | { | |
f72b3435 MK |
1508 | return dev_priv->last_seqno < seqno; |
1509 | } | |
1510 | ||
c8c99b0f BW |
1511 | /** |
1512 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1513 | * | |
1514 | * @waiter - ring that is waiting | |
1515 | * @signaller - ring which has, or will signal | |
1516 | * @seqno - seqno which the waiter will block on | |
1517 | */ | |
5ee426ca BW |
1518 | |
1519 | static int | |
599d924c | 1520 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1521 | struct intel_engine_cs *signaller, |
1522 | u32 seqno) | |
1523 | { | |
4a570db5 | 1524 | struct intel_engine_cs *waiter = waiter_req->engine; |
c033666a | 1525 | struct drm_i915_private *dev_priv = waiter_req->i915; |
c38c651b | 1526 | u64 offset = GEN8_WAIT_OFFSET(waiter, signaller->id); |
6ef48d7f | 1527 | struct i915_hw_ppgtt *ppgtt; |
5ee426ca BW |
1528 | int ret; |
1529 | ||
5fb9de1a | 1530 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1531 | if (ret) |
1532 | return ret; | |
1533 | ||
1534 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1535 | MI_SEMAPHORE_GLOBAL_GTT | | |
1536 | MI_SEMAPHORE_SAD_GTE_SDD); | |
1537 | intel_ring_emit(waiter, seqno); | |
c38c651b TU |
1538 | intel_ring_emit(waiter, lower_32_bits(offset)); |
1539 | intel_ring_emit(waiter, upper_32_bits(offset)); | |
5ee426ca | 1540 | intel_ring_advance(waiter); |
6ef48d7f CW |
1541 | |
1542 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
1543 | * pagetables and we must reload them before executing the batch. | |
1544 | * We do this on the i915_switch_context() following the wait and | |
1545 | * before the dispatch. | |
1546 | */ | |
1547 | ppgtt = waiter_req->ctx->ppgtt; | |
1548 | if (ppgtt && waiter_req->engine->id != RCS) | |
1549 | ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine); | |
5ee426ca BW |
1550 | return 0; |
1551 | } | |
1552 | ||
c8c99b0f | 1553 | static int |
599d924c | 1554 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1555 | struct intel_engine_cs *signaller, |
686cb5f9 | 1556 | u32 seqno) |
1ec14ad3 | 1557 | { |
4a570db5 | 1558 | struct intel_engine_cs *waiter = waiter_req->engine; |
c8c99b0f BW |
1559 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1560 | MI_SEMAPHORE_COMPARE | | |
1561 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1562 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1563 | int ret; | |
1ec14ad3 | 1564 | |
1500f7ea BW |
1565 | /* Throughout all of the GEM code, seqno passed implies our current |
1566 | * seqno is >= the last seqno executed. However for hardware the | |
1567 | * comparison is strictly greater than. | |
1568 | */ | |
1569 | seqno -= 1; | |
1570 | ||
ebc348b2 | 1571 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1572 | |
5fb9de1a | 1573 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1574 | if (ret) |
1575 | return ret; | |
1576 | ||
f72b3435 | 1577 | /* If seqno wrap happened, omit the wait with no-ops */ |
c033666a | 1578 | if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) { |
ebc348b2 | 1579 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1580 | intel_ring_emit(waiter, seqno); |
1581 | intel_ring_emit(waiter, 0); | |
1582 | intel_ring_emit(waiter, MI_NOOP); | |
1583 | } else { | |
1584 | intel_ring_emit(waiter, MI_NOOP); | |
1585 | intel_ring_emit(waiter, MI_NOOP); | |
1586 | intel_ring_emit(waiter, MI_NOOP); | |
1587 | intel_ring_emit(waiter, MI_NOOP); | |
1588 | } | |
c8c99b0f | 1589 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1590 | |
1591 | return 0; | |
1592 | } | |
1593 | ||
c6df541c CW |
1594 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1595 | do { \ | |
fcbc34e4 KG |
1596 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1597 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1598 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1599 | intel_ring_emit(ring__, 0); \ | |
1600 | intel_ring_emit(ring__, 0); \ | |
1601 | } while (0) | |
1602 | ||
1603 | static int | |
ee044a88 | 1604 | pc_render_add_request(struct drm_i915_gem_request *req) |
c6df541c | 1605 | { |
4a570db5 | 1606 | struct intel_engine_cs *engine = req->engine; |
1b7744e7 CW |
1607 | u32 addr = engine->status_page.gfx_addr + |
1608 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1609 | u32 scratch_addr = addr; | |
c6df541c CW |
1610 | int ret; |
1611 | ||
1612 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1613 | * incoherent with writes to memory, i.e. completely fubar, | |
1614 | * so we need to use PIPE_NOTIFY instead. | |
1615 | * | |
1616 | * However, we also need to workaround the qword write | |
1617 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1618 | * memory before requesting an interrupt. | |
1619 | */ | |
5fb9de1a | 1620 | ret = intel_ring_begin(req, 32); |
c6df541c CW |
1621 | if (ret) |
1622 | return ret; | |
1623 | ||
e2f80391 | 1624 | intel_ring_emit(engine, |
1b7744e7 CW |
1625 | GFX_OP_PIPE_CONTROL(4) | |
1626 | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1627 | PIPE_CONTROL_WRITE_FLUSH | |
1628 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
1b7744e7 CW |
1629 | intel_ring_emit(engine, addr | PIPE_CONTROL_GLOBAL_GTT); |
1630 | intel_ring_emit(engine, req->seqno); | |
e2f80391 TU |
1631 | intel_ring_emit(engine, 0); |
1632 | PIPE_CONTROL_FLUSH(engine, scratch_addr); | |
18393f63 | 1633 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
e2f80391 | 1634 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1635 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1636 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1637 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1638 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1639 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1640 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1641 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1642 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
a71d8d94 | 1643 | |
e2f80391 TU |
1644 | intel_ring_emit(engine, |
1645 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1646 | PIPE_CONTROL_WRITE_FLUSH | |
1647 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1648 | PIPE_CONTROL_NOTIFY); |
1b7744e7 CW |
1649 | intel_ring_emit(engine, addr | PIPE_CONTROL_GLOBAL_GTT); |
1650 | intel_ring_emit(engine, req->seqno); | |
e2f80391 TU |
1651 | intel_ring_emit(engine, 0); |
1652 | __intel_ring_advance(engine); | |
c6df541c | 1653 | |
c6df541c CW |
1654 | return 0; |
1655 | } | |
1656 | ||
c04e0f3b CW |
1657 | static void |
1658 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1659 | { |
c033666a | 1660 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 1661 | |
4cd53c0c DV |
1662 | /* Workaround to force correct ordering between irq and seqno writes on |
1663 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1664 | * ACTHD) before reading the status page. |
1665 | * | |
1666 | * Note that this effectively stalls the read by the time it takes to | |
1667 | * do a memory transaction, which more or less ensures that the write | |
1668 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1669 | * Alternatively we could delay the interrupt from the CS ring to give | |
1670 | * the write time to land, but that would incur a delay after every | |
1671 | * batch i.e. much more frequent than a delay when waiting for the | |
1672 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1673 | * |
1674 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1675 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1676 | */ |
bcbdb6d0 | 1677 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1678 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1679 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1680 | } |
1681 | ||
e48d8634 | 1682 | static bool |
0bc40be8 | 1683 | gen5_ring_get_irq(struct intel_engine_cs *engine) |
e48d8634 | 1684 | { |
c033666a | 1685 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1686 | unsigned long flags; |
e48d8634 | 1687 | |
7cd512f1 | 1688 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1689 | return false; |
1690 | ||
7338aefa | 1691 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1692 | if (engine->irq_refcount++ == 0) |
1693 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1694 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1695 | |
1696 | return true; | |
1697 | } | |
1698 | ||
1699 | static void | |
0bc40be8 | 1700 | gen5_ring_put_irq(struct intel_engine_cs *engine) |
e48d8634 | 1701 | { |
c033666a | 1702 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1703 | unsigned long flags; |
e48d8634 | 1704 | |
7338aefa | 1705 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1706 | if (--engine->irq_refcount == 0) |
1707 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1708 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1709 | } |
1710 | ||
b13c2b96 | 1711 | static bool |
0bc40be8 | 1712 | i9xx_ring_get_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1713 | { |
c033666a | 1714 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1715 | unsigned long flags; |
62fdfeaf | 1716 | |
7cd512f1 | 1717 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1718 | return false; |
1719 | ||
7338aefa | 1720 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1721 | if (engine->irq_refcount++ == 0) { |
1722 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
f637fde4 DV |
1723 | I915_WRITE(IMR, dev_priv->irq_mask); |
1724 | POSTING_READ(IMR); | |
1725 | } | |
7338aefa | 1726 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1727 | |
1728 | return true; | |
62fdfeaf EA |
1729 | } |
1730 | ||
8187a2b7 | 1731 | static void |
0bc40be8 | 1732 | i9xx_ring_put_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1733 | { |
c033666a | 1734 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1735 | unsigned long flags; |
62fdfeaf | 1736 | |
7338aefa | 1737 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1738 | if (--engine->irq_refcount == 0) { |
1739 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
f637fde4 DV |
1740 | I915_WRITE(IMR, dev_priv->irq_mask); |
1741 | POSTING_READ(IMR); | |
1742 | } | |
7338aefa | 1743 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1744 | } |
1745 | ||
c2798b19 | 1746 | static bool |
0bc40be8 | 1747 | i8xx_ring_get_irq(struct intel_engine_cs *engine) |
c2798b19 | 1748 | { |
c033666a | 1749 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1750 | unsigned long flags; |
c2798b19 | 1751 | |
7cd512f1 | 1752 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1753 | return false; |
1754 | ||
7338aefa | 1755 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1756 | if (engine->irq_refcount++ == 0) { |
1757 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
c2798b19 CW |
1758 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1759 | POSTING_READ16(IMR); | |
1760 | } | |
7338aefa | 1761 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1762 | |
1763 | return true; | |
1764 | } | |
1765 | ||
1766 | static void | |
0bc40be8 | 1767 | i8xx_ring_put_irq(struct intel_engine_cs *engine) |
c2798b19 | 1768 | { |
c033666a | 1769 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1770 | unsigned long flags; |
c2798b19 | 1771 | |
7338aefa | 1772 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1773 | if (--engine->irq_refcount == 0) { |
1774 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
c2798b19 CW |
1775 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1776 | POSTING_READ16(IMR); | |
1777 | } | |
7338aefa | 1778 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1779 | } |
1780 | ||
b72f3acb | 1781 | static int |
a84c3ae1 | 1782 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1783 | u32 invalidate_domains, |
1784 | u32 flush_domains) | |
d1b851fc | 1785 | { |
4a570db5 | 1786 | struct intel_engine_cs *engine = req->engine; |
b72f3acb CW |
1787 | int ret; |
1788 | ||
5fb9de1a | 1789 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1790 | if (ret) |
1791 | return ret; | |
1792 | ||
e2f80391 TU |
1793 | intel_ring_emit(engine, MI_FLUSH); |
1794 | intel_ring_emit(engine, MI_NOOP); | |
1795 | intel_ring_advance(engine); | |
b72f3acb | 1796 | return 0; |
d1b851fc ZN |
1797 | } |
1798 | ||
3cce469c | 1799 | static int |
ee044a88 | 1800 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1801 | { |
4a570db5 | 1802 | struct intel_engine_cs *engine = req->engine; |
3cce469c CW |
1803 | int ret; |
1804 | ||
5fb9de1a | 1805 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1806 | if (ret) |
1807 | return ret; | |
6f392d54 | 1808 | |
e2f80391 TU |
1809 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1810 | intel_ring_emit(engine, | |
1811 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1b7744e7 | 1812 | intel_ring_emit(engine, req->seqno); |
e2f80391 TU |
1813 | intel_ring_emit(engine, MI_USER_INTERRUPT); |
1814 | __intel_ring_advance(engine); | |
d1b851fc | 1815 | |
3cce469c | 1816 | return 0; |
d1b851fc ZN |
1817 | } |
1818 | ||
0f46832f | 1819 | static bool |
0bc40be8 | 1820 | gen6_ring_get_irq(struct intel_engine_cs *engine) |
0f46832f | 1821 | { |
c033666a | 1822 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1823 | unsigned long flags; |
0f46832f | 1824 | |
7cd512f1 DV |
1825 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1826 | return false; | |
0f46832f | 1827 | |
7338aefa | 1828 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 | 1829 | if (engine->irq_refcount++ == 0) { |
c033666a | 1830 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) |
0bc40be8 TU |
1831 | I915_WRITE_IMR(engine, |
1832 | ~(engine->irq_enable_mask | | |
c033666a | 1833 | GT_PARITY_ERROR(dev_priv))); |
15b9f80e | 1834 | else |
0bc40be8 TU |
1835 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1836 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
0f46832f | 1837 | } |
7338aefa | 1838 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1839 | |
1840 | return true; | |
1841 | } | |
1842 | ||
1843 | static void | |
0bc40be8 | 1844 | gen6_ring_put_irq(struct intel_engine_cs *engine) |
0f46832f | 1845 | { |
c033666a | 1846 | struct drm_i915_private *dev_priv = engine->i915; |
7338aefa | 1847 | unsigned long flags; |
0f46832f | 1848 | |
7338aefa | 1849 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 | 1850 | if (--engine->irq_refcount == 0) { |
c033666a CW |
1851 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) |
1852 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv)); | |
15b9f80e | 1853 | else |
0bc40be8 TU |
1854 | I915_WRITE_IMR(engine, ~0); |
1855 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
1ec14ad3 | 1856 | } |
7338aefa | 1857 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1858 | } |
1859 | ||
a19d2933 | 1860 | static bool |
0bc40be8 | 1861 | hsw_vebox_get_irq(struct intel_engine_cs *engine) |
a19d2933 | 1862 | { |
c033666a | 1863 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 BW |
1864 | unsigned long flags; |
1865 | ||
7cd512f1 | 1866 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1867 | return false; |
1868 | ||
59cdb63d | 1869 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1870 | if (engine->irq_refcount++ == 0) { |
1871 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); | |
1872 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1873 | } |
59cdb63d | 1874 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1875 | |
1876 | return true; | |
1877 | } | |
1878 | ||
1879 | static void | |
0bc40be8 | 1880 | hsw_vebox_put_irq(struct intel_engine_cs *engine) |
a19d2933 | 1881 | { |
c033666a | 1882 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 BW |
1883 | unsigned long flags; |
1884 | ||
59cdb63d | 1885 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1886 | if (--engine->irq_refcount == 0) { |
1887 | I915_WRITE_IMR(engine, ~0); | |
1888 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1889 | } |
59cdb63d | 1890 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1891 | } |
1892 | ||
abd58f01 | 1893 | static bool |
0bc40be8 | 1894 | gen8_ring_get_irq(struct intel_engine_cs *engine) |
abd58f01 | 1895 | { |
c033666a | 1896 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 BW |
1897 | unsigned long flags; |
1898 | ||
7cd512f1 | 1899 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1900 | return false; |
1901 | ||
1902 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 | 1903 | if (engine->irq_refcount++ == 0) { |
c033666a | 1904 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) { |
0bc40be8 TU |
1905 | I915_WRITE_IMR(engine, |
1906 | ~(engine->irq_enable_mask | | |
abd58f01 BW |
1907 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
1908 | } else { | |
0bc40be8 | 1909 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
abd58f01 | 1910 | } |
0bc40be8 | 1911 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1912 | } |
1913 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1914 | ||
1915 | return true; | |
1916 | } | |
1917 | ||
1918 | static void | |
0bc40be8 | 1919 | gen8_ring_put_irq(struct intel_engine_cs *engine) |
abd58f01 | 1920 | { |
c033666a | 1921 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 BW |
1922 | unsigned long flags; |
1923 | ||
1924 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 | 1925 | if (--engine->irq_refcount == 0) { |
c033666a | 1926 | if (HAS_L3_DPF(dev_priv) && engine->id == RCS) { |
0bc40be8 | 1927 | I915_WRITE_IMR(engine, |
abd58f01 BW |
1928 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
1929 | } else { | |
0bc40be8 | 1930 | I915_WRITE_IMR(engine, ~0); |
abd58f01 | 1931 | } |
0bc40be8 | 1932 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1933 | } |
1934 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1935 | } | |
1936 | ||
d1b851fc | 1937 | static int |
53fddaf7 | 1938 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1939 | u64 offset, u32 length, |
8e004efc | 1940 | unsigned dispatch_flags) |
d1b851fc | 1941 | { |
4a570db5 | 1942 | struct intel_engine_cs *engine = req->engine; |
e1f99ce6 | 1943 | int ret; |
78501eac | 1944 | |
5fb9de1a | 1945 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1946 | if (ret) |
1947 | return ret; | |
1948 | ||
e2f80391 | 1949 | intel_ring_emit(engine, |
65f56876 CW |
1950 | MI_BATCH_BUFFER_START | |
1951 | MI_BATCH_GTT | | |
8e004efc JH |
1952 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1953 | 0 : MI_BATCH_NON_SECURE_I965)); | |
e2f80391 TU |
1954 | intel_ring_emit(engine, offset); |
1955 | intel_ring_advance(engine); | |
78501eac | 1956 | |
d1b851fc ZN |
1957 | return 0; |
1958 | } | |
1959 | ||
b45305fc DV |
1960 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1961 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1962 | #define I830_TLB_ENTRIES (2) |
1963 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1964 | static int |
53fddaf7 | 1965 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1966 | u64 offset, u32 len, |
1967 | unsigned dispatch_flags) | |
62fdfeaf | 1968 | { |
4a570db5 | 1969 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1970 | u32 cs_offset = engine->scratch.gtt_offset; |
c4e7a414 | 1971 | int ret; |
62fdfeaf | 1972 | |
5fb9de1a | 1973 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1974 | if (ret) |
1975 | return ret; | |
62fdfeaf | 1976 | |
c4d69da1 | 1977 | /* Evict the invalid PTE TLBs */ |
e2f80391 TU |
1978 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1979 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1980 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1981 | intel_ring_emit(engine, cs_offset); | |
1982 | intel_ring_emit(engine, 0xdeadbeef); | |
1983 | intel_ring_emit(engine, MI_NOOP); | |
1984 | intel_ring_advance(engine); | |
b45305fc | 1985 | |
8e004efc | 1986 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1987 | if (len > I830_BATCH_LIMIT) |
1988 | return -ENOSPC; | |
1989 | ||
5fb9de1a | 1990 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1991 | if (ret) |
1992 | return ret; | |
c4d69da1 CW |
1993 | |
1994 | /* Blit the batch (which has now all relocs applied) to the | |
1995 | * stable batch scratch bo area (so that the CS never | |
1996 | * stumbles over its tlb invalidation bug) ... | |
1997 | */ | |
e2f80391 TU |
1998 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1999 | intel_ring_emit(engine, | |
2000 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
2001 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); | |
2002 | intel_ring_emit(engine, cs_offset); | |
2003 | intel_ring_emit(engine, 4096); | |
2004 | intel_ring_emit(engine, offset); | |
2005 | ||
2006 | intel_ring_emit(engine, MI_FLUSH); | |
2007 | intel_ring_emit(engine, MI_NOOP); | |
2008 | intel_ring_advance(engine); | |
b45305fc DV |
2009 | |
2010 | /* ... and execute it. */ | |
c4d69da1 | 2011 | offset = cs_offset; |
b45305fc | 2012 | } |
e1f99ce6 | 2013 | |
9d611c03 | 2014 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
2015 | if (ret) |
2016 | return ret; | |
2017 | ||
e2f80391 TU |
2018 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
2019 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
2020 | 0 : MI_BATCH_NON_SECURE)); | |
2021 | intel_ring_advance(engine); | |
c4d69da1 | 2022 | |
fb3256da DV |
2023 | return 0; |
2024 | } | |
2025 | ||
2026 | static int | |
53fddaf7 | 2027 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2028 | u64 offset, u32 len, |
8e004efc | 2029 | unsigned dispatch_flags) |
fb3256da | 2030 | { |
4a570db5 | 2031 | struct intel_engine_cs *engine = req->engine; |
fb3256da DV |
2032 | int ret; |
2033 | ||
5fb9de1a | 2034 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
2035 | if (ret) |
2036 | return ret; | |
2037 | ||
e2f80391 TU |
2038 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
2039 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
2040 | 0 : MI_BATCH_NON_SECURE)); | |
2041 | intel_ring_advance(engine); | |
62fdfeaf | 2042 | |
62fdfeaf EA |
2043 | return 0; |
2044 | } | |
2045 | ||
0bc40be8 | 2046 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 2047 | { |
c033666a | 2048 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
2049 | |
2050 | if (!dev_priv->status_page_dmah) | |
2051 | return; | |
2052 | ||
c033666a | 2053 | drm_pci_free(dev_priv->dev, dev_priv->status_page_dmah); |
0bc40be8 | 2054 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
2055 | } |
2056 | ||
0bc40be8 | 2057 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2058 | { |
05394f39 | 2059 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2060 | |
0bc40be8 | 2061 | obj = engine->status_page.obj; |
8187a2b7 | 2062 | if (obj == NULL) |
62fdfeaf | 2063 | return; |
62fdfeaf | 2064 | |
9da3da66 | 2065 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 2066 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 2067 | drm_gem_object_unreference(&obj->base); |
0bc40be8 | 2068 | engine->status_page.obj = NULL; |
62fdfeaf EA |
2069 | } |
2070 | ||
0bc40be8 | 2071 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2072 | { |
0bc40be8 | 2073 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 2074 | |
7d3fdfff | 2075 | if (obj == NULL) { |
1f767e02 | 2076 | unsigned flags; |
e3efda49 | 2077 | int ret; |
e4ffd173 | 2078 | |
c033666a | 2079 | obj = i915_gem_object_create(engine->i915->dev, 4096); |
fe3db79b | 2080 | if (IS_ERR(obj)) { |
e3efda49 | 2081 | DRM_ERROR("Failed to allocate status page\n"); |
fe3db79b | 2082 | return PTR_ERR(obj); |
e3efda49 | 2083 | } |
62fdfeaf | 2084 | |
e3efda49 CW |
2085 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
2086 | if (ret) | |
2087 | goto err_unref; | |
2088 | ||
1f767e02 | 2089 | flags = 0; |
c033666a | 2090 | if (!HAS_LLC(engine->i915)) |
1f767e02 CW |
2091 | /* On g33, we cannot place HWS above 256MiB, so |
2092 | * restrict its pinning to the low mappable arena. | |
2093 | * Though this restriction is not documented for | |
2094 | * gen4, gen5, or byt, they also behave similarly | |
2095 | * and hang if the HWS is placed at the top of the | |
2096 | * GTT. To generalise, it appears that all !llc | |
2097 | * platforms have issues with us placing the HWS | |
2098 | * above the mappable region (even though we never | |
2099 | * actualy map it). | |
2100 | */ | |
2101 | flags |= PIN_MAPPABLE; | |
2102 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
2103 | if (ret) { |
2104 | err_unref: | |
2105 | drm_gem_object_unreference(&obj->base); | |
2106 | return ret; | |
2107 | } | |
2108 | ||
0bc40be8 | 2109 | engine->status_page.obj = obj; |
e3efda49 | 2110 | } |
62fdfeaf | 2111 | |
0bc40be8 TU |
2112 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
2113 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
2114 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 2115 | |
8187a2b7 | 2116 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 2117 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
2118 | |
2119 | return 0; | |
62fdfeaf EA |
2120 | } |
2121 | ||
0bc40be8 | 2122 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 2123 | { |
c033666a | 2124 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 CW |
2125 | |
2126 | if (!dev_priv->status_page_dmah) { | |
2127 | dev_priv->status_page_dmah = | |
c033666a | 2128 | drm_pci_alloc(dev_priv->dev, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
2129 | if (!dev_priv->status_page_dmah) |
2130 | return -ENOMEM; | |
2131 | } | |
2132 | ||
0bc40be8 TU |
2133 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
2134 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
2135 | |
2136 | return 0; | |
2137 | } | |
2138 | ||
7ba717cf | 2139 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 2140 | { |
3d77e9be CW |
2141 | GEM_BUG_ON(ringbuf->vma == NULL); |
2142 | GEM_BUG_ON(ringbuf->virtual_start == NULL); | |
2143 | ||
def0c5f6 | 2144 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
0a798eb9 | 2145 | i915_gem_object_unpin_map(ringbuf->obj); |
def0c5f6 | 2146 | else |
3d77e9be | 2147 | i915_vma_unpin_iomap(ringbuf->vma); |
8305216f | 2148 | ringbuf->virtual_start = NULL; |
3d77e9be | 2149 | |
2919d291 | 2150 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
3d77e9be | 2151 | ringbuf->vma = NULL; |
7ba717cf TD |
2152 | } |
2153 | ||
c033666a | 2154 | int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv, |
7ba717cf TD |
2155 | struct intel_ringbuffer *ringbuf) |
2156 | { | |
7ba717cf | 2157 | struct drm_i915_gem_object *obj = ringbuf->obj; |
a687a43a CW |
2158 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
2159 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 2160 | void *addr; |
7ba717cf TD |
2161 | int ret; |
2162 | ||
def0c5f6 | 2163 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
a687a43a | 2164 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
def0c5f6 CW |
2165 | if (ret) |
2166 | return ret; | |
7ba717cf | 2167 | |
def0c5f6 | 2168 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
2169 | if (ret) |
2170 | goto err_unpin; | |
def0c5f6 | 2171 | |
8305216f DG |
2172 | addr = i915_gem_object_pin_map(obj); |
2173 | if (IS_ERR(addr)) { | |
2174 | ret = PTR_ERR(addr); | |
d2cad535 | 2175 | goto err_unpin; |
def0c5f6 CW |
2176 | } |
2177 | } else { | |
a687a43a CW |
2178 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
2179 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
2180 | if (ret) |
2181 | return ret; | |
7ba717cf | 2182 | |
def0c5f6 | 2183 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2184 | if (ret) |
2185 | goto err_unpin; | |
def0c5f6 | 2186 | |
ff3dc087 DCS |
2187 | /* Access through the GTT requires the device to be awake. */ |
2188 | assert_rpm_wakelock_held(dev_priv); | |
2189 | ||
3d77e9be CW |
2190 | addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj)); |
2191 | if (IS_ERR(addr)) { | |
2192 | ret = PTR_ERR(addr); | |
d2cad535 | 2193 | goto err_unpin; |
def0c5f6 | 2194 | } |
7ba717cf TD |
2195 | } |
2196 | ||
8305216f | 2197 | ringbuf->virtual_start = addr; |
0eb973d3 | 2198 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
7ba717cf | 2199 | return 0; |
d2cad535 CW |
2200 | |
2201 | err_unpin: | |
2202 | i915_gem_object_ggtt_unpin(obj); | |
2203 | return ret; | |
7ba717cf TD |
2204 | } |
2205 | ||
01101fa7 | 2206 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
7ba717cf | 2207 | { |
2919d291 OM |
2208 | drm_gem_object_unreference(&ringbuf->obj->base); |
2209 | ringbuf->obj = NULL; | |
2210 | } | |
2211 | ||
01101fa7 CW |
2212 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
2213 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 2214 | { |
05394f39 | 2215 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2216 | |
ebc052e0 CW |
2217 | obj = NULL; |
2218 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 2219 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 2220 | if (obj == NULL) |
d37cd8a8 | 2221 | obj = i915_gem_object_create(dev, ringbuf->size); |
fe3db79b CW |
2222 | if (IS_ERR(obj)) |
2223 | return PTR_ERR(obj); | |
8187a2b7 | 2224 | |
24f3a8cf AG |
2225 | /* mark ring buffers as read-only from GPU side by default */ |
2226 | obj->gt_ro = 1; | |
2227 | ||
93b0a4e0 | 2228 | ringbuf->obj = obj; |
e3efda49 | 2229 | |
7ba717cf | 2230 | return 0; |
e3efda49 CW |
2231 | } |
2232 | ||
01101fa7 CW |
2233 | struct intel_ringbuffer * |
2234 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) | |
2235 | { | |
2236 | struct intel_ringbuffer *ring; | |
2237 | int ret; | |
2238 | ||
2239 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2240 | if (ring == NULL) { |
2241 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2242 | engine->name); | |
01101fa7 | 2243 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2244 | } |
01101fa7 | 2245 | |
4a570db5 | 2246 | ring->engine = engine; |
608c1a52 | 2247 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2248 | |
2249 | ring->size = size; | |
2250 | /* Workaround an erratum on the i830 which causes a hang if | |
2251 | * the TAIL pointer points to within the last 2 cachelines | |
2252 | * of the buffer. | |
2253 | */ | |
2254 | ring->effective_size = size; | |
c033666a | 2255 | if (IS_I830(engine->i915) || IS_845G(engine->i915)) |
01101fa7 CW |
2256 | ring->effective_size -= 2 * CACHELINE_BYTES; |
2257 | ||
2258 | ring->last_retired_head = -1; | |
2259 | intel_ring_update_space(ring); | |
2260 | ||
c033666a | 2261 | ret = intel_alloc_ringbuffer_obj(engine->i915->dev, ring); |
01101fa7 | 2262 | if (ret) { |
608c1a52 CW |
2263 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2264 | engine->name, ret); | |
2265 | list_del(&ring->link); | |
01101fa7 CW |
2266 | kfree(ring); |
2267 | return ERR_PTR(ret); | |
2268 | } | |
2269 | ||
2270 | return ring; | |
2271 | } | |
2272 | ||
2273 | void | |
2274 | intel_ringbuffer_free(struct intel_ringbuffer *ring) | |
2275 | { | |
2276 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2277 | list_del(&ring->link); |
01101fa7 CW |
2278 | kfree(ring); |
2279 | } | |
2280 | ||
0cb26a8e CW |
2281 | static int intel_ring_context_pin(struct i915_gem_context *ctx, |
2282 | struct intel_engine_cs *engine) | |
2283 | { | |
2284 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2285 | int ret; | |
2286 | ||
2287 | lockdep_assert_held(&ctx->i915->dev->struct_mutex); | |
2288 | ||
2289 | if (ce->pin_count++) | |
2290 | return 0; | |
2291 | ||
2292 | if (ce->state) { | |
2293 | ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0); | |
2294 | if (ret) | |
2295 | goto error; | |
2296 | } | |
2297 | ||
c7c3c07d CW |
2298 | /* The kernel context is only used as a placeholder for flushing the |
2299 | * active context. It is never used for submitting user rendering and | |
2300 | * as such never requires the golden render context, and so we can skip | |
2301 | * emitting it when we switch to the kernel context. This is required | |
2302 | * as during eviction we cannot allocate and pin the renderstate in | |
2303 | * order to initialise the context. | |
2304 | */ | |
2305 | if (ctx == ctx->i915->kernel_context) | |
2306 | ce->initialised = true; | |
2307 | ||
0cb26a8e CW |
2308 | i915_gem_context_reference(ctx); |
2309 | return 0; | |
2310 | ||
2311 | error: | |
2312 | ce->pin_count = 0; | |
2313 | return ret; | |
2314 | } | |
2315 | ||
2316 | static void intel_ring_context_unpin(struct i915_gem_context *ctx, | |
2317 | struct intel_engine_cs *engine) | |
2318 | { | |
2319 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2320 | ||
2321 | lockdep_assert_held(&ctx->i915->dev->struct_mutex); | |
2322 | ||
2323 | if (--ce->pin_count) | |
2324 | return; | |
2325 | ||
2326 | if (ce->state) | |
2327 | i915_gem_object_ggtt_unpin(ce->state); | |
2328 | ||
2329 | i915_gem_context_unreference(ctx); | |
2330 | } | |
2331 | ||
e3efda49 | 2332 | static int intel_init_ring_buffer(struct drm_device *dev, |
0bc40be8 | 2333 | struct intel_engine_cs *engine) |
e3efda49 | 2334 | { |
c033666a | 2335 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfc882b4 | 2336 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
2337 | int ret; |
2338 | ||
0bc40be8 | 2339 | WARN_ON(engine->buffer); |
bfc882b4 | 2340 | |
c033666a | 2341 | engine->i915 = dev_priv; |
0bc40be8 TU |
2342 | INIT_LIST_HEAD(&engine->active_list); |
2343 | INIT_LIST_HEAD(&engine->request_list); | |
2344 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2345 | INIT_LIST_HEAD(&engine->buffers); | |
2346 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2347 | memset(engine->semaphore.sync_seqno, 0, | |
2348 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2349 | |
688e6c72 CW |
2350 | ret = intel_engine_init_breadcrumbs(engine); |
2351 | if (ret) | |
2352 | goto error; | |
e3efda49 | 2353 | |
0cb26a8e CW |
2354 | /* We may need to do things with the shrinker which |
2355 | * require us to immediately switch back to the default | |
2356 | * context. This can cause a problem as pinning the | |
2357 | * default context also requires GTT space which may not | |
2358 | * be available. To avoid this we always pin the default | |
2359 | * context. | |
2360 | */ | |
2361 | ret = intel_ring_context_pin(dev_priv->kernel_context, engine); | |
2362 | if (ret) | |
2363 | goto error; | |
2364 | ||
0bc40be8 | 2365 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
b0366a54 DG |
2366 | if (IS_ERR(ringbuf)) { |
2367 | ret = PTR_ERR(ringbuf); | |
2368 | goto error; | |
2369 | } | |
0bc40be8 | 2370 | engine->buffer = ringbuf; |
01101fa7 | 2371 | |
c033666a | 2372 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2373 | ret = init_status_page(engine); |
e3efda49 | 2374 | if (ret) |
8ee14975 | 2375 | goto error; |
e3efda49 | 2376 | } else { |
0bc40be8 TU |
2377 | WARN_ON(engine->id != RCS); |
2378 | ret = init_phys_status_page(engine); | |
e3efda49 | 2379 | if (ret) |
8ee14975 | 2380 | goto error; |
e3efda49 CW |
2381 | } |
2382 | ||
c033666a | 2383 | ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf); |
bfc882b4 DV |
2384 | if (ret) { |
2385 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2386 | engine->name, ret); |
bfc882b4 DV |
2387 | intel_destroy_ringbuffer_obj(ringbuf); |
2388 | goto error; | |
e3efda49 | 2389 | } |
62fdfeaf | 2390 | |
0bc40be8 | 2391 | ret = i915_cmd_parser_init_ring(engine); |
44e895a8 | 2392 | if (ret) |
8ee14975 OM |
2393 | goto error; |
2394 | ||
8ee14975 | 2395 | return 0; |
351e3db2 | 2396 | |
8ee14975 | 2397 | error: |
117897f4 | 2398 | intel_cleanup_engine(engine); |
8ee14975 | 2399 | return ret; |
62fdfeaf EA |
2400 | } |
2401 | ||
117897f4 | 2402 | void intel_cleanup_engine(struct intel_engine_cs *engine) |
62fdfeaf | 2403 | { |
6402c330 | 2404 | struct drm_i915_private *dev_priv; |
33626e6a | 2405 | |
117897f4 | 2406 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2407 | return; |
2408 | ||
c033666a | 2409 | dev_priv = engine->i915; |
6402c330 | 2410 | |
0bc40be8 | 2411 | if (engine->buffer) { |
117897f4 | 2412 | intel_stop_engine(engine); |
c033666a | 2413 | WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2414 | |
0bc40be8 TU |
2415 | intel_unpin_ringbuffer_obj(engine->buffer); |
2416 | intel_ringbuffer_free(engine->buffer); | |
2417 | engine->buffer = NULL; | |
b0366a54 | 2418 | } |
78501eac | 2419 | |
0bc40be8 TU |
2420 | if (engine->cleanup) |
2421 | engine->cleanup(engine); | |
8d19215b | 2422 | |
c033666a | 2423 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2424 | cleanup_status_page(engine); |
7d3fdfff | 2425 | } else { |
0bc40be8 TU |
2426 | WARN_ON(engine->id != RCS); |
2427 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2428 | } |
44e895a8 | 2429 | |
0bc40be8 TU |
2430 | i915_cmd_parser_fini_ring(engine); |
2431 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
688e6c72 | 2432 | intel_engine_fini_breadcrumbs(engine); |
0cb26a8e CW |
2433 | |
2434 | intel_ring_context_unpin(dev_priv->kernel_context, engine); | |
2435 | ||
c033666a | 2436 | engine->i915 = NULL; |
62fdfeaf EA |
2437 | } |
2438 | ||
666796da | 2439 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2440 | { |
a4b3a571 | 2441 | struct drm_i915_gem_request *req; |
3e960501 | 2442 | |
3e960501 | 2443 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2444 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2445 | return 0; |
2446 | ||
0bc40be8 TU |
2447 | req = list_entry(engine->request_list.prev, |
2448 | struct drm_i915_gem_request, | |
2449 | list); | |
b4716185 CW |
2450 | |
2451 | /* Make sure we do not trigger any retires */ | |
2452 | return __i915_wait_request(req, | |
c19ae989 | 2453 | req->i915->mm.interruptible, |
b4716185 | 2454 | NULL, NULL); |
3e960501 CW |
2455 | } |
2456 | ||
6689cb2b | 2457 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2458 | { |
6310346e CW |
2459 | int ret; |
2460 | ||
2461 | /* Flush enough space to reduce the likelihood of waiting after | |
2462 | * we start building the request - in which case we will just | |
2463 | * have to repeat work. | |
2464 | */ | |
a0442461 | 2465 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2466 | |
4a570db5 | 2467 | request->ringbuf = request->engine->buffer; |
6310346e CW |
2468 | |
2469 | ret = intel_ring_begin(request, 0); | |
2470 | if (ret) | |
2471 | return ret; | |
2472 | ||
a0442461 | 2473 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2474 | return 0; |
9d773091 CW |
2475 | } |
2476 | ||
987046ad CW |
2477 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2478 | { | |
2479 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
2480 | struct intel_engine_cs *engine = req->engine; | |
2481 | struct drm_i915_gem_request *target; | |
2482 | ||
2483 | intel_ring_update_space(ringbuf); | |
2484 | if (ringbuf->space >= bytes) | |
2485 | return 0; | |
2486 | ||
2487 | /* | |
2488 | * Space is reserved in the ringbuffer for finalising the request, | |
2489 | * as that cannot be allowed to fail. During request finalisation, | |
2490 | * reserved_space is set to 0 to stop the overallocation and the | |
2491 | * assumption is that then we never need to wait (which has the | |
2492 | * risk of failing with EINTR). | |
2493 | * | |
2494 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2495 | */ | |
0251a963 | 2496 | GEM_BUG_ON(!req->reserved_space); |
987046ad CW |
2497 | |
2498 | list_for_each_entry(target, &engine->request_list, list) { | |
2499 | unsigned space; | |
2500 | ||
79bbcc29 | 2501 | /* |
987046ad CW |
2502 | * The request queue is per-engine, so can contain requests |
2503 | * from multiple ringbuffers. Here, we must ignore any that | |
2504 | * aren't from the ringbuffer we're considering. | |
79bbcc29 | 2505 | */ |
987046ad CW |
2506 | if (target->ringbuf != ringbuf) |
2507 | continue; | |
2508 | ||
2509 | /* Would completion of this request free enough space? */ | |
2510 | space = __intel_ring_space(target->postfix, ringbuf->tail, | |
2511 | ringbuf->size); | |
2512 | if (space >= bytes) | |
2513 | break; | |
79bbcc29 | 2514 | } |
29b1b415 | 2515 | |
987046ad CW |
2516 | if (WARN_ON(&target->list == &engine->request_list)) |
2517 | return -ENOSPC; | |
2518 | ||
2519 | return i915_wait_request(target); | |
29b1b415 JH |
2520 | } |
2521 | ||
987046ad | 2522 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2523 | { |
987046ad | 2524 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 | 2525 | int remain_actual = ringbuf->size - ringbuf->tail; |
987046ad CW |
2526 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
2527 | int bytes = num_dwords * sizeof(u32); | |
2528 | int total_bytes, wait_bytes; | |
79bbcc29 | 2529 | bool need_wrap = false; |
29b1b415 | 2530 | |
0251a963 | 2531 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2532 | |
79bbcc29 JH |
2533 | if (unlikely(bytes > remain_usable)) { |
2534 | /* | |
2535 | * Not enough space for the basic request. So need to flush | |
2536 | * out the remainder and then wait for base + reserved. | |
2537 | */ | |
2538 | wait_bytes = remain_actual + total_bytes; | |
2539 | need_wrap = true; | |
987046ad CW |
2540 | } else if (unlikely(total_bytes > remain_usable)) { |
2541 | /* | |
2542 | * The base request will fit but the reserved space | |
2543 | * falls off the end. So we don't need an immediate wrap | |
2544 | * and only need to effectively wait for the reserved | |
2545 | * size space from the start of ringbuffer. | |
2546 | */ | |
0251a963 | 2547 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2548 | } else { |
987046ad CW |
2549 | /* No wrapping required, just waiting. */ |
2550 | wait_bytes = total_bytes; | |
cbcc80df MK |
2551 | } |
2552 | ||
987046ad CW |
2553 | if (wait_bytes > ringbuf->space) { |
2554 | int ret = wait_for_space(req, wait_bytes); | |
cbcc80df MK |
2555 | if (unlikely(ret)) |
2556 | return ret; | |
79bbcc29 | 2557 | |
987046ad | 2558 | intel_ring_update_space(ringbuf); |
e075a32f CW |
2559 | if (unlikely(ringbuf->space < wait_bytes)) |
2560 | return -EAGAIN; | |
cbcc80df MK |
2561 | } |
2562 | ||
987046ad CW |
2563 | if (unlikely(need_wrap)) { |
2564 | GEM_BUG_ON(remain_actual > ringbuf->space); | |
2565 | GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size); | |
78501eac | 2566 | |
987046ad CW |
2567 | /* Fill the tail with MI_NOOP */ |
2568 | memset(ringbuf->virtual_start + ringbuf->tail, | |
2569 | 0, remain_actual); | |
2570 | ringbuf->tail = 0; | |
2571 | ringbuf->space -= remain_actual; | |
2572 | } | |
304d695c | 2573 | |
987046ad CW |
2574 | ringbuf->space -= bytes; |
2575 | GEM_BUG_ON(ringbuf->space < 0); | |
304d695c | 2576 | return 0; |
8187a2b7 | 2577 | } |
78501eac | 2578 | |
753b1ad4 | 2579 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2580 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2581 | { |
4a570db5 | 2582 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2583 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2584 | int ret; |
2585 | ||
2586 | if (num_dwords == 0) | |
2587 | return 0; | |
2588 | ||
18393f63 | 2589 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2590 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2591 | if (ret) |
2592 | return ret; | |
2593 | ||
2594 | while (num_dwords--) | |
e2f80391 | 2595 | intel_ring_emit(engine, MI_NOOP); |
753b1ad4 | 2596 | |
e2f80391 | 2597 | intel_ring_advance(engine); |
753b1ad4 VS |
2598 | |
2599 | return 0; | |
2600 | } | |
2601 | ||
0bc40be8 | 2602 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2603 | { |
c033666a | 2604 | struct drm_i915_private *dev_priv = engine->i915; |
498d2ac1 | 2605 | |
29dcb570 CW |
2606 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2607 | * so long as the semaphore value in the register/page is greater | |
2608 | * than the sync value), so whenever we reset the seqno, | |
2609 | * so long as we reset the tracking semaphore value to 0, it will | |
2610 | * always be before the next request's seqno. If we don't reset | |
2611 | * the semaphore value, then when the seqno moves backwards all | |
2612 | * future waits will complete instantly (causing rendering corruption). | |
2613 | */ | |
7e22dbbb | 2614 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
0bc40be8 TU |
2615 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2616 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2617 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2618 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2619 | } |
a058d934 CW |
2620 | if (dev_priv->semaphore_obj) { |
2621 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2622 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2623 | void *semaphores = kmap(page); | |
2624 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2625 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2626 | kunmap(page); | |
2627 | } | |
29dcb570 CW |
2628 | memset(engine->semaphore.sync_seqno, 0, |
2629 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2630 | |
1b7744e7 CW |
2631 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
2632 | if (engine->irq_seqno_barrier) | |
2633 | engine->irq_seqno_barrier(engine); | |
01347126 | 2634 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2635 | |
0bc40be8 | 2636 | engine->hangcheck.seqno = seqno; |
688e6c72 CW |
2637 | |
2638 | /* After manually advancing the seqno, fake the interrupt in case | |
2639 | * there are any waiters for that seqno. | |
2640 | */ | |
2641 | rcu_read_lock(); | |
2642 | intel_engine_wakeup(engine); | |
2643 | rcu_read_unlock(); | |
8187a2b7 | 2644 | } |
62fdfeaf | 2645 | |
0bc40be8 | 2646 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2647 | u32 value) |
881f47b6 | 2648 | { |
c033666a | 2649 | struct drm_i915_private *dev_priv = engine->i915; |
881f47b6 | 2650 | |
76f8421f CW |
2651 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2652 | ||
881f47b6 | 2653 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2654 | |
2655 | /* Disable notification that the ring is IDLE. The GT | |
2656 | * will then assume that it is busy and bring it out of rc6. | |
2657 | */ | |
76f8421f CW |
2658 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2659 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2660 | |
2661 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2662 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2663 | |
12f55818 | 2664 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
2665 | if (intel_wait_for_register_fw(dev_priv, |
2666 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2667 | GEN6_BSD_SLEEP_INDICATOR, | |
2668 | 0, | |
2669 | 50)) | |
12f55818 | 2670 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2671 | |
12f55818 | 2672 | /* Now that the ring is fully powered up, update the tail */ |
76f8421f CW |
2673 | I915_WRITE_FW(RING_TAIL(engine->mmio_base), value); |
2674 | POSTING_READ_FW(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2675 | |
2676 | /* Let the ring send IDLE messages to the GT again, | |
2677 | * and so let it sleep to conserve power when idle. | |
2678 | */ | |
76f8421f CW |
2679 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2680 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2681 | ||
2682 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2683 | } |
2684 | ||
a84c3ae1 | 2685 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2686 | u32 invalidate, u32 flush) |
881f47b6 | 2687 | { |
4a570db5 | 2688 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2689 | uint32_t cmd; |
b72f3acb CW |
2690 | int ret; |
2691 | ||
5fb9de1a | 2692 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2693 | if (ret) |
2694 | return ret; | |
2695 | ||
71a77e07 | 2696 | cmd = MI_FLUSH_DW; |
c033666a | 2697 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2698 | cmd += 1; |
f0a1fb10 CW |
2699 | |
2700 | /* We always require a command barrier so that subsequent | |
2701 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2702 | * wrt the contents of the write cache being flushed to memory | |
2703 | * (and thus being coherent from the CPU). | |
2704 | */ | |
2705 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2706 | ||
9a289771 JB |
2707 | /* |
2708 | * Bspec vol 1c.5 - video engine command streamer: | |
2709 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2710 | * operation is complete. This bit is only valid when the | |
2711 | * Post-Sync Operation field is a value of 1h or 3h." | |
2712 | */ | |
71a77e07 | 2713 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2714 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2715 | ||
e2f80391 TU |
2716 | intel_ring_emit(engine, cmd); |
2717 | intel_ring_emit(engine, | |
2718 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2719 | if (INTEL_GEN(req->i915) >= 8) { |
e2f80391 TU |
2720 | intel_ring_emit(engine, 0); /* upper addr */ |
2721 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2722 | } else { |
e2f80391 TU |
2723 | intel_ring_emit(engine, 0); |
2724 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2725 | } |
e2f80391 | 2726 | intel_ring_advance(engine); |
b72f3acb | 2727 | return 0; |
881f47b6 XH |
2728 | } |
2729 | ||
1c7a0623 | 2730 | static int |
53fddaf7 | 2731 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2732 | u64 offset, u32 len, |
8e004efc | 2733 | unsigned dispatch_flags) |
1c7a0623 | 2734 | { |
4a570db5 | 2735 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2736 | bool ppgtt = USES_PPGTT(engine->dev) && |
8e004efc | 2737 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2738 | int ret; |
2739 | ||
5fb9de1a | 2740 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2741 | if (ret) |
2742 | return ret; | |
2743 | ||
2744 | /* FIXME(BDW): Address space and security selectors. */ | |
e2f80391 | 2745 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2746 | (dispatch_flags & I915_DISPATCH_RS ? |
2747 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
e2f80391 TU |
2748 | intel_ring_emit(engine, lower_32_bits(offset)); |
2749 | intel_ring_emit(engine, upper_32_bits(offset)); | |
2750 | intel_ring_emit(engine, MI_NOOP); | |
2751 | intel_ring_advance(engine); | |
1c7a0623 BW |
2752 | |
2753 | return 0; | |
2754 | } | |
2755 | ||
d7d4eedd | 2756 | static int |
53fddaf7 | 2757 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2758 | u64 offset, u32 len, |
2759 | unsigned dispatch_flags) | |
d7d4eedd | 2760 | { |
4a570db5 | 2761 | struct intel_engine_cs *engine = req->engine; |
d7d4eedd CW |
2762 | int ret; |
2763 | ||
5fb9de1a | 2764 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2765 | if (ret) |
2766 | return ret; | |
2767 | ||
e2f80391 | 2768 | intel_ring_emit(engine, |
77072258 | 2769 | MI_BATCH_BUFFER_START | |
8e004efc | 2770 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2771 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2772 | (dispatch_flags & I915_DISPATCH_RS ? | |
2773 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2774 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2775 | intel_ring_emit(engine, offset); |
2776 | intel_ring_advance(engine); | |
d7d4eedd CW |
2777 | |
2778 | return 0; | |
2779 | } | |
2780 | ||
881f47b6 | 2781 | static int |
53fddaf7 | 2782 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2783 | u64 offset, u32 len, |
8e004efc | 2784 | unsigned dispatch_flags) |
881f47b6 | 2785 | { |
4a570db5 | 2786 | struct intel_engine_cs *engine = req->engine; |
0206e353 | 2787 | int ret; |
ab6f8e32 | 2788 | |
5fb9de1a | 2789 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2790 | if (ret) |
2791 | return ret; | |
e1f99ce6 | 2792 | |
e2f80391 | 2793 | intel_ring_emit(engine, |
d7d4eedd | 2794 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2795 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2796 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2797 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2798 | intel_ring_emit(engine, offset); |
2799 | intel_ring_advance(engine); | |
ab6f8e32 | 2800 | |
0206e353 | 2801 | return 0; |
881f47b6 XH |
2802 | } |
2803 | ||
549f7365 CW |
2804 | /* Blitter support (SandyBridge+) */ |
2805 | ||
a84c3ae1 | 2806 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2807 | u32 invalidate, u32 flush) |
8d19215b | 2808 | { |
4a570db5 | 2809 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2810 | uint32_t cmd; |
b72f3acb CW |
2811 | int ret; |
2812 | ||
5fb9de1a | 2813 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2814 | if (ret) |
2815 | return ret; | |
2816 | ||
71a77e07 | 2817 | cmd = MI_FLUSH_DW; |
c033666a | 2818 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2819 | cmd += 1; |
f0a1fb10 CW |
2820 | |
2821 | /* We always require a command barrier so that subsequent | |
2822 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2823 | * wrt the contents of the write cache being flushed to memory | |
2824 | * (and thus being coherent from the CPU). | |
2825 | */ | |
2826 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2827 | ||
9a289771 JB |
2828 | /* |
2829 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2830 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2831 | * operation is complete. This bit is only valid when the | |
2832 | * Post-Sync Operation field is a value of 1h or 3h." | |
2833 | */ | |
71a77e07 | 2834 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2835 | cmd |= MI_INVALIDATE_TLB; |
e2f80391 TU |
2836 | intel_ring_emit(engine, cmd); |
2837 | intel_ring_emit(engine, | |
2838 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2839 | if (INTEL_GEN(req->i915) >= 8) { |
e2f80391 TU |
2840 | intel_ring_emit(engine, 0); /* upper addr */ |
2841 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2842 | } else { |
e2f80391 TU |
2843 | intel_ring_emit(engine, 0); |
2844 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2845 | } |
e2f80391 | 2846 | intel_ring_advance(engine); |
fd3da6c9 | 2847 | |
b72f3acb | 2848 | return 0; |
8d19215b ZN |
2849 | } |
2850 | ||
d9a64610 TU |
2851 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
2852 | struct intel_engine_cs *engine) | |
2853 | { | |
db3d4019 | 2854 | struct drm_i915_gem_object *obj; |
1b9e6650 | 2855 | int ret, i; |
db3d4019 TU |
2856 | |
2857 | if (!i915_semaphore_is_enabled(dev_priv)) | |
2858 | return; | |
2859 | ||
2860 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) { | |
2861 | obj = i915_gem_object_create(dev_priv->dev, 4096); | |
2862 | if (IS_ERR(obj)) { | |
2863 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2864 | i915.semaphores = 0; | |
2865 | } else { | |
2866 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2867 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2868 | if (ret != 0) { | |
2869 | drm_gem_object_unreference(&obj->base); | |
2870 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2871 | i915.semaphores = 0; | |
2872 | } else { | |
2873 | dev_priv->semaphore_obj = obj; | |
2874 | } | |
2875 | } | |
2876 | } | |
2877 | ||
d9a64610 TU |
2878 | if (!i915_semaphore_is_enabled(dev_priv)) |
2879 | return; | |
2880 | ||
2881 | if (INTEL_GEN(dev_priv) >= 8) { | |
1b9e6650 TU |
2882 | u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj); |
2883 | ||
d9a64610 TU |
2884 | engine->semaphore.sync_to = gen8_ring_sync; |
2885 | engine->semaphore.signal = gen8_xcs_signal; | |
1b9e6650 TU |
2886 | |
2887 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2888 | u64 ring_offset; | |
2889 | ||
2890 | if (i != engine->id) | |
2891 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
2892 | else | |
2893 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
2894 | ||
2895 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
2896 | } | |
d9a64610 TU |
2897 | } else if (INTEL_GEN(dev_priv) >= 6) { |
2898 | engine->semaphore.sync_to = gen6_ring_sync; | |
2899 | engine->semaphore.signal = gen6_signal; | |
4b8e38a9 TU |
2900 | |
2901 | /* | |
2902 | * The current semaphore is only applied on pre-gen8 | |
2903 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2904 | * platform. So the semaphore between RCS and VCS2 is | |
2905 | * initialized as INVALID. Gen8 will initialize the | |
2906 | * sema between VCS2 and RCS later. | |
2907 | */ | |
2908 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2909 | static const struct { | |
2910 | u32 wait_mbox; | |
2911 | i915_reg_t mbox_reg; | |
2912 | } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { | |
2913 | [RCS] = { | |
2914 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2915 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2916 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
2917 | }, | |
2918 | [VCS] = { | |
2919 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2920 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2921 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
2922 | }, | |
2923 | [BCS] = { | |
2924 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2925 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2926 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
2927 | }, | |
2928 | [VECS] = { | |
2929 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2930 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2931 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
2932 | }, | |
2933 | }; | |
2934 | u32 wait_mbox; | |
2935 | i915_reg_t mbox_reg; | |
2936 | ||
2937 | if (i == engine->id || i == VCS2) { | |
2938 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; | |
2939 | mbox_reg = GEN6_NOSYNC; | |
2940 | } else { | |
2941 | wait_mbox = sem_data[engine->id][i].wait_mbox; | |
2942 | mbox_reg = sem_data[engine->id][i].mbox_reg; | |
2943 | } | |
2944 | ||
2945 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2946 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2947 | } | |
d9a64610 TU |
2948 | } |
2949 | } | |
2950 | ||
ed003078 CW |
2951 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2952 | struct intel_engine_cs *engine) | |
2953 | { | |
2954 | if (INTEL_GEN(dev_priv) >= 8) { | |
2955 | engine->irq_get = gen8_ring_get_irq; | |
2956 | engine->irq_put = gen8_ring_put_irq; | |
2957 | engine->irq_seqno_barrier = gen6_seqno_barrier; | |
2958 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
2959 | engine->irq_get = gen6_ring_get_irq; | |
2960 | engine->irq_put = gen6_ring_put_irq; | |
2961 | engine->irq_seqno_barrier = gen6_seqno_barrier; | |
2962 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
2963 | engine->irq_get = gen5_ring_get_irq; | |
2964 | engine->irq_put = gen5_ring_put_irq; | |
2965 | } else if (INTEL_GEN(dev_priv) >= 3) { | |
2966 | engine->irq_get = i9xx_ring_get_irq; | |
2967 | engine->irq_put = i9xx_ring_put_irq; | |
2968 | } else { | |
2969 | engine->irq_get = i8xx_ring_get_irq; | |
2970 | engine->irq_put = i8xx_ring_put_irq; | |
2971 | } | |
2972 | } | |
2973 | ||
06a2fe22 TU |
2974 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2975 | struct intel_engine_cs *engine) | |
2976 | { | |
1d8a1337 | 2977 | engine->init_hw = init_ring_common; |
06a2fe22 | 2978 | engine->write_tail = ring_write_tail; |
7445a2a4 | 2979 | |
6f7bef75 CW |
2980 | engine->add_request = i9xx_add_request; |
2981 | if (INTEL_GEN(dev_priv) >= 6) | |
960ecaad | 2982 | engine->add_request = gen6_add_request; |
6f7bef75 CW |
2983 | |
2984 | if (INTEL_GEN(dev_priv) >= 8) | |
2985 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
2986 | else if (INTEL_GEN(dev_priv) >= 6) | |
960ecaad | 2987 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
6f7bef75 | 2988 | else if (INTEL_GEN(dev_priv) >= 4) |
960ecaad | 2989 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
6f7bef75 CW |
2990 | else if (IS_I830(dev_priv) || IS_845G(dev_priv)) |
2991 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2992 | else | |
2993 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; | |
b9700325 | 2994 | |
ed003078 | 2995 | intel_ring_init_irq(dev_priv, engine); |
d9a64610 | 2996 | intel_ring_init_semaphores(dev_priv, engine); |
06a2fe22 TU |
2997 | } |
2998 | ||
5c1143bb XH |
2999 | int intel_init_render_ring_buffer(struct drm_device *dev) |
3000 | { | |
4640c4ff | 3001 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3002 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
3e78998a BW |
3003 | struct drm_i915_gem_object *obj; |
3004 | int ret; | |
5c1143bb | 3005 | |
e2f80391 TU |
3006 | engine->name = "render ring"; |
3007 | engine->id = RCS; | |
3008 | engine->exec_id = I915_EXEC_RENDER; | |
215a7e32 | 3009 | engine->hw_id = 0; |
e2f80391 | 3010 | engine->mmio_base = RENDER_RING_BASE; |
59465b5f | 3011 | |
06a2fe22 TU |
3012 | intel_ring_default_vfuncs(dev_priv, engine); |
3013 | ||
c033666a | 3014 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 3015 | engine->init_context = intel_rcs_ctx_init; |
a58c01aa | 3016 | engine->add_request = gen8_render_add_request; |
e2f80391 | 3017 | engine->flush = gen8_render_ring_flush; |
e2f80391 | 3018 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
db3d4019 | 3019 | if (i915_semaphore_is_enabled(dev_priv)) |
e2f80391 | 3020 | engine->semaphore.signal = gen8_rcs_signal; |
c033666a | 3021 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 3022 | engine->init_context = intel_rcs_ctx_init; |
e2f80391 | 3023 | engine->flush = gen7_render_ring_flush; |
c033666a | 3024 | if (IS_GEN6(dev_priv)) |
e2f80391 | 3025 | engine->flush = gen6_render_ring_flush; |
e2f80391 | 3026 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
c033666a | 3027 | } else if (IS_GEN5(dev_priv)) { |
e2f80391 TU |
3028 | engine->add_request = pc_render_add_request; |
3029 | engine->flush = gen4_render_ring_flush; | |
e2f80391 | 3030 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
cc609d5d | 3031 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
59465b5f | 3032 | } else { |
c033666a | 3033 | if (INTEL_GEN(dev_priv) < 4) |
e2f80391 | 3034 | engine->flush = gen2_render_ring_flush; |
46f0f8d1 | 3035 | else |
e2f80391 | 3036 | engine->flush = gen4_render_ring_flush; |
e2f80391 | 3037 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 3038 | } |
707d9cf9 | 3039 | |
c033666a | 3040 | if (IS_HASWELL(dev_priv)) |
e2f80391 | 3041 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
6f7bef75 | 3042 | |
e2f80391 TU |
3043 | engine->init_hw = init_render_ring; |
3044 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 3045 | |
b45305fc | 3046 | /* Workaround batchbuffer to combat CS tlb bug. */ |
c033666a | 3047 | if (HAS_BROKEN_CS_TLB(dev_priv)) { |
d37cd8a8 | 3048 | obj = i915_gem_object_create(dev, I830_WA_SIZE); |
fe3db79b | 3049 | if (IS_ERR(obj)) { |
b45305fc | 3050 | DRM_ERROR("Failed to allocate batch bo\n"); |
fe3db79b | 3051 | return PTR_ERR(obj); |
b45305fc DV |
3052 | } |
3053 | ||
be1fa129 | 3054 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
3055 | if (ret != 0) { |
3056 | drm_gem_object_unreference(&obj->base); | |
3057 | DRM_ERROR("Failed to ping batch bo\n"); | |
3058 | return ret; | |
3059 | } | |
3060 | ||
e2f80391 TU |
3061 | engine->scratch.obj = obj; |
3062 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
3063 | } |
3064 | ||
e2f80391 | 3065 | ret = intel_init_ring_buffer(dev, engine); |
99be1dfe DV |
3066 | if (ret) |
3067 | return ret; | |
3068 | ||
c033666a | 3069 | if (INTEL_GEN(dev_priv) >= 5) { |
e2f80391 | 3070 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
3071 | if (ret) |
3072 | return ret; | |
3073 | } | |
3074 | ||
3075 | return 0; | |
5c1143bb XH |
3076 | } |
3077 | ||
3078 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
3079 | { | |
4640c4ff | 3080 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3081 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
5c1143bb | 3082 | |
e2f80391 TU |
3083 | engine->name = "bsd ring"; |
3084 | engine->id = VCS; | |
3085 | engine->exec_id = I915_EXEC_BSD; | |
215a7e32 | 3086 | engine->hw_id = 1; |
58fa3835 | 3087 | |
06a2fe22 TU |
3088 | intel_ring_default_vfuncs(dev_priv, engine); |
3089 | ||
c033666a | 3090 | if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 3091 | engine->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 | 3092 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 3093 | if (IS_GEN6(dev_priv)) |
e2f80391 TU |
3094 | engine->write_tail = gen6_bsd_ring_write_tail; |
3095 | engine->flush = gen6_bsd_ring_flush; | |
8d228911 | 3096 | if (INTEL_GEN(dev_priv) >= 8) |
e2f80391 | 3097 | engine->irq_enable_mask = |
abd58f01 | 3098 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
8d228911 | 3099 | else |
e2f80391 | 3100 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 3101 | } else { |
e2f80391 TU |
3102 | engine->mmio_base = BSD_RING_BASE; |
3103 | engine->flush = bsd_ring_flush; | |
8d228911 | 3104 | if (IS_GEN5(dev_priv)) |
e2f80391 | 3105 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 3106 | else |
e2f80391 | 3107 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 3108 | } |
58fa3835 | 3109 | |
e2f80391 | 3110 | return intel_init_ring_buffer(dev, engine); |
5c1143bb | 3111 | } |
549f7365 | 3112 | |
845f74a7 | 3113 | /** |
62659920 | 3114 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
3115 | */ |
3116 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
3117 | { | |
3118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 3119 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
e2f80391 TU |
3120 | |
3121 | engine->name = "bsd2 ring"; | |
3122 | engine->id = VCS2; | |
3123 | engine->exec_id = I915_EXEC_BSD; | |
215a7e32 | 3124 | engine->hw_id = 4; |
e2f80391 | 3125 | engine->mmio_base = GEN8_BSD2_RING_BASE; |
06a2fe22 TU |
3126 | |
3127 | intel_ring_default_vfuncs(dev_priv, engine); | |
3128 | ||
e2f80391 | 3129 | engine->flush = gen6_bsd_ring_flush; |
e2f80391 | 3130 | engine->irq_enable_mask = |
845f74a7 | 3131 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
845f74a7 | 3132 | |
e2f80391 | 3133 | return intel_init_ring_buffer(dev, engine); |
845f74a7 ZY |
3134 | } |
3135 | ||
549f7365 CW |
3136 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
3137 | { | |
4640c4ff | 3138 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3139 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
e2f80391 TU |
3140 | |
3141 | engine->name = "blitter ring"; | |
3142 | engine->id = BCS; | |
3143 | engine->exec_id = I915_EXEC_BLT; | |
215a7e32 | 3144 | engine->hw_id = 2; |
e2f80391 | 3145 | engine->mmio_base = BLT_RING_BASE; |
06a2fe22 TU |
3146 | |
3147 | intel_ring_default_vfuncs(dev_priv, engine); | |
3148 | ||
e2f80391 | 3149 | engine->flush = gen6_ring_flush; |
8d228911 | 3150 | if (INTEL_GEN(dev_priv) >= 8) |
e2f80391 | 3151 | engine->irq_enable_mask = |
abd58f01 | 3152 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
8d228911 | 3153 | else |
e2f80391 | 3154 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 3155 | |
e2f80391 | 3156 | return intel_init_ring_buffer(dev, engine); |
549f7365 | 3157 | } |
a7b9761d | 3158 | |
9a8a2213 BW |
3159 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
3160 | { | |
4640c4ff | 3161 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3162 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
9a8a2213 | 3163 | |
e2f80391 TU |
3164 | engine->name = "video enhancement ring"; |
3165 | engine->id = VECS; | |
3166 | engine->exec_id = I915_EXEC_VEBOX; | |
215a7e32 | 3167 | engine->hw_id = 3; |
e2f80391 | 3168 | engine->mmio_base = VEBOX_RING_BASE; |
06a2fe22 TU |
3169 | |
3170 | intel_ring_default_vfuncs(dev_priv, engine); | |
3171 | ||
e2f80391 | 3172 | engine->flush = gen6_ring_flush; |
abd58f01 | 3173 | |
c033666a | 3174 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 3175 | engine->irq_enable_mask = |
40c499f9 | 3176 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 | 3177 | } else { |
e2f80391 TU |
3178 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
3179 | engine->irq_get = hsw_vebox_get_irq; | |
3180 | engine->irq_put = hsw_vebox_put_irq; | |
abd58f01 | 3181 | } |
9a8a2213 | 3182 | |
e2f80391 | 3183 | return intel_init_ring_buffer(dev, engine); |
9a8a2213 BW |
3184 | } |
3185 | ||
a7b9761d | 3186 | int |
4866d729 | 3187 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3188 | { |
4a570db5 | 3189 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3190 | int ret; |
3191 | ||
e2f80391 | 3192 | if (!engine->gpu_caches_dirty) |
a7b9761d CW |
3193 | return 0; |
3194 | ||
e2f80391 | 3195 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3196 | if (ret) |
3197 | return ret; | |
3198 | ||
a84c3ae1 | 3199 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d | 3200 | |
e2f80391 | 3201 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3202 | return 0; |
3203 | } | |
3204 | ||
3205 | int | |
2f20055d | 3206 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3207 | { |
4a570db5 | 3208 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3209 | uint32_t flush_domains; |
3210 | int ret; | |
3211 | ||
3212 | flush_domains = 0; | |
e2f80391 | 3213 | if (engine->gpu_caches_dirty) |
a7b9761d CW |
3214 | flush_domains = I915_GEM_GPU_DOMAINS; |
3215 | ||
e2f80391 | 3216 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3217 | if (ret) |
3218 | return ret; | |
3219 | ||
a84c3ae1 | 3220 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d | 3221 | |
e2f80391 | 3222 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3223 | return 0; |
3224 | } | |
e3efda49 CW |
3225 | |
3226 | void | |
117897f4 | 3227 | intel_stop_engine(struct intel_engine_cs *engine) |
e3efda49 CW |
3228 | { |
3229 | int ret; | |
3230 | ||
117897f4 | 3231 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
3232 | return; |
3233 | ||
666796da | 3234 | ret = intel_engine_idle(engine); |
f4457ae7 | 3235 | if (ret) |
e3efda49 | 3236 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 3237 | engine->name, ret); |
e3efda49 | 3238 | |
0bc40be8 | 3239 | stop_ring(engine); |
e3efda49 | 3240 | } |