Commit | Line | Data |
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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
c7dca47b CW |
37 | static inline int ring_space(struct intel_ring_buffer *ring) |
38 | { | |
39 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); | |
40 | if (space < 0) | |
41 | space += ring->size; | |
42 | return space; | |
43 | } | |
44 | ||
6f392d54 CW |
45 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
46 | { | |
47 | drm_i915_private_t *dev_priv = dev->dev_private; | |
48 | u32 seqno; | |
49 | ||
50 | seqno = dev_priv->next_seqno; | |
51 | ||
52 | /* reserve 0 for non-seqno */ | |
53 | if (++dev_priv->next_seqno == 0) | |
54 | dev_priv->next_seqno = 1; | |
55 | ||
56 | return seqno; | |
57 | } | |
58 | ||
b72f3acb | 59 | static int |
78501eac | 60 | render_ring_flush(struct intel_ring_buffer *ring, |
ab6f8e32 CW |
61 | u32 invalidate_domains, |
62 | u32 flush_domains) | |
62fdfeaf | 63 | { |
78501eac | 64 | struct drm_device *dev = ring->dev; |
6f392d54 | 65 | u32 cmd; |
b72f3acb | 66 | int ret; |
6f392d54 | 67 | |
36d527de CW |
68 | /* |
69 | * read/write caches: | |
70 | * | |
71 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
72 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
73 | * also flushed at 2d versus 3d pipeline switches. | |
74 | * | |
75 | * read-only caches: | |
76 | * | |
77 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
78 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
79 | * | |
80 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
81 | * | |
82 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
83 | * invalidated when MI_EXE_FLUSH is set. | |
84 | * | |
85 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
86 | * invalidated with every MI_FLUSH. | |
87 | * | |
88 | * TLBs: | |
89 | * | |
90 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
91 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
92 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
93 | * are flushed at any MI_FLUSH. | |
94 | */ | |
95 | ||
96 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
97 | if ((invalidate_domains|flush_domains) & | |
98 | I915_GEM_DOMAIN_RENDER) | |
99 | cmd &= ~MI_NO_WRITE_FLUSH; | |
100 | if (INTEL_INFO(dev)->gen < 4) { | |
62fdfeaf | 101 | /* |
36d527de CW |
102 | * On the 965, the sampler cache always gets flushed |
103 | * and this bit is reserved. | |
62fdfeaf | 104 | */ |
36d527de CW |
105 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
106 | cmd |= MI_READ_FLUSH; | |
107 | } | |
108 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
109 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 110 | |
36d527de CW |
111 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
112 | (IS_G4X(dev) || IS_GEN5(dev))) | |
113 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 114 | |
36d527de CW |
115 | ret = intel_ring_begin(ring, 2); |
116 | if (ret) | |
117 | return ret; | |
b72f3acb | 118 | |
36d527de CW |
119 | intel_ring_emit(ring, cmd); |
120 | intel_ring_emit(ring, MI_NOOP); | |
121 | intel_ring_advance(ring); | |
b72f3acb CW |
122 | |
123 | return 0; | |
8187a2b7 ZN |
124 | } |
125 | ||
78501eac | 126 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 127 | u32 value) |
d46eefa2 | 128 | { |
78501eac | 129 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 130 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
131 | } |
132 | ||
78501eac | 133 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 134 | { |
78501eac CW |
135 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
136 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 137 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
138 | |
139 | return I915_READ(acthd_reg); | |
140 | } | |
141 | ||
78501eac | 142 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 143 | { |
78501eac | 144 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
05394f39 | 145 | struct drm_i915_gem_object *obj = ring->obj; |
8187a2b7 | 146 | u32 head; |
8187a2b7 ZN |
147 | |
148 | /* Stop the ring if it's running. */ | |
7f2ab699 | 149 | I915_WRITE_CTL(ring, 0); |
570ef608 | 150 | I915_WRITE_HEAD(ring, 0); |
78501eac | 151 | ring->write_tail(ring, 0); |
8187a2b7 ZN |
152 | |
153 | /* Initialize the ring. */ | |
05394f39 | 154 | I915_WRITE_START(ring, obj->gtt_offset); |
570ef608 | 155 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
156 | |
157 | /* G45 ring initialization fails to reset head to zero */ | |
158 | if (head != 0) { | |
6fd0d56e CW |
159 | DRM_DEBUG_KMS("%s head not reset to zero " |
160 | "ctl %08x head %08x tail %08x start %08x\n", | |
161 | ring->name, | |
162 | I915_READ_CTL(ring), | |
163 | I915_READ_HEAD(ring), | |
164 | I915_READ_TAIL(ring), | |
165 | I915_READ_START(ring)); | |
8187a2b7 | 166 | |
570ef608 | 167 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 168 | |
6fd0d56e CW |
169 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
170 | DRM_ERROR("failed to set %s head to zero " | |
171 | "ctl %08x head %08x tail %08x start %08x\n", | |
172 | ring->name, | |
173 | I915_READ_CTL(ring), | |
174 | I915_READ_HEAD(ring), | |
175 | I915_READ_TAIL(ring), | |
176 | I915_READ_START(ring)); | |
177 | } | |
8187a2b7 ZN |
178 | } |
179 | ||
7f2ab699 | 180 | I915_WRITE_CTL(ring, |
ae69b42a | 181 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
6aa56062 | 182 | | RING_REPORT_64K | RING_VALID); |
8187a2b7 | 183 | |
8187a2b7 | 184 | /* If the head is still not zero, the ring is dead */ |
176f28eb | 185 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
05394f39 | 186 | I915_READ_START(ring) != obj->gtt_offset || |
176f28eb | 187 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
e74cfed5 CW |
188 | DRM_ERROR("%s initialization failed " |
189 | "ctl %08x head %08x tail %08x start %08x\n", | |
190 | ring->name, | |
191 | I915_READ_CTL(ring), | |
192 | I915_READ_HEAD(ring), | |
193 | I915_READ_TAIL(ring), | |
194 | I915_READ_START(ring)); | |
195 | return -EIO; | |
8187a2b7 ZN |
196 | } |
197 | ||
78501eac CW |
198 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
199 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 200 | else { |
c7dca47b | 201 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 202 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 203 | ring->space = ring_space(ring); |
8187a2b7 | 204 | } |
1ec14ad3 | 205 | |
8187a2b7 ZN |
206 | return 0; |
207 | } | |
208 | ||
c6df541c CW |
209 | /* |
210 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
211 | * over cache flushing. | |
212 | */ | |
213 | struct pipe_control { | |
214 | struct drm_i915_gem_object *obj; | |
215 | volatile u32 *cpu_page; | |
216 | u32 gtt_offset; | |
217 | }; | |
218 | ||
219 | static int | |
220 | init_pipe_control(struct intel_ring_buffer *ring) | |
221 | { | |
222 | struct pipe_control *pc; | |
223 | struct drm_i915_gem_object *obj; | |
224 | int ret; | |
225 | ||
226 | if (ring->private) | |
227 | return 0; | |
228 | ||
229 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); | |
230 | if (!pc) | |
231 | return -ENOMEM; | |
232 | ||
233 | obj = i915_gem_alloc_object(ring->dev, 4096); | |
234 | if (obj == NULL) { | |
235 | DRM_ERROR("Failed to allocate seqno page\n"); | |
236 | ret = -ENOMEM; | |
237 | goto err; | |
238 | } | |
e4ffd173 CW |
239 | |
240 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
c6df541c CW |
241 | |
242 | ret = i915_gem_object_pin(obj, 4096, true); | |
243 | if (ret) | |
244 | goto err_unref; | |
245 | ||
246 | pc->gtt_offset = obj->gtt_offset; | |
247 | pc->cpu_page = kmap(obj->pages[0]); | |
248 | if (pc->cpu_page == NULL) | |
249 | goto err_unpin; | |
250 | ||
251 | pc->obj = obj; | |
252 | ring->private = pc; | |
253 | return 0; | |
254 | ||
255 | err_unpin: | |
256 | i915_gem_object_unpin(obj); | |
257 | err_unref: | |
258 | drm_gem_object_unreference(&obj->base); | |
259 | err: | |
260 | kfree(pc); | |
261 | return ret; | |
262 | } | |
263 | ||
264 | static void | |
265 | cleanup_pipe_control(struct intel_ring_buffer *ring) | |
266 | { | |
267 | struct pipe_control *pc = ring->private; | |
268 | struct drm_i915_gem_object *obj; | |
269 | ||
270 | if (!ring->private) | |
271 | return; | |
272 | ||
273 | obj = pc->obj; | |
274 | kunmap(obj->pages[0]); | |
275 | i915_gem_object_unpin(obj); | |
276 | drm_gem_object_unreference(&obj->base); | |
277 | ||
278 | kfree(pc); | |
279 | ring->private = NULL; | |
280 | } | |
281 | ||
78501eac | 282 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 283 | { |
78501eac | 284 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 285 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 286 | int ret = init_ring_common(ring); |
a69ffdbf | 287 | |
a6c45cf0 | 288 | if (INTEL_INFO(dev)->gen > 3) { |
78501eac | 289 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
65d3eb1e | 290 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
a69ffdbf ZW |
291 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; |
292 | I915_WRITE(MI_MODE, mode); | |
b095cd0a JB |
293 | if (IS_GEN7(dev)) |
294 | I915_WRITE(GFX_MODE_GEN7, | |
295 | GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | | |
296 | GFX_MODE_ENABLE(GFX_REPLAY_MODE)); | |
8187a2b7 | 297 | } |
78501eac | 298 | |
c6df541c CW |
299 | if (INTEL_INFO(dev)->gen >= 6) { |
300 | } else if (IS_GEN5(dev)) { | |
301 | ret = init_pipe_control(ring); | |
302 | if (ret) | |
303 | return ret; | |
304 | } | |
305 | ||
8187a2b7 ZN |
306 | return ret; |
307 | } | |
308 | ||
c6df541c CW |
309 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
310 | { | |
311 | if (!ring->private) | |
312 | return; | |
313 | ||
314 | cleanup_pipe_control(ring); | |
315 | } | |
316 | ||
1ec14ad3 | 317 | static void |
c8c99b0f BW |
318 | update_mboxes(struct intel_ring_buffer *ring, |
319 | u32 seqno, | |
320 | u32 mmio_offset) | |
1ec14ad3 | 321 | { |
c8c99b0f BW |
322 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
323 | MI_SEMAPHORE_GLOBAL_GTT | | |
324 | MI_SEMAPHORE_REGISTER | | |
325 | MI_SEMAPHORE_UPDATE); | |
1ec14ad3 | 326 | intel_ring_emit(ring, seqno); |
c8c99b0f | 327 | intel_ring_emit(ring, mmio_offset); |
1ec14ad3 CW |
328 | } |
329 | ||
c8c99b0f BW |
330 | /** |
331 | * gen6_add_request - Update the semaphore mailbox registers | |
332 | * | |
333 | * @ring - ring that is adding a request | |
334 | * @seqno - return seqno stuck into the ring | |
335 | * | |
336 | * Update the mailbox registers in the *other* rings with the current seqno. | |
337 | * This acts like a signal in the canonical semaphore. | |
338 | */ | |
1ec14ad3 CW |
339 | static int |
340 | gen6_add_request(struct intel_ring_buffer *ring, | |
c8c99b0f | 341 | u32 *seqno) |
1ec14ad3 | 342 | { |
c8c99b0f BW |
343 | u32 mbox1_reg; |
344 | u32 mbox2_reg; | |
1ec14ad3 CW |
345 | int ret; |
346 | ||
347 | ret = intel_ring_begin(ring, 10); | |
348 | if (ret) | |
349 | return ret; | |
350 | ||
c8c99b0f BW |
351 | mbox1_reg = ring->signal_mbox[0]; |
352 | mbox2_reg = ring->signal_mbox[1]; | |
1ec14ad3 | 353 | |
c8c99b0f BW |
354 | *seqno = i915_gem_get_seqno(ring->dev); |
355 | ||
356 | update_mboxes(ring, *seqno, mbox1_reg); | |
357 | update_mboxes(ring, *seqno, mbox2_reg); | |
1ec14ad3 CW |
358 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
359 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
c8c99b0f | 360 | intel_ring_emit(ring, *seqno); |
1ec14ad3 CW |
361 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
362 | intel_ring_advance(ring); | |
363 | ||
1ec14ad3 CW |
364 | return 0; |
365 | } | |
366 | ||
c8c99b0f BW |
367 | /** |
368 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
369 | * | |
370 | * @waiter - ring that is waiting | |
371 | * @signaller - ring which has, or will signal | |
372 | * @seqno - seqno which the waiter will block on | |
373 | */ | |
374 | static int | |
375 | intel_ring_sync(struct intel_ring_buffer *waiter, | |
376 | struct intel_ring_buffer *signaller, | |
377 | int ring, | |
1ec14ad3 CW |
378 | u32 seqno) |
379 | { | |
380 | int ret; | |
c8c99b0f BW |
381 | u32 dw1 = MI_SEMAPHORE_MBOX | |
382 | MI_SEMAPHORE_COMPARE | | |
383 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 384 | |
c8c99b0f | 385 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
386 | if (ret) |
387 | return ret; | |
388 | ||
c8c99b0f BW |
389 | intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]); |
390 | intel_ring_emit(waiter, seqno); | |
391 | intel_ring_emit(waiter, 0); | |
392 | intel_ring_emit(waiter, MI_NOOP); | |
393 | intel_ring_advance(waiter); | |
1ec14ad3 CW |
394 | |
395 | return 0; | |
396 | } | |
397 | ||
c8c99b0f BW |
398 | /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */ |
399 | int | |
400 | render_ring_sync_to(struct intel_ring_buffer *waiter, | |
401 | struct intel_ring_buffer *signaller, | |
402 | u32 seqno) | |
403 | { | |
404 | WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID); | |
405 | return intel_ring_sync(waiter, | |
406 | signaller, | |
407 | RCS, | |
408 | seqno); | |
409 | } | |
410 | ||
411 | /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */ | |
412 | int | |
413 | gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter, | |
414 | struct intel_ring_buffer *signaller, | |
415 | u32 seqno) | |
416 | { | |
417 | WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID); | |
418 | return intel_ring_sync(waiter, | |
419 | signaller, | |
420 | VCS, | |
421 | seqno); | |
422 | } | |
423 | ||
424 | /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */ | |
425 | int | |
426 | gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter, | |
427 | struct intel_ring_buffer *signaller, | |
428 | u32 seqno) | |
429 | { | |
430 | WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID); | |
431 | return intel_ring_sync(waiter, | |
432 | signaller, | |
433 | BCS, | |
434 | seqno); | |
435 | } | |
436 | ||
437 | ||
438 | ||
c6df541c CW |
439 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
440 | do { \ | |
fcbc34e4 KG |
441 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
442 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
443 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
444 | intel_ring_emit(ring__, 0); \ | |
445 | intel_ring_emit(ring__, 0); \ | |
446 | } while (0) | |
447 | ||
448 | static int | |
449 | pc_render_add_request(struct intel_ring_buffer *ring, | |
450 | u32 *result) | |
451 | { | |
452 | struct drm_device *dev = ring->dev; | |
453 | u32 seqno = i915_gem_get_seqno(dev); | |
454 | struct pipe_control *pc = ring->private; | |
455 | u32 scratch_addr = pc->gtt_offset + 128; | |
456 | int ret; | |
457 | ||
458 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
459 | * incoherent with writes to memory, i.e. completely fubar, | |
460 | * so we need to use PIPE_NOTIFY instead. | |
461 | * | |
462 | * However, we also need to workaround the qword write | |
463 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
464 | * memory before requesting an interrupt. | |
465 | */ | |
466 | ret = intel_ring_begin(ring, 32); | |
467 | if (ret) | |
468 | return ret; | |
469 | ||
fcbc34e4 | 470 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
c6df541c CW |
471 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); |
472 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
473 | intel_ring_emit(ring, seqno); | |
474 | intel_ring_emit(ring, 0); | |
475 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
476 | scratch_addr += 128; /* write to separate cachelines */ | |
477 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
478 | scratch_addr += 128; | |
479 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
480 | scratch_addr += 128; | |
481 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
482 | scratch_addr += 128; | |
483 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
484 | scratch_addr += 128; | |
485 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
fcbc34e4 | 486 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
c6df541c CW |
487 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | |
488 | PIPE_CONTROL_NOTIFY); | |
489 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
490 | intel_ring_emit(ring, seqno); | |
491 | intel_ring_emit(ring, 0); | |
492 | intel_ring_advance(ring); | |
493 | ||
494 | *result = seqno; | |
495 | return 0; | |
496 | } | |
497 | ||
1ec14ad3 CW |
498 | static int |
499 | render_ring_add_request(struct intel_ring_buffer *ring, | |
500 | u32 *result) | |
501 | { | |
502 | struct drm_device *dev = ring->dev; | |
503 | u32 seqno = i915_gem_get_seqno(dev); | |
504 | int ret; | |
3cce469c | 505 | |
1ec14ad3 CW |
506 | ret = intel_ring_begin(ring, 4); |
507 | if (ret) | |
508 | return ret; | |
3cce469c | 509 | |
1ec14ad3 CW |
510 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
511 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
512 | intel_ring_emit(ring, seqno); | |
513 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
3cce469c | 514 | intel_ring_advance(ring); |
1ec14ad3 | 515 | |
3cce469c CW |
516 | *result = seqno; |
517 | return 0; | |
62fdfeaf EA |
518 | } |
519 | ||
8187a2b7 | 520 | static u32 |
1ec14ad3 | 521 | ring_get_seqno(struct intel_ring_buffer *ring) |
8187a2b7 | 522 | { |
1ec14ad3 CW |
523 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
524 | } | |
525 | ||
c6df541c CW |
526 | static u32 |
527 | pc_render_get_seqno(struct intel_ring_buffer *ring) | |
528 | { | |
529 | struct pipe_control *pc = ring->private; | |
530 | return pc->cpu_page[0]; | |
531 | } | |
532 | ||
0f46832f CW |
533 | static void |
534 | ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
535 | { | |
536 | dev_priv->gt_irq_mask &= ~mask; | |
537 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
538 | POSTING_READ(GTIMR); | |
539 | } | |
540 | ||
541 | static void | |
542 | ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
543 | { | |
544 | dev_priv->gt_irq_mask |= mask; | |
545 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
546 | POSTING_READ(GTIMR); | |
547 | } | |
548 | ||
549 | static void | |
550 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
551 | { | |
552 | dev_priv->irq_mask &= ~mask; | |
553 | I915_WRITE(IMR, dev_priv->irq_mask); | |
554 | POSTING_READ(IMR); | |
555 | } | |
556 | ||
557 | static void | |
558 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
559 | { | |
560 | dev_priv->irq_mask |= mask; | |
561 | I915_WRITE(IMR, dev_priv->irq_mask); | |
562 | POSTING_READ(IMR); | |
563 | } | |
564 | ||
b13c2b96 | 565 | static bool |
1ec14ad3 | 566 | render_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 567 | { |
78501eac | 568 | struct drm_device *dev = ring->dev; |
01a03331 | 569 | drm_i915_private_t *dev_priv = dev->dev_private; |
62fdfeaf | 570 | |
b13c2b96 CW |
571 | if (!dev->irq_enabled) |
572 | return false; | |
573 | ||
0dc79fb2 | 574 | spin_lock(&ring->irq_lock); |
01a03331 | 575 | if (ring->irq_refcount++ == 0) { |
62fdfeaf | 576 | if (HAS_PCH_SPLIT(dev)) |
0f46832f CW |
577 | ironlake_enable_irq(dev_priv, |
578 | GT_PIPE_NOTIFY | GT_USER_INTERRUPT); | |
62fdfeaf EA |
579 | else |
580 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
581 | } | |
0dc79fb2 | 582 | spin_unlock(&ring->irq_lock); |
b13c2b96 CW |
583 | |
584 | return true; | |
62fdfeaf EA |
585 | } |
586 | ||
8187a2b7 | 587 | static void |
1ec14ad3 | 588 | render_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 589 | { |
78501eac | 590 | struct drm_device *dev = ring->dev; |
01a03331 | 591 | drm_i915_private_t *dev_priv = dev->dev_private; |
62fdfeaf | 592 | |
0dc79fb2 | 593 | spin_lock(&ring->irq_lock); |
01a03331 | 594 | if (--ring->irq_refcount == 0) { |
62fdfeaf | 595 | if (HAS_PCH_SPLIT(dev)) |
0f46832f CW |
596 | ironlake_disable_irq(dev_priv, |
597 | GT_USER_INTERRUPT | | |
598 | GT_PIPE_NOTIFY); | |
62fdfeaf EA |
599 | else |
600 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
601 | } | |
0dc79fb2 | 602 | spin_unlock(&ring->irq_lock); |
62fdfeaf EA |
603 | } |
604 | ||
78501eac | 605 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 606 | { |
4593010b | 607 | struct drm_device *dev = ring->dev; |
78501eac | 608 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
609 | u32 mmio = 0; |
610 | ||
611 | /* The ring status page addresses are no longer next to the rest of | |
612 | * the ring registers as of gen7. | |
613 | */ | |
614 | if (IS_GEN7(dev)) { | |
615 | switch (ring->id) { | |
616 | case RING_RENDER: | |
617 | mmio = RENDER_HWS_PGA_GEN7; | |
618 | break; | |
619 | case RING_BLT: | |
620 | mmio = BLT_HWS_PGA_GEN7; | |
621 | break; | |
622 | case RING_BSD: | |
623 | mmio = BSD_HWS_PGA_GEN7; | |
624 | break; | |
625 | } | |
626 | } else if (IS_GEN6(ring->dev)) { | |
627 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
628 | } else { | |
629 | mmio = RING_HWS_PGA(ring->mmio_base); | |
630 | } | |
631 | ||
78501eac CW |
632 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
633 | POSTING_READ(mmio); | |
8187a2b7 ZN |
634 | } |
635 | ||
b72f3acb | 636 | static int |
78501eac CW |
637 | bsd_ring_flush(struct intel_ring_buffer *ring, |
638 | u32 invalidate_domains, | |
639 | u32 flush_domains) | |
d1b851fc | 640 | { |
b72f3acb CW |
641 | int ret; |
642 | ||
b72f3acb CW |
643 | ret = intel_ring_begin(ring, 2); |
644 | if (ret) | |
645 | return ret; | |
646 | ||
647 | intel_ring_emit(ring, MI_FLUSH); | |
648 | intel_ring_emit(ring, MI_NOOP); | |
649 | intel_ring_advance(ring); | |
650 | return 0; | |
d1b851fc ZN |
651 | } |
652 | ||
3cce469c | 653 | static int |
78501eac | 654 | ring_add_request(struct intel_ring_buffer *ring, |
3cce469c | 655 | u32 *result) |
d1b851fc ZN |
656 | { |
657 | u32 seqno; | |
3cce469c CW |
658 | int ret; |
659 | ||
660 | ret = intel_ring_begin(ring, 4); | |
661 | if (ret) | |
662 | return ret; | |
6f392d54 | 663 | |
78501eac | 664 | seqno = i915_gem_get_seqno(ring->dev); |
6f392d54 | 665 | |
3cce469c CW |
666 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
667 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
668 | intel_ring_emit(ring, seqno); | |
669 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
670 | intel_ring_advance(ring); | |
d1b851fc | 671 | |
3cce469c CW |
672 | *result = seqno; |
673 | return 0; | |
d1b851fc ZN |
674 | } |
675 | ||
0f46832f CW |
676 | static bool |
677 | gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) | |
678 | { | |
679 | struct drm_device *dev = ring->dev; | |
01a03331 | 680 | drm_i915_private_t *dev_priv = dev->dev_private; |
0f46832f CW |
681 | |
682 | if (!dev->irq_enabled) | |
683 | return false; | |
684 | ||
0dc79fb2 | 685 | spin_lock(&ring->irq_lock); |
01a03331 | 686 | if (ring->irq_refcount++ == 0) { |
0f46832f CW |
687 | ring->irq_mask &= ~rflag; |
688 | I915_WRITE_IMR(ring, ring->irq_mask); | |
689 | ironlake_enable_irq(dev_priv, gflag); | |
0f46832f | 690 | } |
0dc79fb2 | 691 | spin_unlock(&ring->irq_lock); |
0f46832f CW |
692 | |
693 | return true; | |
694 | } | |
695 | ||
696 | static void | |
697 | gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) | |
698 | { | |
699 | struct drm_device *dev = ring->dev; | |
01a03331 | 700 | drm_i915_private_t *dev_priv = dev->dev_private; |
0f46832f | 701 | |
0dc79fb2 | 702 | spin_lock(&ring->irq_lock); |
01a03331 | 703 | if (--ring->irq_refcount == 0) { |
0f46832f CW |
704 | ring->irq_mask |= rflag; |
705 | I915_WRITE_IMR(ring, ring->irq_mask); | |
706 | ironlake_disable_irq(dev_priv, gflag); | |
1ec14ad3 | 707 | } |
0dc79fb2 | 708 | spin_unlock(&ring->irq_lock); |
d1b851fc ZN |
709 | } |
710 | ||
b13c2b96 | 711 | static bool |
1ec14ad3 | 712 | bsd_ring_get_irq(struct intel_ring_buffer *ring) |
d1b851fc | 713 | { |
5bfa1063 FB |
714 | struct drm_device *dev = ring->dev; |
715 | drm_i915_private_t *dev_priv = dev->dev_private; | |
716 | ||
717 | if (!dev->irq_enabled) | |
718 | return false; | |
719 | ||
720 | spin_lock(&ring->irq_lock); | |
721 | if (ring->irq_refcount++ == 0) { | |
722 | if (IS_G4X(dev)) | |
723 | i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT); | |
724 | else | |
725 | ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT); | |
726 | } | |
727 | spin_unlock(&ring->irq_lock); | |
728 | ||
729 | return true; | |
1ec14ad3 CW |
730 | } |
731 | static void | |
732 | bsd_ring_put_irq(struct intel_ring_buffer *ring) | |
733 | { | |
5bfa1063 FB |
734 | struct drm_device *dev = ring->dev; |
735 | drm_i915_private_t *dev_priv = dev->dev_private; | |
736 | ||
737 | spin_lock(&ring->irq_lock); | |
738 | if (--ring->irq_refcount == 0) { | |
739 | if (IS_G4X(dev)) | |
740 | i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT); | |
741 | else | |
742 | ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT); | |
743 | } | |
744 | spin_unlock(&ring->irq_lock); | |
d1b851fc ZN |
745 | } |
746 | ||
747 | static int | |
c4e7a414 | 748 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
d1b851fc | 749 | { |
e1f99ce6 | 750 | int ret; |
78501eac | 751 | |
e1f99ce6 CW |
752 | ret = intel_ring_begin(ring, 2); |
753 | if (ret) | |
754 | return ret; | |
755 | ||
78501eac | 756 | intel_ring_emit(ring, |
c4e7a414 | 757 | MI_BATCH_BUFFER_START | (2 << 6) | |
78501eac | 758 | MI_BATCH_NON_SECURE_I965); |
c4e7a414 | 759 | intel_ring_emit(ring, offset); |
78501eac CW |
760 | intel_ring_advance(ring); |
761 | ||
d1b851fc ZN |
762 | return 0; |
763 | } | |
764 | ||
8187a2b7 | 765 | static int |
78501eac | 766 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 767 | u32 offset, u32 len) |
62fdfeaf | 768 | { |
78501eac | 769 | struct drm_device *dev = ring->dev; |
c4e7a414 | 770 | int ret; |
62fdfeaf | 771 | |
c4e7a414 CW |
772 | if (IS_I830(dev) || IS_845G(dev)) { |
773 | ret = intel_ring_begin(ring, 4); | |
774 | if (ret) | |
775 | return ret; | |
62fdfeaf | 776 | |
c4e7a414 CW |
777 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
778 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
779 | intel_ring_emit(ring, offset + len - 8); | |
780 | intel_ring_emit(ring, 0); | |
781 | } else { | |
782 | ret = intel_ring_begin(ring, 2); | |
783 | if (ret) | |
784 | return ret; | |
e1f99ce6 | 785 | |
c4e7a414 CW |
786 | if (INTEL_INFO(dev)->gen >= 4) { |
787 | intel_ring_emit(ring, | |
788 | MI_BATCH_BUFFER_START | (2 << 6) | | |
789 | MI_BATCH_NON_SECURE_I965); | |
790 | intel_ring_emit(ring, offset); | |
62fdfeaf | 791 | } else { |
c4e7a414 CW |
792 | intel_ring_emit(ring, |
793 | MI_BATCH_BUFFER_START | (2 << 6)); | |
794 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
62fdfeaf EA |
795 | } |
796 | } | |
c4e7a414 | 797 | intel_ring_advance(ring); |
62fdfeaf | 798 | |
62fdfeaf EA |
799 | return 0; |
800 | } | |
801 | ||
78501eac | 802 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 803 | { |
78501eac | 804 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
05394f39 | 805 | struct drm_i915_gem_object *obj; |
62fdfeaf | 806 | |
8187a2b7 ZN |
807 | obj = ring->status_page.obj; |
808 | if (obj == NULL) | |
62fdfeaf | 809 | return; |
62fdfeaf | 810 | |
05394f39 | 811 | kunmap(obj->pages[0]); |
62fdfeaf | 812 | i915_gem_object_unpin(obj); |
05394f39 | 813 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 814 | ring->status_page.obj = NULL; |
62fdfeaf EA |
815 | |
816 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
817 | } |
818 | ||
78501eac | 819 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 820 | { |
78501eac | 821 | struct drm_device *dev = ring->dev; |
62fdfeaf | 822 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 823 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
824 | int ret; |
825 | ||
62fdfeaf EA |
826 | obj = i915_gem_alloc_object(dev, 4096); |
827 | if (obj == NULL) { | |
828 | DRM_ERROR("Failed to allocate status page\n"); | |
829 | ret = -ENOMEM; | |
830 | goto err; | |
831 | } | |
e4ffd173 CW |
832 | |
833 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 834 | |
75e9e915 | 835 | ret = i915_gem_object_pin(obj, 4096, true); |
62fdfeaf | 836 | if (ret != 0) { |
62fdfeaf EA |
837 | goto err_unref; |
838 | } | |
839 | ||
05394f39 CW |
840 | ring->status_page.gfx_addr = obj->gtt_offset; |
841 | ring->status_page.page_addr = kmap(obj->pages[0]); | |
8187a2b7 | 842 | if (ring->status_page.page_addr == NULL) { |
62fdfeaf | 843 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
844 | goto err_unpin; |
845 | } | |
8187a2b7 ZN |
846 | ring->status_page.obj = obj; |
847 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 848 | |
78501eac | 849 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
850 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
851 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
852 | |
853 | return 0; | |
854 | ||
855 | err_unpin: | |
856 | i915_gem_object_unpin(obj); | |
857 | err_unref: | |
05394f39 | 858 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 859 | err: |
8187a2b7 | 860 | return ret; |
62fdfeaf EA |
861 | } |
862 | ||
8187a2b7 | 863 | int intel_init_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 864 | struct intel_ring_buffer *ring) |
62fdfeaf | 865 | { |
05394f39 | 866 | struct drm_i915_gem_object *obj; |
dd785e35 CW |
867 | int ret; |
868 | ||
8187a2b7 | 869 | ring->dev = dev; |
23bc5982 CW |
870 | INIT_LIST_HEAD(&ring->active_list); |
871 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 | 872 | INIT_LIST_HEAD(&ring->gpu_write_list); |
0dc79fb2 | 873 | |
b259f673 | 874 | init_waitqueue_head(&ring->irq_queue); |
0dc79fb2 | 875 | spin_lock_init(&ring->irq_lock); |
0f46832f | 876 | ring->irq_mask = ~0; |
62fdfeaf | 877 | |
8187a2b7 | 878 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 879 | ret = init_status_page(ring); |
8187a2b7 ZN |
880 | if (ret) |
881 | return ret; | |
882 | } | |
62fdfeaf | 883 | |
8187a2b7 | 884 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
885 | if (obj == NULL) { |
886 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 887 | ret = -ENOMEM; |
dd785e35 | 888 | goto err_hws; |
62fdfeaf | 889 | } |
62fdfeaf | 890 | |
05394f39 | 891 | ring->obj = obj; |
8187a2b7 | 892 | |
75e9e915 | 893 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
dd785e35 CW |
894 | if (ret) |
895 | goto err_unref; | |
62fdfeaf | 896 | |
8187a2b7 | 897 | ring->map.size = ring->size; |
05394f39 | 898 | ring->map.offset = dev->agp->base + obj->gtt_offset; |
62fdfeaf EA |
899 | ring->map.type = 0; |
900 | ring->map.flags = 0; | |
901 | ring->map.mtrr = 0; | |
902 | ||
903 | drm_core_ioremap_wc(&ring->map, dev); | |
904 | if (ring->map.handle == NULL) { | |
905 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 906 | ret = -EINVAL; |
dd785e35 | 907 | goto err_unpin; |
62fdfeaf EA |
908 | } |
909 | ||
8187a2b7 | 910 | ring->virtual_start = ring->map.handle; |
78501eac | 911 | ret = ring->init(ring); |
dd785e35 CW |
912 | if (ret) |
913 | goto err_unmap; | |
62fdfeaf | 914 | |
55249baa CW |
915 | /* Workaround an erratum on the i830 which causes a hang if |
916 | * the TAIL pointer points to within the last 2 cachelines | |
917 | * of the buffer. | |
918 | */ | |
919 | ring->effective_size = ring->size; | |
920 | if (IS_I830(ring->dev)) | |
921 | ring->effective_size -= 128; | |
922 | ||
c584fe47 | 923 | return 0; |
dd785e35 CW |
924 | |
925 | err_unmap: | |
926 | drm_core_ioremapfree(&ring->map, dev); | |
927 | err_unpin: | |
928 | i915_gem_object_unpin(obj); | |
929 | err_unref: | |
05394f39 CW |
930 | drm_gem_object_unreference(&obj->base); |
931 | ring->obj = NULL; | |
dd785e35 | 932 | err_hws: |
78501eac | 933 | cleanup_status_page(ring); |
8187a2b7 | 934 | return ret; |
62fdfeaf EA |
935 | } |
936 | ||
78501eac | 937 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 938 | { |
33626e6a CW |
939 | struct drm_i915_private *dev_priv; |
940 | int ret; | |
941 | ||
05394f39 | 942 | if (ring->obj == NULL) |
62fdfeaf EA |
943 | return; |
944 | ||
33626e6a CW |
945 | /* Disable the ring buffer. The ring must be idle at this point */ |
946 | dev_priv = ring->dev->dev_private; | |
96f298aa | 947 | ret = intel_wait_ring_idle(ring); |
29ee3991 CW |
948 | if (ret) |
949 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
950 | ring->name, ret); | |
951 | ||
33626e6a CW |
952 | I915_WRITE_CTL(ring, 0); |
953 | ||
78501eac | 954 | drm_core_ioremapfree(&ring->map, ring->dev); |
62fdfeaf | 955 | |
05394f39 CW |
956 | i915_gem_object_unpin(ring->obj); |
957 | drm_gem_object_unreference(&ring->obj->base); | |
958 | ring->obj = NULL; | |
78501eac | 959 | |
8d19215b ZN |
960 | if (ring->cleanup) |
961 | ring->cleanup(ring); | |
962 | ||
78501eac | 963 | cleanup_status_page(ring); |
62fdfeaf EA |
964 | } |
965 | ||
78501eac | 966 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 967 | { |
8187a2b7 | 968 | unsigned int *virt; |
55249baa | 969 | int rem = ring->size - ring->tail; |
62fdfeaf | 970 | |
8187a2b7 | 971 | if (ring->space < rem) { |
78501eac | 972 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
973 | if (ret) |
974 | return ret; | |
975 | } | |
62fdfeaf | 976 | |
8187a2b7 | 977 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
978 | rem /= 8; |
979 | while (rem--) { | |
62fdfeaf | 980 | *virt++ = MI_NOOP; |
1741dd4a CW |
981 | *virt++ = MI_NOOP; |
982 | } | |
62fdfeaf | 983 | |
8187a2b7 | 984 | ring->tail = 0; |
c7dca47b | 985 | ring->space = ring_space(ring); |
62fdfeaf EA |
986 | |
987 | return 0; | |
988 | } | |
989 | ||
78501eac | 990 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 991 | { |
78501eac | 992 | struct drm_device *dev = ring->dev; |
cae5852d | 993 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 994 | unsigned long end; |
6aa56062 CW |
995 | u32 head; |
996 | ||
c7dca47b CW |
997 | /* If the reported head position has wrapped or hasn't advanced, |
998 | * fallback to the slow and accurate path. | |
999 | */ | |
1000 | head = intel_read_status_page(ring, 4); | |
1001 | if (head > ring->head) { | |
1002 | ring->head = head; | |
1003 | ring->space = ring_space(ring); | |
1004 | if (ring->space >= n) | |
1005 | return 0; | |
1006 | } | |
1007 | ||
db53a302 | 1008 | trace_i915_ring_wait_begin(ring); |
8187a2b7 ZN |
1009 | end = jiffies + 3 * HZ; |
1010 | do { | |
c7dca47b CW |
1011 | ring->head = I915_READ_HEAD(ring); |
1012 | ring->space = ring_space(ring); | |
62fdfeaf | 1013 | if (ring->space >= n) { |
db53a302 | 1014 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1015 | return 0; |
1016 | } | |
1017 | ||
1018 | if (dev->primary->master) { | |
1019 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1020 | if (master_priv->sarea_priv) | |
1021 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1022 | } | |
d1b851fc | 1023 | |
e60a0b10 | 1024 | msleep(1); |
f4e0b29b CW |
1025 | if (atomic_read(&dev_priv->mm.wedged)) |
1026 | return -EAGAIN; | |
8187a2b7 | 1027 | } while (!time_after(jiffies, end)); |
db53a302 | 1028 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1029 | return -EBUSY; |
1030 | } | |
62fdfeaf | 1031 | |
e1f99ce6 CW |
1032 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1033 | int num_dwords) | |
8187a2b7 | 1034 | { |
21dd3734 | 1035 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
be26a10b | 1036 | int n = 4*num_dwords; |
e1f99ce6 | 1037 | int ret; |
78501eac | 1038 | |
21dd3734 CW |
1039 | if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
1040 | return -EIO; | |
1041 | ||
55249baa | 1042 | if (unlikely(ring->tail + n > ring->effective_size)) { |
e1f99ce6 CW |
1043 | ret = intel_wrap_ring_buffer(ring); |
1044 | if (unlikely(ret)) | |
1045 | return ret; | |
1046 | } | |
78501eac | 1047 | |
e1f99ce6 CW |
1048 | if (unlikely(ring->space < n)) { |
1049 | ret = intel_wait_ring_buffer(ring, n); | |
1050 | if (unlikely(ret)) | |
1051 | return ret; | |
1052 | } | |
d97ed339 CW |
1053 | |
1054 | ring->space -= n; | |
e1f99ce6 | 1055 | return 0; |
8187a2b7 | 1056 | } |
62fdfeaf | 1057 | |
78501eac | 1058 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 1059 | { |
d97ed339 | 1060 | ring->tail &= ring->size - 1; |
78501eac | 1061 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 1062 | } |
62fdfeaf | 1063 | |
e070868e | 1064 | static const struct intel_ring_buffer render_ring = { |
8187a2b7 | 1065 | .name = "render ring", |
9220434a | 1066 | .id = RING_RENDER, |
333e9fe9 | 1067 | .mmio_base = RENDER_RING_BASE, |
8187a2b7 | 1068 | .size = 32 * PAGE_SIZE, |
8187a2b7 | 1069 | .init = init_render_ring, |
297b0c5b | 1070 | .write_tail = ring_write_tail, |
8187a2b7 ZN |
1071 | .flush = render_ring_flush, |
1072 | .add_request = render_ring_add_request, | |
1ec14ad3 CW |
1073 | .get_seqno = ring_get_seqno, |
1074 | .irq_get = render_ring_get_irq, | |
1075 | .irq_put = render_ring_put_irq, | |
78501eac | 1076 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
0206e353 | 1077 | .cleanup = render_ring_cleanup, |
c8c99b0f BW |
1078 | .sync_to = render_ring_sync_to, |
1079 | .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID, | |
1080 | MI_SEMAPHORE_SYNC_RV, | |
1081 | MI_SEMAPHORE_SYNC_RB}, | |
1082 | .signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC}, | |
8187a2b7 | 1083 | }; |
d1b851fc ZN |
1084 | |
1085 | /* ring buffer for bit-stream decoder */ | |
1086 | ||
e070868e | 1087 | static const struct intel_ring_buffer bsd_ring = { |
d1b851fc | 1088 | .name = "bsd ring", |
9220434a | 1089 | .id = RING_BSD, |
333e9fe9 | 1090 | .mmio_base = BSD_RING_BASE, |
d1b851fc | 1091 | .size = 32 * PAGE_SIZE, |
78501eac | 1092 | .init = init_ring_common, |
297b0c5b | 1093 | .write_tail = ring_write_tail, |
d1b851fc | 1094 | .flush = bsd_ring_flush, |
549f7365 | 1095 | .add_request = ring_add_request, |
1ec14ad3 CW |
1096 | .get_seqno = ring_get_seqno, |
1097 | .irq_get = bsd_ring_get_irq, | |
1098 | .irq_put = bsd_ring_put_irq, | |
78501eac | 1099 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
d1b851fc | 1100 | }; |
5c1143bb | 1101 | |
881f47b6 | 1102 | |
78501eac | 1103 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1104 | u32 value) |
881f47b6 | 1105 | { |
0206e353 | 1106 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1107 | |
1108 | /* Every tail move must follow the sequence below */ | |
0206e353 AJ |
1109 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1110 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
1111 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
1112 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
1113 | ||
1114 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
1115 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
1116 | 50)) | |
1117 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
1118 | ||
1119 | I915_WRITE_TAIL(ring, value); | |
1120 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1121 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
1122 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
881f47b6 XH |
1123 | } |
1124 | ||
b72f3acb | 1125 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1126 | u32 invalidate, u32 flush) |
881f47b6 | 1127 | { |
71a77e07 | 1128 | uint32_t cmd; |
b72f3acb CW |
1129 | int ret; |
1130 | ||
b72f3acb CW |
1131 | ret = intel_ring_begin(ring, 4); |
1132 | if (ret) | |
1133 | return ret; | |
1134 | ||
71a77e07 CW |
1135 | cmd = MI_FLUSH_DW; |
1136 | if (invalidate & I915_GEM_GPU_DOMAINS) | |
1137 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; | |
1138 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1139 | intel_ring_emit(ring, 0); |
1140 | intel_ring_emit(ring, 0); | |
71a77e07 | 1141 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1142 | intel_ring_advance(ring); |
1143 | return 0; | |
881f47b6 XH |
1144 | } |
1145 | ||
1146 | static int | |
78501eac | 1147 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 1148 | u32 offset, u32 len) |
881f47b6 | 1149 | { |
0206e353 | 1150 | int ret; |
ab6f8e32 | 1151 | |
0206e353 AJ |
1152 | ret = intel_ring_begin(ring, 2); |
1153 | if (ret) | |
1154 | return ret; | |
e1f99ce6 | 1155 | |
0206e353 AJ |
1156 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
1157 | /* bit0-7 is the length on GEN6+ */ | |
1158 | intel_ring_emit(ring, offset); | |
1159 | intel_ring_advance(ring); | |
ab6f8e32 | 1160 | |
0206e353 | 1161 | return 0; |
881f47b6 XH |
1162 | } |
1163 | ||
0f46832f CW |
1164 | static bool |
1165 | gen6_render_ring_get_irq(struct intel_ring_buffer *ring) | |
1166 | { | |
1167 | return gen6_ring_get_irq(ring, | |
1168 | GT_USER_INTERRUPT, | |
1169 | GEN6_RENDER_USER_INTERRUPT); | |
1170 | } | |
1171 | ||
1172 | static void | |
1173 | gen6_render_ring_put_irq(struct intel_ring_buffer *ring) | |
1174 | { | |
1175 | return gen6_ring_put_irq(ring, | |
1176 | GT_USER_INTERRUPT, | |
1177 | GEN6_RENDER_USER_INTERRUPT); | |
1178 | } | |
1179 | ||
b13c2b96 | 1180 | static bool |
1ec14ad3 CW |
1181 | gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
1182 | { | |
0f46832f CW |
1183 | return gen6_ring_get_irq(ring, |
1184 | GT_GEN6_BSD_USER_INTERRUPT, | |
1185 | GEN6_BSD_USER_INTERRUPT); | |
1ec14ad3 CW |
1186 | } |
1187 | ||
1188 | static void | |
1189 | gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) | |
1190 | { | |
0f46832f CW |
1191 | return gen6_ring_put_irq(ring, |
1192 | GT_GEN6_BSD_USER_INTERRUPT, | |
1193 | GEN6_BSD_USER_INTERRUPT); | |
1ec14ad3 CW |
1194 | } |
1195 | ||
881f47b6 | 1196 | /* ring buffer for Video Codec for Gen6+ */ |
e070868e | 1197 | static const struct intel_ring_buffer gen6_bsd_ring = { |
1ec14ad3 CW |
1198 | .name = "gen6 bsd ring", |
1199 | .id = RING_BSD, | |
1200 | .mmio_base = GEN6_BSD_RING_BASE, | |
1201 | .size = 32 * PAGE_SIZE, | |
1202 | .init = init_ring_common, | |
1203 | .write_tail = gen6_bsd_ring_write_tail, | |
1204 | .flush = gen6_ring_flush, | |
1205 | .add_request = gen6_add_request, | |
1206 | .get_seqno = ring_get_seqno, | |
1207 | .irq_get = gen6_bsd_ring_get_irq, | |
1208 | .irq_put = gen6_bsd_ring_put_irq, | |
1209 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, | |
c8c99b0f BW |
1210 | .sync_to = gen6_bsd_ring_sync_to, |
1211 | .semaphore_register = {MI_SEMAPHORE_SYNC_VR, | |
1212 | MI_SEMAPHORE_SYNC_INVALID, | |
1213 | MI_SEMAPHORE_SYNC_VB}, | |
1214 | .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC}, | |
549f7365 CW |
1215 | }; |
1216 | ||
1217 | /* Blitter support (SandyBridge+) */ | |
1218 | ||
b13c2b96 | 1219 | static bool |
1ec14ad3 | 1220 | blt_ring_get_irq(struct intel_ring_buffer *ring) |
549f7365 | 1221 | { |
0f46832f CW |
1222 | return gen6_ring_get_irq(ring, |
1223 | GT_BLT_USER_INTERRUPT, | |
1224 | GEN6_BLITTER_USER_INTERRUPT); | |
549f7365 | 1225 | } |
1ec14ad3 | 1226 | |
549f7365 | 1227 | static void |
1ec14ad3 | 1228 | blt_ring_put_irq(struct intel_ring_buffer *ring) |
549f7365 | 1229 | { |
0f46832f CW |
1230 | gen6_ring_put_irq(ring, |
1231 | GT_BLT_USER_INTERRUPT, | |
1232 | GEN6_BLITTER_USER_INTERRUPT); | |
549f7365 CW |
1233 | } |
1234 | ||
8d19215b ZN |
1235 | |
1236 | /* Workaround for some stepping of SNB, | |
1237 | * each time when BLT engine ring tail moved, | |
1238 | * the first command in the ring to be parsed | |
1239 | * should be MI_BATCH_BUFFER_START | |
1240 | */ | |
1241 | #define NEED_BLT_WORKAROUND(dev) \ | |
1242 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) | |
1243 | ||
1244 | static inline struct drm_i915_gem_object * | |
1245 | to_blt_workaround(struct intel_ring_buffer *ring) | |
1246 | { | |
1247 | return ring->private; | |
1248 | } | |
1249 | ||
1250 | static int blt_ring_init(struct intel_ring_buffer *ring) | |
1251 | { | |
1252 | if (NEED_BLT_WORKAROUND(ring->dev)) { | |
1253 | struct drm_i915_gem_object *obj; | |
27153f72 | 1254 | u32 *ptr; |
8d19215b ZN |
1255 | int ret; |
1256 | ||
05394f39 | 1257 | obj = i915_gem_alloc_object(ring->dev, 4096); |
8d19215b ZN |
1258 | if (obj == NULL) |
1259 | return -ENOMEM; | |
1260 | ||
05394f39 | 1261 | ret = i915_gem_object_pin(obj, 4096, true); |
8d19215b ZN |
1262 | if (ret) { |
1263 | drm_gem_object_unreference(&obj->base); | |
1264 | return ret; | |
1265 | } | |
1266 | ||
1267 | ptr = kmap(obj->pages[0]); | |
27153f72 CW |
1268 | *ptr++ = MI_BATCH_BUFFER_END; |
1269 | *ptr++ = MI_NOOP; | |
8d19215b ZN |
1270 | kunmap(obj->pages[0]); |
1271 | ||
05394f39 | 1272 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
8d19215b | 1273 | if (ret) { |
05394f39 | 1274 | i915_gem_object_unpin(obj); |
8d19215b ZN |
1275 | drm_gem_object_unreference(&obj->base); |
1276 | return ret; | |
1277 | } | |
1278 | ||
1279 | ring->private = obj; | |
1280 | } | |
1281 | ||
1282 | return init_ring_common(ring); | |
1283 | } | |
1284 | ||
1285 | static int blt_ring_begin(struct intel_ring_buffer *ring, | |
1286 | int num_dwords) | |
1287 | { | |
1288 | if (ring->private) { | |
1289 | int ret = intel_ring_begin(ring, num_dwords+2); | |
1290 | if (ret) | |
1291 | return ret; | |
1292 | ||
1293 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); | |
1294 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); | |
1295 | ||
1296 | return 0; | |
1297 | } else | |
1298 | return intel_ring_begin(ring, 4); | |
1299 | } | |
1300 | ||
b72f3acb | 1301 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1302 | u32 invalidate, u32 flush) |
8d19215b | 1303 | { |
71a77e07 | 1304 | uint32_t cmd; |
b72f3acb CW |
1305 | int ret; |
1306 | ||
b72f3acb CW |
1307 | ret = blt_ring_begin(ring, 4); |
1308 | if (ret) | |
1309 | return ret; | |
1310 | ||
71a77e07 CW |
1311 | cmd = MI_FLUSH_DW; |
1312 | if (invalidate & I915_GEM_DOMAIN_RENDER) | |
1313 | cmd |= MI_INVALIDATE_TLB; | |
1314 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1315 | intel_ring_emit(ring, 0); |
1316 | intel_ring_emit(ring, 0); | |
71a77e07 | 1317 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1318 | intel_ring_advance(ring); |
1319 | return 0; | |
8d19215b ZN |
1320 | } |
1321 | ||
8d19215b ZN |
1322 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) |
1323 | { | |
1324 | if (!ring->private) | |
1325 | return; | |
1326 | ||
1327 | i915_gem_object_unpin(ring->private); | |
1328 | drm_gem_object_unreference(ring->private); | |
1329 | ring->private = NULL; | |
1330 | } | |
1331 | ||
549f7365 | 1332 | static const struct intel_ring_buffer gen6_blt_ring = { |
0206e353 AJ |
1333 | .name = "blt ring", |
1334 | .id = RING_BLT, | |
1335 | .mmio_base = BLT_RING_BASE, | |
1336 | .size = 32 * PAGE_SIZE, | |
1337 | .init = blt_ring_init, | |
1338 | .write_tail = ring_write_tail, | |
1339 | .flush = blt_ring_flush, | |
1340 | .add_request = gen6_add_request, | |
1341 | .get_seqno = ring_get_seqno, | |
c8c99b0f BW |
1342 | .irq_get = blt_ring_get_irq, |
1343 | .irq_put = blt_ring_put_irq, | |
0206e353 | 1344 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
c8c99b0f BW |
1345 | .cleanup = blt_ring_cleanup, |
1346 | .sync_to = gen6_blt_ring_sync_to, | |
1347 | .semaphore_register = {MI_SEMAPHORE_SYNC_BR, | |
1348 | MI_SEMAPHORE_SYNC_BV, | |
1349 | MI_SEMAPHORE_SYNC_INVALID}, | |
1350 | .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC}, | |
881f47b6 XH |
1351 | }; |
1352 | ||
5c1143bb XH |
1353 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1354 | { | |
1355 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1356 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1357 | |
1ec14ad3 CW |
1358 | *ring = render_ring; |
1359 | if (INTEL_INFO(dev)->gen >= 6) { | |
1360 | ring->add_request = gen6_add_request; | |
0f46832f CW |
1361 | ring->irq_get = gen6_render_ring_get_irq; |
1362 | ring->irq_put = gen6_render_ring_put_irq; | |
c6df541c CW |
1363 | } else if (IS_GEN5(dev)) { |
1364 | ring->add_request = pc_render_add_request; | |
1365 | ring->get_seqno = pc_render_get_seqno; | |
1ec14ad3 | 1366 | } |
5c1143bb XH |
1367 | |
1368 | if (!I915_NEED_GFX_HWS(dev)) { | |
1ec14ad3 CW |
1369 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1370 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
5c1143bb XH |
1371 | } |
1372 | ||
1ec14ad3 | 1373 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1374 | } |
1375 | ||
e8616b6c CW |
1376 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1377 | { | |
1378 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1379 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
1380 | ||
1381 | *ring = render_ring; | |
1382 | if (INTEL_INFO(dev)->gen >= 6) { | |
1383 | ring->add_request = gen6_add_request; | |
1384 | ring->irq_get = gen6_render_ring_get_irq; | |
1385 | ring->irq_put = gen6_render_ring_put_irq; | |
1386 | } else if (IS_GEN5(dev)) { | |
1387 | ring->add_request = pc_render_add_request; | |
1388 | ring->get_seqno = pc_render_get_seqno; | |
1389 | } | |
1390 | ||
f3234706 KP |
1391 | if (!I915_NEED_GFX_HWS(dev)) |
1392 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; | |
1393 | ||
e8616b6c CW |
1394 | ring->dev = dev; |
1395 | INIT_LIST_HEAD(&ring->active_list); | |
1396 | INIT_LIST_HEAD(&ring->request_list); | |
1397 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
1398 | ||
1399 | ring->size = size; | |
1400 | ring->effective_size = ring->size; | |
1401 | if (IS_I830(ring->dev)) | |
1402 | ring->effective_size -= 128; | |
1403 | ||
1404 | ring->map.offset = start; | |
1405 | ring->map.size = size; | |
1406 | ring->map.type = 0; | |
1407 | ring->map.flags = 0; | |
1408 | ring->map.mtrr = 0; | |
1409 | ||
1410 | drm_core_ioremap_wc(&ring->map, dev); | |
1411 | if (ring->map.handle == NULL) { | |
1412 | DRM_ERROR("can not ioremap virtual address for" | |
1413 | " ring buffer\n"); | |
1414 | return -ENOMEM; | |
1415 | } | |
1416 | ||
1417 | ring->virtual_start = (void __force __iomem *)ring->map.handle; | |
1418 | return 0; | |
1419 | } | |
1420 | ||
5c1143bb XH |
1421 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1422 | { | |
1423 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1424 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1425 | |
65d3eb1e | 1426 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
1ec14ad3 | 1427 | *ring = gen6_bsd_ring; |
881f47b6 | 1428 | else |
1ec14ad3 | 1429 | *ring = bsd_ring; |
5c1143bb | 1430 | |
1ec14ad3 | 1431 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 1432 | } |
549f7365 CW |
1433 | |
1434 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1435 | { | |
1436 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1437 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 1438 | |
1ec14ad3 | 1439 | *ring = gen6_blt_ring; |
549f7365 | 1440 | |
1ec14ad3 | 1441 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 1442 | } |