Commit | Line | Data |
---|---|---|
8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
4 | struct intel_hw_status_page { | |
4225d0f2 | 5 | u32 *page_addr; |
8187a2b7 | 6 | unsigned int gfx_addr; |
05394f39 | 7 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
8 | }; |
9 | ||
b7287d80 BW |
10 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
11 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 12 | |
b7287d80 BW |
13 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
14 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 15 | |
b7287d80 BW |
16 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
17 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 18 | |
b7287d80 BW |
19 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
20 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
cae5852d | 21 | |
b7287d80 BW |
22 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
23 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | |
870e86dd | 24 | |
b7287d80 BW |
25 | #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) |
26 | #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) | |
27 | #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) | |
1ec14ad3 | 28 | |
8187a2b7 ZN |
29 | struct intel_ring_buffer { |
30 | const char *name; | |
9220434a | 31 | enum intel_ring_id { |
96154f2f DV |
32 | RCS = 0x0, |
33 | VCS, | |
34 | BCS, | |
9220434a | 35 | } id; |
96154f2f | 36 | #define I915_NUM_RINGS 3 |
333e9fe9 | 37 | u32 mmio_base; |
311bd68e | 38 | void __iomem *virtual_start; |
8187a2b7 | 39 | struct drm_device *dev; |
05394f39 | 40 | struct drm_i915_gem_object *obj; |
8187a2b7 | 41 | |
8c0a6bfe CW |
42 | u32 head; |
43 | u32 tail; | |
780f0ca3 | 44 | int space; |
c2c347a9 | 45 | int size; |
55249baa | 46 | int effective_size; |
8187a2b7 ZN |
47 | struct intel_hw_status_page status_page; |
48 | ||
a71d8d94 CW |
49 | /** We track the position of the requests in the ring buffer, and |
50 | * when each is retired we increment last_retired_head as the GPU | |
51 | * must have finished processing the request and so we know we | |
52 | * can advance the ringbuffer up to that position. | |
53 | * | |
54 | * last_retired_head is set to -1 after the value is consumed so | |
55 | * we can detect new retirements. | |
56 | */ | |
57 | u32 last_retired_head; | |
58 | ||
7338aefa | 59 | u32 irq_refcount; /* protected by dev_priv->irq_lock */ |
6a848ccb | 60 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
db53a302 | 61 | u32 trace_irq_seqno; |
1ec14ad3 | 62 | u32 sync_seqno[I915_NUM_RINGS-1]; |
b13c2b96 | 63 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
1ec14ad3 | 64 | void (*irq_put)(struct intel_ring_buffer *ring); |
8187a2b7 | 65 | |
78501eac | 66 | int (*init)(struct intel_ring_buffer *ring); |
8187a2b7 | 67 | |
78501eac | 68 | void (*write_tail)(struct intel_ring_buffer *ring, |
297b0c5b | 69 | u32 value); |
b72f3acb CW |
70 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
71 | u32 invalidate_domains, | |
72 | u32 flush_domains); | |
3cce469c CW |
73 | int (*add_request)(struct intel_ring_buffer *ring, |
74 | u32 *seqno); | |
b2eadbc8 CW |
75 | /* Some chipsets are not quite as coherent as advertised and need |
76 | * an expensive kick to force a true read of the up-to-date seqno. | |
77 | * However, the up-to-date seqno is not always required and the last | |
78 | * seen value is good enough. Note that the seqno will always be | |
79 | * monotonic, even if not coherent. | |
80 | */ | |
81 | u32 (*get_seqno)(struct intel_ring_buffer *ring, | |
82 | bool lazy_coherency); | |
78501eac | 83 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
d7d4eedd CW |
84 | u32 offset, u32 length, |
85 | unsigned flags); | |
86 | #define I915_DISPATCH_SECURE 0x1 | |
8d19215b | 87 | void (*cleanup)(struct intel_ring_buffer *ring); |
c8c99b0f BW |
88 | int (*sync_to)(struct intel_ring_buffer *ring, |
89 | struct intel_ring_buffer *to, | |
90 | u32 seqno); | |
8187a2b7 | 91 | |
c8c99b0f BW |
92 | u32 semaphore_register[3]; /*our mbox written by others */ |
93 | u32 signal_mbox[2]; /* mboxes this ring signals to */ | |
8187a2b7 ZN |
94 | /** |
95 | * List of objects currently involved in rendering from the | |
96 | * ringbuffer. | |
97 | * | |
98 | * Includes buffers having the contents of their GPU caches | |
99 | * flushed, not necessarily primitives. last_rendering_seqno | |
100 | * represents when the rendering involved will be completed. | |
101 | * | |
102 | * A reference is held on the buffer while on this list. | |
103 | */ | |
104 | struct list_head active_list; | |
105 | ||
106 | /** | |
107 | * List of breadcrumbs associated with GPU requests currently | |
108 | * outstanding. | |
109 | */ | |
110 | struct list_head request_list; | |
111 | ||
a56ba56c CW |
112 | /** |
113 | * Do we have some not yet emitted requests outstanding? | |
114 | */ | |
5d97eb69 | 115 | u32 outstanding_lazy_request; |
cc889e0f | 116 | bool gpu_caches_dirty; |
a56ba56c | 117 | |
8187a2b7 | 118 | wait_queue_head_t irq_queue; |
8d19215b | 119 | |
12b0286f BW |
120 | /** |
121 | * Do an explicit TLB flush before MI_SET_CONTEXT | |
122 | */ | |
123 | bool itlb_before_ctx_switch; | |
40521054 | 124 | struct i915_hw_context *default_context; |
e0556841 | 125 | struct drm_i915_gem_object *last_context_obj; |
40521054 | 126 | |
8d19215b | 127 | void *private; |
8187a2b7 ZN |
128 | }; |
129 | ||
b4519513 CW |
130 | static inline bool |
131 | intel_ring_initialized(struct intel_ring_buffer *ring) | |
132 | { | |
133 | return ring->obj != NULL; | |
134 | } | |
135 | ||
96154f2f DV |
136 | static inline unsigned |
137 | intel_ring_flag(struct intel_ring_buffer *ring) | |
138 | { | |
139 | return 1 << ring->id; | |
140 | } | |
141 | ||
1ec14ad3 CW |
142 | static inline u32 |
143 | intel_ring_sync_index(struct intel_ring_buffer *ring, | |
144 | struct intel_ring_buffer *other) | |
145 | { | |
146 | int idx; | |
147 | ||
148 | /* | |
149 | * cs -> 0 = vcs, 1 = bcs | |
150 | * vcs -> 0 = bcs, 1 = cs, | |
151 | * bcs -> 0 = cs, 1 = vcs. | |
152 | */ | |
153 | ||
154 | idx = (other - ring) - 1; | |
155 | if (idx < 0) | |
156 | idx += I915_NUM_RINGS; | |
157 | ||
158 | return idx; | |
159 | } | |
160 | ||
8187a2b7 ZN |
161 | static inline u32 |
162 | intel_read_status_page(struct intel_ring_buffer *ring, | |
78501eac | 163 | int reg) |
8187a2b7 | 164 | { |
4225d0f2 DV |
165 | /* Ensure that the compiler doesn't optimize away the load. */ |
166 | barrier(); | |
167 | return ring->status_page.page_addr[reg]; | |
8187a2b7 ZN |
168 | } |
169 | ||
311bd68e CW |
170 | /** |
171 | * Reads a dword out of the status page, which is written to from the command | |
172 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
173 | * MI_STORE_DATA_IMM. | |
174 | * | |
175 | * The following dwords have a reserved meaning: | |
176 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
177 | * 0x04: ring 0 head pointer | |
178 | * 0x05: ring 1 head pointer (915-class) | |
179 | * 0x06: ring 2 head pointer (915-class) | |
180 | * 0x10-0x1b: Context status DWords (GM45) | |
181 | * 0x1f: Last written status offset. (GM45) | |
182 | * | |
183 | * The area from dword 0x20 to 0x3ff is available for driver usage. | |
184 | */ | |
311bd68e | 185 | #define I915_GEM_HWS_INDEX 0x20 |
311bd68e | 186 | |
78501eac | 187 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
96f298aa | 188 | |
e1f99ce6 | 189 | int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); |
96f298aa BW |
190 | static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) |
191 | { | |
a94919ea | 192 | return intel_wait_ring_buffer(ring, ring->size - 8); |
96f298aa BW |
193 | } |
194 | ||
e1f99ce6 | 195 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
78501eac CW |
196 | |
197 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, | |
198 | u32 data) | |
e898cd22 | 199 | { |
78501eac | 200 | iowrite32(data, ring->virtual_start + ring->tail); |
e898cd22 CW |
201 | ring->tail += 4; |
202 | } | |
203 | ||
78501eac | 204 | void intel_ring_advance(struct intel_ring_buffer *ring); |
8187a2b7 | 205 | |
78501eac | 206 | u32 intel_ring_get_seqno(struct intel_ring_buffer *ring); |
a7b9761d CW |
207 | int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); |
208 | int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); | |
8187a2b7 | 209 | |
5c1143bb XH |
210 | int intel_init_render_ring_buffer(struct drm_device *dev); |
211 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
549f7365 | 212 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
8187a2b7 | 213 | |
78501eac CW |
214 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
215 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); | |
79f321b7 | 216 | |
a71d8d94 CW |
217 | static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) |
218 | { | |
219 | return ring->tail; | |
220 | } | |
221 | ||
db53a302 CW |
222 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
223 | { | |
224 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) | |
225 | ring->trace_irq_seqno = seqno; | |
226 | } | |
227 | ||
e8616b6c CW |
228 | /* DRI warts */ |
229 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); | |
230 | ||
8187a2b7 | 231 | #endif /* _INTEL_RINGBUFFER_H_ */ |