Commit | Line | Data |
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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
633cf8f5 VS |
4 | /* |
5 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" | |
6 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" | |
7 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" | |
8 | * | |
9 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same | |
10 | * cacheline, the Head Pointer must not be greater than the Tail | |
11 | * Pointer." | |
12 | */ | |
13 | #define I915_RING_FREE_SPACE 64 | |
14 | ||
8187a2b7 | 15 | struct intel_hw_status_page { |
4225d0f2 | 16 | u32 *page_addr; |
8187a2b7 | 17 | unsigned int gfx_addr; |
05394f39 | 18 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
19 | }; |
20 | ||
b7287d80 BW |
21 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
22 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 23 | |
b7287d80 BW |
24 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
25 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 26 | |
b7287d80 BW |
27 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
28 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 29 | |
b7287d80 BW |
30 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
31 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
cae5852d | 32 | |
b7287d80 BW |
33 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
34 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | |
870e86dd | 35 | |
f2f4d82f JN |
36 | enum intel_ring_hangcheck_action { |
37 | HANGCHECK_WAIT, | |
38 | HANGCHECK_ACTIVE, | |
39 | HANGCHECK_KICK, | |
40 | HANGCHECK_HUNG, | |
41 | }; | |
ad8beaea | 42 | |
92cab734 | 43 | struct intel_ring_hangcheck { |
6274f212 | 44 | bool deadlock; |
92cab734 | 45 | u32 seqno; |
05407ff8 MK |
46 | u32 acthd; |
47 | int score; | |
ad8beaea | 48 | enum intel_ring_hangcheck_action action; |
92cab734 MK |
49 | }; |
50 | ||
8187a2b7 ZN |
51 | struct intel_ring_buffer { |
52 | const char *name; | |
9220434a | 53 | enum intel_ring_id { |
96154f2f DV |
54 | RCS = 0x0, |
55 | VCS, | |
56 | BCS, | |
4a3dd19d | 57 | VECS, |
9220434a | 58 | } id; |
4a3dd19d | 59 | #define I915_NUM_RINGS 4 |
333e9fe9 | 60 | u32 mmio_base; |
311bd68e | 61 | void __iomem *virtual_start; |
8187a2b7 | 62 | struct drm_device *dev; |
05394f39 | 63 | struct drm_i915_gem_object *obj; |
8187a2b7 | 64 | |
8c0a6bfe CW |
65 | u32 head; |
66 | u32 tail; | |
780f0ca3 | 67 | int space; |
c2c347a9 | 68 | int size; |
55249baa | 69 | int effective_size; |
8187a2b7 ZN |
70 | struct intel_hw_status_page status_page; |
71 | ||
a71d8d94 CW |
72 | /** We track the position of the requests in the ring buffer, and |
73 | * when each is retired we increment last_retired_head as the GPU | |
74 | * must have finished processing the request and so we know we | |
75 | * can advance the ringbuffer up to that position. | |
76 | * | |
77 | * last_retired_head is set to -1 after the value is consumed so | |
78 | * we can detect new retirements. | |
79 | */ | |
80 | u32 last_retired_head; | |
81 | ||
c7113cc3 | 82 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
6a848ccb | 83 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
db53a302 | 84 | u32 trace_irq_seqno; |
1ec14ad3 | 85 | u32 sync_seqno[I915_NUM_RINGS-1]; |
b13c2b96 | 86 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
1ec14ad3 | 87 | void (*irq_put)(struct intel_ring_buffer *ring); |
8187a2b7 | 88 | |
78501eac | 89 | int (*init)(struct intel_ring_buffer *ring); |
8187a2b7 | 90 | |
78501eac | 91 | void (*write_tail)(struct intel_ring_buffer *ring, |
297b0c5b | 92 | u32 value); |
b72f3acb CW |
93 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
94 | u32 invalidate_domains, | |
95 | u32 flush_domains); | |
9d773091 | 96 | int (*add_request)(struct intel_ring_buffer *ring); |
b2eadbc8 CW |
97 | /* Some chipsets are not quite as coherent as advertised and need |
98 | * an expensive kick to force a true read of the up-to-date seqno. | |
99 | * However, the up-to-date seqno is not always required and the last | |
100 | * seen value is good enough. Note that the seqno will always be | |
101 | * monotonic, even if not coherent. | |
102 | */ | |
103 | u32 (*get_seqno)(struct intel_ring_buffer *ring, | |
104 | bool lazy_coherency); | |
b70ec5bf MK |
105 | void (*set_seqno)(struct intel_ring_buffer *ring, |
106 | u32 seqno); | |
78501eac | 107 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
d7d4eedd CW |
108 | u32 offset, u32 length, |
109 | unsigned flags); | |
110 | #define I915_DISPATCH_SECURE 0x1 | |
b45305fc | 111 | #define I915_DISPATCH_PINNED 0x2 |
8d19215b | 112 | void (*cleanup)(struct intel_ring_buffer *ring); |
c8c99b0f BW |
113 | int (*sync_to)(struct intel_ring_buffer *ring, |
114 | struct intel_ring_buffer *to, | |
115 | u32 seqno); | |
ad776f8b | 116 | |
5586181f BW |
117 | /* our mbox written by others */ |
118 | u32 semaphore_register[I915_NUM_RINGS]; | |
ad776f8b BW |
119 | /* mboxes this ring signals to */ |
120 | u32 signal_mbox[I915_NUM_RINGS]; | |
121 | ||
8187a2b7 ZN |
122 | /** |
123 | * List of objects currently involved in rendering from the | |
124 | * ringbuffer. | |
125 | * | |
126 | * Includes buffers having the contents of their GPU caches | |
127 | * flushed, not necessarily primitives. last_rendering_seqno | |
128 | * represents when the rendering involved will be completed. | |
129 | * | |
130 | * A reference is held on the buffer while on this list. | |
131 | */ | |
132 | struct list_head active_list; | |
133 | ||
134 | /** | |
135 | * List of breadcrumbs associated with GPU requests currently | |
136 | * outstanding. | |
137 | */ | |
138 | struct list_head request_list; | |
139 | ||
a56ba56c CW |
140 | /** |
141 | * Do we have some not yet emitted requests outstanding? | |
142 | */ | |
5d97eb69 | 143 | u32 outstanding_lazy_request; |
cc889e0f | 144 | bool gpu_caches_dirty; |
c65355bb | 145 | bool fbc_dirty; |
a56ba56c | 146 | |
8187a2b7 | 147 | wait_queue_head_t irq_queue; |
8d19215b | 148 | |
12b0286f BW |
149 | /** |
150 | * Do an explicit TLB flush before MI_SET_CONTEXT | |
151 | */ | |
152 | bool itlb_before_ctx_switch; | |
40521054 | 153 | struct i915_hw_context *default_context; |
112522f6 | 154 | struct i915_hw_context *last_context; |
40521054 | 155 | |
92cab734 MK |
156 | struct intel_ring_hangcheck hangcheck; |
157 | ||
0d1aacac CW |
158 | struct { |
159 | struct drm_i915_gem_object *obj; | |
160 | u32 gtt_offset; | |
161 | volatile u32 *cpu_page; | |
162 | } scratch; | |
8187a2b7 ZN |
163 | }; |
164 | ||
b4519513 CW |
165 | static inline bool |
166 | intel_ring_initialized(struct intel_ring_buffer *ring) | |
167 | { | |
168 | return ring->obj != NULL; | |
169 | } | |
170 | ||
96154f2f DV |
171 | static inline unsigned |
172 | intel_ring_flag(struct intel_ring_buffer *ring) | |
173 | { | |
174 | return 1 << ring->id; | |
175 | } | |
176 | ||
1ec14ad3 CW |
177 | static inline u32 |
178 | intel_ring_sync_index(struct intel_ring_buffer *ring, | |
179 | struct intel_ring_buffer *other) | |
180 | { | |
181 | int idx; | |
182 | ||
183 | /* | |
184 | * cs -> 0 = vcs, 1 = bcs | |
185 | * vcs -> 0 = bcs, 1 = cs, | |
186 | * bcs -> 0 = cs, 1 = vcs. | |
187 | */ | |
188 | ||
189 | idx = (other - ring) - 1; | |
190 | if (idx < 0) | |
191 | idx += I915_NUM_RINGS; | |
192 | ||
193 | return idx; | |
194 | } | |
195 | ||
8187a2b7 ZN |
196 | static inline u32 |
197 | intel_read_status_page(struct intel_ring_buffer *ring, | |
78501eac | 198 | int reg) |
8187a2b7 | 199 | { |
4225d0f2 DV |
200 | /* Ensure that the compiler doesn't optimize away the load. */ |
201 | barrier(); | |
202 | return ring->status_page.page_addr[reg]; | |
8187a2b7 ZN |
203 | } |
204 | ||
b70ec5bf MK |
205 | static inline void |
206 | intel_write_status_page(struct intel_ring_buffer *ring, | |
207 | int reg, u32 value) | |
208 | { | |
209 | ring->status_page.page_addr[reg] = value; | |
210 | } | |
211 | ||
311bd68e CW |
212 | /** |
213 | * Reads a dword out of the status page, which is written to from the command | |
214 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
215 | * MI_STORE_DATA_IMM. | |
216 | * | |
217 | * The following dwords have a reserved meaning: | |
218 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
219 | * 0x04: ring 0 head pointer | |
220 | * 0x05: ring 1 head pointer (915-class) | |
221 | * 0x06: ring 2 head pointer (915-class) | |
222 | * 0x10-0x1b: Context status DWords (GM45) | |
223 | * 0x1f: Last written status offset. (GM45) | |
224 | * | |
225 | * The area from dword 0x20 to 0x3ff is available for driver usage. | |
226 | */ | |
311bd68e | 227 | #define I915_GEM_HWS_INDEX 0x20 |
9a289771 JB |
228 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
229 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) | |
311bd68e | 230 | |
78501eac | 231 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
96f298aa | 232 | |
e1f99ce6 | 233 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
78501eac CW |
234 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, |
235 | u32 data) | |
e898cd22 | 236 | { |
78501eac | 237 | iowrite32(data, ring->virtual_start + ring->tail); |
e898cd22 CW |
238 | ring->tail += 4; |
239 | } | |
78501eac | 240 | void intel_ring_advance(struct intel_ring_buffer *ring); |
3e960501 | 241 | int __must_check intel_ring_idle(struct intel_ring_buffer *ring); |
f7e98ad4 | 242 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno); |
a7b9761d CW |
243 | int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); |
244 | int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); | |
8187a2b7 | 245 | |
5c1143bb XH |
246 | int intel_init_render_ring_buffer(struct drm_device *dev); |
247 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
549f7365 | 248 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
9a8a2213 | 249 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
8187a2b7 | 250 | |
78501eac CW |
251 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
252 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); | |
79f321b7 | 253 | |
a71d8d94 CW |
254 | static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) |
255 | { | |
256 | return ring->tail; | |
257 | } | |
258 | ||
9d773091 CW |
259 | static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring) |
260 | { | |
261 | BUG_ON(ring->outstanding_lazy_request == 0); | |
262 | return ring->outstanding_lazy_request; | |
263 | } | |
264 | ||
db53a302 CW |
265 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
266 | { | |
267 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) | |
268 | ring->trace_irq_seqno = seqno; | |
269 | } | |
270 | ||
e8616b6c CW |
271 | /* DRI warts */ |
272 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); | |
273 | ||
8187a2b7 | 274 | #endif /* _INTEL_RINGBUFFER_H_ */ |