[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.h

#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_

#include <linux/hashtable.h>

#define I915_CMD_HASH_ORDER 9

/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64

struct  intel_hw_status_page {
	u32		*page_addr;
	unsigned int	gfx_addr;
	struct		drm_i915_gem_object *obj;
};

#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)

#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)

#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)

#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)

#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)

#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)

/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
 */
#define i915_semaphore_seqno_size sizeof(uint64_t)
#define GEN8_SIGNAL_OFFSET(__ring, to)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) +	\
	(i915_semaphore_seqno_size * (to)))

#define GEN8_WAIT_OFFSET(__ring, from)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	(i915_semaphore_seqno_size * (__ring)->id))

#define GEN8_RING_SEMAPHORE_INIT do { \
	if (!dev_priv->semaphore_obj) { \
		break; \
	} \
	ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
	ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
	ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
	ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
	ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
	ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
	} while(0)

enum intel_ring_hangcheck_action {
	HANGCHECK_IDLE = 0,
	HANGCHECK_WAIT,
	HANGCHECK_ACTIVE,
	HANGCHECK_ACTIVE_LOOP,
	HANGCHECK_KICK,
	HANGCHECK_HUNG,
};

#define HANGCHECK_SCORE_RING_HUNG 31

struct intel_ring_hangcheck {
	u64 acthd;
	u64 max_acthd;
	u32 seqno;
	int score;
	enum intel_ring_hangcheck_action action;
	int deadlock;
};

struct intel_ringbuffer {
	struct drm_i915_gem_object *obj;
	void __iomem *virtual_start;

	u32 head;
	u32 tail;
	int space;
	int size;
	int effective_size;

	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32 last_retired_head;
};

struct  intel_engine_cs {
	const char	*name;
	enum intel_ring_id {
		RCS = 0x0,
		VCS,
		BCS,
		VECS,
		VCS2
	} id;
#define I915_NUM_RINGS 5
#define LAST_USER_RING (VECS + 1)
	u32		mmio_base;
	struct		drm_device *dev;
	struct intel_ringbuffer *buffer;

	struct intel_hw_status_page status_page;

	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
	u32		trace_irq_seqno;
	bool __must_check (*irq_get)(struct intel_engine_cs *ring);
	void		(*irq_put)(struct intel_engine_cs *ring);

	int		(*init)(struct intel_engine_cs *ring);

	void		(*write_tail)(struct intel_engine_cs *ring,
				      u32 value);
	int __must_check (*flush)(struct intel_engine_cs *ring,
				  u32	invalidate_domains,
				  u32	flush_domains);
	int		(*add_request)(struct intel_engine_cs *ring);
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
	u32		(*get_seqno)(struct intel_engine_cs *ring,
				     bool lazy_coherency);
	void		(*set_seqno)(struct intel_engine_cs *ring,
				     u32 seqno);
	int		(*dispatch_execbuffer)(struct intel_engine_cs *ring,
					       u64 offset, u32 length,
					       unsigned flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
	void		(*cleanup)(struct intel_engine_cs *ring);

	/* GEN8 signal/wait table - never trust comments!
	 *	  signal to	signal to    signal to   signal to      signal to
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) |  NOP (0x90) | VCS2 (0x98) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP  (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	 *  ie. transpose of g(x, y)
	 *
	 *	 sync from	sync from    sync from    sync from	sync from
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) |  NOP (0x90) | VCS2 (0xb8) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) |  NOP (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	 *  ie. transpose of f(x, y)
	 */
	struct {
		u32	sync_seqno[I915_NUM_RINGS-1];

		union {
			struct {
				/* our mbox written by others */
				u32		wait[I915_NUM_RINGS];
				/* mboxes this ring signals to */
				u32		signal[I915_NUM_RINGS];
			} mbox;
			u64		signal_ggtt[I915_NUM_RINGS];
		};

		/* AKA wait() */
		int	(*sync_to)(struct intel_engine_cs *ring,
				   struct intel_engine_cs *to,
				   u32 seqno);
		int	(*signal)(struct intel_engine_cs *signaller,
				  /* num_dwords needed by caller */
				  unsigned int num_dwords);
	} semaphore;

	/**
	 * List of objects currently involved in rendering from the
	 * ringbuffer.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives.  last_rendering_seqno
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;

	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;

	/**
	 * Do we have some not yet emitted requests outstanding?
	 */
	struct drm_i915_gem_request *preallocated_lazy_request;
	u32 outstanding_lazy_seqno;
	bool gpu_caches_dirty;
	bool fbc_dirty;

	wait_queue_head_t irq_queue;

	struct intel_context *default_context;
	struct intel_context *last_context;

	struct intel_ring_hangcheck hangcheck;

	struct {
		struct drm_i915_gem_object *obj;
		u32 gtt_offset;
		volatile u32 *cpu_page;
	} scratch;

	bool needs_cmd_parser;

	/*
	 * Table of commands the command parser needs to know about
	 * for this ring.
	 */
	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);

	/*
	 * Table of registers allowed in commands that read/write registers.
	 */
	const u32 *reg_table;
	int reg_count;

	/*
	 * Table of registers allowed in commands that read/write registers, but
	 * only from the DRM master.
	 */
	const u32 *master_reg_table;
	int master_reg_count;

	/*
	 * Returns the bitmask for the length field of the specified command.
	 * Return 0 for an unrecognized/invalid command.
	 *
	 * If the command parser finds an entry for a command in the ring's
	 * cmd_tables, it gets the command's length based on the table entry.
	 * If not, it calls this function to determine the per-ring length field
	 * encoding for the command (i.e. certain opcode ranges use certain bits
	 * to encode the command length in the header).
	 */
	u32 (*get_cmd_length_mask)(u32 cmd_header);
};

static inline bool
intel_ring_initialized(struct intel_engine_cs *ring)
{
	return ring->buffer && ring->buffer->obj;
}

static inline unsigned
intel_ring_flag(struct intel_engine_cs *ring)
{
	return 1 << ring->id;
}

static inline u32
intel_ring_sync_index(struct intel_engine_cs *ring,
		      struct intel_engine_cs *other)
{
	int idx;

	/*
	 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
	 */

	idx = (other - ring) - 1;
	if (idx < 0)
		idx += I915_NUM_RINGS;

	return idx;
}

static inline u32
intel_read_status_page(struct intel_engine_cs *ring,
		       int reg)
{
	/* Ensure that the compiler doesn't optimize away the load. */
	barrier();
	return ring->status_page.page_addr[reg];
}

static inline void
intel_write_status_page(struct intel_engine_cs *ring,
			int reg, u32 value)
{
	ring->status_page.page_addr[reg] = value;
}

/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
 *
 * The area from dword 0x20 to 0x3ff is available for driver usage.
 */
#define I915_GEM_HWS_INDEX		0x20
#define I915_GEM_HWS_SCRATCH_INDEX	0x30
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)

void intel_stop_ring_buffer(struct intel_engine_cs *ring);
void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);

int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
static inline void intel_ring_emit(struct intel_engine_cs *ring,
				   u32 data)
{
	struct intel_ringbuffer *ringbuf = ring->buffer;
	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	ringbuf->tail += 4;
}
static inline void intel_ring_advance(struct intel_engine_cs *ring)
{
	struct intel_ringbuffer *ringbuf = ring->buffer;
	ringbuf->tail &= ringbuf->size - 1;
}
void __intel_ring_advance(struct intel_engine_cs *ring);

int __must_check intel_ring_idle(struct intel_engine_cs *ring);
void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);

int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_bsd2_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
int intel_init_vebox_ring_buffer(struct drm_device *dev);

u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
void intel_ring_setup_status_page(struct intel_engine_cs *ring);

static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
{
	return ringbuf->tail;
}

static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring)
{
	BUG_ON(ring->outstanding_lazy_seqno == 0);
	return ring->outstanding_lazy_seqno;
}

static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno)
{
	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
		ring->trace_irq_seqno = seqno;
}

/* DRI warts */
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);

#endif /* _INTEL_RINGBUFFER_H_ */
Commit	Line	Data
8187a2b7 ZN	1	#ifndef _INTEL_RINGBUFFER_H_
	2	#define _INTEL_RINGBUFFER_H_
	3
44e895a8 BV	4	#include <linux/hashtable.h>
	5
	6	#define I915_CMD_HASH_ORDER 9
	7
633cf8f5 VS	8	/*
	9	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
	10	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
	11	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
	12	*
	13	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
	14	* cacheline, the Head Pointer must not be greater than the Tail
	15	* Pointer."
	16	*/
	17	#define I915_RING_FREE_SPACE 64
	18
8187a2b7	19	struct intel_hw_status_page {
4225d0f2	20	u32 *page_addr;
8187a2b7	21	unsigned int gfx_addr;
05394f39	22	struct drm_i915_gem_object *obj;
8187a2b7 ZN	23	};
8187a2b7 ZN	24
b7287d80 BW	25	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
b7287d80 BW	26	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
cae5852d	27
b7287d80 BW	28	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
b7287d80 BW	29	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
cae5852d	30
b7287d80 BW	31	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
b7287d80 BW	32	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
cae5852d	33
b7287d80 BW	34	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
b7287d80 BW	35	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
cae5852d	36
b7287d80 BW	37	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
b7287d80 BW	38	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
870e86dd	39
e9fea574	40	#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
9991ae78	41	#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
e9fea574	42
3e78998a BW	43	/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
	44	* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
	45	*/
	46	#define i915_semaphore_seqno_size sizeof(uint64_t)
	47	#define GEN8_SIGNAL_OFFSET(__ring, to) \
	48	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	49	((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	50	(i915_semaphore_seqno_size * (to)))
	51
	52	#define GEN8_WAIT_OFFSET(__ring, from) \
	53	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	54	((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	55	(i915_semaphore_seqno_size * (__ring)->id))
	56
	57	#define GEN8_RING_SEMAPHORE_INIT do { \
	58	if (!dev_priv->semaphore_obj) { \
	59	break; \
	60	} \
	61	ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
	62	ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
	63	ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
	64	ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
	65	ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
	66	ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
	67	} while(0)
	68
f2f4d82f	69	enum intel_ring_hangcheck_action {
da661464	70	HANGCHECK_IDLE = 0,
f2f4d82f JN	71	HANGCHECK_WAIT,
f2f4d82f JN	72	HANGCHECK_ACTIVE,
f260fe7b	73	HANGCHECK_ACTIVE_LOOP,
f2f4d82f JN	74	HANGCHECK_KICK,
	75	HANGCHECK_HUNG,
	76	};
ad8beaea	77
b6b0fac0 MK	78	#define HANGCHECK_SCORE_RING_HUNG 31
b6b0fac0 MK	79
92cab734	80	struct intel_ring_hangcheck {
50877445	81	u64 acthd;
f260fe7b	82	u64 max_acthd;
92cab734	83	u32 seqno;
05407ff8	84	int score;
ad8beaea	85	enum intel_ring_hangcheck_action action;
4be17381	86	int deadlock;
92cab734 MK	87	};
92cab734 MK	88
8ee14975 OM	89	struct intel_ringbuffer {
	90	struct drm_i915_gem_object *obj;
	91	void __iomem *virtual_start;
	92
	93	u32 head;
	94	u32 tail;
	95	int space;
	96	int size;
	97	int effective_size;
	98
	99	/** We track the position of the requests in the ring buffer, and
	100	* when each is retired we increment last_retired_head as the GPU
	101	* must have finished processing the request and so we know we
	102	* can advance the ringbuffer up to that position.
	103	*
	104	* last_retired_head is set to -1 after the value is consumed so
	105	* we can detect new retirements.
	106	*/
	107	u32 last_retired_head;
	108	};
	109
a4872ba6	110	struct intel_engine_cs {
8187a2b7	111	const char *name;
9220434a	112	enum intel_ring_id {
96154f2f DV	113	RCS = 0x0,
	114	VCS,
	115	BCS,
4a3dd19d	116	VECS,
845f74a7	117	VCS2
9220434a	118	} id;
845f74a7	119	#define I915_NUM_RINGS 5
b1a93306	120	#define LAST_USER_RING (VECS + 1)
333e9fe9	121	u32 mmio_base;
8187a2b7	122	struct drm_device *dev;
8ee14975	123	struct intel_ringbuffer *buffer;
8187a2b7	124
8187a2b7 ZN	125	struct intel_hw_status_page status_page;
8187a2b7 ZN	126
c7113cc3	127	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
6a848ccb	128	u32 irq_enable_mask; /* bitmask to enable ring interrupt */
db53a302	129	u32 trace_irq_seqno;
a4872ba6 OM	130	bool __must_check (irq_get)(struct intel_engine_cs ring);
a4872ba6 OM	131	void (irq_put)(struct intel_engine_cs ring);
8187a2b7	132
a4872ba6	133	int (init)(struct intel_engine_cs ring);
8187a2b7	134
a4872ba6	135	void (write_tail)(struct intel_engine_cs ring,
297b0c5b	136	u32 value);
a4872ba6	137	int __must_check (flush)(struct intel_engine_cs ring,
b72f3acb CW	138	u32 invalidate_domains,
b72f3acb CW	139	u32 flush_domains);
a4872ba6	140	int (add_request)(struct intel_engine_cs ring);
b2eadbc8 CW	141	/* Some chipsets are not quite as coherent as advertised and need
	142	* an expensive kick to force a true read of the up-to-date seqno.
	143	* However, the up-to-date seqno is not always required and the last
	144	* seen value is good enough. Note that the seqno will always be
	145	* monotonic, even if not coherent.
	146	*/
a4872ba6	147	u32 (get_seqno)(struct intel_engine_cs ring,
b2eadbc8	148	bool lazy_coherency);
a4872ba6	149	void (set_seqno)(struct intel_engine_cs ring,
b70ec5bf	150	u32 seqno);
a4872ba6	151	int (dispatch_execbuffer)(struct intel_engine_cs ring,
9bcb144c	152	u64 offset, u32 length,
d7d4eedd CW	153	unsigned flags);
d7d4eedd CW	154	#define I915_DISPATCH_SECURE 0x1
b45305fc	155	#define I915_DISPATCH_PINNED 0x2
a4872ba6	156	void (cleanup)(struct intel_engine_cs ring);
ebc348b2	157
3e78998a BW	158	/* GEN8 signal/wait table - never trust comments!
	159	* signal to signal to signal to signal to signal to
	160	* RCS VCS BCS VECS VCS2
	161	* --------------------------------------------------------------------
	162	* RCS \| NOP (0x00) \| VCS (0x08) \| BCS (0x10) \| VECS (0x18) \| VCS2 (0x20) \|
	163	* \|-------------------------------------------------------------------
	164	* VCS \| RCS (0x28) \| NOP (0x30) \| BCS (0x38) \| VECS (0x40) \| VCS2 (0x48) \|
	165	* \|-------------------------------------------------------------------
	166	* BCS \| RCS (0x50) \| VCS (0x58) \| NOP (0x60) \| VECS (0x68) \| VCS2 (0x70) \|
	167	* \|-------------------------------------------------------------------
	168	* VECS \| RCS (0x78) \| VCS (0x80) \| BCS (0x88) \| NOP (0x90) \| VCS2 (0x98) \|
	169	* \|-------------------------------------------------------------------
	170	* VCS2 \| RCS (0xa0) \| VCS (0xa8) \| BCS (0xb0) \| VECS (0xb8) \| NOP (0xc0) \|
	171	* \|-------------------------------------------------------------------
	172	*
	173	* Generalization:
	174	* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	175	* ie. transpose of g(x, y)
	176	*
	177	* sync from sync from sync from sync from sync from
	178	* RCS VCS BCS VECS VCS2
	179	* --------------------------------------------------------------------
	180	* RCS \| NOP (0x00) \| VCS (0x28) \| BCS (0x50) \| VECS (0x78) \| VCS2 (0xa0) \|
	181	* \|-------------------------------------------------------------------
	182	* VCS \| RCS (0x08) \| NOP (0x30) \| BCS (0x58) \| VECS (0x80) \| VCS2 (0xa8) \|
	183	* \|-------------------------------------------------------------------
	184	* BCS \| RCS (0x10) \| VCS (0x38) \| NOP (0x60) \| VECS (0x88) \| VCS2 (0xb0) \|
	185	* \|-------------------------------------------------------------------
	186	* VECS \| RCS (0x18) \| VCS (0x40) \| BCS (0x68) \| NOP (0x90) \| VCS2 (0xb8) \|
	187	* \|-------------------------------------------------------------------
	188	* VCS2 \| RCS (0x20) \| VCS (0x48) \| BCS (0x70) \| VECS (0x98) \| NOP (0xc0) \|
	189	* \|-------------------------------------------------------------------
	190	*
	191	* Generalization:
	192	* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	193	* ie. transpose of f(x, y)
	194	*/
ebc348b2 BW	195	struct {
ebc348b2 BW	196	u32 sync_seqno[I915_NUM_RINGS-1];
78325f2d	197
3e78998a BW	198	union {
	199	struct {
	200	/* our mbox written by others */
	201	u32 wait[I915_NUM_RINGS];
	202	/* mboxes this ring signals to */
	203	u32 signal[I915_NUM_RINGS];
	204	} mbox;
	205	u64 signal_ggtt[I915_NUM_RINGS];
	206	};
78325f2d BW	207
78325f2d BW	208	/* AKA wait() */
a4872ba6 OM	209	int (sync_to)(struct intel_engine_cs ring,
a4872ba6 OM	210	struct intel_engine_cs *to,
78325f2d	211	u32 seqno);
a4872ba6	212	int (signal)(struct intel_engine_cs signaller,
024a43e1 BW	213	/* num_dwords needed by caller */
024a43e1 BW	214	unsigned int num_dwords);
ebc348b2	215	} semaphore;
ad776f8b	216
8187a2b7 ZN	217	/**
	218	* List of objects currently involved in rendering from the
	219	* ringbuffer.
	220	*
	221	* Includes buffers having the contents of their GPU caches
	222	* flushed, not necessarily primitives. last_rendering_seqno
	223	* represents when the rendering involved will be completed.
	224	*
	225	* A reference is held on the buffer while on this list.
	226	*/
	227	struct list_head active_list;
	228
	229	/**
	230	* List of breadcrumbs associated with GPU requests currently
	231	* outstanding.
	232	*/
	233	struct list_head request_list;
	234
a56ba56c CW	235	/**
	236	* Do we have some not yet emitted requests outstanding?
	237	*/
3c0e234c	238	struct drm_i915_gem_request *preallocated_lazy_request;
1823521d	239	u32 outstanding_lazy_seqno;
cc889e0f	240	bool gpu_caches_dirty;
c65355bb	241	bool fbc_dirty;
a56ba56c	242
8187a2b7	243	wait_queue_head_t irq_queue;
8d19215b	244
273497e5 OM	245	struct intel_context *default_context;
273497e5 OM	246	struct intel_context *last_context;
40521054	247
92cab734 MK	248	struct intel_ring_hangcheck hangcheck;
92cab734 MK	249
0d1aacac CW	250	struct {
	251	struct drm_i915_gem_object *obj;
	252	u32 gtt_offset;
	253	volatile u32 *cpu_page;
	254	} scratch;
351e3db2	255
44e895a8 BV	256	bool needs_cmd_parser;
44e895a8 BV	257
351e3db2	258	/*
44e895a8	259	* Table of commands the command parser needs to know about
351e3db2 BV	260	* for this ring.
351e3db2 BV	261	*/
44e895a8	262	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
351e3db2 BV	263
	264	/*
	265	* Table of registers allowed in commands that read/write registers.
	266	*/
	267	const u32 *reg_table;
	268	int reg_count;
	269
	270	/*
	271	* Table of registers allowed in commands that read/write registers, but
	272	* only from the DRM master.
	273	*/
	274	const u32 *master_reg_table;
	275	int master_reg_count;
	276
	277	/*
	278	* Returns the bitmask for the length field of the specified command.
	279	* Return 0 for an unrecognized/invalid command.
	280	*
	281	* If the command parser finds an entry for a command in the ring's
	282	* cmd_tables, it gets the command's length based on the table entry.
	283	* If not, it calls this function to determine the per-ring length field
	284	* encoding for the command (i.e. certain opcode ranges use certain bits
	285	* to encode the command length in the header).
	286	*/
	287	u32 (*get_cmd_length_mask)(u32 cmd_header);
8187a2b7 ZN	288	};
8187a2b7 ZN	289
b4519513	290	static inline bool
a4872ba6	291	intel_ring_initialized(struct intel_engine_cs *ring)
b4519513	292	{
ee1b1e5e	293	return ring->buffer && ring->buffer->obj;
b4519513 CW	294	}
b4519513 CW	295
96154f2f	296	static inline unsigned
a4872ba6	297	intel_ring_flag(struct intel_engine_cs *ring)
96154f2f DV	298	{
	299	return 1 << ring->id;
	300	}
	301
1ec14ad3	302	static inline u32
a4872ba6 OM	303	intel_ring_sync_index(struct intel_engine_cs *ring,
a4872ba6 OM	304	struct intel_engine_cs *other)
1ec14ad3 CW	305	{
	306	int idx;
	307
	308	/*
ddd4dbc6 RV	309	* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	310	* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	311	* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	312	* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	313	* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
1ec14ad3 CW	314	*/
	315
	316	idx = (other - ring) - 1;
	317	if (idx < 0)
	318	idx += I915_NUM_RINGS;
	319
	320	return idx;
	321	}
	322
8187a2b7	323	static inline u32
a4872ba6	324	intel_read_status_page(struct intel_engine_cs *ring,
78501eac	325	int reg)
8187a2b7	326	{
4225d0f2 DV	327	/* Ensure that the compiler doesn't optimize away the load. */
	328	barrier();
	329	return ring->status_page.page_addr[reg];
8187a2b7 ZN	330	}
8187a2b7 ZN	331
b70ec5bf	332	static inline void
a4872ba6	333	intel_write_status_page(struct intel_engine_cs *ring,
b70ec5bf MK	334	int reg, u32 value)
	335	{
	336	ring->status_page.page_addr[reg] = value;
	337	}
	338
311bd68e CW	339	/**
	340	* Reads a dword out of the status page, which is written to from the command
	341	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
	342	* MI_STORE_DATA_IMM.
	343	*
	344	* The following dwords have a reserved meaning:
	345	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
	346	* 0x04: ring 0 head pointer
	347	* 0x05: ring 1 head pointer (915-class)
	348	* 0x06: ring 2 head pointer (915-class)
	349	* 0x10-0x1b: Context status DWords (GM45)
	350	* 0x1f: Last written status offset. (GM45)
	351	*
	352	* The area from dword 0x20 to 0x3ff is available for driver usage.
	353	*/
311bd68e	354	#define I915_GEM_HWS_INDEX 0x20
9a289771 JB	355	#define I915_GEM_HWS_SCRATCH_INDEX 0x30
9a289771 JB	356	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
311bd68e	357
a4872ba6 OM	358	void intel_stop_ring_buffer(struct intel_engine_cs *ring);
a4872ba6 OM	359	void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
96f298aa	360
a4872ba6 OM	361	int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
	362	int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
	363	static inline void intel_ring_emit(struct intel_engine_cs *ring,
78501eac	364	u32 data)
e898cd22	365	{
93b0a4e0 OM	366	struct intel_ringbuffer *ringbuf = ring->buffer;
	367	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	368	ringbuf->tail += 4;
e898cd22	369	}
a4872ba6	370	static inline void intel_ring_advance(struct intel_engine_cs *ring)
09246732	371	{
93b0a4e0 OM	372	struct intel_ringbuffer *ringbuf = ring->buffer;
93b0a4e0 OM	373	ringbuf->tail &= ringbuf->size - 1;
09246732	374	}
a4872ba6	375	void __intel_ring_advance(struct intel_engine_cs *ring);
09246732	376
a4872ba6 OM	377	int __must_check intel_ring_idle(struct intel_engine_cs *ring);
	378	void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
	379	int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
	380	int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);
8187a2b7	381
5c1143bb XH	382	int intel_init_render_ring_buffer(struct drm_device *dev);
5c1143bb XH	383	int intel_init_bsd_ring_buffer(struct drm_device *dev);
845f74a7	384	int intel_init_bsd2_ring_buffer(struct drm_device *dev);
549f7365	385	int intel_init_blt_ring_buffer(struct drm_device *dev);
9a8a2213	386	int intel_init_vebox_ring_buffer(struct drm_device *dev);
8187a2b7	387
a4872ba6 OM	388	u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
a4872ba6 OM	389	void intel_ring_setup_status_page(struct intel_engine_cs *ring);
79f321b7	390
1b5d063f	391	static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
a71d8d94	392	{
1b5d063f	393	return ringbuf->tail;
a71d8d94 CW	394	}
a71d8d94 CW	395
a4872ba6	396	static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring)
9d773091	397	{
1823521d CW	398	BUG_ON(ring->outstanding_lazy_seqno == 0);
1823521d CW	399	return ring->outstanding_lazy_seqno;
9d773091 CW	400	}
9d773091 CW	401
a4872ba6	402	static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno)
db53a302 CW	403	{
	404	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
	405	ring->trace_irq_seqno = seqno;
	406	}
	407
e8616b6c CW	408	/* DRI warts */
	409	int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
	410
8187a2b7	411	#endif /* _INTEL_RINGBUFFER_H_ */