[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.h

#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_

#include <linux/hashtable.h>

#define I915_CMD_HASH_ORDER 9

/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
 * to give some inclination as to some of the magic values used in the various
 * workarounds!
 */
#define CACHELINE_BYTES 64

/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64

struct  intel_hw_status_page {
	u32		*page_addr;
	unsigned int	gfx_addr;
	struct		drm_i915_gem_object *obj;
};

#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)

#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)

#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)

#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)

#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)

#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)

/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
 */
#define i915_semaphore_seqno_size sizeof(uint64_t)
#define GEN8_SIGNAL_OFFSET(__ring, to)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) +	\
	(i915_semaphore_seqno_size * (to)))

#define GEN8_WAIT_OFFSET(__ring, from)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	(i915_semaphore_seqno_size * (__ring)->id))

#define GEN8_RING_SEMAPHORE_INIT do { \
	if (!dev_priv->semaphore_obj) { \
		break; \
	} \
	ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
	ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
	ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
	ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
	ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
	ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
	} while(0)

enum intel_ring_hangcheck_action {
	HANGCHECK_IDLE = 0,
	HANGCHECK_WAIT,
	HANGCHECK_ACTIVE,
	HANGCHECK_ACTIVE_LOOP,
	HANGCHECK_KICK,
	HANGCHECK_HUNG,
};

#define HANGCHECK_SCORE_RING_HUNG 31

struct intel_ring_hangcheck {
	u64 acthd;
	u64 max_acthd;
	u32 seqno;
	int score;
	enum intel_ring_hangcheck_action action;
	int deadlock;
};

struct intel_ringbuffer {
	struct drm_i915_gem_object *obj;
	void __iomem *virtual_start;

	struct intel_engine_cs *ring;

	/*
	 * FIXME: This backpointer is an artifact of the history of how the
	 * execlist patches came into being. It will get removed once the basic
	 * code has landed.
	 */
	struct intel_context *FIXME_lrc_ctx;

	u32 head;
	u32 tail;
	int space;
	int size;
	int effective_size;

	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32 last_retired_head;
};

struct  intel_engine_cs {
	const char	*name;
	enum intel_ring_id {
		RCS = 0x0,
		VCS,
		BCS,
		VECS,
		VCS2
	} id;
#define I915_NUM_RINGS 5
#define LAST_USER_RING (VECS + 1)
	u32		mmio_base;
	struct		drm_device *dev;
	struct intel_ringbuffer *buffer;

	struct intel_hw_status_page status_page;

	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
	u32		trace_irq_seqno;
	bool __must_check (*irq_get)(struct intel_engine_cs *ring);
	void		(*irq_put)(struct intel_engine_cs *ring);

	int		(*init)(struct intel_engine_cs *ring);

	int		(*init_context)(struct intel_engine_cs *ring);

	void		(*write_tail)(struct intel_engine_cs *ring,
				      u32 value);
	int __must_check (*flush)(struct intel_engine_cs *ring,
				  u32	invalidate_domains,
				  u32	flush_domains);
	int		(*add_request)(struct intel_engine_cs *ring);
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
	u32		(*get_seqno)(struct intel_engine_cs *ring,
				     bool lazy_coherency);
	void		(*set_seqno)(struct intel_engine_cs *ring,
				     u32 seqno);
	int		(*dispatch_execbuffer)(struct intel_engine_cs *ring,
					       u64 offset, u32 length,
					       unsigned flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
	void		(*cleanup)(struct intel_engine_cs *ring);

	/* GEN8 signal/wait table - never trust comments!
	 *	  signal to	signal to    signal to   signal to      signal to
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) |  NOP (0x90) | VCS2 (0x98) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP  (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	 *  ie. transpose of g(x, y)
	 *
	 *	 sync from	sync from    sync from    sync from	sync from
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) |  NOP (0x90) | VCS2 (0xb8) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) |  NOP (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	 *  ie. transpose of f(x, y)
	 */
	struct {
		u32	sync_seqno[I915_NUM_RINGS-1];

		union {
			struct {
				/* our mbox written by others */
				u32		wait[I915_NUM_RINGS];
				/* mboxes this ring signals to */
				u32		signal[I915_NUM_RINGS];
			} mbox;
			u64		signal_ggtt[I915_NUM_RINGS];
		};

		/* AKA wait() */
		int	(*sync_to)(struct intel_engine_cs *ring,
				   struct intel_engine_cs *to,
				   u32 seqno);
		int	(*signal)(struct intel_engine_cs *signaller,
				  /* num_dwords needed by caller */
				  unsigned int num_dwords);
	} semaphore;

	/* Execlists */
	spinlock_t execlist_lock;
	struct list_head execlist_queue;
	u8 next_context_status_buffer;
	u32             irq_keep_mask; /* bitmask for interrupts that should not be masked */
	int		(*emit_request)(struct intel_ringbuffer *ringbuf);
	int		(*emit_flush)(struct intel_ringbuffer *ringbuf,
				      u32 invalidate_domains,
				      u32 flush_domains);
	int		(*emit_bb_start)(struct intel_ringbuffer *ringbuf,
					 u64 offset, unsigned flags);

	/**
	 * List of objects currently involved in rendering from the
	 * ringbuffer.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives.  last_rendering_seqno
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;

	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;

	/**
	 * Do we have some not yet emitted requests outstanding?
	 */
	struct drm_i915_gem_request *preallocated_lazy_request;
	u32 outstanding_lazy_seqno;
	bool gpu_caches_dirty;
	bool fbc_dirty;

	wait_queue_head_t irq_queue;

	struct intel_context *default_context;
	struct intel_context *last_context;

	struct intel_ring_hangcheck hangcheck;

	struct {
		struct drm_i915_gem_object *obj;
		u32 gtt_offset;
		volatile u32 *cpu_page;
	} scratch;

	bool needs_cmd_parser;

	/*
	 * Table of commands the command parser needs to know about
	 * for this ring.
	 */
	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);

	/*
	 * Table of registers allowed in commands that read/write registers.
	 */
	const u32 *reg_table;
	int reg_count;

	/*
	 * Table of registers allowed in commands that read/write registers, but
	 * only from the DRM master.
	 */
	const u32 *master_reg_table;
	int master_reg_count;

	/*
	 * Returns the bitmask for the length field of the specified command.
	 * Return 0 for an unrecognized/invalid command.
	 *
	 * If the command parser finds an entry for a command in the ring's
	 * cmd_tables, it gets the command's length based on the table entry.
	 * If not, it calls this function to determine the per-ring length field
	 * encoding for the command (i.e. certain opcode ranges use certain bits
	 * to encode the command length in the header).
	 */
	u32 (*get_cmd_length_mask)(u32 cmd_header);
};

bool intel_ring_initialized(struct intel_engine_cs *ring);

static inline unsigned
intel_ring_flag(struct intel_engine_cs *ring)
{
	return 1 << ring->id;
}

static inline u32
intel_ring_sync_index(struct intel_engine_cs *ring,
		      struct intel_engine_cs *other)
{
	int idx;

	/*
	 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
	 */

	idx = (other - ring) - 1;
	if (idx < 0)
		idx += I915_NUM_RINGS;

	return idx;
}

static inline u32
intel_read_status_page(struct intel_engine_cs *ring,
		       int reg)
{
	/* Ensure that the compiler doesn't optimize away the load. */
	barrier();
	return ring->status_page.page_addr[reg];
}

static inline void
intel_write_status_page(struct intel_engine_cs *ring,
			int reg, u32 value)
{
	ring->status_page.page_addr[reg] = value;
}

/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
 *
 * The area from dword 0x20 to 0x3ff is available for driver usage.
 */
#define I915_GEM_HWS_INDEX		0x20
#define I915_GEM_HWS_SCRATCH_INDEX	0x30
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)

void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
int intel_alloc_ringbuffer_obj(struct drm_device *dev,
			       struct intel_ringbuffer *ringbuf);

void intel_stop_ring_buffer(struct intel_engine_cs *ring);
void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);

int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
static inline void intel_ring_emit(struct intel_engine_cs *ring,
				   u32 data)
{
	struct intel_ringbuffer *ringbuf = ring->buffer;
	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	ringbuf->tail += 4;
}
static inline void intel_ring_advance(struct intel_engine_cs *ring)
{
	struct intel_ringbuffer *ringbuf = ring->buffer;
	ringbuf->tail &= ringbuf->size - 1;
}
int __intel_ring_space(int head, int tail, int size);
int intel_ring_space(struct intel_ringbuffer *ringbuf);
bool intel_ring_stopped(struct intel_engine_cs *ring);
void __intel_ring_advance(struct intel_engine_cs *ring);

int __must_check intel_ring_idle(struct intel_engine_cs *ring);
void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);

void intel_fini_pipe_control(struct intel_engine_cs *ring);
int intel_init_pipe_control(struct intel_engine_cs *ring);

int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_bsd2_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
int intel_init_vebox_ring_buffer(struct drm_device *dev);

u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
void intel_ring_setup_status_page(struct intel_engine_cs *ring);

static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
{
	return ringbuf->tail;
}

static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring)
{
	BUG_ON(ring->outstanding_lazy_seqno == 0);
	return ring->outstanding_lazy_seqno;
}

static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno)
{
	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
		ring->trace_irq_seqno = seqno;
}

/* DRI warts */
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);

#endif /* _INTEL_RINGBUFFER_H_ */
Commit	Line	Data
8187a2b7 ZN	1	#ifndef _INTEL_RINGBUFFER_H_
	2	#define _INTEL_RINGBUFFER_H_
	3
44e895a8 BV	4	#include <linux/hashtable.h>
	5
	6	#define I915_CMD_HASH_ORDER 9
	7
4712274c OM	8	/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
	9	* but keeps the logic simple. Indeed, the whole purpose of this macro is just
	10	* to give some inclination as to some of the magic values used in the various
	11	* workarounds!
	12	*/
	13	#define CACHELINE_BYTES 64
	14
633cf8f5 VS	15	/*
	16	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
	17	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
	18	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
	19	*
	20	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
	21	* cacheline, the Head Pointer must not be greater than the Tail
	22	* Pointer."
	23	*/
	24	#define I915_RING_FREE_SPACE 64
	25
8187a2b7	26	struct intel_hw_status_page {
4225d0f2	27	u32 *page_addr;
8187a2b7	28	unsigned int gfx_addr;
05394f39	29	struct drm_i915_gem_object *obj;
8187a2b7 ZN	30	};
8187a2b7 ZN	31
b7287d80 BW	32	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
b7287d80 BW	33	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
cae5852d	34
b7287d80 BW	35	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
b7287d80 BW	36	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
cae5852d	37
b7287d80 BW	38	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
b7287d80 BW	39	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
cae5852d	40
b7287d80 BW	41	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
b7287d80 BW	42	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
cae5852d	43
b7287d80 BW	44	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
b7287d80 BW	45	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
870e86dd	46
e9fea574	47	#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
9991ae78	48	#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
e9fea574	49
3e78998a BW	50	/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
	51	* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
	52	*/
	53	#define i915_semaphore_seqno_size sizeof(uint64_t)
	54	#define GEN8_SIGNAL_OFFSET(__ring, to) \
	55	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	56	((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	57	(i915_semaphore_seqno_size * (to)))
	58
	59	#define GEN8_WAIT_OFFSET(__ring, from) \
	60	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	61	((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	62	(i915_semaphore_seqno_size * (__ring)->id))
	63
	64	#define GEN8_RING_SEMAPHORE_INIT do { \
	65	if (!dev_priv->semaphore_obj) { \
	66	break; \
	67	} \
	68	ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
	69	ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
	70	ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
	71	ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
	72	ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
	73	ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
	74	} while(0)
	75
f2f4d82f	76	enum intel_ring_hangcheck_action {
da661464	77	HANGCHECK_IDLE = 0,
f2f4d82f JN	78	HANGCHECK_WAIT,
f2f4d82f JN	79	HANGCHECK_ACTIVE,
f260fe7b	80	HANGCHECK_ACTIVE_LOOP,
f2f4d82f JN	81	HANGCHECK_KICK,
	82	HANGCHECK_HUNG,
	83	};
ad8beaea	84
b6b0fac0 MK	85	#define HANGCHECK_SCORE_RING_HUNG 31
b6b0fac0 MK	86
92cab734	87	struct intel_ring_hangcheck {
50877445	88	u64 acthd;
f260fe7b	89	u64 max_acthd;
92cab734	90	u32 seqno;
05407ff8	91	int score;
ad8beaea	92	enum intel_ring_hangcheck_action action;
4be17381	93	int deadlock;
92cab734 MK	94	};
92cab734 MK	95
8ee14975 OM	96	struct intel_ringbuffer {
	97	struct drm_i915_gem_object *obj;
	98	void __iomem *virtual_start;
	99
0c7dd53b DV	100	struct intel_engine_cs *ring;
0c7dd53b DV	101
582d67f0 OM	102	/*
	103	* FIXME: This backpointer is an artifact of the history of how the
	104	* execlist patches came into being. It will get removed once the basic
	105	* code has landed.
	106	*/
	107	struct intel_context *FIXME_lrc_ctx;
	108
8ee14975 OM	109	u32 head;
	110	u32 tail;
	111	int space;
	112	int size;
	113	int effective_size;
	114
	115	/** We track the position of the requests in the ring buffer, and
	116	* when each is retired we increment last_retired_head as the GPU
	117	* must have finished processing the request and so we know we
	118	* can advance the ringbuffer up to that position.
	119	*
	120	* last_retired_head is set to -1 after the value is consumed so
	121	* we can detect new retirements.
	122	*/
	123	u32 last_retired_head;
	124	};
	125
a4872ba6	126	struct intel_engine_cs {
8187a2b7	127	const char *name;
9220434a	128	enum intel_ring_id {
96154f2f DV	129	RCS = 0x0,
	130	VCS,
	131	BCS,
4a3dd19d	132	VECS,
845f74a7	133	VCS2
9220434a	134	} id;
845f74a7	135	#define I915_NUM_RINGS 5
b1a93306	136	#define LAST_USER_RING (VECS + 1)
333e9fe9	137	u32 mmio_base;
8187a2b7	138	struct drm_device *dev;
8ee14975	139	struct intel_ringbuffer *buffer;
8187a2b7	140
8187a2b7 ZN	141	struct intel_hw_status_page status_page;
8187a2b7 ZN	142
c7113cc3	143	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
6a848ccb	144	u32 irq_enable_mask; /* bitmask to enable ring interrupt */
db53a302	145	u32 trace_irq_seqno;
a4872ba6 OM	146	bool __must_check (irq_get)(struct intel_engine_cs ring);
a4872ba6 OM	147	void (irq_put)(struct intel_engine_cs ring);
8187a2b7	148
a4872ba6	149	int (init)(struct intel_engine_cs ring);
8187a2b7	150
86d7f238 AS	151	int (init_context)(struct intel_engine_cs ring);
86d7f238 AS	152
a4872ba6	153	void (write_tail)(struct intel_engine_cs ring,
297b0c5b	154	u32 value);
a4872ba6	155	int __must_check (flush)(struct intel_engine_cs ring,
b72f3acb CW	156	u32 invalidate_domains,
b72f3acb CW	157	u32 flush_domains);
a4872ba6	158	int (add_request)(struct intel_engine_cs ring);
b2eadbc8 CW	159	/* Some chipsets are not quite as coherent as advertised and need
	160	* an expensive kick to force a true read of the up-to-date seqno.
	161	* However, the up-to-date seqno is not always required and the last
	162	* seen value is good enough. Note that the seqno will always be
	163	* monotonic, even if not coherent.
	164	*/
a4872ba6	165	u32 (get_seqno)(struct intel_engine_cs ring,
b2eadbc8	166	bool lazy_coherency);
a4872ba6	167	void (set_seqno)(struct intel_engine_cs ring,
b70ec5bf	168	u32 seqno);
a4872ba6	169	int (dispatch_execbuffer)(struct intel_engine_cs ring,
9bcb144c	170	u64 offset, u32 length,
d7d4eedd CW	171	unsigned flags);
d7d4eedd CW	172	#define I915_DISPATCH_SECURE 0x1
b45305fc	173	#define I915_DISPATCH_PINNED 0x2
a4872ba6	174	void (cleanup)(struct intel_engine_cs ring);
ebc348b2	175
3e78998a BW	176	/* GEN8 signal/wait table - never trust comments!
	177	* signal to signal to signal to signal to signal to
	178	* RCS VCS BCS VECS VCS2
	179	* --------------------------------------------------------------------
	180	* RCS \| NOP (0x00) \| VCS (0x08) \| BCS (0x10) \| VECS (0x18) \| VCS2 (0x20) \|
	181	* \|-------------------------------------------------------------------
	182	* VCS \| RCS (0x28) \| NOP (0x30) \| BCS (0x38) \| VECS (0x40) \| VCS2 (0x48) \|
	183	* \|-------------------------------------------------------------------
	184	* BCS \| RCS (0x50) \| VCS (0x58) \| NOP (0x60) \| VECS (0x68) \| VCS2 (0x70) \|
	185	* \|-------------------------------------------------------------------
	186	* VECS \| RCS (0x78) \| VCS (0x80) \| BCS (0x88) \| NOP (0x90) \| VCS2 (0x98) \|
	187	* \|-------------------------------------------------------------------
	188	* VCS2 \| RCS (0xa0) \| VCS (0xa8) \| BCS (0xb0) \| VECS (0xb8) \| NOP (0xc0) \|
	189	* \|-------------------------------------------------------------------
	190	*
	191	* Generalization:
	192	* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	193	* ie. transpose of g(x, y)
	194	*
	195	* sync from sync from sync from sync from sync from
	196	* RCS VCS BCS VECS VCS2
	197	* --------------------------------------------------------------------
	198	* RCS \| NOP (0x00) \| VCS (0x28) \| BCS (0x50) \| VECS (0x78) \| VCS2 (0xa0) \|
	199	* \|-------------------------------------------------------------------
	200	* VCS \| RCS (0x08) \| NOP (0x30) \| BCS (0x58) \| VECS (0x80) \| VCS2 (0xa8) \|
	201	* \|-------------------------------------------------------------------
	202	* BCS \| RCS (0x10) \| VCS (0x38) \| NOP (0x60) \| VECS (0x88) \| VCS2 (0xb0) \|
	203	* \|-------------------------------------------------------------------
	204	* VECS \| RCS (0x18) \| VCS (0x40) \| BCS (0x68) \| NOP (0x90) \| VCS2 (0xb8) \|
	205	* \|-------------------------------------------------------------------
	206	* VCS2 \| RCS (0x20) \| VCS (0x48) \| BCS (0x70) \| VECS (0x98) \| NOP (0xc0) \|
	207	* \|-------------------------------------------------------------------
	208	*
	209	* Generalization:
	210	* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	211	* ie. transpose of f(x, y)
	212	*/
ebc348b2 BW	213	struct {
ebc348b2 BW	214	u32 sync_seqno[I915_NUM_RINGS-1];
78325f2d	215
3e78998a BW	216	union {
	217	struct {
	218	/* our mbox written by others */
	219	u32 wait[I915_NUM_RINGS];
	220	/* mboxes this ring signals to */
	221	u32 signal[I915_NUM_RINGS];
	222	} mbox;
	223	u64 signal_ggtt[I915_NUM_RINGS];
	224	};
78325f2d BW	225
78325f2d BW	226	/* AKA wait() */
a4872ba6 OM	227	int (sync_to)(struct intel_engine_cs ring,
a4872ba6 OM	228	struct intel_engine_cs *to,
78325f2d	229	u32 seqno);
a4872ba6	230	int (signal)(struct intel_engine_cs signaller,
024a43e1 BW	231	/* num_dwords needed by caller */
024a43e1 BW	232	unsigned int num_dwords);
ebc348b2	233	} semaphore;
ad776f8b	234
4da46e1e	235	/* Execlists */
acdd884a MT	236	spinlock_t execlist_lock;
acdd884a MT	237	struct list_head execlist_queue;
e981e7b1	238	u8 next_context_status_buffer;
73d477f6	239	u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
4da46e1e	240	int (emit_request)(struct intel_ringbuffer ringbuf);
4712274c OM	241	int (emit_flush)(struct intel_ringbuffer ringbuf,
	242	u32 invalidate_domains,
	243	u32 flush_domains);
15648585 OM	244	int (emit_bb_start)(struct intel_ringbuffer ringbuf,
15648585 OM	245	u64 offset, unsigned flags);
4da46e1e	246
8187a2b7 ZN	247	/**
	248	* List of objects currently involved in rendering from the
	249	* ringbuffer.
	250	*
	251	* Includes buffers having the contents of their GPU caches
	252	* flushed, not necessarily primitives. last_rendering_seqno
	253	* represents when the rendering involved will be completed.
	254	*
	255	* A reference is held on the buffer while on this list.
	256	*/
	257	struct list_head active_list;
	258
	259	/**
	260	* List of breadcrumbs associated with GPU requests currently
	261	* outstanding.
	262	*/
	263	struct list_head request_list;
	264
a56ba56c CW	265	/**
	266	* Do we have some not yet emitted requests outstanding?
	267	*/
3c0e234c	268	struct drm_i915_gem_request *preallocated_lazy_request;
1823521d	269	u32 outstanding_lazy_seqno;
cc889e0f	270	bool gpu_caches_dirty;
c65355bb	271	bool fbc_dirty;
a56ba56c	272
8187a2b7	273	wait_queue_head_t irq_queue;
8d19215b	274
273497e5 OM	275	struct intel_context *default_context;
273497e5 OM	276	struct intel_context *last_context;
40521054	277
92cab734 MK	278	struct intel_ring_hangcheck hangcheck;
92cab734 MK	279
0d1aacac CW	280	struct {
	281	struct drm_i915_gem_object *obj;
	282	u32 gtt_offset;
	283	volatile u32 *cpu_page;
	284	} scratch;
351e3db2	285
44e895a8 BV	286	bool needs_cmd_parser;
44e895a8 BV	287
351e3db2	288	/*
44e895a8	289	* Table of commands the command parser needs to know about
351e3db2 BV	290	* for this ring.
351e3db2 BV	291	*/
44e895a8	292	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
351e3db2 BV	293
	294	/*
	295	* Table of registers allowed in commands that read/write registers.
	296	*/
	297	const u32 *reg_table;
	298	int reg_count;
	299
	300	/*
	301	* Table of registers allowed in commands that read/write registers, but
	302	* only from the DRM master.
	303	*/
	304	const u32 *master_reg_table;
	305	int master_reg_count;
	306
	307	/*
	308	* Returns the bitmask for the length field of the specified command.
	309	* Return 0 for an unrecognized/invalid command.
	310	*
	311	* If the command parser finds an entry for a command in the ring's
	312	* cmd_tables, it gets the command's length based on the table entry.
	313	* If not, it calls this function to determine the per-ring length field
	314	* encoding for the command (i.e. certain opcode ranges use certain bits
	315	* to encode the command length in the header).
	316	*/
	317	u32 (*get_cmd_length_mask)(u32 cmd_header);
8187a2b7 ZN	318	};
8187a2b7 ZN	319
48d82387	320	bool intel_ring_initialized(struct intel_engine_cs *ring);
b4519513	321
96154f2f	322	static inline unsigned
a4872ba6	323	intel_ring_flag(struct intel_engine_cs *ring)
96154f2f DV	324	{
	325	return 1 << ring->id;
	326	}
	327
1ec14ad3	328	static inline u32
a4872ba6 OM	329	intel_ring_sync_index(struct intel_engine_cs *ring,
a4872ba6 OM	330	struct intel_engine_cs *other)
1ec14ad3 CW	331	{
	332	int idx;
	333
	334	/*
ddd4dbc6 RV	335	* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	336	* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	337	* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	338	* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	339	* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
1ec14ad3 CW	340	*/
	341
	342	idx = (other - ring) - 1;
	343	if (idx < 0)
	344	idx += I915_NUM_RINGS;
	345
	346	return idx;
	347	}
	348
8187a2b7	349	static inline u32
a4872ba6	350	intel_read_status_page(struct intel_engine_cs *ring,
78501eac	351	int reg)
8187a2b7	352	{
4225d0f2 DV	353	/* Ensure that the compiler doesn't optimize away the load. */
	354	barrier();
	355	return ring->status_page.page_addr[reg];
8187a2b7 ZN	356	}
8187a2b7 ZN	357
b70ec5bf	358	static inline void
a4872ba6	359	intel_write_status_page(struct intel_engine_cs *ring,
b70ec5bf MK	360	int reg, u32 value)
	361	{
	362	ring->status_page.page_addr[reg] = value;
	363	}
	364
311bd68e CW	365	/**
	366	* Reads a dword out of the status page, which is written to from the command
	367	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
	368	* MI_STORE_DATA_IMM.
	369	*
	370	* The following dwords have a reserved meaning:
	371	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
	372	* 0x04: ring 0 head pointer
	373	* 0x05: ring 1 head pointer (915-class)
	374	* 0x06: ring 2 head pointer (915-class)
	375	* 0x10-0x1b: Context status DWords (GM45)
	376	* 0x1f: Last written status offset. (GM45)
	377	*
	378	* The area from dword 0x20 to 0x3ff is available for driver usage.
	379	*/
311bd68e	380	#define I915_GEM_HWS_INDEX 0x20
9a289771 JB	381	#define I915_GEM_HWS_SCRATCH_INDEX 0x30
9a289771 JB	382	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
311bd68e	383
84c2377f OM	384	void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
	385	int intel_alloc_ringbuffer_obj(struct drm_device *dev,
	386	struct intel_ringbuffer *ringbuf);
	387
a4872ba6 OM	388	void intel_stop_ring_buffer(struct intel_engine_cs *ring);
a4872ba6 OM	389	void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
96f298aa	390
a4872ba6 OM	391	int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
	392	int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
	393	static inline void intel_ring_emit(struct intel_engine_cs *ring,
78501eac	394	u32 data)
e898cd22	395	{
93b0a4e0 OM	396	struct intel_ringbuffer *ringbuf = ring->buffer;
	397	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	398	ringbuf->tail += 4;
e898cd22	399	}
a4872ba6	400	static inline void intel_ring_advance(struct intel_engine_cs *ring)
09246732	401	{
93b0a4e0 OM	402	struct intel_ringbuffer *ringbuf = ring->buffer;
93b0a4e0 OM	403	ringbuf->tail &= ringbuf->size - 1;
09246732	404	}
82e104cc OM	405	int __intel_ring_space(int head, int tail, int size);
	406	int intel_ring_space(struct intel_ringbuffer *ringbuf);
	407	bool intel_ring_stopped(struct intel_engine_cs *ring);
a4872ba6	408	void __intel_ring_advance(struct intel_engine_cs *ring);
09246732	409
a4872ba6 OM	410	int __must_check intel_ring_idle(struct intel_engine_cs *ring);
	411	void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
	412	int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
	413	int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);
8187a2b7	414
9b1136d5 OM	415	void intel_fini_pipe_control(struct intel_engine_cs *ring);
	416	int intel_init_pipe_control(struct intel_engine_cs *ring);
	417
5c1143bb XH	418	int intel_init_render_ring_buffer(struct drm_device *dev);
5c1143bb XH	419	int intel_init_bsd_ring_buffer(struct drm_device *dev);
845f74a7	420	int intel_init_bsd2_ring_buffer(struct drm_device *dev);
549f7365	421	int intel_init_blt_ring_buffer(struct drm_device *dev);
9a8a2213	422	int intel_init_vebox_ring_buffer(struct drm_device *dev);
8187a2b7	423
a4872ba6 OM	424	u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
a4872ba6 OM	425	void intel_ring_setup_status_page(struct intel_engine_cs *ring);
79f321b7	426
1b5d063f	427	static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
a71d8d94	428	{
1b5d063f	429	return ringbuf->tail;
a71d8d94 CW	430	}
a71d8d94 CW	431
a4872ba6	432	static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring)
9d773091	433	{
1823521d CW	434	BUG_ON(ring->outstanding_lazy_seqno == 0);
1823521d CW	435	return ring->outstanding_lazy_seqno;
9d773091 CW	436	}
9d773091 CW	437
a4872ba6	438	static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno)
db53a302 CW	439	{
	440	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
	441	ring->trace_irq_seqno = seqno;
	442	}
	443
e8616b6c CW	444	/* DRI warts */
	445	int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
	446
8187a2b7	447	#endif /* _INTEL_RINGBUFFER_H_ */