Commit | Line | Data |
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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
1ec14ad3 CW |
4 | enum { |
5 | RCS = 0x0, | |
6 | VCS, | |
7 | BCS, | |
8 | I915_NUM_RINGS, | |
9 | }; | |
10 | ||
8187a2b7 | 11 | struct intel_hw_status_page { |
78501eac | 12 | u32 __iomem *page_addr; |
8187a2b7 | 13 | unsigned int gfx_addr; |
05394f39 | 14 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
15 | }; |
16 | ||
cae5852d ZN |
17 | #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg) |
18 | ||
9862e600 CW |
19 | #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base)) |
20 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 21 | |
9862e600 CW |
22 | #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base)) |
23 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 24 | |
9862e600 CW |
25 | #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base)) |
26 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 27 | |
9862e600 CW |
28 | #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base)) |
29 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
870e86dd | 30 | |
9862e600 CW |
31 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
32 | #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base)) | |
0f46832f | 33 | |
9862e600 CW |
34 | #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base)) |
35 | #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base)) | |
36 | #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base)) | |
1ec14ad3 | 37 | |
8187a2b7 ZN |
38 | struct intel_ring_buffer { |
39 | const char *name; | |
9220434a CW |
40 | enum intel_ring_id { |
41 | RING_RENDER = 0x1, | |
42 | RING_BSD = 0x2, | |
549f7365 | 43 | RING_BLT = 0x4, |
9220434a | 44 | } id; |
333e9fe9 | 45 | u32 mmio_base; |
8187a2b7 ZN |
46 | void *virtual_start; |
47 | struct drm_device *dev; | |
05394f39 | 48 | struct drm_i915_gem_object *obj; |
8187a2b7 | 49 | |
8c0a6bfe CW |
50 | u32 actual_head; |
51 | u32 head; | |
52 | u32 tail; | |
780f0ca3 | 53 | int space; |
c2c347a9 | 54 | int size; |
55249baa | 55 | int effective_size; |
8187a2b7 ZN |
56 | struct intel_hw_status_page status_page; |
57 | ||
01a03331 | 58 | u32 irq_refcount; |
0f46832f | 59 | u32 irq_mask; |
b2223497 CW |
60 | u32 irq_seqno; /* last seq seem at irq time */ |
61 | u32 waiting_seqno; | |
1ec14ad3 | 62 | u32 sync_seqno[I915_NUM_RINGS-1]; |
b13c2b96 | 63 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
1ec14ad3 | 64 | void (*irq_put)(struct intel_ring_buffer *ring); |
8187a2b7 | 65 | |
78501eac | 66 | int (*init)(struct intel_ring_buffer *ring); |
8187a2b7 | 67 | |
78501eac | 68 | void (*write_tail)(struct intel_ring_buffer *ring, |
297b0c5b | 69 | u32 value); |
b72f3acb CW |
70 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
71 | u32 invalidate_domains, | |
72 | u32 flush_domains); | |
3cce469c CW |
73 | int (*add_request)(struct intel_ring_buffer *ring, |
74 | u32 *seqno); | |
78501eac CW |
75 | u32 (*get_seqno)(struct intel_ring_buffer *ring); |
76 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, | |
c4e7a414 | 77 | u32 offset, u32 length); |
8d19215b | 78 | void (*cleanup)(struct intel_ring_buffer *ring); |
8187a2b7 ZN |
79 | |
80 | /** | |
81 | * List of objects currently involved in rendering from the | |
82 | * ringbuffer. | |
83 | * | |
84 | * Includes buffers having the contents of their GPU caches | |
85 | * flushed, not necessarily primitives. last_rendering_seqno | |
86 | * represents when the rendering involved will be completed. | |
87 | * | |
88 | * A reference is held on the buffer while on this list. | |
89 | */ | |
90 | struct list_head active_list; | |
91 | ||
92 | /** | |
93 | * List of breadcrumbs associated with GPU requests currently | |
94 | * outstanding. | |
95 | */ | |
96 | struct list_head request_list; | |
97 | ||
64193406 CW |
98 | /** |
99 | * List of objects currently pending a GPU write flush. | |
100 | * | |
101 | * All elements on this list will belong to either the | |
102 | * active_list or flushing_list, last_rendering_seqno can | |
103 | * be used to differentiate between the two elements. | |
104 | */ | |
105 | struct list_head gpu_write_list; | |
106 | ||
a56ba56c CW |
107 | /** |
108 | * Do we have some not yet emitted requests outstanding? | |
109 | */ | |
5d97eb69 | 110 | u32 outstanding_lazy_request; |
a56ba56c | 111 | |
8187a2b7 ZN |
112 | wait_queue_head_t irq_queue; |
113 | drm_local_map_t map; | |
8d19215b ZN |
114 | |
115 | void *private; | |
8187a2b7 ZN |
116 | }; |
117 | ||
1ec14ad3 CW |
118 | static inline u32 |
119 | intel_ring_sync_index(struct intel_ring_buffer *ring, | |
120 | struct intel_ring_buffer *other) | |
121 | { | |
122 | int idx; | |
123 | ||
124 | /* | |
125 | * cs -> 0 = vcs, 1 = bcs | |
126 | * vcs -> 0 = bcs, 1 = cs, | |
127 | * bcs -> 0 = cs, 1 = vcs. | |
128 | */ | |
129 | ||
130 | idx = (other - ring) - 1; | |
131 | if (idx < 0) | |
132 | idx += I915_NUM_RINGS; | |
133 | ||
134 | return idx; | |
135 | } | |
136 | ||
8187a2b7 ZN |
137 | static inline u32 |
138 | intel_read_status_page(struct intel_ring_buffer *ring, | |
78501eac | 139 | int reg) |
8187a2b7 | 140 | { |
78501eac | 141 | return ioread32(ring->status_page.page_addr + reg); |
8187a2b7 ZN |
142 | } |
143 | ||
78501eac | 144 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
e1f99ce6 CW |
145 | int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); |
146 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); | |
78501eac CW |
147 | |
148 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, | |
149 | u32 data) | |
e898cd22 | 150 | { |
78501eac | 151 | iowrite32(data, ring->virtual_start + ring->tail); |
e898cd22 CW |
152 | ring->tail += 4; |
153 | } | |
154 | ||
78501eac | 155 | void intel_ring_advance(struct intel_ring_buffer *ring); |
8187a2b7 | 156 | |
78501eac | 157 | u32 intel_ring_get_seqno(struct intel_ring_buffer *ring); |
1ec14ad3 CW |
158 | int intel_ring_sync(struct intel_ring_buffer *ring, |
159 | struct intel_ring_buffer *to, | |
160 | u32 seqno); | |
8187a2b7 | 161 | |
5c1143bb XH |
162 | int intel_init_render_ring_buffer(struct drm_device *dev); |
163 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
549f7365 | 164 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
8187a2b7 | 165 | |
78501eac CW |
166 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
167 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); | |
79f321b7 | 168 | |
8187a2b7 | 169 | #endif /* _INTEL_RINGBUFFER_H_ */ |