Commit | Line | Data |
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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
1ec14ad3 CW |
4 | enum { |
5 | RCS = 0x0, | |
6 | VCS, | |
7 | BCS, | |
8 | I915_NUM_RINGS, | |
9 | }; | |
10 | ||
8187a2b7 | 11 | struct intel_hw_status_page { |
78501eac | 12 | u32 __iomem *page_addr; |
8187a2b7 | 13 | unsigned int gfx_addr; |
05394f39 | 14 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
15 | }; |
16 | ||
b7287d80 BW |
17 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
18 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 19 | |
b7287d80 BW |
20 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
21 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 22 | |
b7287d80 BW |
23 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
24 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 25 | |
b7287d80 BW |
26 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
27 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
cae5852d | 28 | |
b7287d80 BW |
29 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
30 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | |
870e86dd | 31 | |
b7287d80 BW |
32 | #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) |
33 | #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) | |
34 | #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) | |
1ec14ad3 | 35 | |
8187a2b7 ZN |
36 | struct intel_ring_buffer { |
37 | const char *name; | |
9220434a CW |
38 | enum intel_ring_id { |
39 | RING_RENDER = 0x1, | |
40 | RING_BSD = 0x2, | |
549f7365 | 41 | RING_BLT = 0x4, |
9220434a | 42 | } id; |
333e9fe9 | 43 | u32 mmio_base; |
311bd68e | 44 | void __iomem *virtual_start; |
8187a2b7 | 45 | struct drm_device *dev; |
05394f39 | 46 | struct drm_i915_gem_object *obj; |
8187a2b7 | 47 | |
8c0a6bfe CW |
48 | u32 head; |
49 | u32 tail; | |
780f0ca3 | 50 | int space; |
c2c347a9 | 51 | int size; |
55249baa | 52 | int effective_size; |
8187a2b7 ZN |
53 | struct intel_hw_status_page status_page; |
54 | ||
0dc79fb2 | 55 | spinlock_t irq_lock; |
01a03331 | 56 | u32 irq_refcount; |
0f46832f | 57 | u32 irq_mask; |
b2223497 | 58 | u32 irq_seqno; /* last seq seem at irq time */ |
db53a302 | 59 | u32 trace_irq_seqno; |
b2223497 | 60 | u32 waiting_seqno; |
1ec14ad3 | 61 | u32 sync_seqno[I915_NUM_RINGS-1]; |
b13c2b96 | 62 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
1ec14ad3 | 63 | void (*irq_put)(struct intel_ring_buffer *ring); |
8187a2b7 | 64 | |
78501eac | 65 | int (*init)(struct intel_ring_buffer *ring); |
8187a2b7 | 66 | |
78501eac | 67 | void (*write_tail)(struct intel_ring_buffer *ring, |
297b0c5b | 68 | u32 value); |
b72f3acb CW |
69 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
70 | u32 invalidate_domains, | |
71 | u32 flush_domains); | |
3cce469c CW |
72 | int (*add_request)(struct intel_ring_buffer *ring, |
73 | u32 *seqno); | |
78501eac CW |
74 | u32 (*get_seqno)(struct intel_ring_buffer *ring); |
75 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, | |
c4e7a414 | 76 | u32 offset, u32 length); |
8d19215b | 77 | void (*cleanup)(struct intel_ring_buffer *ring); |
8187a2b7 ZN |
78 | |
79 | /** | |
80 | * List of objects currently involved in rendering from the | |
81 | * ringbuffer. | |
82 | * | |
83 | * Includes buffers having the contents of their GPU caches | |
84 | * flushed, not necessarily primitives. last_rendering_seqno | |
85 | * represents when the rendering involved will be completed. | |
86 | * | |
87 | * A reference is held on the buffer while on this list. | |
88 | */ | |
89 | struct list_head active_list; | |
90 | ||
91 | /** | |
92 | * List of breadcrumbs associated with GPU requests currently | |
93 | * outstanding. | |
94 | */ | |
95 | struct list_head request_list; | |
96 | ||
64193406 CW |
97 | /** |
98 | * List of objects currently pending a GPU write flush. | |
99 | * | |
100 | * All elements on this list will belong to either the | |
101 | * active_list or flushing_list, last_rendering_seqno can | |
102 | * be used to differentiate between the two elements. | |
103 | */ | |
104 | struct list_head gpu_write_list; | |
105 | ||
a56ba56c CW |
106 | /** |
107 | * Do we have some not yet emitted requests outstanding? | |
108 | */ | |
5d97eb69 | 109 | u32 outstanding_lazy_request; |
a56ba56c | 110 | |
8187a2b7 ZN |
111 | wait_queue_head_t irq_queue; |
112 | drm_local_map_t map; | |
8d19215b ZN |
113 | |
114 | void *private; | |
8187a2b7 ZN |
115 | }; |
116 | ||
1ec14ad3 CW |
117 | static inline u32 |
118 | intel_ring_sync_index(struct intel_ring_buffer *ring, | |
119 | struct intel_ring_buffer *other) | |
120 | { | |
121 | int idx; | |
122 | ||
123 | /* | |
124 | * cs -> 0 = vcs, 1 = bcs | |
125 | * vcs -> 0 = bcs, 1 = cs, | |
126 | * bcs -> 0 = cs, 1 = vcs. | |
127 | */ | |
128 | ||
129 | idx = (other - ring) - 1; | |
130 | if (idx < 0) | |
131 | idx += I915_NUM_RINGS; | |
132 | ||
133 | return idx; | |
134 | } | |
135 | ||
8187a2b7 ZN |
136 | static inline u32 |
137 | intel_read_status_page(struct intel_ring_buffer *ring, | |
78501eac | 138 | int reg) |
8187a2b7 | 139 | { |
78501eac | 140 | return ioread32(ring->status_page.page_addr + reg); |
8187a2b7 ZN |
141 | } |
142 | ||
311bd68e CW |
143 | /** |
144 | * Reads a dword out of the status page, which is written to from the command | |
145 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
146 | * MI_STORE_DATA_IMM. | |
147 | * | |
148 | * The following dwords have a reserved meaning: | |
149 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
150 | * 0x04: ring 0 head pointer | |
151 | * 0x05: ring 1 head pointer (915-class) | |
152 | * 0x06: ring 2 head pointer (915-class) | |
153 | * 0x10-0x1b: Context status DWords (GM45) | |
154 | * 0x1f: Last written status offset. (GM45) | |
155 | * | |
156 | * The area from dword 0x20 to 0x3ff is available for driver usage. | |
157 | */ | |
158 | #define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg) | |
159 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) | |
160 | #define I915_GEM_HWS_INDEX 0x20 | |
161 | #define I915_BREADCRUMB_INDEX 0x21 | |
162 | ||
78501eac | 163 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
96f298aa | 164 | |
e1f99ce6 | 165 | int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); |
96f298aa BW |
166 | static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) |
167 | { | |
168 | return intel_wait_ring_buffer(ring, ring->space - 8); | |
169 | } | |
170 | ||
e1f99ce6 | 171 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
78501eac CW |
172 | |
173 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, | |
174 | u32 data) | |
e898cd22 | 175 | { |
78501eac | 176 | iowrite32(data, ring->virtual_start + ring->tail); |
e898cd22 CW |
177 | ring->tail += 4; |
178 | } | |
179 | ||
78501eac | 180 | void intel_ring_advance(struct intel_ring_buffer *ring); |
8187a2b7 | 181 | |
78501eac | 182 | u32 intel_ring_get_seqno(struct intel_ring_buffer *ring); |
1ec14ad3 CW |
183 | int intel_ring_sync(struct intel_ring_buffer *ring, |
184 | struct intel_ring_buffer *to, | |
185 | u32 seqno); | |
8187a2b7 | 186 | |
5c1143bb XH |
187 | int intel_init_render_ring_buffer(struct drm_device *dev); |
188 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
549f7365 | 189 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
8187a2b7 | 190 | |
78501eac CW |
191 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
192 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); | |
79f321b7 | 193 | |
db53a302 CW |
194 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
195 | { | |
196 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) | |
197 | ring->trace_irq_seqno = seqno; | |
198 | } | |
199 | ||
e8616b6c CW |
200 | /* DRI warts */ |
201 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); | |
202 | ||
8187a2b7 | 203 | #endif /* _INTEL_RINGBUFFER_H_ */ |