Commit | Line | Data |
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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
633cf8f5 VS |
4 | /* |
5 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" | |
6 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" | |
7 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" | |
8 | * | |
9 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same | |
10 | * cacheline, the Head Pointer must not be greater than the Tail | |
11 | * Pointer." | |
12 | */ | |
13 | #define I915_RING_FREE_SPACE 64 | |
14 | ||
8187a2b7 | 15 | struct intel_hw_status_page { |
4225d0f2 | 16 | u32 *page_addr; |
8187a2b7 | 17 | unsigned int gfx_addr; |
05394f39 | 18 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
19 | }; |
20 | ||
b7287d80 BW |
21 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
22 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 23 | |
b7287d80 BW |
24 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
25 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 26 | |
b7287d80 BW |
27 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
28 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 29 | |
b7287d80 BW |
30 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
31 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
cae5852d | 32 | |
b7287d80 BW |
33 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
34 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | |
870e86dd | 35 | |
e9fea574 | 36 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
9991ae78 | 37 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) |
e9fea574 | 38 | |
f2f4d82f | 39 | enum intel_ring_hangcheck_action { |
da661464 | 40 | HANGCHECK_IDLE = 0, |
f2f4d82f JN |
41 | HANGCHECK_WAIT, |
42 | HANGCHECK_ACTIVE, | |
43 | HANGCHECK_KICK, | |
44 | HANGCHECK_HUNG, | |
45 | }; | |
ad8beaea | 46 | |
b6b0fac0 MK |
47 | #define HANGCHECK_SCORE_RING_HUNG 31 |
48 | ||
92cab734 | 49 | struct intel_ring_hangcheck { |
50877445 | 50 | u64 acthd; |
92cab734 | 51 | u32 seqno; |
05407ff8 | 52 | int score; |
ad8beaea | 53 | enum intel_ring_hangcheck_action action; |
50877445 | 54 | bool deadlock; |
92cab734 MK |
55 | }; |
56 | ||
8187a2b7 ZN |
57 | struct intel_ring_buffer { |
58 | const char *name; | |
9220434a | 59 | enum intel_ring_id { |
96154f2f DV |
60 | RCS = 0x0, |
61 | VCS, | |
62 | BCS, | |
4a3dd19d | 63 | VECS, |
845f74a7 | 64 | VCS2 |
9220434a | 65 | } id; |
845f74a7 | 66 | #define I915_NUM_RINGS 5 |
b1a93306 | 67 | #define LAST_USER_RING (VECS + 1) |
333e9fe9 | 68 | u32 mmio_base; |
311bd68e | 69 | void __iomem *virtual_start; |
8187a2b7 | 70 | struct drm_device *dev; |
05394f39 | 71 | struct drm_i915_gem_object *obj; |
8187a2b7 | 72 | |
8c0a6bfe CW |
73 | u32 head; |
74 | u32 tail; | |
780f0ca3 | 75 | int space; |
c2c347a9 | 76 | int size; |
55249baa | 77 | int effective_size; |
8187a2b7 ZN |
78 | struct intel_hw_status_page status_page; |
79 | ||
a71d8d94 CW |
80 | /** We track the position of the requests in the ring buffer, and |
81 | * when each is retired we increment last_retired_head as the GPU | |
82 | * must have finished processing the request and so we know we | |
83 | * can advance the ringbuffer up to that position. | |
84 | * | |
85 | * last_retired_head is set to -1 after the value is consumed so | |
86 | * we can detect new retirements. | |
87 | */ | |
88 | u32 last_retired_head; | |
89 | ||
c7113cc3 | 90 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
6a848ccb | 91 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
db53a302 | 92 | u32 trace_irq_seqno; |
1ec14ad3 | 93 | u32 sync_seqno[I915_NUM_RINGS-1]; |
b13c2b96 | 94 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
1ec14ad3 | 95 | void (*irq_put)(struct intel_ring_buffer *ring); |
8187a2b7 | 96 | |
78501eac | 97 | int (*init)(struct intel_ring_buffer *ring); |
8187a2b7 | 98 | |
78501eac | 99 | void (*write_tail)(struct intel_ring_buffer *ring, |
297b0c5b | 100 | u32 value); |
b72f3acb CW |
101 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
102 | u32 invalidate_domains, | |
103 | u32 flush_domains); | |
9d773091 | 104 | int (*add_request)(struct intel_ring_buffer *ring); |
b2eadbc8 CW |
105 | /* Some chipsets are not quite as coherent as advertised and need |
106 | * an expensive kick to force a true read of the up-to-date seqno. | |
107 | * However, the up-to-date seqno is not always required and the last | |
108 | * seen value is good enough. Note that the seqno will always be | |
109 | * monotonic, even if not coherent. | |
110 | */ | |
111 | u32 (*get_seqno)(struct intel_ring_buffer *ring, | |
112 | bool lazy_coherency); | |
b70ec5bf MK |
113 | void (*set_seqno)(struct intel_ring_buffer *ring, |
114 | u32 seqno); | |
78501eac | 115 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
d7d4eedd CW |
116 | u32 offset, u32 length, |
117 | unsigned flags); | |
118 | #define I915_DISPATCH_SECURE 0x1 | |
b45305fc | 119 | #define I915_DISPATCH_PINNED 0x2 |
8d19215b | 120 | void (*cleanup)(struct intel_ring_buffer *ring); |
c8c99b0f BW |
121 | int (*sync_to)(struct intel_ring_buffer *ring, |
122 | struct intel_ring_buffer *to, | |
123 | u32 seqno); | |
ad776f8b | 124 | |
5586181f BW |
125 | /* our mbox written by others */ |
126 | u32 semaphore_register[I915_NUM_RINGS]; | |
ad776f8b BW |
127 | /* mboxes this ring signals to */ |
128 | u32 signal_mbox[I915_NUM_RINGS]; | |
129 | ||
8187a2b7 ZN |
130 | /** |
131 | * List of objects currently involved in rendering from the | |
132 | * ringbuffer. | |
133 | * | |
134 | * Includes buffers having the contents of their GPU caches | |
135 | * flushed, not necessarily primitives. last_rendering_seqno | |
136 | * represents when the rendering involved will be completed. | |
137 | * | |
138 | * A reference is held on the buffer while on this list. | |
139 | */ | |
140 | struct list_head active_list; | |
141 | ||
142 | /** | |
143 | * List of breadcrumbs associated with GPU requests currently | |
144 | * outstanding. | |
145 | */ | |
146 | struct list_head request_list; | |
147 | ||
a56ba56c CW |
148 | /** |
149 | * Do we have some not yet emitted requests outstanding? | |
150 | */ | |
3c0e234c | 151 | struct drm_i915_gem_request *preallocated_lazy_request; |
1823521d | 152 | u32 outstanding_lazy_seqno; |
cc889e0f | 153 | bool gpu_caches_dirty; |
c65355bb | 154 | bool fbc_dirty; |
a56ba56c | 155 | |
8187a2b7 | 156 | wait_queue_head_t irq_queue; |
8d19215b | 157 | |
40521054 | 158 | struct i915_hw_context *default_context; |
112522f6 | 159 | struct i915_hw_context *last_context; |
40521054 | 160 | |
92cab734 MK |
161 | struct intel_ring_hangcheck hangcheck; |
162 | ||
0d1aacac CW |
163 | struct { |
164 | struct drm_i915_gem_object *obj; | |
165 | u32 gtt_offset; | |
166 | volatile u32 *cpu_page; | |
167 | } scratch; | |
351e3db2 BV |
168 | |
169 | /* | |
170 | * Tables of commands the command parser needs to know about | |
171 | * for this ring. | |
172 | */ | |
173 | const struct drm_i915_cmd_table *cmd_tables; | |
174 | int cmd_table_count; | |
175 | ||
176 | /* | |
177 | * Table of registers allowed in commands that read/write registers. | |
178 | */ | |
179 | const u32 *reg_table; | |
180 | int reg_count; | |
181 | ||
182 | /* | |
183 | * Table of registers allowed in commands that read/write registers, but | |
184 | * only from the DRM master. | |
185 | */ | |
186 | const u32 *master_reg_table; | |
187 | int master_reg_count; | |
188 | ||
189 | /* | |
190 | * Returns the bitmask for the length field of the specified command. | |
191 | * Return 0 for an unrecognized/invalid command. | |
192 | * | |
193 | * If the command parser finds an entry for a command in the ring's | |
194 | * cmd_tables, it gets the command's length based on the table entry. | |
195 | * If not, it calls this function to determine the per-ring length field | |
196 | * encoding for the command (i.e. certain opcode ranges use certain bits | |
197 | * to encode the command length in the header). | |
198 | */ | |
199 | u32 (*get_cmd_length_mask)(u32 cmd_header); | |
8187a2b7 ZN |
200 | }; |
201 | ||
b4519513 CW |
202 | static inline bool |
203 | intel_ring_initialized(struct intel_ring_buffer *ring) | |
204 | { | |
205 | return ring->obj != NULL; | |
206 | } | |
207 | ||
96154f2f DV |
208 | static inline unsigned |
209 | intel_ring_flag(struct intel_ring_buffer *ring) | |
210 | { | |
211 | return 1 << ring->id; | |
212 | } | |
213 | ||
1ec14ad3 CW |
214 | static inline u32 |
215 | intel_ring_sync_index(struct intel_ring_buffer *ring, | |
216 | struct intel_ring_buffer *other) | |
217 | { | |
218 | int idx; | |
219 | ||
220 | /* | |
221 | * cs -> 0 = vcs, 1 = bcs | |
222 | * vcs -> 0 = bcs, 1 = cs, | |
223 | * bcs -> 0 = cs, 1 = vcs. | |
224 | */ | |
225 | ||
226 | idx = (other - ring) - 1; | |
227 | if (idx < 0) | |
228 | idx += I915_NUM_RINGS; | |
229 | ||
230 | return idx; | |
231 | } | |
232 | ||
8187a2b7 ZN |
233 | static inline u32 |
234 | intel_read_status_page(struct intel_ring_buffer *ring, | |
78501eac | 235 | int reg) |
8187a2b7 | 236 | { |
4225d0f2 DV |
237 | /* Ensure that the compiler doesn't optimize away the load. */ |
238 | barrier(); | |
239 | return ring->status_page.page_addr[reg]; | |
8187a2b7 ZN |
240 | } |
241 | ||
b70ec5bf MK |
242 | static inline void |
243 | intel_write_status_page(struct intel_ring_buffer *ring, | |
244 | int reg, u32 value) | |
245 | { | |
246 | ring->status_page.page_addr[reg] = value; | |
247 | } | |
248 | ||
311bd68e CW |
249 | /** |
250 | * Reads a dword out of the status page, which is written to from the command | |
251 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
252 | * MI_STORE_DATA_IMM. | |
253 | * | |
254 | * The following dwords have a reserved meaning: | |
255 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
256 | * 0x04: ring 0 head pointer | |
257 | * 0x05: ring 1 head pointer (915-class) | |
258 | * 0x06: ring 2 head pointer (915-class) | |
259 | * 0x10-0x1b: Context status DWords (GM45) | |
260 | * 0x1f: Last written status offset. (GM45) | |
261 | * | |
262 | * The area from dword 0x20 to 0x3ff is available for driver usage. | |
263 | */ | |
311bd68e | 264 | #define I915_GEM_HWS_INDEX 0x20 |
9a289771 JB |
265 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
266 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) | |
311bd68e | 267 | |
e3efda49 | 268 | void intel_stop_ring_buffer(struct intel_ring_buffer *ring); |
78501eac | 269 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
96f298aa | 270 | |
e1f99ce6 | 271 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
753b1ad4 | 272 | int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring); |
78501eac CW |
273 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, |
274 | u32 data) | |
e898cd22 | 275 | { |
78501eac | 276 | iowrite32(data, ring->virtual_start + ring->tail); |
e898cd22 CW |
277 | ring->tail += 4; |
278 | } | |
09246732 CW |
279 | static inline void intel_ring_advance(struct intel_ring_buffer *ring) |
280 | { | |
281 | ring->tail &= ring->size - 1; | |
282 | } | |
283 | void __intel_ring_advance(struct intel_ring_buffer *ring); | |
284 | ||
3e960501 | 285 | int __must_check intel_ring_idle(struct intel_ring_buffer *ring); |
f7e98ad4 | 286 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno); |
a7b9761d CW |
287 | int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); |
288 | int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); | |
8187a2b7 | 289 | |
5c1143bb XH |
290 | int intel_init_render_ring_buffer(struct drm_device *dev); |
291 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
845f74a7 | 292 | int intel_init_bsd2_ring_buffer(struct drm_device *dev); |
549f7365 | 293 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
9a8a2213 | 294 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
8187a2b7 | 295 | |
50877445 | 296 | u64 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
78501eac | 297 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); |
79f321b7 | 298 | |
a71d8d94 CW |
299 | static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) |
300 | { | |
301 | return ring->tail; | |
302 | } | |
303 | ||
9d773091 CW |
304 | static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring) |
305 | { | |
1823521d CW |
306 | BUG_ON(ring->outstanding_lazy_seqno == 0); |
307 | return ring->outstanding_lazy_seqno; | |
9d773091 CW |
308 | } |
309 | ||
db53a302 CW |
310 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
311 | { | |
312 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) | |
313 | ring->trace_irq_seqno = seqno; | |
314 | } | |
315 | ||
e8616b6c CW |
316 | /* DRI warts */ |
317 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); | |
318 | ||
8187a2b7 | 319 | #endif /* _INTEL_RINGBUFFER_H_ */ |