[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.h

#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_

#include <linux/hashtable.h>
#include "i915_gem_batch_pool.h"

#define I915_CMD_HASH_ORDER 9

/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
 * to give some inclination as to some of the magic values used in the various
 * workarounds!
 */
#define CACHELINE_BYTES 64

/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64

struct  intel_hw_status_page {
	u32		*page_addr;
	unsigned int	gfx_addr;
	struct		drm_i915_gem_object *obj;
};

#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)

#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)

#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)

#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)

#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)

#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)

/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
 */
#define i915_semaphore_seqno_size sizeof(uint64_t)
#define GEN8_SIGNAL_OFFSET(__ring, to)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) +	\
	(i915_semaphore_seqno_size * (to)))

#define GEN8_WAIT_OFFSET(__ring, from)			     \
	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	(i915_semaphore_seqno_size * (__ring)->id))

#define GEN8_RING_SEMAPHORE_INIT do { \
	if (!dev_priv->semaphore_obj) { \
		break; \
	} \
	ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
	ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
	ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
	ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
	ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
	ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
	} while(0)

enum intel_ring_hangcheck_action {
	HANGCHECK_IDLE = 0,
	HANGCHECK_WAIT,
	HANGCHECK_ACTIVE,
	HANGCHECK_ACTIVE_LOOP,
	HANGCHECK_KICK,
	HANGCHECK_HUNG,
};

#define HANGCHECK_SCORE_RING_HUNG 31

struct intel_ring_hangcheck {
	u64 acthd;
	u64 max_acthd;
	u32 seqno;
	int score;
	enum intel_ring_hangcheck_action action;
	int deadlock;
};

struct intel_ringbuffer {
	struct drm_i915_gem_object *obj;
	void __iomem *virtual_start;

	struct intel_engine_cs *ring;

	u32 head;
	u32 tail;
	int space;
	int size;
	int effective_size;

	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32 last_retired_head;
};

struct	intel_context;

struct  intel_engine_cs {
	const char	*name;
	enum intel_ring_id {
		RCS = 0x0,
		VCS,
		BCS,
		VECS,
		VCS2
	} id;
#define I915_NUM_RINGS 5
#define LAST_USER_RING (VECS + 1)
	u32		mmio_base;
	struct		drm_device *dev;
	struct intel_ringbuffer *buffer;

	/*
	 * A pool of objects to use as shadow copies of client batch buffers
	 * when the command parser is enabled. Prevents the client from
	 * modifying the batch contents after software parsing.
	 */
	struct i915_gem_batch_pool batch_pool;

	struct intel_hw_status_page status_page;

	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
	struct drm_i915_gem_request *trace_irq_req;
	bool __must_check (*irq_get)(struct intel_engine_cs *ring);
	void		(*irq_put)(struct intel_engine_cs *ring);

	int		(*init_hw)(struct intel_engine_cs *ring);

	int		(*init_context)(struct intel_engine_cs *ring,
					struct intel_context *ctx);

	void		(*write_tail)(struct intel_engine_cs *ring,
				      u32 value);
	int __must_check (*flush)(struct intel_engine_cs *ring,
				  u32	invalidate_domains,
				  u32	flush_domains);
	int		(*add_request)(struct intel_engine_cs *ring);
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
	u32		(*get_seqno)(struct intel_engine_cs *ring,
				     bool lazy_coherency);
	void		(*set_seqno)(struct intel_engine_cs *ring,
				     u32 seqno);
	int		(*dispatch_execbuffer)(struct intel_engine_cs *ring,
					       u64 offset, u32 length,
					       unsigned dispatch_flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
	void		(*cleanup)(struct intel_engine_cs *ring);

	/* GEN8 signal/wait table - never trust comments!
	 *	  signal to	signal to    signal to   signal to      signal to
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) |  NOP (0x90) | VCS2 (0x98) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP  (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	 *  ie. transpose of g(x, y)
	 *
	 *	 sync from	sync from    sync from    sync from	sync from
	 *	    RCS		   VCS          BCS        VECS		 VCS2
	 *      --------------------------------------------------------------------
	 *  RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
	 *	|-------------------------------------------------------------------
	 *  VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
	 *	|-------------------------------------------------------------------
	 *  BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
	 *	|-------------------------------------------------------------------
	 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) |  NOP (0x90) | VCS2 (0xb8) |
	 *	|-------------------------------------------------------------------
	 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) |  NOP (0xc0) |
	 *	|-------------------------------------------------------------------
	 *
	 * Generalization:
	 *  g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	 *  ie. transpose of f(x, y)
	 */
	struct {
		u32	sync_seqno[I915_NUM_RINGS-1];

		union {
			struct {
				/* our mbox written by others */
				u32		wait[I915_NUM_RINGS];
				/* mboxes this ring signals to */
				u32		signal[I915_NUM_RINGS];
			} mbox;
			u64		signal_ggtt[I915_NUM_RINGS];
		};

		/* AKA wait() */
		int	(*sync_to)(struct intel_engine_cs *ring,
				   struct intel_engine_cs *to,
				   u32 seqno);
		int	(*signal)(struct intel_engine_cs *signaller,
				  /* num_dwords needed by caller */
				  unsigned int num_dwords);
	} semaphore;

	/* Execlists */
	spinlock_t execlist_lock;
	struct list_head execlist_queue;
	struct list_head execlist_retired_req_list;
	u8 next_context_status_buffer;
	u32             irq_keep_mask; /* bitmask for interrupts that should not be masked */
	int		(*emit_request)(struct intel_ringbuffer *ringbuf,
					struct drm_i915_gem_request *request);
	int		(*emit_flush)(struct intel_ringbuffer *ringbuf,
				      struct intel_context *ctx,
				      u32 invalidate_domains,
				      u32 flush_domains);
	int		(*emit_bb_start)(struct intel_ringbuffer *ringbuf,
					 struct intel_context *ctx,
					 u64 offset, unsigned dispatch_flags);

	/**
	 * List of objects currently involved in rendering from the
	 * ringbuffer.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives.  last_read_req
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;

	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;

	/**
	 * Do we have some not yet emitted requests outstanding?
	 */
	struct drm_i915_gem_request *outstanding_lazy_request;
	bool gpu_caches_dirty;

	wait_queue_head_t irq_queue;

	struct intel_context *default_context;
	struct intel_context *last_context;

	struct intel_ring_hangcheck hangcheck;

	struct {
		struct drm_i915_gem_object *obj;
		u32 gtt_offset;
		volatile u32 *cpu_page;
	} scratch;

	bool needs_cmd_parser;

	/*
	 * Table of commands the command parser needs to know about
	 * for this ring.
	 */
	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);

	/*
	 * Table of registers allowed in commands that read/write registers.
	 */
	const u32 *reg_table;
	int reg_count;

	/*
	 * Table of registers allowed in commands that read/write registers, but
	 * only from the DRM master.
	 */
	const u32 *master_reg_table;
	int master_reg_count;

	/*
	 * Returns the bitmask for the length field of the specified command.
	 * Return 0 for an unrecognized/invalid command.
	 *
	 * If the command parser finds an entry for a command in the ring's
	 * cmd_tables, it gets the command's length based on the table entry.
	 * If not, it calls this function to determine the per-ring length field
	 * encoding for the command (i.e. certain opcode ranges use certain bits
	 * to encode the command length in the header).
	 */
	u32 (*get_cmd_length_mask)(u32 cmd_header);
};

bool intel_ring_initialized(struct intel_engine_cs *ring);

static inline unsigned
intel_ring_flag(struct intel_engine_cs *ring)
{
	return 1 << ring->id;
}

static inline u32
intel_ring_sync_index(struct intel_engine_cs *ring,
		      struct intel_engine_cs *other)
{
	int idx;

	/*
	 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
	 */

	idx = (other - ring) - 1;
	if (idx < 0)
		idx += I915_NUM_RINGS;

	return idx;
}

static inline u32
intel_read_status_page(struct intel_engine_cs *ring,
		       int reg)
{
	/* Ensure that the compiler doesn't optimize away the load. */
	barrier();
	return ring->status_page.page_addr[reg];
}

static inline void
intel_write_status_page(struct intel_engine_cs *ring,
			int reg, u32 value)
{
	ring->status_page.page_addr[reg] = value;
}

/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
 * 0x20-0x2f: Reserved (Gen6+)
 *
 * The area from dword 0x30 to 0x3ff is available for driver usage.
 */
#define I915_GEM_HWS_INDEX		0x30
#define I915_GEM_HWS_SCRATCH_INDEX	0x40
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)

void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
				     struct intel_ringbuffer *ringbuf);
void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
int intel_alloc_ringbuffer_obj(struct drm_device *dev,
			       struct intel_ringbuffer *ringbuf);

void intel_stop_ring_buffer(struct intel_engine_cs *ring);
void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);

int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);

int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
static inline void intel_ring_emit(struct intel_engine_cs *ring,
				   u32 data)
{
	struct intel_ringbuffer *ringbuf = ring->buffer;
	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	ringbuf->tail += 4;
}
static inline void intel_ring_advance(struct intel_engine_cs *ring)
{
	struct intel_ringbuffer *ringbuf = ring->buffer;
	ringbuf->tail &= ringbuf->size - 1;
}
int __intel_ring_space(int head, int tail, int size);
void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
int intel_ring_space(struct intel_ringbuffer *ringbuf);
bool intel_ring_stopped(struct intel_engine_cs *ring);
void __intel_ring_advance(struct intel_engine_cs *ring);

int __must_check intel_ring_idle(struct intel_engine_cs *ring);
void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);

void intel_fini_pipe_control(struct intel_engine_cs *ring);
int intel_init_pipe_control(struct intel_engine_cs *ring);

int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_bsd2_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
int intel_init_vebox_ring_buffer(struct drm_device *dev);

u64 intel_ring_get_active_head(struct intel_engine_cs *ring);

int init_workarounds_ring(struct intel_engine_cs *ring);

static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
{
	return ringbuf->tail;
}

static inline struct drm_i915_gem_request *
intel_ring_get_request(struct intel_engine_cs *ring)
{
	BUG_ON(ring->outstanding_lazy_request == NULL);
	return ring->outstanding_lazy_request;
}

#endif /* _INTEL_RINGBUFFER_H_ */
Commit	Line	Data
8187a2b7 ZN	1	#ifndef _INTEL_RINGBUFFER_H_
	2	#define _INTEL_RINGBUFFER_H_
	3
44e895a8	4	#include <linux/hashtable.h>
06fbca71	5	#include "i915_gem_batch_pool.h"
44e895a8 BV	6
	7	#define I915_CMD_HASH_ORDER 9
	8
4712274c OM	9	/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
	10	* but keeps the logic simple. Indeed, the whole purpose of this macro is just
	11	* to give some inclination as to some of the magic values used in the various
	12	* workarounds!
	13	*/
	14	#define CACHELINE_BYTES 64
	15
633cf8f5 VS	16	/*
	17	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
	18	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
	19	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
	20	*
	21	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
	22	* cacheline, the Head Pointer must not be greater than the Tail
	23	* Pointer."
	24	*/
	25	#define I915_RING_FREE_SPACE 64
	26
8187a2b7	27	struct intel_hw_status_page {
4225d0f2	28	u32 *page_addr;
8187a2b7	29	unsigned int gfx_addr;
05394f39	30	struct drm_i915_gem_object *obj;
8187a2b7 ZN	31	};
8187a2b7 ZN	32
b7287d80 BW	33	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
b7287d80 BW	34	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
cae5852d	35
b7287d80 BW	36	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
b7287d80 BW	37	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
cae5852d	38
b7287d80 BW	39	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
b7287d80 BW	40	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
cae5852d	41
b7287d80 BW	42	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
b7287d80 BW	43	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
cae5852d	44
b7287d80 BW	45	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
b7287d80 BW	46	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
870e86dd	47
e9fea574	48	#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
9991ae78	49	#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
e9fea574	50
3e78998a BW	51	/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
	52	* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
	53	*/
	54	#define i915_semaphore_seqno_size sizeof(uint64_t)
	55	#define GEN8_SIGNAL_OFFSET(__ring, to) \
	56	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	57	((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	58	(i915_semaphore_seqno_size * (to)))
	59
	60	#define GEN8_WAIT_OFFSET(__ring, from) \
	61	(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
	62	((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
	63	(i915_semaphore_seqno_size * (__ring)->id))
	64
	65	#define GEN8_RING_SEMAPHORE_INIT do { \
	66	if (!dev_priv->semaphore_obj) { \
	67	break; \
	68	} \
	69	ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
	70	ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
	71	ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
	72	ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
	73	ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
	74	ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
	75	} while(0)
	76
f2f4d82f	77	enum intel_ring_hangcheck_action {
da661464	78	HANGCHECK_IDLE = 0,
f2f4d82f JN	79	HANGCHECK_WAIT,
f2f4d82f JN	80	HANGCHECK_ACTIVE,
f260fe7b	81	HANGCHECK_ACTIVE_LOOP,
f2f4d82f JN	82	HANGCHECK_KICK,
	83	HANGCHECK_HUNG,
	84	};
ad8beaea	85
b6b0fac0 MK	86	#define HANGCHECK_SCORE_RING_HUNG 31
b6b0fac0 MK	87
92cab734	88	struct intel_ring_hangcheck {
50877445	89	u64 acthd;
f260fe7b	90	u64 max_acthd;
92cab734	91	u32 seqno;
05407ff8	92	int score;
ad8beaea	93	enum intel_ring_hangcheck_action action;
4be17381	94	int deadlock;
92cab734 MK	95	};
92cab734 MK	96
8ee14975 OM	97	struct intel_ringbuffer {
	98	struct drm_i915_gem_object *obj;
	99	void __iomem *virtual_start;
	100
0c7dd53b DV	101	struct intel_engine_cs *ring;
0c7dd53b DV	102
8ee14975 OM	103	u32 head;
	104	u32 tail;
	105	int space;
	106	int size;
	107	int effective_size;
	108
	109	/** We track the position of the requests in the ring buffer, and
	110	* when each is retired we increment last_retired_head as the GPU
	111	* must have finished processing the request and so we know we
	112	* can advance the ringbuffer up to that position.
	113	*
	114	* last_retired_head is set to -1 after the value is consumed so
	115	* we can detect new retirements.
	116	*/
	117	u32 last_retired_head;
	118	};
	119
21076372 NH	120	struct intel_context;
21076372 NH	121
a4872ba6	122	struct intel_engine_cs {
8187a2b7	123	const char *name;
9220434a	124	enum intel_ring_id {
96154f2f DV	125	RCS = 0x0,
	126	VCS,
	127	BCS,
4a3dd19d	128	VECS,
845f74a7	129	VCS2
9220434a	130	} id;
845f74a7	131	#define I915_NUM_RINGS 5
b1a93306	132	#define LAST_USER_RING (VECS + 1)
333e9fe9	133	u32 mmio_base;
8187a2b7	134	struct drm_device *dev;
8ee14975	135	struct intel_ringbuffer *buffer;
8187a2b7	136
06fbca71 CW	137	/*
	138	* A pool of objects to use as shadow copies of client batch buffers
	139	* when the command parser is enabled. Prevents the client from
	140	* modifying the batch contents after software parsing.
	141	*/
	142	struct i915_gem_batch_pool batch_pool;
	143
8187a2b7 ZN	144	struct intel_hw_status_page status_page;
8187a2b7 ZN	145
c7113cc3	146	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
6a848ccb	147	u32 irq_enable_mask; /* bitmask to enable ring interrupt */
581c26e8	148	struct drm_i915_gem_request *trace_irq_req;
a4872ba6 OM	149	bool __must_check (irq_get)(struct intel_engine_cs ring);
a4872ba6 OM	150	void (irq_put)(struct intel_engine_cs ring);
8187a2b7	151
ecfe00d8	152	int (init_hw)(struct intel_engine_cs ring);
8187a2b7	153
771b9a53 MT	154	int (init_context)(struct intel_engine_cs ring,
771b9a53 MT	155	struct intel_context *ctx);
86d7f238	156
a4872ba6	157	void (write_tail)(struct intel_engine_cs ring,
297b0c5b	158	u32 value);
a4872ba6	159	int __must_check (flush)(struct intel_engine_cs ring,
b72f3acb CW	160	u32 invalidate_domains,
b72f3acb CW	161	u32 flush_domains);
a4872ba6	162	int (add_request)(struct intel_engine_cs ring);
b2eadbc8 CW	163	/* Some chipsets are not quite as coherent as advertised and need
	164	* an expensive kick to force a true read of the up-to-date seqno.
	165	* However, the up-to-date seqno is not always required and the last
	166	* seen value is good enough. Note that the seqno will always be
	167	* monotonic, even if not coherent.
	168	*/
a4872ba6	169	u32 (get_seqno)(struct intel_engine_cs ring,
b2eadbc8	170	bool lazy_coherency);
a4872ba6	171	void (set_seqno)(struct intel_engine_cs ring,
b70ec5bf	172	u32 seqno);
a4872ba6	173	int (dispatch_execbuffer)(struct intel_engine_cs ring,
9bcb144c	174	u64 offset, u32 length,
8e004efc	175	unsigned dispatch_flags);
d7d4eedd	176	#define I915_DISPATCH_SECURE 0x1
b45305fc	177	#define I915_DISPATCH_PINNED 0x2
a4872ba6	178	void (cleanup)(struct intel_engine_cs ring);
ebc348b2	179
3e78998a BW	180	/* GEN8 signal/wait table - never trust comments!
	181	* signal to signal to signal to signal to signal to
	182	* RCS VCS BCS VECS VCS2
	183	* --------------------------------------------------------------------
	184	* RCS \| NOP (0x00) \| VCS (0x08) \| BCS (0x10) \| VECS (0x18) \| VCS2 (0x20) \|
	185	* \|-------------------------------------------------------------------
	186	* VCS \| RCS (0x28) \| NOP (0x30) \| BCS (0x38) \| VECS (0x40) \| VCS2 (0x48) \|
	187	* \|-------------------------------------------------------------------
	188	* BCS \| RCS (0x50) \| VCS (0x58) \| NOP (0x60) \| VECS (0x68) \| VCS2 (0x70) \|
	189	* \|-------------------------------------------------------------------
	190	* VECS \| RCS (0x78) \| VCS (0x80) \| BCS (0x88) \| NOP (0x90) \| VCS2 (0x98) \|
	191	* \|-------------------------------------------------------------------
	192	* VCS2 \| RCS (0xa0) \| VCS (0xa8) \| BCS (0xb0) \| VECS (0xb8) \| NOP (0xc0) \|
	193	* \|-------------------------------------------------------------------
	194	*
	195	* Generalization:
	196	* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
	197	* ie. transpose of g(x, y)
	198	*
	199	* sync from sync from sync from sync from sync from
	200	* RCS VCS BCS VECS VCS2
	201	* --------------------------------------------------------------------
	202	* RCS \| NOP (0x00) \| VCS (0x28) \| BCS (0x50) \| VECS (0x78) \| VCS2 (0xa0) \|
	203	* \|-------------------------------------------------------------------
	204	* VCS \| RCS (0x08) \| NOP (0x30) \| BCS (0x58) \| VECS (0x80) \| VCS2 (0xa8) \|
	205	* \|-------------------------------------------------------------------
	206	* BCS \| RCS (0x10) \| VCS (0x38) \| NOP (0x60) \| VECS (0x88) \| VCS2 (0xb0) \|
	207	* \|-------------------------------------------------------------------
	208	* VECS \| RCS (0x18) \| VCS (0x40) \| BCS (0x68) \| NOP (0x90) \| VCS2 (0xb8) \|
	209	* \|-------------------------------------------------------------------
	210	* VCS2 \| RCS (0x20) \| VCS (0x48) \| BCS (0x70) \| VECS (0x98) \| NOP (0xc0) \|
	211	* \|-------------------------------------------------------------------
	212	*
	213	* Generalization:
	214	* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
	215	* ie. transpose of f(x, y)
	216	*/
ebc348b2 BW	217	struct {
ebc348b2 BW	218	u32 sync_seqno[I915_NUM_RINGS-1];
78325f2d	219
3e78998a BW	220	union {
	221	struct {
	222	/* our mbox written by others */
	223	u32 wait[I915_NUM_RINGS];
	224	/* mboxes this ring signals to */
	225	u32 signal[I915_NUM_RINGS];
	226	} mbox;
	227	u64 signal_ggtt[I915_NUM_RINGS];
	228	};
78325f2d BW	229
78325f2d BW	230	/* AKA wait() */
a4872ba6 OM	231	int (sync_to)(struct intel_engine_cs ring,
a4872ba6 OM	232	struct intel_engine_cs *to,
78325f2d	233	u32 seqno);
a4872ba6	234	int (signal)(struct intel_engine_cs signaller,
024a43e1 BW	235	/* num_dwords needed by caller */
024a43e1 BW	236	unsigned int num_dwords);
ebc348b2	237	} semaphore;
ad776f8b	238
4da46e1e	239	/* Execlists */
acdd884a MT	240	spinlock_t execlist_lock;
acdd884a MT	241	struct list_head execlist_queue;
c86ee3a9	242	struct list_head execlist_retired_req_list;
e981e7b1	243	u8 next_context_status_buffer;
73d477f6	244	u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
72f95afa NH	245	int (emit_request)(struct intel_ringbuffer ringbuf,
72f95afa NH	246	struct drm_i915_gem_request *request);
4712274c	247	int (emit_flush)(struct intel_ringbuffer ringbuf,
21076372	248	struct intel_context *ctx,
4712274c OM	249	u32 invalidate_domains,
4712274c OM	250	u32 flush_domains);
15648585	251	int (emit_bb_start)(struct intel_ringbuffer ringbuf,
21076372	252	struct intel_context *ctx,
8e004efc	253	u64 offset, unsigned dispatch_flags);
4da46e1e	254
8187a2b7 ZN	255	/**
	256	* List of objects currently involved in rendering from the
	257	* ringbuffer.
	258	*
	259	* Includes buffers having the contents of their GPU caches
97b2a6a1	260	* flushed, not necessarily primitives. last_read_req
8187a2b7 ZN	261	* represents when the rendering involved will be completed.
	262	*
	263	* A reference is held on the buffer while on this list.
	264	*/
	265	struct list_head active_list;
	266
	267	/**
	268	* List of breadcrumbs associated with GPU requests currently
	269	* outstanding.
	270	*/
	271	struct list_head request_list;
	272
a56ba56c CW	273	/**
	274	* Do we have some not yet emitted requests outstanding?
	275	*/
6259cead	276	struct drm_i915_gem_request *outstanding_lazy_request;
cc889e0f	277	bool gpu_caches_dirty;
a56ba56c	278
8187a2b7	279	wait_queue_head_t irq_queue;
8d19215b	280
273497e5 OM	281	struct intel_context *default_context;
273497e5 OM	282	struct intel_context *last_context;
40521054	283
92cab734 MK	284	struct intel_ring_hangcheck hangcheck;
92cab734 MK	285
0d1aacac CW	286	struct {
	287	struct drm_i915_gem_object *obj;
	288	u32 gtt_offset;
	289	volatile u32 *cpu_page;
	290	} scratch;
351e3db2	291
44e895a8 BV	292	bool needs_cmd_parser;
44e895a8 BV	293
351e3db2	294	/*
44e895a8	295	* Table of commands the command parser needs to know about
351e3db2 BV	296	* for this ring.
351e3db2 BV	297	*/
44e895a8	298	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
351e3db2 BV	299
	300	/*
	301	* Table of registers allowed in commands that read/write registers.
	302	*/
	303	const u32 *reg_table;
	304	int reg_count;
	305
	306	/*
	307	* Table of registers allowed in commands that read/write registers, but
	308	* only from the DRM master.
	309	*/
	310	const u32 *master_reg_table;
	311	int master_reg_count;
	312
	313	/*
	314	* Returns the bitmask for the length field of the specified command.
	315	* Return 0 for an unrecognized/invalid command.
	316	*
	317	* If the command parser finds an entry for a command in the ring's
	318	* cmd_tables, it gets the command's length based on the table entry.
	319	* If not, it calls this function to determine the per-ring length field
	320	* encoding for the command (i.e. certain opcode ranges use certain bits
	321	* to encode the command length in the header).
	322	*/
	323	u32 (*get_cmd_length_mask)(u32 cmd_header);
8187a2b7 ZN	324	};
8187a2b7 ZN	325
48d82387	326	bool intel_ring_initialized(struct intel_engine_cs *ring);
b4519513	327
96154f2f	328	static inline unsigned
a4872ba6	329	intel_ring_flag(struct intel_engine_cs *ring)
96154f2f DV	330	{
	331	return 1 << ring->id;
	332	}
	333
1ec14ad3	334	static inline u32
a4872ba6 OM	335	intel_ring_sync_index(struct intel_engine_cs *ring,
a4872ba6 OM	336	struct intel_engine_cs *other)
1ec14ad3 CW	337	{
	338	int idx;
	339
	340	/*
ddd4dbc6 RV	341	* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	342	* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	343	* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	344	* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	345	* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
1ec14ad3 CW	346	*/
	347
	348	idx = (other - ring) - 1;
	349	if (idx < 0)
	350	idx += I915_NUM_RINGS;
	351
	352	return idx;
	353	}
	354
8187a2b7	355	static inline u32
a4872ba6	356	intel_read_status_page(struct intel_engine_cs *ring,
78501eac	357	int reg)
8187a2b7	358	{
4225d0f2 DV	359	/* Ensure that the compiler doesn't optimize away the load. */
	360	barrier();
	361	return ring->status_page.page_addr[reg];
8187a2b7 ZN	362	}
8187a2b7 ZN	363
b70ec5bf	364	static inline void
a4872ba6	365	intel_write_status_page(struct intel_engine_cs *ring,
b70ec5bf MK	366	int reg, u32 value)
	367	{
	368	ring->status_page.page_addr[reg] = value;
	369	}
	370
311bd68e CW	371	/**
	372	* Reads a dword out of the status page, which is written to from the command
	373	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
	374	* MI_STORE_DATA_IMM.
	375	*
	376	* The following dwords have a reserved meaning:
	377	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
	378	* 0x04: ring 0 head pointer
	379	* 0x05: ring 1 head pointer (915-class)
	380	* 0x06: ring 2 head pointer (915-class)
	381	* 0x10-0x1b: Context status DWords (GM45)
	382	* 0x1f: Last written status offset. (GM45)
b07da53c	383	* 0x20-0x2f: Reserved (Gen6+)
311bd68e	384	*
b07da53c	385	* The area from dword 0x30 to 0x3ff is available for driver usage.
311bd68e	386	*/
b07da53c TD	387	#define I915_GEM_HWS_INDEX 0x30
b07da53c TD	388	#define I915_GEM_HWS_SCRATCH_INDEX 0x40
9a289771	389	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
311bd68e	390
7ba717cf TD	391	void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
	392	int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
	393	struct intel_ringbuffer *ringbuf);
84c2377f OM	394	void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
	395	int intel_alloc_ringbuffer_obj(struct drm_device *dev,
	396	struct intel_ringbuffer *ringbuf);
	397
a4872ba6 OM	398	void intel_stop_ring_buffer(struct intel_engine_cs *ring);
a4872ba6 OM	399	void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
96f298aa	400
6689cb2b JH	401	int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
6689cb2b JH	402
a4872ba6 OM	403	int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
	404	int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
	405	static inline void intel_ring_emit(struct intel_engine_cs *ring,
78501eac	406	u32 data)
e898cd22	407	{
93b0a4e0 OM	408	struct intel_ringbuffer *ringbuf = ring->buffer;
	409	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	410	ringbuf->tail += 4;
e898cd22	411	}
a4872ba6	412	static inline void intel_ring_advance(struct intel_engine_cs *ring)
09246732	413	{
93b0a4e0 OM	414	struct intel_ringbuffer *ringbuf = ring->buffer;
93b0a4e0 OM	415	ringbuf->tail &= ringbuf->size - 1;
09246732	416	}
82e104cc	417	int __intel_ring_space(int head, int tail, int size);
ebd0fd4b	418	void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
82e104cc OM	419	int intel_ring_space(struct intel_ringbuffer *ringbuf);
82e104cc OM	420	bool intel_ring_stopped(struct intel_engine_cs *ring);
a4872ba6	421	void __intel_ring_advance(struct intel_engine_cs *ring);
09246732	422
a4872ba6 OM	423	int __must_check intel_ring_idle(struct intel_engine_cs *ring);
	424	void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
	425	int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
	426	int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);
8187a2b7	427
9b1136d5 OM	428	void intel_fini_pipe_control(struct intel_engine_cs *ring);
	429	int intel_init_pipe_control(struct intel_engine_cs *ring);
	430
5c1143bb XH	431	int intel_init_render_ring_buffer(struct drm_device *dev);
5c1143bb XH	432	int intel_init_bsd_ring_buffer(struct drm_device *dev);
845f74a7	433	int intel_init_bsd2_ring_buffer(struct drm_device *dev);
549f7365	434	int intel_init_blt_ring_buffer(struct drm_device *dev);
9a8a2213	435	int intel_init_vebox_ring_buffer(struct drm_device *dev);
8187a2b7	436
a4872ba6	437	u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
79f321b7	438
771b9a53 MT	439	int init_workarounds_ring(struct intel_engine_cs *ring);
771b9a53 MT	440
1b5d063f	441	static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
a71d8d94	442	{
1b5d063f	443	return ringbuf->tail;
a71d8d94 CW	444	}
a71d8d94 CW	445
b793a00a JH	446	static inline struct drm_i915_gem_request *
	447	intel_ring_get_request(struct intel_engine_cs *ring)
	448	{
6259cead JH	449	BUG_ON(ring->outstanding_lazy_request == NULL);
6259cead JH	450	return ring->outstanding_lazy_request;
b793a00a JH	451	}
b793a00a JH	452
8187a2b7	453	#endif /* _INTEL_RINGBUFFER_H_ */