[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.h

#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_

/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64

struct  intel_hw_status_page {
	u32		*page_addr;
	unsigned int	gfx_addr;
	struct		drm_i915_gem_object *obj;
};

#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)

#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)

#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)

#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)

#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)

#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)

enum intel_ring_hangcheck_action {
	HANGCHECK_IDLE = 0,
	HANGCHECK_WAIT,
	HANGCHECK_ACTIVE,
	HANGCHECK_KICK,
	HANGCHECK_HUNG,
};

#define HANGCHECK_SCORE_RING_HUNG 31

struct intel_ring_hangcheck {
	u64 acthd;
	u32 seqno;
	int score;
	enum intel_ring_hangcheck_action action;
	bool deadlock;
};

struct  intel_ring_buffer {
	const char	*name;
	enum intel_ring_id {
		RCS = 0x0,
		VCS,
		BCS,
		VECS,
		VCS2
	} id;
#define I915_NUM_RINGS 5
#define LAST_USER_RING (VECS + 1)
	u32		mmio_base;
	void		__iomem *virtual_start;
	struct		drm_device *dev;
	struct		drm_i915_gem_object *obj;

	u32		head;
	u32		tail;
	int		space;
	int		size;
	int		effective_size;
	struct intel_hw_status_page status_page;

	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32		last_retired_head;

	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
	u32		trace_irq_seqno;
	bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
	void		(*irq_put)(struct intel_ring_buffer *ring);

	int		(*init)(struct intel_ring_buffer *ring);

	void		(*write_tail)(struct intel_ring_buffer *ring,
				      u32 value);
	int __must_check (*flush)(struct intel_ring_buffer *ring,
				  u32	invalidate_domains,
				  u32	flush_domains);
	int		(*add_request)(struct intel_ring_buffer *ring);
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
	u32		(*get_seqno)(struct intel_ring_buffer *ring,
				     bool lazy_coherency);
	void		(*set_seqno)(struct intel_ring_buffer *ring,
				     u32 seqno);
	int		(*dispatch_execbuffer)(struct intel_ring_buffer *ring,
					       u32 offset, u32 length,
					       unsigned flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
	void		(*cleanup)(struct intel_ring_buffer *ring);

	struct {
		u32	sync_seqno[I915_NUM_RINGS-1];
		/* AKA wait() */
		int	(*sync_to)(struct intel_ring_buffer *ring,
				   struct intel_ring_buffer *to,
				   u32 seqno);
		struct {
			/* our mbox written by others */
			u32		wait[I915_NUM_RINGS];
			/* mboxes this ring signals to */
			u32		signal[I915_NUM_RINGS];
		} mbox;
	} semaphore;

	/**
	 * List of objects currently involved in rendering from the
	 * ringbuffer.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives.  last_rendering_seqno
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;

	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;

	/**
	 * Do we have some not yet emitted requests outstanding?
	 */
	struct drm_i915_gem_request *preallocated_lazy_request;
	u32 outstanding_lazy_seqno;
	bool gpu_caches_dirty;
	bool fbc_dirty;

	wait_queue_head_t irq_queue;

	struct i915_hw_context *default_context;
	struct i915_hw_context *last_context;

	struct intel_ring_hangcheck hangcheck;

	struct {
		struct drm_i915_gem_object *obj;
		u32 gtt_offset;
		volatile u32 *cpu_page;
	} scratch;

	/*
	 * Tables of commands the command parser needs to know about
	 * for this ring.
	 */
	const struct drm_i915_cmd_table *cmd_tables;
	int cmd_table_count;

	/*
	 * Table of registers allowed in commands that read/write registers.
	 */
	const u32 *reg_table;
	int reg_count;

	/*
	 * Table of registers allowed in commands that read/write registers, but
	 * only from the DRM master.
	 */
	const u32 *master_reg_table;
	int master_reg_count;

	/*
	 * Returns the bitmask for the length field of the specified command.
	 * Return 0 for an unrecognized/invalid command.
	 *
	 * If the command parser finds an entry for a command in the ring's
	 * cmd_tables, it gets the command's length based on the table entry.
	 * If not, it calls this function to determine the per-ring length field
	 * encoding for the command (i.e. certain opcode ranges use certain bits
	 * to encode the command length in the header).
	 */
	u32 (*get_cmd_length_mask)(u32 cmd_header);
};

static inline bool
intel_ring_initialized(struct intel_ring_buffer *ring)
{
	return ring->obj != NULL;
}

static inline unsigned
intel_ring_flag(struct intel_ring_buffer *ring)
{
	return 1 << ring->id;
}

static inline u32
intel_ring_sync_index(struct intel_ring_buffer *ring,
		      struct intel_ring_buffer *other)
{
	int idx;

	/*
	 * cs -> 0 = vcs, 1 = bcs
	 * vcs -> 0 = bcs, 1 = cs,
	 * bcs -> 0 = cs, 1 = vcs.
	 */

	idx = (other - ring) - 1;
	if (idx < 0)
		idx += I915_NUM_RINGS;

	return idx;
}

static inline u32
intel_read_status_page(struct intel_ring_buffer *ring,
		       int reg)
{
	/* Ensure that the compiler doesn't optimize away the load. */
	barrier();
	return ring->status_page.page_addr[reg];
}

static inline void
intel_write_status_page(struct intel_ring_buffer *ring,
			int reg, u32 value)
{
	ring->status_page.page_addr[reg] = value;
}

/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
 *
 * The area from dword 0x20 to 0x3ff is available for driver usage.
 */
#define I915_GEM_HWS_INDEX		0x20
#define I915_GEM_HWS_SCRATCH_INDEX	0x30
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)

void intel_stop_ring_buffer(struct intel_ring_buffer *ring);
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);

int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring);
static inline void intel_ring_emit(struct intel_ring_buffer *ring,
				   u32 data)
{
	iowrite32(data, ring->virtual_start + ring->tail);
	ring->tail += 4;
}
static inline void intel_ring_advance(struct intel_ring_buffer *ring)
{
	ring->tail &= ring->size - 1;
}
void __intel_ring_advance(struct intel_ring_buffer *ring);

int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);

int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_bsd2_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
int intel_init_vebox_ring_buffer(struct drm_device *dev);

u64 intel_ring_get_active_head(struct intel_ring_buffer *ring);
void intel_ring_setup_status_page(struct intel_ring_buffer *ring);

static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
{
	return ring->tail;
}

static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
{
	BUG_ON(ring->outstanding_lazy_seqno == 0);
	return ring->outstanding_lazy_seqno;
}

static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
{
	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
		ring->trace_irq_seqno = seqno;
}

/* DRI warts */
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);

#endif /* _INTEL_RINGBUFFER_H_ */
Commit	Line	Data
8187a2b7 ZN	1	#ifndef _INTEL_RINGBUFFER_H_
	2	#define _INTEL_RINGBUFFER_H_
	3
633cf8f5 VS	4	/*
	5	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
	6	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
	7	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
	8	*
	9	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
	10	* cacheline, the Head Pointer must not be greater than the Tail
	11	* Pointer."
	12	*/
	13	#define I915_RING_FREE_SPACE 64
	14
8187a2b7	15	struct intel_hw_status_page {
4225d0f2	16	u32 *page_addr;
8187a2b7	17	unsigned int gfx_addr;
05394f39	18	struct drm_i915_gem_object *obj;
8187a2b7 ZN	19	};
8187a2b7 ZN	20
b7287d80 BW	21	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
b7287d80 BW	22	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
cae5852d	23
b7287d80 BW	24	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
b7287d80 BW	25	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
cae5852d	26
b7287d80 BW	27	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
b7287d80 BW	28	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
cae5852d	29
b7287d80 BW	30	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
b7287d80 BW	31	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
cae5852d	32
b7287d80 BW	33	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
b7287d80 BW	34	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
870e86dd	35
e9fea574	36	#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
9991ae78	37	#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
e9fea574	38
f2f4d82f	39	enum intel_ring_hangcheck_action {
da661464	40	HANGCHECK_IDLE = 0,
f2f4d82f JN	41	HANGCHECK_WAIT,
	42	HANGCHECK_ACTIVE,
	43	HANGCHECK_KICK,
	44	HANGCHECK_HUNG,
	45	};
ad8beaea	46
b6b0fac0 MK	47	#define HANGCHECK_SCORE_RING_HUNG 31
b6b0fac0 MK	48
92cab734	49	struct intel_ring_hangcheck {
50877445	50	u64 acthd;
92cab734	51	u32 seqno;
05407ff8	52	int score;
ad8beaea	53	enum intel_ring_hangcheck_action action;
50877445	54	bool deadlock;
92cab734 MK	55	};
92cab734 MK	56
8187a2b7 ZN	57	struct intel_ring_buffer {
8187a2b7 ZN	58	const char *name;
9220434a	59	enum intel_ring_id {
96154f2f DV	60	RCS = 0x0,
	61	VCS,
	62	BCS,
4a3dd19d	63	VECS,
845f74a7	64	VCS2
9220434a	65	} id;
845f74a7	66	#define I915_NUM_RINGS 5
b1a93306	67	#define LAST_USER_RING (VECS + 1)
333e9fe9	68	u32 mmio_base;
311bd68e	69	void __iomem *virtual_start;
8187a2b7	70	struct drm_device *dev;
05394f39	71	struct drm_i915_gem_object *obj;
8187a2b7	72
8c0a6bfe CW	73	u32 head;
8c0a6bfe CW	74	u32 tail;
780f0ca3	75	int space;
c2c347a9	76	int size;
55249baa	77	int effective_size;
8187a2b7 ZN	78	struct intel_hw_status_page status_page;
8187a2b7 ZN	79
a71d8d94 CW	80	/** We track the position of the requests in the ring buffer, and
	81	* when each is retired we increment last_retired_head as the GPU
	82	* must have finished processing the request and so we know we
	83	* can advance the ringbuffer up to that position.
	84	*
	85	* last_retired_head is set to -1 after the value is consumed so
	86	* we can detect new retirements.
	87	*/
	88	u32 last_retired_head;
	89
c7113cc3	90	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
6a848ccb	91	u32 irq_enable_mask; /* bitmask to enable ring interrupt */
db53a302	92	u32 trace_irq_seqno;
b13c2b96	93	bool __must_check (irq_get)(struct intel_ring_buffer ring);
1ec14ad3	94	void (irq_put)(struct intel_ring_buffer ring);
8187a2b7	95
78501eac	96	int (init)(struct intel_ring_buffer ring);
8187a2b7	97
78501eac	98	void (write_tail)(struct intel_ring_buffer ring,
297b0c5b	99	u32 value);
b72f3acb CW	100	int __must_check (flush)(struct intel_ring_buffer ring,
	101	u32 invalidate_domains,
	102	u32 flush_domains);
9d773091	103	int (add_request)(struct intel_ring_buffer ring);
b2eadbc8 CW	104	/* Some chipsets are not quite as coherent as advertised and need
	105	* an expensive kick to force a true read of the up-to-date seqno.
	106	* However, the up-to-date seqno is not always required and the last
	107	* seen value is good enough. Note that the seqno will always be
	108	* monotonic, even if not coherent.
	109	*/
	110	u32 (get_seqno)(struct intel_ring_buffer ring,
	111	bool lazy_coherency);
b70ec5bf MK	112	void (set_seqno)(struct intel_ring_buffer ring,
b70ec5bf MK	113	u32 seqno);
78501eac	114	int (dispatch_execbuffer)(struct intel_ring_buffer ring,
d7d4eedd CW	115	u32 offset, u32 length,
	116	unsigned flags);
	117	#define I915_DISPATCH_SECURE 0x1
b45305fc	118	#define I915_DISPATCH_PINNED 0x2
8d19215b	119	void (cleanup)(struct intel_ring_buffer ring);
ebc348b2 BW	120
	121	struct {
	122	u32 sync_seqno[I915_NUM_RINGS-1];
	123	/* AKA wait() */
	124	int (sync_to)(struct intel_ring_buffer ring,
c8c99b0f BW	125	struct intel_ring_buffer *to,
c8c99b0f BW	126	u32 seqno);
ebc348b2 BW	127	struct {
	128	/* our mbox written by others */
	129	u32 wait[I915_NUM_RINGS];
	130	/* mboxes this ring signals to */
	131	u32 signal[I915_NUM_RINGS];
	132	} mbox;
	133	} semaphore;
ad776f8b	134
8187a2b7 ZN	135	/**
	136	* List of objects currently involved in rendering from the
	137	* ringbuffer.
	138	*
	139	* Includes buffers having the contents of their GPU caches
	140	* flushed, not necessarily primitives. last_rendering_seqno
	141	* represents when the rendering involved will be completed.
	142	*
	143	* A reference is held on the buffer while on this list.
	144	*/
	145	struct list_head active_list;
	146
	147	/**
	148	* List of breadcrumbs associated with GPU requests currently
	149	* outstanding.
	150	*/
	151	struct list_head request_list;
	152
a56ba56c CW	153	/**
	154	* Do we have some not yet emitted requests outstanding?
	155	*/
3c0e234c	156	struct drm_i915_gem_request *preallocated_lazy_request;
1823521d	157	u32 outstanding_lazy_seqno;
cc889e0f	158	bool gpu_caches_dirty;
c65355bb	159	bool fbc_dirty;
a56ba56c	160
8187a2b7	161	wait_queue_head_t irq_queue;
8d19215b	162
40521054	163	struct i915_hw_context *default_context;
112522f6	164	struct i915_hw_context *last_context;
40521054	165
92cab734 MK	166	struct intel_ring_hangcheck hangcheck;
92cab734 MK	167
0d1aacac CW	168	struct {
	169	struct drm_i915_gem_object *obj;
	170	u32 gtt_offset;
	171	volatile u32 *cpu_page;
	172	} scratch;
351e3db2 BV	173
	174	/*
	175	* Tables of commands the command parser needs to know about
	176	* for this ring.
	177	*/
	178	const struct drm_i915_cmd_table *cmd_tables;
	179	int cmd_table_count;
	180
	181	/*
	182	* Table of registers allowed in commands that read/write registers.
	183	*/
	184	const u32 *reg_table;
	185	int reg_count;
	186
	187	/*
	188	* Table of registers allowed in commands that read/write registers, but
	189	* only from the DRM master.
	190	*/
	191	const u32 *master_reg_table;
	192	int master_reg_count;
	193
	194	/*
	195	* Returns the bitmask for the length field of the specified command.
	196	* Return 0 for an unrecognized/invalid command.
	197	*
	198	* If the command parser finds an entry for a command in the ring's
	199	* cmd_tables, it gets the command's length based on the table entry.
	200	* If not, it calls this function to determine the per-ring length field
	201	* encoding for the command (i.e. certain opcode ranges use certain bits
	202	* to encode the command length in the header).
	203	*/
	204	u32 (*get_cmd_length_mask)(u32 cmd_header);
8187a2b7 ZN	205	};
8187a2b7 ZN	206
b4519513 CW	207	static inline bool
	208	intel_ring_initialized(struct intel_ring_buffer *ring)
	209	{
	210	return ring->obj != NULL;
	211	}
	212
96154f2f DV	213	static inline unsigned
	214	intel_ring_flag(struct intel_ring_buffer *ring)
	215	{
	216	return 1 << ring->id;
	217	}
	218
1ec14ad3 CW	219	static inline u32
	220	intel_ring_sync_index(struct intel_ring_buffer *ring,
	221	struct intel_ring_buffer *other)
	222	{
	223	int idx;
	224
	225	/*
	226	* cs -> 0 = vcs, 1 = bcs
	227	* vcs -> 0 = bcs, 1 = cs,
	228	* bcs -> 0 = cs, 1 = vcs.
	229	*/
	230
	231	idx = (other - ring) - 1;
	232	if (idx < 0)
	233	idx += I915_NUM_RINGS;
	234
	235	return idx;
	236	}
	237
8187a2b7 ZN	238	static inline u32
8187a2b7 ZN	239	intel_read_status_page(struct intel_ring_buffer *ring,
78501eac	240	int reg)
8187a2b7	241	{
4225d0f2 DV	242	/* Ensure that the compiler doesn't optimize away the load. */
	243	barrier();
	244	return ring->status_page.page_addr[reg];
8187a2b7 ZN	245	}
8187a2b7 ZN	246
b70ec5bf MK	247	static inline void
	248	intel_write_status_page(struct intel_ring_buffer *ring,
	249	int reg, u32 value)
	250	{
	251	ring->status_page.page_addr[reg] = value;
	252	}
	253
311bd68e CW	254	/**
	255	* Reads a dword out of the status page, which is written to from the command
	256	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
	257	* MI_STORE_DATA_IMM.
	258	*
	259	* The following dwords have a reserved meaning:
	260	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
	261	* 0x04: ring 0 head pointer
	262	* 0x05: ring 1 head pointer (915-class)
	263	* 0x06: ring 2 head pointer (915-class)
	264	* 0x10-0x1b: Context status DWords (GM45)
	265	* 0x1f: Last written status offset. (GM45)
	266	*
	267	* The area from dword 0x20 to 0x3ff is available for driver usage.
	268	*/
311bd68e	269	#define I915_GEM_HWS_INDEX 0x20
9a289771 JB	270	#define I915_GEM_HWS_SCRATCH_INDEX 0x30
9a289771 JB	271	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
311bd68e	272
e3efda49	273	void intel_stop_ring_buffer(struct intel_ring_buffer *ring);
78501eac	274	void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
96f298aa	275
e1f99ce6	276	int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
753b1ad4	277	int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring);
78501eac CW	278	static inline void intel_ring_emit(struct intel_ring_buffer *ring,
78501eac CW	279	u32 data)
e898cd22	280	{
78501eac	281	iowrite32(data, ring->virtual_start + ring->tail);
e898cd22 CW	282	ring->tail += 4;
e898cd22 CW	283	}
09246732 CW	284	static inline void intel_ring_advance(struct intel_ring_buffer *ring)
	285	{
	286	ring->tail &= ring->size - 1;
	287	}
	288	void __intel_ring_advance(struct intel_ring_buffer *ring);
	289
3e960501	290	int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
f7e98ad4	291	void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
a7b9761d CW	292	int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
a7b9761d CW	293	int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
8187a2b7	294
5c1143bb XH	295	int intel_init_render_ring_buffer(struct drm_device *dev);
5c1143bb XH	296	int intel_init_bsd_ring_buffer(struct drm_device *dev);
845f74a7	297	int intel_init_bsd2_ring_buffer(struct drm_device *dev);
549f7365	298	int intel_init_blt_ring_buffer(struct drm_device *dev);
9a8a2213	299	int intel_init_vebox_ring_buffer(struct drm_device *dev);
8187a2b7	300
50877445	301	u64 intel_ring_get_active_head(struct intel_ring_buffer *ring);
78501eac	302	void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
79f321b7	303
a71d8d94 CW	304	static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
	305	{
	306	return ring->tail;
	307	}
	308
9d773091 CW	309	static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
9d773091 CW	310	{
1823521d CW	311	BUG_ON(ring->outstanding_lazy_seqno == 0);
1823521d CW	312	return ring->outstanding_lazy_seqno;
9d773091 CW	313	}
9d773091 CW	314
db53a302 CW	315	static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
	316	{
	317	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
	318	ring->trace_irq_seqno = seqno;
	319	}
	320
e8616b6c CW	321	/* DRI warts */
	322	int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
	323
8187a2b7	324	#endif /* _INTEL_RINGBUFFER_H_ */