Commit | Line | Data |
---|---|---|
9c065a7d DV |
1 | /* |
2 | * Copyright © 2012-2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * Daniel Vetter <daniel.vetter@ffwll.ch> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/vgaarb.h> | |
31 | ||
32 | #include "i915_drv.h" | |
33 | #include "intel_drv.h" | |
9c065a7d | 34 | |
e4e7684f DV |
35 | /** |
36 | * DOC: runtime pm | |
37 | * | |
38 | * The i915 driver supports dynamic enabling and disabling of entire hardware | |
39 | * blocks at runtime. This is especially important on the display side where | |
40 | * software is supposed to control many power gates manually on recent hardware, | |
41 | * since on the GT side a lot of the power management is done by the hardware. | |
42 | * But even there some manual control at the device level is required. | |
43 | * | |
44 | * Since i915 supports a diverse set of platforms with a unified codebase and | |
45 | * hardware engineers just love to shuffle functionality around between power | |
46 | * domains there's a sizeable amount of indirection required. This file provides | |
47 | * generic functions to the driver for grabbing and releasing references for | |
48 | * abstract power domains. It then maps those to the actual power wells | |
49 | * present for a given platform. | |
50 | */ | |
51 | ||
f75a1985 SS |
52 | #define GEN9_ENABLE_DC5(dev) 0 |
53 | #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev) | |
dc174300 | 54 | |
9c065a7d DV |
55 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
56 | for (i = 0; \ | |
57 | i < (power_domains)->power_well_count && \ | |
58 | ((power_well) = &(power_domains)->power_wells[i]); \ | |
59 | i++) \ | |
60 | if ((power_well)->domains & (domain_mask)) | |
61 | ||
62 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ | |
63 | for (i = (power_domains)->power_well_count - 1; \ | |
64 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ | |
65 | i--) \ | |
66 | if ((power_well)->domains & (domain_mask)) | |
67 | ||
5aefb239 SS |
68 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
69 | int power_well_id); | |
70 | ||
e4e7684f | 71 | /* |
9c065a7d DV |
72 | * We should only use the power well if we explicitly asked the hardware to |
73 | * enable it, so check if it's enabled and also check if we've requested it to | |
74 | * be enabled. | |
75 | */ | |
76 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, | |
77 | struct i915_power_well *power_well) | |
78 | { | |
79 | return I915_READ(HSW_PWR_WELL_DRIVER) == | |
80 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); | |
81 | } | |
82 | ||
e4e7684f DV |
83 | /** |
84 | * __intel_display_power_is_enabled - unlocked check for a power domain | |
85 | * @dev_priv: i915 device instance | |
86 | * @domain: power domain to check | |
87 | * | |
88 | * This is the unlocked version of intel_display_power_is_enabled() and should | |
89 | * only be used from error capture and recovery code where deadlocks are | |
90 | * possible. | |
91 | * | |
92 | * Returns: | |
93 | * True when the power domain is enabled, false otherwise. | |
94 | */ | |
f458ebbc DV |
95 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
96 | enum intel_display_power_domain domain) | |
9c065a7d DV |
97 | { |
98 | struct i915_power_domains *power_domains; | |
99 | struct i915_power_well *power_well; | |
100 | bool is_enabled; | |
101 | int i; | |
102 | ||
103 | if (dev_priv->pm.suspended) | |
104 | return false; | |
105 | ||
106 | power_domains = &dev_priv->power_domains; | |
107 | ||
108 | is_enabled = true; | |
109 | ||
110 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
111 | if (power_well->always_on) | |
112 | continue; | |
113 | ||
114 | if (!power_well->hw_enabled) { | |
115 | is_enabled = false; | |
116 | break; | |
117 | } | |
118 | } | |
119 | ||
120 | return is_enabled; | |
121 | } | |
122 | ||
e4e7684f | 123 | /** |
f61ccae3 | 124 | * intel_display_power_is_enabled - check for a power domain |
e4e7684f DV |
125 | * @dev_priv: i915 device instance |
126 | * @domain: power domain to check | |
127 | * | |
128 | * This function can be used to check the hw power domain state. It is mostly | |
129 | * used in hardware state readout functions. Everywhere else code should rely | |
130 | * upon explicit power domain reference counting to ensure that the hardware | |
131 | * block is powered up before accessing it. | |
132 | * | |
133 | * Callers must hold the relevant modesetting locks to ensure that concurrent | |
134 | * threads can't disable the power well while the caller tries to read a few | |
135 | * registers. | |
136 | * | |
137 | * Returns: | |
138 | * True when the power domain is enabled, false otherwise. | |
139 | */ | |
f458ebbc DV |
140 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
141 | enum intel_display_power_domain domain) | |
9c065a7d DV |
142 | { |
143 | struct i915_power_domains *power_domains; | |
144 | bool ret; | |
145 | ||
146 | power_domains = &dev_priv->power_domains; | |
147 | ||
148 | mutex_lock(&power_domains->lock); | |
f458ebbc | 149 | ret = __intel_display_power_is_enabled(dev_priv, domain); |
9c065a7d DV |
150 | mutex_unlock(&power_domains->lock); |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
e4e7684f DV |
155 | /** |
156 | * intel_display_set_init_power - set the initial power domain state | |
157 | * @dev_priv: i915 device instance | |
158 | * @enable: whether to enable or disable the initial power domain state | |
159 | * | |
160 | * For simplicity our driver load/unload and system suspend/resume code assumes | |
161 | * that all power domains are always enabled. This functions controls the state | |
162 | * of this little hack. While the initial power domain state is enabled runtime | |
163 | * pm is effectively disabled. | |
164 | */ | |
d9bc89d9 DV |
165 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
166 | bool enable) | |
167 | { | |
168 | if (dev_priv->power_domains.init_power_on == enable) | |
169 | return; | |
170 | ||
171 | if (enable) | |
172 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
173 | else | |
174 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
175 | ||
176 | dev_priv->power_domains.init_power_on = enable; | |
177 | } | |
178 | ||
9c065a7d DV |
179 | /* |
180 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
181 | * when not needed anymore. We have 4 registers that can request the power well | |
182 | * to be enabled, and it will only be disabled if none of the registers is | |
183 | * requesting it to be enabled. | |
184 | */ | |
185 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) | |
186 | { | |
187 | struct drm_device *dev = dev_priv->dev; | |
188 | ||
189 | /* | |
190 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
191 | * we'll get unclaimed register interrupts. This stops after we write | |
192 | * anything to the VGA MSR register. The vgacon module uses this | |
193 | * register all the time, so if we unbind our driver and, as a | |
194 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
195 | * console_unlock(). So make here we touch the VGA MSR register, making | |
196 | * sure vgacon can keep working normally without triggering interrupts | |
197 | * and error messages. | |
198 | */ | |
199 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
200 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
201 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
202 | ||
25400392 | 203 | if (IS_BROADWELL(dev)) |
4c6c03be DL |
204 | gen8_irq_power_well_post_enable(dev_priv, |
205 | 1 << PIPE_C | 1 << PIPE_B); | |
9c065a7d DV |
206 | } |
207 | ||
d14c0343 DL |
208 | static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, |
209 | struct i915_power_well *power_well) | |
210 | { | |
211 | struct drm_device *dev = dev_priv->dev; | |
212 | ||
213 | /* | |
214 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
215 | * we'll get unclaimed register interrupts. This stops after we write | |
216 | * anything to the VGA MSR register. The vgacon module uses this | |
217 | * register all the time, so if we unbind our driver and, as a | |
218 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
219 | * console_unlock(). So make here we touch the VGA MSR register, making | |
220 | * sure vgacon can keep working normally without triggering interrupts | |
221 | * and error messages. | |
222 | */ | |
223 | if (power_well->data == SKL_DISP_PW_2) { | |
224 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
225 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
226 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
227 | ||
228 | gen8_irq_power_well_post_enable(dev_priv, | |
229 | 1 << PIPE_C | 1 << PIPE_B); | |
230 | } | |
231 | ||
1d2b9526 DL |
232 | if (power_well->data == SKL_DISP_PW_1) { |
233 | intel_prepare_ddi(dev); | |
d14c0343 | 234 | gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); |
1d2b9526 | 235 | } |
d14c0343 DL |
236 | } |
237 | ||
9c065a7d DV |
238 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
239 | struct i915_power_well *power_well, bool enable) | |
240 | { | |
241 | bool is_enabled, enable_requested; | |
242 | uint32_t tmp; | |
243 | ||
244 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
245 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; | |
246 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; | |
247 | ||
248 | if (enable) { | |
249 | if (!enable_requested) | |
250 | I915_WRITE(HSW_PWR_WELL_DRIVER, | |
251 | HSW_PWR_WELL_ENABLE_REQUEST); | |
252 | ||
253 | if (!is_enabled) { | |
254 | DRM_DEBUG_KMS("Enabling power well\n"); | |
255 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
256 | HSW_PWR_WELL_STATE_ENABLED), 20)) | |
257 | DRM_ERROR("Timeout enabling power well\n"); | |
6d729bff | 258 | hsw_power_well_post_enable(dev_priv); |
9c065a7d DV |
259 | } |
260 | ||
9c065a7d DV |
261 | } else { |
262 | if (enable_requested) { | |
263 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | |
264 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
265 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); | |
266 | } | |
267 | } | |
268 | } | |
269 | ||
94dd5138 S |
270 | #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
271 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
272 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
273 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
274 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
275 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
276 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
277 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
278 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
279 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
280 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
281 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
282 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
283 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
284 | BIT(POWER_DOMAIN_AUX_B) | \ | |
285 | BIT(POWER_DOMAIN_AUX_C) | \ | |
286 | BIT(POWER_DOMAIN_AUX_D) | \ | |
287 | BIT(POWER_DOMAIN_AUDIO) | \ | |
288 | BIT(POWER_DOMAIN_VGA) | \ | |
289 | BIT(POWER_DOMAIN_INIT)) | |
290 | #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ | |
291 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
292 | BIT(POWER_DOMAIN_PLLS) | \ | |
293 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
294 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
295 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
296 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
297 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
298 | BIT(POWER_DOMAIN_AUX_A) | \ | |
299 | BIT(POWER_DOMAIN_INIT)) | |
300 | #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ | |
301 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
302 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
303 | BIT(POWER_DOMAIN_INIT)) | |
304 | #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ | |
305 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
306 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
307 | BIT(POWER_DOMAIN_INIT)) | |
308 | #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ | |
309 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
310 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
311 | BIT(POWER_DOMAIN_INIT)) | |
312 | #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ | |
313 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
314 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
315 | BIT(POWER_DOMAIN_INIT)) | |
316 | #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ | |
aeaa2122 | 317 | SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ |
6222709d | 318 | BIT(POWER_DOMAIN_PLLS) | \ |
aeaa2122 | 319 | BIT(POWER_DOMAIN_INIT)) |
94dd5138 S |
320 | #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
321 | (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ | |
322 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
323 | SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \ | |
324 | SKL_DISPLAY_DDI_B_POWER_DOMAINS | \ | |
325 | SKL_DISPLAY_DDI_C_POWER_DOMAINS | \ | |
326 | SKL_DISPLAY_DDI_D_POWER_DOMAINS | \ | |
327 | SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ | |
328 | BIT(POWER_DOMAIN_INIT)) | |
329 | ||
0b4a2a36 S |
330 | #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
331 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
332 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
333 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
334 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
335 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
336 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
337 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
338 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
339 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
340 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
341 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
342 | BIT(POWER_DOMAIN_AUX_B) | \ | |
343 | BIT(POWER_DOMAIN_AUX_C) | \ | |
344 | BIT(POWER_DOMAIN_AUDIO) | \ | |
345 | BIT(POWER_DOMAIN_VGA) | \ | |
346 | BIT(POWER_DOMAIN_INIT)) | |
347 | #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ | |
348 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
349 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
350 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
351 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
352 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
353 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
354 | BIT(POWER_DOMAIN_AUX_A) | \ | |
355 | BIT(POWER_DOMAIN_PLLS) | \ | |
356 | BIT(POWER_DOMAIN_INIT)) | |
357 | #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ | |
358 | (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ | |
359 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ | |
360 | BIT(POWER_DOMAIN_INIT)) | |
361 | ||
664326f8 SK |
362 | static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) |
363 | { | |
364 | struct drm_device *dev = dev_priv->dev; | |
365 | ||
366 | WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); | |
367 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), | |
368 | "DC9 already programmed to be enabled.\n"); | |
369 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
370 | "DC5 still not disabled to enable DC9.\n"); | |
371 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); | |
372 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); | |
373 | ||
374 | /* | |
375 | * TODO: check for the following to verify the conditions to enter DC9 | |
376 | * state are satisfied: | |
377 | * 1] Check relevant display engine registers to verify if mode set | |
378 | * disable sequence was followed. | |
379 | * 2] Check if display uninitialize sequence is initialized. | |
380 | */ | |
381 | } | |
382 | ||
383 | static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) | |
384 | { | |
385 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); | |
386 | WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), | |
387 | "DC9 already programmed to be disabled.\n"); | |
388 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
389 | "DC5 still not disabled.\n"); | |
390 | ||
391 | /* | |
392 | * TODO: check for the following to verify DC9 state was indeed | |
393 | * entered before programming to disable it: | |
394 | * 1] Check relevant display engine registers to verify if mode | |
395 | * set disable sequence was followed. | |
396 | * 2] Check if display uninitialize sequence is initialized. | |
397 | */ | |
398 | } | |
399 | ||
400 | void bxt_enable_dc9(struct drm_i915_private *dev_priv) | |
401 | { | |
402 | uint32_t val; | |
403 | ||
404 | assert_can_enable_dc9(dev_priv); | |
405 | ||
406 | DRM_DEBUG_KMS("Enabling DC9\n"); | |
407 | ||
408 | val = I915_READ(DC_STATE_EN); | |
409 | val |= DC_STATE_EN_DC9; | |
410 | I915_WRITE(DC_STATE_EN, val); | |
411 | POSTING_READ(DC_STATE_EN); | |
412 | } | |
413 | ||
414 | void bxt_disable_dc9(struct drm_i915_private *dev_priv) | |
415 | { | |
416 | uint32_t val; | |
417 | ||
418 | assert_can_disable_dc9(dev_priv); | |
419 | ||
420 | DRM_DEBUG_KMS("Disabling DC9\n"); | |
421 | ||
422 | val = I915_READ(DC_STATE_EN); | |
423 | val &= ~DC_STATE_EN_DC9; | |
424 | I915_WRITE(DC_STATE_EN, val); | |
425 | POSTING_READ(DC_STATE_EN); | |
426 | } | |
427 | ||
6b457d31 SK |
428 | static void gen9_set_dc_state_debugmask_memory_up( |
429 | struct drm_i915_private *dev_priv) | |
430 | { | |
431 | uint32_t val; | |
432 | ||
433 | /* The below bit doesn't need to be cleared ever afterwards */ | |
434 | val = I915_READ(DC_STATE_DEBUG); | |
435 | if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { | |
436 | val |= DC_STATE_DEBUG_MASK_MEMORY_UP; | |
437 | I915_WRITE(DC_STATE_DEBUG, val); | |
438 | POSTING_READ(DC_STATE_DEBUG); | |
439 | } | |
440 | } | |
441 | ||
5aefb239 | 442 | static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) |
dc174300 | 443 | { |
6b457d31 | 444 | struct drm_device *dev = dev_priv->dev; |
5aefb239 SS |
445 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
446 | SKL_DISP_PW_2); | |
447 | ||
448 | WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); | |
449 | WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); | |
450 | WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n"); | |
451 | ||
452 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), | |
453 | "DC5 already programmed to be enabled.\n"); | |
454 | WARN(dev_priv->pm.suspended, | |
455 | "DC5 cannot be enabled, if platform is runtime-suspended.\n"); | |
456 | ||
457 | assert_csr_loaded(dev_priv); | |
458 | } | |
459 | ||
460 | static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) | |
461 | { | |
462 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, | |
463 | SKL_DISP_PW_2); | |
93c7cb6c SS |
464 | /* |
465 | * During initialization, the firmware may not be loaded yet. | |
466 | * We still want to make sure that the DC enabling flag is cleared. | |
467 | */ | |
468 | if (dev_priv->power_domains.initializing) | |
469 | return; | |
5aefb239 SS |
470 | |
471 | WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n"); | |
472 | WARN(dev_priv->pm.suspended, | |
473 | "Disabling of DC5 while platform is runtime-suspended should never happen.\n"); | |
474 | } | |
475 | ||
476 | static void gen9_enable_dc5(struct drm_i915_private *dev_priv) | |
477 | { | |
6b457d31 SK |
478 | uint32_t val; |
479 | ||
5aefb239 | 480 | assert_can_enable_dc5(dev_priv); |
6b457d31 SK |
481 | |
482 | DRM_DEBUG_KMS("Enabling DC5\n"); | |
483 | ||
484 | gen9_set_dc_state_debugmask_memory_up(dev_priv); | |
485 | ||
486 | val = I915_READ(DC_STATE_EN); | |
487 | val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; | |
488 | val |= DC_STATE_EN_UPTO_DC5; | |
489 | I915_WRITE(DC_STATE_EN, val); | |
490 | POSTING_READ(DC_STATE_EN); | |
dc174300 SS |
491 | } |
492 | ||
493 | static void gen9_disable_dc5(struct drm_i915_private *dev_priv) | |
494 | { | |
6b457d31 SK |
495 | uint32_t val; |
496 | ||
5aefb239 | 497 | assert_can_disable_dc5(dev_priv); |
6b457d31 SK |
498 | |
499 | DRM_DEBUG_KMS("Disabling DC5\n"); | |
500 | ||
501 | val = I915_READ(DC_STATE_EN); | |
502 | val &= ~DC_STATE_EN_UPTO_DC5; | |
503 | I915_WRITE(DC_STATE_EN, val); | |
504 | POSTING_READ(DC_STATE_EN); | |
dc174300 SS |
505 | } |
506 | ||
93c7cb6c | 507 | static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) |
f75a1985 | 508 | { |
74b4f371 | 509 | struct drm_device *dev = dev_priv->dev; |
93c7cb6c SS |
510 | |
511 | WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); | |
512 | WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); | |
513 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
514 | "Backlight is not disabled.\n"); | |
515 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), | |
516 | "DC6 already programmed to be enabled.\n"); | |
517 | ||
518 | assert_csr_loaded(dev_priv); | |
519 | } | |
520 | ||
521 | static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) | |
522 | { | |
523 | /* | |
524 | * During initialization, the firmware may not be loaded yet. | |
525 | * We still want to make sure that the DC enabling flag is cleared. | |
526 | */ | |
527 | if (dev_priv->power_domains.initializing) | |
528 | return; | |
529 | ||
530 | assert_csr_loaded(dev_priv); | |
531 | WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), | |
532 | "DC6 already programmed to be disabled.\n"); | |
533 | } | |
534 | ||
535 | static void skl_enable_dc6(struct drm_i915_private *dev_priv) | |
536 | { | |
74b4f371 SK |
537 | uint32_t val; |
538 | ||
93c7cb6c | 539 | assert_can_enable_dc6(dev_priv); |
74b4f371 SK |
540 | |
541 | DRM_DEBUG_KMS("Enabling DC6\n"); | |
542 | ||
543 | gen9_set_dc_state_debugmask_memory_up(dev_priv); | |
544 | ||
545 | val = I915_READ(DC_STATE_EN); | |
546 | val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; | |
547 | val |= DC_STATE_EN_UPTO_DC6; | |
548 | I915_WRITE(DC_STATE_EN, val); | |
549 | POSTING_READ(DC_STATE_EN); | |
f75a1985 SS |
550 | } |
551 | ||
552 | static void skl_disable_dc6(struct drm_i915_private *dev_priv) | |
553 | { | |
74b4f371 SK |
554 | uint32_t val; |
555 | ||
93c7cb6c | 556 | assert_can_disable_dc6(dev_priv); |
74b4f371 SK |
557 | |
558 | DRM_DEBUG_KMS("Disabling DC6\n"); | |
559 | ||
560 | val = I915_READ(DC_STATE_EN); | |
561 | val &= ~DC_STATE_EN_UPTO_DC6; | |
562 | I915_WRITE(DC_STATE_EN, val); | |
563 | POSTING_READ(DC_STATE_EN); | |
f75a1985 SS |
564 | } |
565 | ||
94dd5138 S |
566 | static void skl_set_power_well(struct drm_i915_private *dev_priv, |
567 | struct i915_power_well *power_well, bool enable) | |
568 | { | |
dc174300 | 569 | struct drm_device *dev = dev_priv->dev; |
94dd5138 S |
570 | uint32_t tmp, fuse_status; |
571 | uint32_t req_mask, state_mask; | |
2a51835f | 572 | bool is_enabled, enable_requested, check_fuse_status = false; |
94dd5138 S |
573 | |
574 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
575 | fuse_status = I915_READ(SKL_FUSE_STATUS); | |
576 | ||
577 | switch (power_well->data) { | |
578 | case SKL_DISP_PW_1: | |
579 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
580 | SKL_FUSE_PG0_DIST_STATUS), 1)) { | |
581 | DRM_ERROR("PG0 not enabled\n"); | |
582 | return; | |
583 | } | |
584 | break; | |
585 | case SKL_DISP_PW_2: | |
586 | if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { | |
587 | DRM_ERROR("PG1 in disabled state\n"); | |
588 | return; | |
589 | } | |
590 | break; | |
591 | case SKL_DISP_PW_DDI_A_E: | |
592 | case SKL_DISP_PW_DDI_B: | |
593 | case SKL_DISP_PW_DDI_C: | |
594 | case SKL_DISP_PW_DDI_D: | |
595 | case SKL_DISP_PW_MISC_IO: | |
596 | break; | |
597 | default: | |
598 | WARN(1, "Unknown power well %lu\n", power_well->data); | |
599 | return; | |
600 | } | |
601 | ||
602 | req_mask = SKL_POWER_WELL_REQ(power_well->data); | |
2a51835f | 603 | enable_requested = tmp & req_mask; |
94dd5138 | 604 | state_mask = SKL_POWER_WELL_STATE(power_well->data); |
2a51835f | 605 | is_enabled = tmp & state_mask; |
94dd5138 S |
606 | |
607 | if (enable) { | |
2a51835f | 608 | if (!enable_requested) { |
dc174300 SS |
609 | WARN((tmp & state_mask) && |
610 | !I915_READ(HSW_PWR_WELL_BIOS), | |
611 | "Invalid for power well status to be enabled, unless done by the BIOS, \ | |
612 | when request is to disable!\n"); | |
f75a1985 SS |
613 | if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && |
614 | power_well->data == SKL_DISP_PW_2) { | |
615 | if (SKL_ENABLE_DC6(dev)) { | |
616 | skl_disable_dc6(dev_priv); | |
617 | /* | |
618 | * DDI buffer programming unnecessary during driver-load/resume | |
619 | * as it's already done during modeset initialization then. | |
620 | * It's also invalid here as encoder list is still uninitialized. | |
621 | */ | |
622 | if (!dev_priv->power_domains.initializing) | |
623 | intel_prepare_ddi(dev); | |
624 | } else { | |
625 | gen9_disable_dc5(dev_priv); | |
626 | } | |
627 | } | |
94dd5138 | 628 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
94dd5138 S |
629 | } |
630 | ||
2a51835f | 631 | if (!is_enabled) { |
510e6fdd | 632 | DRM_DEBUG_KMS("Enabling %s\n", power_well->name); |
94dd5138 S |
633 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
634 | state_mask), 1)) | |
635 | DRM_ERROR("%s enable timeout\n", | |
636 | power_well->name); | |
637 | check_fuse_status = true; | |
638 | } | |
639 | } else { | |
2a51835f | 640 | if (enable_requested) { |
94dd5138 S |
641 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); |
642 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
643 | DRM_DEBUG_KMS("Disabling %s\n", power_well->name); | |
dc174300 | 644 | |
f75a1985 | 645 | if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && |
dc174300 SS |
646 | power_well->data == SKL_DISP_PW_2) { |
647 | enum csr_state state; | |
f75a1985 SS |
648 | /* TODO: wait for a completion event or |
649 | * similar here instead of busy | |
650 | * waiting using wait_for function. | |
651 | */ | |
dc174300 SS |
652 | wait_for((state = intel_csr_load_status_get(dev_priv)) != |
653 | FW_UNINITIALIZED, 1000); | |
654 | if (state != FW_LOADED) | |
655 | DRM_ERROR("CSR firmware not ready (%d)\n", | |
656 | state); | |
657 | else | |
f75a1985 SS |
658 | if (SKL_ENABLE_DC6(dev)) |
659 | skl_enable_dc6(dev_priv); | |
660 | else | |
661 | gen9_enable_dc5(dev_priv); | |
dc174300 | 662 | } |
94dd5138 S |
663 | } |
664 | } | |
665 | ||
666 | if (check_fuse_status) { | |
667 | if (power_well->data == SKL_DISP_PW_1) { | |
668 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
669 | SKL_FUSE_PG1_DIST_STATUS), 1)) | |
670 | DRM_ERROR("PG1 distributing status timeout\n"); | |
671 | } else if (power_well->data == SKL_DISP_PW_2) { | |
672 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
673 | SKL_FUSE_PG2_DIST_STATUS), 1)) | |
674 | DRM_ERROR("PG2 distributing status timeout\n"); | |
675 | } | |
676 | } | |
d14c0343 DL |
677 | |
678 | if (enable && !is_enabled) | |
679 | skl_power_well_post_enable(dev_priv, power_well); | |
94dd5138 S |
680 | } |
681 | ||
9c065a7d DV |
682 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
683 | struct i915_power_well *power_well) | |
684 | { | |
685 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); | |
686 | ||
687 | /* | |
688 | * We're taking over the BIOS, so clear any requests made by it since | |
689 | * the driver is in charge now. | |
690 | */ | |
691 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) | |
692 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
693 | } | |
694 | ||
695 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, | |
696 | struct i915_power_well *power_well) | |
697 | { | |
698 | hsw_set_power_well(dev_priv, power_well, true); | |
699 | } | |
700 | ||
701 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, | |
702 | struct i915_power_well *power_well) | |
703 | { | |
704 | hsw_set_power_well(dev_priv, power_well, false); | |
705 | } | |
706 | ||
94dd5138 S |
707 | static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, |
708 | struct i915_power_well *power_well) | |
709 | { | |
710 | uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | | |
711 | SKL_POWER_WELL_STATE(power_well->data); | |
712 | ||
713 | return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; | |
714 | } | |
715 | ||
716 | static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
717 | struct i915_power_well *power_well) | |
718 | { | |
719 | skl_set_power_well(dev_priv, power_well, power_well->count > 0); | |
720 | ||
721 | /* Clear any request made by BIOS as driver is taking over */ | |
722 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
723 | } | |
724 | ||
725 | static void skl_power_well_enable(struct drm_i915_private *dev_priv, | |
726 | struct i915_power_well *power_well) | |
727 | { | |
728 | skl_set_power_well(dev_priv, power_well, true); | |
729 | } | |
730 | ||
731 | static void skl_power_well_disable(struct drm_i915_private *dev_priv, | |
732 | struct i915_power_well *power_well) | |
733 | { | |
734 | skl_set_power_well(dev_priv, power_well, false); | |
735 | } | |
736 | ||
9c065a7d DV |
737 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
738 | struct i915_power_well *power_well) | |
739 | { | |
740 | } | |
741 | ||
742 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, | |
743 | struct i915_power_well *power_well) | |
744 | { | |
745 | return true; | |
746 | } | |
747 | ||
748 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, | |
749 | struct i915_power_well *power_well, bool enable) | |
750 | { | |
751 | enum punit_power_well power_well_id = power_well->data; | |
752 | u32 mask; | |
753 | u32 state; | |
754 | u32 ctrl; | |
755 | ||
756 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
757 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : | |
758 | PUNIT_PWRGT_PWR_GATE(power_well_id); | |
759 | ||
760 | mutex_lock(&dev_priv->rps.hw_lock); | |
761 | ||
762 | #define COND \ | |
763 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) | |
764 | ||
765 | if (COND) | |
766 | goto out; | |
767 | ||
768 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); | |
769 | ctrl &= ~mask; | |
770 | ctrl |= state; | |
771 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); | |
772 | ||
773 | if (wait_for(COND, 100)) | |
7e35ab88 | 774 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
9c065a7d DV |
775 | state, |
776 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); | |
777 | ||
778 | #undef COND | |
779 | ||
780 | out: | |
781 | mutex_unlock(&dev_priv->rps.hw_lock); | |
782 | } | |
783 | ||
784 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
785 | struct i915_power_well *power_well) | |
786 | { | |
787 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); | |
788 | } | |
789 | ||
790 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, | |
791 | struct i915_power_well *power_well) | |
792 | { | |
793 | vlv_set_power_well(dev_priv, power_well, true); | |
794 | } | |
795 | ||
796 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, | |
797 | struct i915_power_well *power_well) | |
798 | { | |
799 | vlv_set_power_well(dev_priv, power_well, false); | |
800 | } | |
801 | ||
802 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, | |
803 | struct i915_power_well *power_well) | |
804 | { | |
805 | int power_well_id = power_well->data; | |
806 | bool enabled = false; | |
807 | u32 mask; | |
808 | u32 state; | |
809 | u32 ctrl; | |
810 | ||
811 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
812 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); | |
813 | ||
814 | mutex_lock(&dev_priv->rps.hw_lock); | |
815 | ||
816 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; | |
817 | /* | |
818 | * We only ever set the power-on and power-gate states, anything | |
819 | * else is unexpected. | |
820 | */ | |
821 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && | |
822 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); | |
823 | if (state == ctrl) | |
824 | enabled = true; | |
825 | ||
826 | /* | |
827 | * A transient state at this point would mean some unexpected party | |
828 | * is poking at the power controls too. | |
829 | */ | |
830 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; | |
831 | WARN_ON(ctrl != state); | |
832 | ||
833 | mutex_unlock(&dev_priv->rps.hw_lock); | |
834 | ||
835 | return enabled; | |
836 | } | |
837 | ||
2be7d540 | 838 | static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) |
9c065a7d | 839 | { |
9c065a7d DV |
840 | |
841 | spin_lock_irq(&dev_priv->irq_lock); | |
842 | valleyview_enable_display_irqs(dev_priv); | |
843 | spin_unlock_irq(&dev_priv->irq_lock); | |
844 | ||
845 | /* | |
846 | * During driver initialization/resume we can avoid restoring the | |
847 | * part of the HW/SW state that will be inited anyway explicitly. | |
848 | */ | |
849 | if (dev_priv->power_domains.initializing) | |
850 | return; | |
851 | ||
b963291c | 852 | intel_hpd_init(dev_priv); |
9c065a7d DV |
853 | |
854 | i915_redisable_vga_power_on(dev_priv->dev); | |
855 | } | |
856 | ||
2be7d540 VS |
857 | static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) |
858 | { | |
859 | spin_lock_irq(&dev_priv->irq_lock); | |
860 | valleyview_disable_display_irqs(dev_priv); | |
861 | spin_unlock_irq(&dev_priv->irq_lock); | |
862 | ||
863 | vlv_power_sequencer_reset(dev_priv); | |
864 | } | |
865 | ||
866 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, | |
867 | struct i915_power_well *power_well) | |
868 | { | |
869 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
870 | ||
871 | vlv_set_power_well(dev_priv, power_well, true); | |
872 | ||
873 | vlv_display_power_well_init(dev_priv); | |
874 | } | |
875 | ||
9c065a7d DV |
876 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
877 | struct i915_power_well *power_well) | |
878 | { | |
879 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
880 | ||
2be7d540 | 881 | vlv_display_power_well_deinit(dev_priv); |
9c065a7d DV |
882 | |
883 | vlv_set_power_well(dev_priv, power_well, false); | |
9c065a7d DV |
884 | } |
885 | ||
886 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
887 | struct i915_power_well *power_well) | |
888 | { | |
889 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
890 | ||
891 | /* | |
892 | * Enable the CRI clock source so we can get at the | |
893 | * display and the reference clock for VGA | |
894 | * hotplug / manual detection. | |
895 | */ | |
b8afb911 | 896 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS | |
60bfe44f | 897 | DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
9c065a7d DV |
898 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
899 | ||
900 | vlv_set_power_well(dev_priv, power_well, true); | |
901 | ||
902 | /* | |
903 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
904 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
905 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
906 | * b. The other bits such as sfr settings / modesel may all | |
907 | * be set to 0. | |
908 | * | |
909 | * This should only be done on init and resume from S3 with | |
910 | * both PLLs disabled, or we risk losing DPIO and PLL | |
911 | * synchronization. | |
912 | */ | |
913 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
914 | } | |
915 | ||
916 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
917 | struct i915_power_well *power_well) | |
918 | { | |
919 | enum pipe pipe; | |
920 | ||
921 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
922 | ||
923 | for_each_pipe(dev_priv, pipe) | |
924 | assert_pll_disabled(dev_priv, pipe); | |
925 | ||
926 | /* Assert common reset */ | |
927 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); | |
928 | ||
929 | vlv_set_power_well(dev_priv, power_well, false); | |
930 | } | |
931 | ||
932 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
933 | struct i915_power_well *power_well) | |
934 | { | |
935 | enum dpio_phy phy; | |
936 | ||
937 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
938 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
939 | ||
940 | /* | |
941 | * Enable the CRI clock source so we can get at the | |
942 | * display and the reference clock for VGA | |
943 | * hotplug / manual detection. | |
944 | */ | |
945 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
946 | phy = DPIO_PHY0; | |
b8afb911 | 947 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS | |
60bfe44f | 948 | DPLL_REF_CLK_ENABLE_VLV); |
b8afb911 | 949 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS | |
60bfe44f | 950 | DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
9c065a7d DV |
951 | } else { |
952 | phy = DPIO_PHY1; | |
b8afb911 | 953 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS | |
60bfe44f | 954 | DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
9c065a7d DV |
955 | } |
956 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | |
957 | vlv_set_power_well(dev_priv, power_well, true); | |
958 | ||
959 | /* Poll for phypwrgood signal */ | |
960 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) | |
961 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
962 | ||
70722468 VS |
963 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); |
964 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
9c065a7d DV |
965 | } |
966 | ||
967 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
968 | struct i915_power_well *power_well) | |
969 | { | |
970 | enum dpio_phy phy; | |
971 | ||
972 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
973 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
974 | ||
975 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
976 | phy = DPIO_PHY0; | |
977 | assert_pll_disabled(dev_priv, PIPE_A); | |
978 | assert_pll_disabled(dev_priv, PIPE_B); | |
979 | } else { | |
980 | phy = DPIO_PHY1; | |
981 | assert_pll_disabled(dev_priv, PIPE_C); | |
982 | } | |
983 | ||
70722468 VS |
984 | dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); |
985 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
9c065a7d DV |
986 | |
987 | vlv_set_power_well(dev_priv, power_well, false); | |
988 | } | |
989 | ||
990 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, | |
991 | struct i915_power_well *power_well) | |
992 | { | |
993 | enum pipe pipe = power_well->data; | |
994 | bool enabled; | |
995 | u32 state, ctrl; | |
996 | ||
997 | mutex_lock(&dev_priv->rps.hw_lock); | |
998 | ||
999 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); | |
1000 | /* | |
1001 | * We only ever set the power-on and power-gate states, anything | |
1002 | * else is unexpected. | |
1003 | */ | |
1004 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); | |
1005 | enabled = state == DP_SSS_PWR_ON(pipe); | |
1006 | ||
1007 | /* | |
1008 | * A transient state at this point would mean some unexpected party | |
1009 | * is poking at the power controls too. | |
1010 | */ | |
1011 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); | |
1012 | WARN_ON(ctrl << 16 != state); | |
1013 | ||
1014 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1015 | ||
1016 | return enabled; | |
1017 | } | |
1018 | ||
1019 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, | |
1020 | struct i915_power_well *power_well, | |
1021 | bool enable) | |
1022 | { | |
1023 | enum pipe pipe = power_well->data; | |
1024 | u32 state; | |
1025 | u32 ctrl; | |
1026 | ||
1027 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); | |
1028 | ||
1029 | mutex_lock(&dev_priv->rps.hw_lock); | |
1030 | ||
1031 | #define COND \ | |
1032 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) | |
1033 | ||
1034 | if (COND) | |
1035 | goto out; | |
1036 | ||
1037 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
1038 | ctrl &= ~DP_SSC_MASK(pipe); | |
1039 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); | |
1040 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); | |
1041 | ||
1042 | if (wait_for(COND, 100)) | |
7e35ab88 | 1043 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
9c065a7d DV |
1044 | state, |
1045 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); | |
1046 | ||
1047 | #undef COND | |
1048 | ||
1049 | out: | |
1050 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1051 | } | |
1052 | ||
1053 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
1054 | struct i915_power_well *power_well) | |
1055 | { | |
8fcd5cd8 VS |
1056 | WARN_ON_ONCE(power_well->data != PIPE_A); |
1057 | ||
9c065a7d DV |
1058 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
1059 | } | |
1060 | ||
1061 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, | |
1062 | struct i915_power_well *power_well) | |
1063 | { | |
8fcd5cd8 | 1064 | WARN_ON_ONCE(power_well->data != PIPE_A); |
9c065a7d DV |
1065 | |
1066 | chv_set_pipe_power_well(dev_priv, power_well, true); | |
afd6275d | 1067 | |
2be7d540 | 1068 | vlv_display_power_well_init(dev_priv); |
9c065a7d DV |
1069 | } |
1070 | ||
1071 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, | |
1072 | struct i915_power_well *power_well) | |
1073 | { | |
8fcd5cd8 VS |
1074 | WARN_ON_ONCE(power_well->data != PIPE_A); |
1075 | ||
2be7d540 | 1076 | vlv_display_power_well_deinit(dev_priv); |
afd6275d | 1077 | |
9c065a7d DV |
1078 | chv_set_pipe_power_well(dev_priv, power_well, false); |
1079 | } | |
1080 | ||
e4e7684f DV |
1081 | /** |
1082 | * intel_display_power_get - grab a power domain reference | |
1083 | * @dev_priv: i915 device instance | |
1084 | * @domain: power domain to reference | |
1085 | * | |
1086 | * This function grabs a power domain reference for @domain and ensures that the | |
1087 | * power domain and all its parents are powered up. Therefore users should only | |
1088 | * grab a reference to the innermost power domain they need. | |
1089 | * | |
1090 | * Any power domain reference obtained by this function must have a symmetric | |
1091 | * call to intel_display_power_put() to release the reference again. | |
1092 | */ | |
9c065a7d DV |
1093 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1094 | enum intel_display_power_domain domain) | |
1095 | { | |
1096 | struct i915_power_domains *power_domains; | |
1097 | struct i915_power_well *power_well; | |
1098 | int i; | |
1099 | ||
1100 | intel_runtime_pm_get(dev_priv); | |
1101 | ||
1102 | power_domains = &dev_priv->power_domains; | |
1103 | ||
1104 | mutex_lock(&power_domains->lock); | |
1105 | ||
1106 | for_each_power_well(i, power_well, BIT(domain), power_domains) { | |
1107 | if (!power_well->count++) { | |
1108 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); | |
1109 | power_well->ops->enable(dev_priv, power_well); | |
1110 | power_well->hw_enabled = true; | |
1111 | } | |
9c065a7d DV |
1112 | } |
1113 | ||
1114 | power_domains->domain_use_count[domain]++; | |
1115 | ||
1116 | mutex_unlock(&power_domains->lock); | |
1117 | } | |
1118 | ||
e4e7684f DV |
1119 | /** |
1120 | * intel_display_power_put - release a power domain reference | |
1121 | * @dev_priv: i915 device instance | |
1122 | * @domain: power domain to reference | |
1123 | * | |
1124 | * This function drops the power domain reference obtained by | |
1125 | * intel_display_power_get() and might power down the corresponding hardware | |
1126 | * block right away if this is the last reference. | |
1127 | */ | |
9c065a7d DV |
1128 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
1129 | enum intel_display_power_domain domain) | |
1130 | { | |
1131 | struct i915_power_domains *power_domains; | |
1132 | struct i915_power_well *power_well; | |
1133 | int i; | |
1134 | ||
1135 | power_domains = &dev_priv->power_domains; | |
1136 | ||
1137 | mutex_lock(&power_domains->lock); | |
1138 | ||
1139 | WARN_ON(!power_domains->domain_use_count[domain]); | |
1140 | power_domains->domain_use_count[domain]--; | |
1141 | ||
1142 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
1143 | WARN_ON(!power_well->count); | |
1144 | ||
1145 | if (!--power_well->count && i915.disable_power_well) { | |
1146 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); | |
1147 | power_well->hw_enabled = false; | |
1148 | power_well->ops->disable(dev_priv, power_well); | |
1149 | } | |
9c065a7d DV |
1150 | } |
1151 | ||
1152 | mutex_unlock(&power_domains->lock); | |
1153 | ||
1154 | intel_runtime_pm_put(dev_priv); | |
1155 | } | |
1156 | ||
1157 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) | |
1158 | ||
1159 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ | |
1160 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
1161 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
1162 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
1163 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
1164 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1165 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1166 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1167 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1168 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
1169 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1170 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
1171 | BIT(POWER_DOMAIN_PLLS) | \ | |
1407121a S |
1172 | BIT(POWER_DOMAIN_AUX_A) | \ |
1173 | BIT(POWER_DOMAIN_AUX_B) | \ | |
1174 | BIT(POWER_DOMAIN_AUX_C) | \ | |
1175 | BIT(POWER_DOMAIN_AUX_D) | \ | |
9c065a7d DV |
1176 | BIT(POWER_DOMAIN_INIT)) |
1177 | #define HSW_DISPLAY_POWER_DOMAINS ( \ | |
1178 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ | |
1179 | BIT(POWER_DOMAIN_INIT)) | |
1180 | ||
1181 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ | |
1182 | HSW_ALWAYS_ON_POWER_DOMAINS | \ | |
1183 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
1184 | #define BDW_DISPLAY_POWER_DOMAINS ( \ | |
1185 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ | |
1186 | BIT(POWER_DOMAIN_INIT)) | |
1187 | ||
1188 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) | |
1189 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK | |
1190 | ||
1191 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
1192 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1193 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1194 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1195 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1196 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
1407121a S |
1197 | BIT(POWER_DOMAIN_AUX_B) | \ |
1198 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
1199 | BIT(POWER_DOMAIN_INIT)) |
1200 | ||
1201 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ | |
1202 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1203 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1407121a | 1204 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
1205 | BIT(POWER_DOMAIN_INIT)) |
1206 | ||
1207 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ | |
1208 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1407121a | 1209 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
1210 | BIT(POWER_DOMAIN_INIT)) |
1211 | ||
1212 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ | |
1213 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1214 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a | 1215 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
1216 | BIT(POWER_DOMAIN_INIT)) |
1217 | ||
1218 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ | |
1219 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a | 1220 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
1221 | BIT(POWER_DOMAIN_INIT)) |
1222 | ||
9c065a7d DV |
1223 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
1224 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1225 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1226 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1227 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a S |
1228 | BIT(POWER_DOMAIN_AUX_B) | \ |
1229 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
1230 | BIT(POWER_DOMAIN_INIT)) |
1231 | ||
1232 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ | |
1233 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
1234 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1407121a | 1235 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d DV |
1236 | BIT(POWER_DOMAIN_INIT)) |
1237 | ||
9c065a7d DV |
1238 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
1239 | .sync_hw = i9xx_always_on_power_well_noop, | |
1240 | .enable = i9xx_always_on_power_well_noop, | |
1241 | .disable = i9xx_always_on_power_well_noop, | |
1242 | .is_enabled = i9xx_always_on_power_well_enabled, | |
1243 | }; | |
1244 | ||
1245 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { | |
1246 | .sync_hw = chv_pipe_power_well_sync_hw, | |
1247 | .enable = chv_pipe_power_well_enable, | |
1248 | .disable = chv_pipe_power_well_disable, | |
1249 | .is_enabled = chv_pipe_power_well_enabled, | |
1250 | }; | |
1251 | ||
1252 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { | |
1253 | .sync_hw = vlv_power_well_sync_hw, | |
1254 | .enable = chv_dpio_cmn_power_well_enable, | |
1255 | .disable = chv_dpio_cmn_power_well_disable, | |
1256 | .is_enabled = vlv_power_well_enabled, | |
1257 | }; | |
1258 | ||
1259 | static struct i915_power_well i9xx_always_on_power_well[] = { | |
1260 | { | |
1261 | .name = "always-on", | |
1262 | .always_on = 1, | |
1263 | .domains = POWER_DOMAIN_MASK, | |
1264 | .ops = &i9xx_always_on_power_well_ops, | |
1265 | }, | |
1266 | }; | |
1267 | ||
1268 | static const struct i915_power_well_ops hsw_power_well_ops = { | |
1269 | .sync_hw = hsw_power_well_sync_hw, | |
1270 | .enable = hsw_power_well_enable, | |
1271 | .disable = hsw_power_well_disable, | |
1272 | .is_enabled = hsw_power_well_enabled, | |
1273 | }; | |
1274 | ||
94dd5138 S |
1275 | static const struct i915_power_well_ops skl_power_well_ops = { |
1276 | .sync_hw = skl_power_well_sync_hw, | |
1277 | .enable = skl_power_well_enable, | |
1278 | .disable = skl_power_well_disable, | |
1279 | .is_enabled = skl_power_well_enabled, | |
1280 | }; | |
1281 | ||
9c065a7d DV |
1282 | static struct i915_power_well hsw_power_wells[] = { |
1283 | { | |
1284 | .name = "always-on", | |
1285 | .always_on = 1, | |
1286 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, | |
1287 | .ops = &i9xx_always_on_power_well_ops, | |
1288 | }, | |
1289 | { | |
1290 | .name = "display", | |
1291 | .domains = HSW_DISPLAY_POWER_DOMAINS, | |
1292 | .ops = &hsw_power_well_ops, | |
1293 | }, | |
1294 | }; | |
1295 | ||
1296 | static struct i915_power_well bdw_power_wells[] = { | |
1297 | { | |
1298 | .name = "always-on", | |
1299 | .always_on = 1, | |
1300 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, | |
1301 | .ops = &i9xx_always_on_power_well_ops, | |
1302 | }, | |
1303 | { | |
1304 | .name = "display", | |
1305 | .domains = BDW_DISPLAY_POWER_DOMAINS, | |
1306 | .ops = &hsw_power_well_ops, | |
1307 | }, | |
1308 | }; | |
1309 | ||
1310 | static const struct i915_power_well_ops vlv_display_power_well_ops = { | |
1311 | .sync_hw = vlv_power_well_sync_hw, | |
1312 | .enable = vlv_display_power_well_enable, | |
1313 | .disable = vlv_display_power_well_disable, | |
1314 | .is_enabled = vlv_power_well_enabled, | |
1315 | }; | |
1316 | ||
1317 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { | |
1318 | .sync_hw = vlv_power_well_sync_hw, | |
1319 | .enable = vlv_dpio_cmn_power_well_enable, | |
1320 | .disable = vlv_dpio_cmn_power_well_disable, | |
1321 | .is_enabled = vlv_power_well_enabled, | |
1322 | }; | |
1323 | ||
1324 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { | |
1325 | .sync_hw = vlv_power_well_sync_hw, | |
1326 | .enable = vlv_power_well_enable, | |
1327 | .disable = vlv_power_well_disable, | |
1328 | .is_enabled = vlv_power_well_enabled, | |
1329 | }; | |
1330 | ||
1331 | static struct i915_power_well vlv_power_wells[] = { | |
1332 | { | |
1333 | .name = "always-on", | |
1334 | .always_on = 1, | |
1335 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1336 | .ops = &i9xx_always_on_power_well_ops, | |
1337 | }, | |
1338 | { | |
1339 | .name = "display", | |
1340 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
1341 | .data = PUNIT_POWER_WELL_DISP2D, | |
1342 | .ops = &vlv_display_power_well_ops, | |
1343 | }, | |
1344 | { | |
1345 | .name = "dpio-tx-b-01", | |
1346 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1347 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1348 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1349 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1350 | .ops = &vlv_dpio_power_well_ops, | |
1351 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
1352 | }, | |
1353 | { | |
1354 | .name = "dpio-tx-b-23", | |
1355 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1356 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1357 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1358 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1359 | .ops = &vlv_dpio_power_well_ops, | |
1360 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
1361 | }, | |
1362 | { | |
1363 | .name = "dpio-tx-c-01", | |
1364 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1365 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1366 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1367 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1368 | .ops = &vlv_dpio_power_well_ops, | |
1369 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
1370 | }, | |
1371 | { | |
1372 | .name = "dpio-tx-c-23", | |
1373 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1374 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1375 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1376 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1377 | .ops = &vlv_dpio_power_well_ops, | |
1378 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
1379 | }, | |
1380 | { | |
1381 | .name = "dpio-common", | |
1382 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, | |
1383 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1384 | .ops = &vlv_dpio_cmn_power_well_ops, | |
1385 | }, | |
1386 | }; | |
1387 | ||
1388 | static struct i915_power_well chv_power_wells[] = { | |
1389 | { | |
1390 | .name = "always-on", | |
1391 | .always_on = 1, | |
1392 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1393 | .ops = &i9xx_always_on_power_well_ops, | |
1394 | }, | |
9c065a7d DV |
1395 | { |
1396 | .name = "display", | |
baa4e575 | 1397 | /* |
fde61e4b VS |
1398 | * Pipe A power well is the new disp2d well. Pipe B and C |
1399 | * power wells don't actually exist. Pipe A power well is | |
1400 | * required for any pipe to work. | |
baa4e575 | 1401 | */ |
fde61e4b | 1402 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
9c065a7d DV |
1403 | .data = PIPE_A, |
1404 | .ops = &chv_pipe_power_well_ops, | |
1405 | }, | |
9c065a7d DV |
1406 | { |
1407 | .name = "dpio-common-bc", | |
71849b67 | 1408 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, |
9c065a7d DV |
1409 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
1410 | .ops = &chv_dpio_cmn_power_well_ops, | |
1411 | }, | |
1412 | { | |
1413 | .name = "dpio-common-d", | |
71849b67 | 1414 | .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, |
9c065a7d DV |
1415 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
1416 | .ops = &chv_dpio_cmn_power_well_ops, | |
1417 | }, | |
9c065a7d DV |
1418 | }; |
1419 | ||
1420 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, | |
5aefb239 | 1421 | int power_well_id) |
9c065a7d DV |
1422 | { |
1423 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1424 | struct i915_power_well *power_well; | |
1425 | int i; | |
1426 | ||
1427 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
1428 | if (power_well->data == power_well_id) | |
1429 | return power_well; | |
1430 | } | |
1431 | ||
1432 | return NULL; | |
1433 | } | |
1434 | ||
5aefb239 SS |
1435 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
1436 | int power_well_id) | |
1437 | { | |
1438 | struct i915_power_well *power_well; | |
1439 | bool ret; | |
1440 | ||
1441 | power_well = lookup_power_well(dev_priv, power_well_id); | |
1442 | ret = power_well->ops->is_enabled(dev_priv, power_well); | |
1443 | ||
1444 | return ret; | |
1445 | } | |
1446 | ||
94dd5138 S |
1447 | static struct i915_power_well skl_power_wells[] = { |
1448 | { | |
1449 | .name = "always-on", | |
1450 | .always_on = 1, | |
1451 | .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, | |
1452 | .ops = &i9xx_always_on_power_well_ops, | |
1453 | }, | |
1454 | { | |
1455 | .name = "power well 1", | |
1456 | .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS, | |
1457 | .ops = &skl_power_well_ops, | |
1458 | .data = SKL_DISP_PW_1, | |
1459 | }, | |
1460 | { | |
1461 | .name = "MISC IO power well", | |
1462 | .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS, | |
1463 | .ops = &skl_power_well_ops, | |
1464 | .data = SKL_DISP_PW_MISC_IO, | |
1465 | }, | |
1466 | { | |
1467 | .name = "power well 2", | |
1468 | .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1469 | .ops = &skl_power_well_ops, | |
1470 | .data = SKL_DISP_PW_2, | |
1471 | }, | |
1472 | { | |
1473 | .name = "DDI A/E power well", | |
1474 | .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, | |
1475 | .ops = &skl_power_well_ops, | |
1476 | .data = SKL_DISP_PW_DDI_A_E, | |
1477 | }, | |
1478 | { | |
1479 | .name = "DDI B power well", | |
1480 | .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, | |
1481 | .ops = &skl_power_well_ops, | |
1482 | .data = SKL_DISP_PW_DDI_B, | |
1483 | }, | |
1484 | { | |
1485 | .name = "DDI C power well", | |
1486 | .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, | |
1487 | .ops = &skl_power_well_ops, | |
1488 | .data = SKL_DISP_PW_DDI_C, | |
1489 | }, | |
1490 | { | |
1491 | .name = "DDI D power well", | |
1492 | .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, | |
1493 | .ops = &skl_power_well_ops, | |
1494 | .data = SKL_DISP_PW_DDI_D, | |
1495 | }, | |
1496 | }; | |
1497 | ||
0b4a2a36 S |
1498 | static struct i915_power_well bxt_power_wells[] = { |
1499 | { | |
1500 | .name = "always-on", | |
1501 | .always_on = 1, | |
1502 | .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, | |
1503 | .ops = &i9xx_always_on_power_well_ops, | |
1504 | }, | |
1505 | { | |
1506 | .name = "power well 1", | |
1507 | .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, | |
1508 | .ops = &skl_power_well_ops, | |
1509 | .data = SKL_DISP_PW_1, | |
1510 | }, | |
1511 | { | |
1512 | .name = "power well 2", | |
1513 | .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1514 | .ops = &skl_power_well_ops, | |
1515 | .data = SKL_DISP_PW_2, | |
1516 | } | |
1517 | }; | |
1518 | ||
9c065a7d DV |
1519 | #define set_power_wells(power_domains, __power_wells) ({ \ |
1520 | (power_domains)->power_wells = (__power_wells); \ | |
1521 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ | |
1522 | }) | |
1523 | ||
e4e7684f DV |
1524 | /** |
1525 | * intel_power_domains_init - initializes the power domain structures | |
1526 | * @dev_priv: i915 device instance | |
1527 | * | |
1528 | * Initializes the power domain structures for @dev_priv depending upon the | |
1529 | * supported platform. | |
1530 | */ | |
9c065a7d DV |
1531 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
1532 | { | |
1533 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1534 | ||
1535 | mutex_init(&power_domains->lock); | |
1536 | ||
1537 | /* | |
1538 | * The enabling order will be from lower to higher indexed wells, | |
1539 | * the disabling order is reversed. | |
1540 | */ | |
1541 | if (IS_HASWELL(dev_priv->dev)) { | |
1542 | set_power_wells(power_domains, hsw_power_wells); | |
9c065a7d DV |
1543 | } else if (IS_BROADWELL(dev_priv->dev)) { |
1544 | set_power_wells(power_domains, bdw_power_wells); | |
94dd5138 S |
1545 | } else if (IS_SKYLAKE(dev_priv->dev)) { |
1546 | set_power_wells(power_domains, skl_power_wells); | |
0b4a2a36 S |
1547 | } else if (IS_BROXTON(dev_priv->dev)) { |
1548 | set_power_wells(power_domains, bxt_power_wells); | |
9c065a7d DV |
1549 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1550 | set_power_wells(power_domains, chv_power_wells); | |
1551 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { | |
1552 | set_power_wells(power_domains, vlv_power_wells); | |
1553 | } else { | |
1554 | set_power_wells(power_domains, i9xx_always_on_power_well); | |
1555 | } | |
1556 | ||
1557 | return 0; | |
1558 | } | |
1559 | ||
41373cd5 DV |
1560 | static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) |
1561 | { | |
1562 | struct drm_device *dev = dev_priv->dev; | |
1563 | struct device *device = &dev->pdev->dev; | |
1564 | ||
1565 | if (!HAS_RUNTIME_PM(dev)) | |
1566 | return; | |
1567 | ||
1568 | if (!intel_enable_rc6(dev)) | |
1569 | return; | |
1570 | ||
1571 | /* Make sure we're not suspended first. */ | |
1572 | pm_runtime_get_sync(device); | |
1573 | pm_runtime_disable(device); | |
1574 | } | |
1575 | ||
e4e7684f DV |
1576 | /** |
1577 | * intel_power_domains_fini - finalizes the power domain structures | |
1578 | * @dev_priv: i915 device instance | |
1579 | * | |
1580 | * Finalizes the power domain structures for @dev_priv depending upon the | |
1581 | * supported platform. This function also disables runtime pm and ensures that | |
1582 | * the device stays powered up so that the driver can be reloaded. | |
1583 | */ | |
f458ebbc | 1584 | void intel_power_domains_fini(struct drm_i915_private *dev_priv) |
9c065a7d | 1585 | { |
41373cd5 DV |
1586 | intel_runtime_pm_disable(dev_priv); |
1587 | ||
f458ebbc DV |
1588 | /* The i915.ko module is still not prepared to be loaded when |
1589 | * the power well is not enabled, so just enable it in case | |
1590 | * we're going to unload/reload. */ | |
1591 | intel_display_set_init_power(dev_priv, true); | |
9c065a7d DV |
1592 | } |
1593 | ||
1594 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) | |
1595 | { | |
1596 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1597 | struct i915_power_well *power_well; | |
1598 | int i; | |
1599 | ||
1600 | mutex_lock(&power_domains->lock); | |
1601 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
1602 | power_well->ops->sync_hw(dev_priv, power_well); | |
1603 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, | |
1604 | power_well); | |
1605 | } | |
1606 | mutex_unlock(&power_domains->lock); | |
1607 | } | |
1608 | ||
70722468 VS |
1609 | static void chv_phy_control_init(struct drm_i915_private *dev_priv) |
1610 | { | |
1611 | struct i915_power_well *cmn_bc = | |
1612 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1613 | struct i915_power_well *cmn_d = | |
1614 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); | |
1615 | ||
1616 | /* | |
1617 | * DISPLAY_PHY_CONTROL can get corrupted if read. As a | |
1618 | * workaround never ever read DISPLAY_PHY_CONTROL, and | |
1619 | * instead maintain a shadow copy ourselves. Use the actual | |
1620 | * power well state to reconstruct the expected initial | |
1621 | * value. | |
1622 | */ | |
1623 | dev_priv->chv_phy_control = | |
bc284542 VS |
1624 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | |
1625 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | | |
70722468 VS |
1626 | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) | |
1627 | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) | | |
1628 | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0); | |
1629 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) | |
1630 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); | |
1631 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) | |
1632 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); | |
1633 | } | |
1634 | ||
9c065a7d DV |
1635 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
1636 | { | |
1637 | struct i915_power_well *cmn = | |
1638 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1639 | struct i915_power_well *disp2d = | |
1640 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); | |
1641 | ||
9c065a7d | 1642 | /* If the display might be already active skip this */ |
5d93a6e5 VS |
1643 | if (cmn->ops->is_enabled(dev_priv, cmn) && |
1644 | disp2d->ops->is_enabled(dev_priv, disp2d) && | |
9c065a7d DV |
1645 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
1646 | return; | |
1647 | ||
1648 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); | |
1649 | ||
1650 | /* cmnlane needs DPLL registers */ | |
1651 | disp2d->ops->enable(dev_priv, disp2d); | |
1652 | ||
1653 | /* | |
1654 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
1655 | * Need to assert and de-assert PHY SB reset by gating the | |
1656 | * common lane power, then un-gating it. | |
1657 | * Simply ungating isn't enough to reset the PHY enough to get | |
1658 | * ports and lanes running. | |
1659 | */ | |
1660 | cmn->ops->disable(dev_priv, cmn); | |
1661 | } | |
1662 | ||
e4e7684f DV |
1663 | /** |
1664 | * intel_power_domains_init_hw - initialize hardware power domain state | |
1665 | * @dev_priv: i915 device instance | |
1666 | * | |
1667 | * This function initializes the hardware power domain state and enables all | |
1668 | * power domains using intel_display_set_init_power(). | |
1669 | */ | |
9c065a7d DV |
1670 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
1671 | { | |
1672 | struct drm_device *dev = dev_priv->dev; | |
1673 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1674 | ||
1675 | power_domains->initializing = true; | |
1676 | ||
70722468 VS |
1677 | if (IS_CHERRYVIEW(dev)) { |
1678 | chv_phy_control_init(dev_priv); | |
1679 | } else if (IS_VALLEYVIEW(dev)) { | |
9c065a7d DV |
1680 | mutex_lock(&power_domains->lock); |
1681 | vlv_cmnlane_wa(dev_priv); | |
1682 | mutex_unlock(&power_domains->lock); | |
1683 | } | |
1684 | ||
1685 | /* For now, we need the power well to be always enabled. */ | |
1686 | intel_display_set_init_power(dev_priv, true); | |
1687 | intel_power_domains_resume(dev_priv); | |
1688 | power_domains->initializing = false; | |
1689 | } | |
1690 | ||
e4e7684f | 1691 | /** |
ca2b1403 | 1692 | * intel_aux_display_runtime_get - grab an auxiliary power domain reference |
e4e7684f DV |
1693 | * @dev_priv: i915 device instance |
1694 | * | |
1695 | * This function grabs a power domain reference for the auxiliary power domain | |
1696 | * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its | |
1697 | * parents are powered up. Therefore users should only grab a reference to the | |
1698 | * innermost power domain they need. | |
1699 | * | |
1700 | * Any power domain reference obtained by this function must have a symmetric | |
1701 | * call to intel_aux_display_runtime_put() to release the reference again. | |
1702 | */ | |
9c065a7d DV |
1703 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
1704 | { | |
1705 | intel_runtime_pm_get(dev_priv); | |
1706 | } | |
1707 | ||
e4e7684f | 1708 | /** |
ca2b1403 | 1709 | * intel_aux_display_runtime_put - release an auxiliary power domain reference |
e4e7684f DV |
1710 | * @dev_priv: i915 device instance |
1711 | * | |
ca2b1403 | 1712 | * This function drops the auxiliary power domain reference obtained by |
e4e7684f DV |
1713 | * intel_aux_display_runtime_get() and might power down the corresponding |
1714 | * hardware block right away if this is the last reference. | |
1715 | */ | |
9c065a7d DV |
1716 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) |
1717 | { | |
1718 | intel_runtime_pm_put(dev_priv); | |
1719 | } | |
1720 | ||
e4e7684f DV |
1721 | /** |
1722 | * intel_runtime_pm_get - grab a runtime pm reference | |
1723 | * @dev_priv: i915 device instance | |
1724 | * | |
1725 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
1726 | * code to ensure the GTT or GT is on) and ensures that it is powered up. | |
1727 | * | |
1728 | * Any runtime pm reference obtained by this function must have a symmetric | |
1729 | * call to intel_runtime_pm_put() to release the reference again. | |
1730 | */ | |
9c065a7d DV |
1731 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
1732 | { | |
1733 | struct drm_device *dev = dev_priv->dev; | |
1734 | struct device *device = &dev->pdev->dev; | |
1735 | ||
1736 | if (!HAS_RUNTIME_PM(dev)) | |
1737 | return; | |
1738 | ||
1739 | pm_runtime_get_sync(device); | |
1740 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); | |
1741 | } | |
1742 | ||
e4e7684f DV |
1743 | /** |
1744 | * intel_runtime_pm_get_noresume - grab a runtime pm reference | |
1745 | * @dev_priv: i915 device instance | |
1746 | * | |
1747 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
1748 | * code to ensure the GTT or GT is on). | |
1749 | * | |
1750 | * It will _not_ power up the device but instead only check that it's powered | |
1751 | * on. Therefore it is only valid to call this functions from contexts where | |
1752 | * the device is known to be powered up and where trying to power it up would | |
1753 | * result in hilarity and deadlocks. That pretty much means only the system | |
1754 | * suspend/resume code where this is used to grab runtime pm references for | |
1755 | * delayed setup down in work items. | |
1756 | * | |
1757 | * Any runtime pm reference obtained by this function must have a symmetric | |
1758 | * call to intel_runtime_pm_put() to release the reference again. | |
1759 | */ | |
9c065a7d DV |
1760 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
1761 | { | |
1762 | struct drm_device *dev = dev_priv->dev; | |
1763 | struct device *device = &dev->pdev->dev; | |
1764 | ||
1765 | if (!HAS_RUNTIME_PM(dev)) | |
1766 | return; | |
1767 | ||
1768 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); | |
1769 | pm_runtime_get_noresume(device); | |
1770 | } | |
1771 | ||
e4e7684f DV |
1772 | /** |
1773 | * intel_runtime_pm_put - release a runtime pm reference | |
1774 | * @dev_priv: i915 device instance | |
1775 | * | |
1776 | * This function drops the device-level runtime pm reference obtained by | |
1777 | * intel_runtime_pm_get() and might power down the corresponding | |
1778 | * hardware block right away if this is the last reference. | |
1779 | */ | |
9c065a7d DV |
1780 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
1781 | { | |
1782 | struct drm_device *dev = dev_priv->dev; | |
1783 | struct device *device = &dev->pdev->dev; | |
1784 | ||
1785 | if (!HAS_RUNTIME_PM(dev)) | |
1786 | return; | |
1787 | ||
1788 | pm_runtime_mark_last_busy(device); | |
1789 | pm_runtime_put_autosuspend(device); | |
1790 | } | |
1791 | ||
e4e7684f DV |
1792 | /** |
1793 | * intel_runtime_pm_enable - enable runtime pm | |
1794 | * @dev_priv: i915 device instance | |
1795 | * | |
1796 | * This function enables runtime pm at the end of the driver load sequence. | |
1797 | * | |
1798 | * Note that this function does currently not enable runtime pm for the | |
1799 | * subordinate display power domains. That is only done on the first modeset | |
1800 | * using intel_display_set_init_power(). | |
1801 | */ | |
f458ebbc | 1802 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) |
9c065a7d DV |
1803 | { |
1804 | struct drm_device *dev = dev_priv->dev; | |
1805 | struct device *device = &dev->pdev->dev; | |
1806 | ||
1807 | if (!HAS_RUNTIME_PM(dev)) | |
1808 | return; | |
1809 | ||
1810 | pm_runtime_set_active(device); | |
1811 | ||
1812 | /* | |
1813 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
1814 | * requirement. | |
1815 | */ | |
1816 | if (!intel_enable_rc6(dev)) { | |
1817 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
1818 | return; | |
1819 | } | |
1820 | ||
1821 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ | |
1822 | pm_runtime_mark_last_busy(device); | |
1823 | pm_runtime_use_autosuspend(device); | |
1824 | ||
1825 | pm_runtime_put_autosuspend(device); | |
1826 | } | |
1827 |