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drm/i915/skl: Program the DDB allocation
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
CommitLineData
9c065a7d
DV		 1/*
2 * Copyright © 2012-2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
26 *
27 */
28
29#include <linux/pm_runtime.h>
30#include <linux/vgaarb.h>
31
32#include "i915_drv.h"
33#include "intel_drv.h"
34#include <drm/i915_powerwell.h>
35
e4e7684f
DV		 36/**
37 * DOC: runtime pm
38 *
39 * The i915 driver supports dynamic enabling and disabling of entire hardware
40 * blocks at runtime. This is especially important on the display side where
41 * software is supposed to control many power gates manually on recent hardware,
42 * since on the GT side a lot of the power management is done by the hardware.
43 * But even there some manual control at the device level is required.
44 *
45 * Since i915 supports a diverse set of platforms with a unified codebase and
46 * hardware engineers just love to shuffle functionality around between power
47 * domains there's a sizeable amount of indirection required. This file provides
48 * generic functions to the driver for grabbing and releasing references for
49 * abstract power domains. It then maps those to the actual power wells
50 * present for a given platform.
51 */
52
9c065a7d
DV		 53static struct i915_power_domains *hsw_pwr;
54
55#define for_each_power_well(i, power_well, domain_mask, power_domains) \
56 for (i = 0; \
57 i < (power_domains)->power_well_count && \
58 ((power_well) = &(power_domains)->power_wells[i]); \
59 i++) \
60 if ((power_well)->domains & (domain_mask))
61
62#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
63 for (i = (power_domains)->power_well_count - 1; \
64 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
65 i--) \
66 if ((power_well)->domains & (domain_mask))
67
e4e7684f 68/*
9c065a7d
DV		 69 * We should only use the power well if we explicitly asked the hardware to
70 * enable it, so check if it's enabled and also check if we've requested it to
71 * be enabled.
72 */
73static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
74 struct i915_power_well *power_well)
75{
76 return I915_READ(HSW_PWR_WELL_DRIVER) ==
77 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
78}
79
e4e7684f
DV		 80/**
81 * __intel_display_power_is_enabled - unlocked check for a power domain
82 * @dev_priv: i915 device instance
83 * @domain: power domain to check
84 *
85 * This is the unlocked version of intel_display_power_is_enabled() and should
86 * only be used from error capture and recovery code where deadlocks are
87 * possible.
88 *
89 * Returns:
90 * True when the power domain is enabled, false otherwise.
91 */
f458ebbc
DV		 92bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
93 enum intel_display_power_domain domain)
9c065a7d
DV		 94{
95 struct i915_power_domains *power_domains;
96 struct i915_power_well *power_well;
97 bool is_enabled;
98 int i;
99
100 if (dev_priv->pm.suspended)
101 return false;
102
103 power_domains = &dev_priv->power_domains;
104
105 is_enabled = true;
106
107 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
108 if (power_well->always_on)
109 continue;
110
111 if (!power_well->hw_enabled) {
112 is_enabled = false;
113 break;
114 }
115 }
116
117 return is_enabled;
118}
119
e4e7684f
DV		 120/**
121 * intel_display_power_is_enabled - unlocked check for a power domain
122 * @dev_priv: i915 device instance
123 * @domain: power domain to check
124 *
125 * This function can be used to check the hw power domain state. It is mostly
126 * used in hardware state readout functions. Everywhere else code should rely
127 * upon explicit power domain reference counting to ensure that the hardware
128 * block is powered up before accessing it.
129 *
130 * Callers must hold the relevant modesetting locks to ensure that concurrent
131 * threads can't disable the power well while the caller tries to read a few
132 * registers.
133 *
134 * Returns:
135 * True when the power domain is enabled, false otherwise.
136 */
f458ebbc
DV		 137bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
138 enum intel_display_power_domain domain)
9c065a7d
DV		 139{
140 struct i915_power_domains *power_domains;
141 bool ret;
142
143 power_domains = &dev_priv->power_domains;
144
145 mutex_lock(&power_domains->lock);
f458ebbc 146 ret = __intel_display_power_is_enabled(dev_priv, domain);
9c065a7d
DV		 147 mutex_unlock(&power_domains->lock);
148
149 return ret;
150}
151
e4e7684f
DV		 152/**
153 * intel_display_set_init_power - set the initial power domain state
154 * @dev_priv: i915 device instance
155 * @enable: whether to enable or disable the initial power domain state
156 *
157 * For simplicity our driver load/unload and system suspend/resume code assumes
158 * that all power domains are always enabled. This functions controls the state
159 * of this little hack. While the initial power domain state is enabled runtime
160 * pm is effectively disabled.
161 */
d9bc89d9
DV		 162void intel_display_set_init_power(struct drm_i915_private *dev_priv,
163 bool enable)
164{
165 if (dev_priv->power_domains.init_power_on == enable)
166 return;
167
168 if (enable)
169 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
170 else
171 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
172
173 dev_priv->power_domains.init_power_on = enable;
174}
175
9c065a7d
DV		 176/*
177 * Starting with Haswell, we have a "Power Down Well" that can be turned off
178 * when not needed anymore. We have 4 registers that can request the power well
179 * to be enabled, and it will only be disabled if none of the registers is
180 * requesting it to be enabled.
181 */
182static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
183{
184 struct drm_device *dev = dev_priv->dev;
185
186 /*
187 * After we re-enable the power well, if we touch VGA register 0x3d5
188 * we'll get unclaimed register interrupts. This stops after we write
189 * anything to the VGA MSR register. The vgacon module uses this
190 * register all the time, so if we unbind our driver and, as a
191 * consequence, bind vgacon, we'll get stuck in an infinite loop at
192 * console_unlock(). So make here we touch the VGA MSR register, making
193 * sure vgacon can keep working normally without triggering interrupts
194 * and error messages.
195 */
196 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
197 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
198 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
199
200 if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9))
201 gen8_irq_power_well_post_enable(dev_priv);
202}
203
204static void hsw_set_power_well(struct drm_i915_private *dev_priv,
205 struct i915_power_well *power_well, bool enable)
206{
207 bool is_enabled, enable_requested;
208 uint32_t tmp;
209
210 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
211 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
212 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
213
214 if (enable) {
215 if (!enable_requested)
216 I915_WRITE(HSW_PWR_WELL_DRIVER,
217 HSW_PWR_WELL_ENABLE_REQUEST);
218
219 if (!is_enabled) {
220 DRM_DEBUG_KMS("Enabling power well\n");
221 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
222 HSW_PWR_WELL_STATE_ENABLED), 20))
223 DRM_ERROR("Timeout enabling power well\n");
6d729bff 224 hsw_power_well_post_enable(dev_priv);
9c065a7d
DV		 225 }
226
9c065a7d
DV		 227 } else {
228 if (enable_requested) {
229 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
230 POSTING_READ(HSW_PWR_WELL_DRIVER);
231 DRM_DEBUG_KMS("Requesting to disable the power well\n");
232 }
233 }
234}
235
236static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
237 struct i915_power_well *power_well)
238{
239 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
240
241 /*
242 * We're taking over the BIOS, so clear any requests made by it since
243 * the driver is in charge now.
244 */
245 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
246 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
247}
248
249static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
250 struct i915_power_well *power_well)
251{
252 hsw_set_power_well(dev_priv, power_well, true);
253}
254
255static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
256 struct i915_power_well *power_well)
257{
258 hsw_set_power_well(dev_priv, power_well, false);
259}
260
261static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
262 struct i915_power_well *power_well)
263{
264}
265
266static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
267 struct i915_power_well *power_well)
268{
269 return true;
270}
271
272static void vlv_set_power_well(struct drm_i915_private *dev_priv,
273 struct i915_power_well *power_well, bool enable)
274{
275 enum punit_power_well power_well_id = power_well->data;
276 u32 mask;
277 u32 state;
278 u32 ctrl;
279
280 mask = PUNIT_PWRGT_MASK(power_well_id);
281 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
282 PUNIT_PWRGT_PWR_GATE(power_well_id);
283
284 mutex_lock(&dev_priv->rps.hw_lock);
285
286#define COND \
287 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
288
289 if (COND)
290 goto out;
291
292 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
293 ctrl &= ~mask;
294 ctrl |= state;
295 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
296
297 if (wait_for(COND, 100))
298 DRM_ERROR("timout setting power well state %08x (%08x)\n",
299 state,
300 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
301
302#undef COND
303
304out:
305 mutex_unlock(&dev_priv->rps.hw_lock);
306}
307
308static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
309 struct i915_power_well *power_well)
310{
311 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
312}
313
314static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
315 struct i915_power_well *power_well)
316{
317 vlv_set_power_well(dev_priv, power_well, true);
318}
319
320static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
321 struct i915_power_well *power_well)
322{
323 vlv_set_power_well(dev_priv, power_well, false);
324}
325
326static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
327 struct i915_power_well *power_well)
328{
329 int power_well_id = power_well->data;
330 bool enabled = false;
331 u32 mask;
332 u32 state;
333 u32 ctrl;
334
335 mask = PUNIT_PWRGT_MASK(power_well_id);
336 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
337
338 mutex_lock(&dev_priv->rps.hw_lock);
339
340 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
341 /*
342 * We only ever set the power-on and power-gate states, anything
343 * else is unexpected.
344 */
345 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
346 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
347 if (state == ctrl)
348 enabled = true;
349
350 /*
351 * A transient state at this point would mean some unexpected party
352 * is poking at the power controls too.
353 */
354 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
355 WARN_ON(ctrl != state);
356
357 mutex_unlock(&dev_priv->rps.hw_lock);
358
359 return enabled;
360}
361
362static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
363 struct i915_power_well *power_well)
364{
365 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
366
367 vlv_set_power_well(dev_priv, power_well, true);
368
369 spin_lock_irq(&dev_priv->irq_lock);
370 valleyview_enable_display_irqs(dev_priv);
371 spin_unlock_irq(&dev_priv->irq_lock);
372
373 /*
374 * During driver initialization/resume we can avoid restoring the
375 * part of the HW/SW state that will be inited anyway explicitly.
376 */
377 if (dev_priv->power_domains.initializing)
378 return;
379
b963291c 380 intel_hpd_init(dev_priv);
9c065a7d
DV		 381
382 i915_redisable_vga_power_on(dev_priv->dev);
383}
384
385static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
386 struct i915_power_well *power_well)
387{
388 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
389
390 spin_lock_irq(&dev_priv->irq_lock);
391 valleyview_disable_display_irqs(dev_priv);
392 spin_unlock_irq(&dev_priv->irq_lock);
393
394 vlv_set_power_well(dev_priv, power_well, false);
395
396 vlv_power_sequencer_reset(dev_priv);
397}
398
399static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
400 struct i915_power_well *power_well)
401{
402 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
403
404 /*
405 * Enable the CRI clock source so we can get at the
406 * display and the reference clock for VGA
407 * hotplug / manual detection.
408 */
409 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
410 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
411 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
412
413 vlv_set_power_well(dev_priv, power_well, true);
414
415 /*
416 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
417 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
418 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
419 * b. The other bits such as sfr settings / modesel may all
420 * be set to 0.
421 *
422 * This should only be done on init and resume from S3 with
423 * both PLLs disabled, or we risk losing DPIO and PLL
424 * synchronization.
425 */
426 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
427}
428
429static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
430 struct i915_power_well *power_well)
431{
432 enum pipe pipe;
433
434 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
435
436 for_each_pipe(dev_priv, pipe)
437 assert_pll_disabled(dev_priv, pipe);
438
439 /* Assert common reset */
440 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
441
442 vlv_set_power_well(dev_priv, power_well, false);
443}
444
445static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
446 struct i915_power_well *power_well)
447{
448 enum dpio_phy phy;
449
450 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
451 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
452
453 /*
454 * Enable the CRI clock source so we can get at the
455 * display and the reference clock for VGA
456 * hotplug / manual detection.
457 */
458 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
459 phy = DPIO_PHY0;
460 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
461 DPLL_REFA_CLK_ENABLE_VLV);
462 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
463 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
464 } else {
465 phy = DPIO_PHY1;
466 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
467 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
468 }
469 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
470 vlv_set_power_well(dev_priv, power_well, true);
471
472 /* Poll for phypwrgood signal */
473 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
474 DRM_ERROR("Display PHY %d is not power up\n", phy);
475
476 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
477 PHY_COM_LANE_RESET_DEASSERT(phy));
478}
479
480static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
481 struct i915_power_well *power_well)
482{
483 enum dpio_phy phy;
484
485 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
486 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
487
488 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
489 phy = DPIO_PHY0;
490 assert_pll_disabled(dev_priv, PIPE_A);
491 assert_pll_disabled(dev_priv, PIPE_B);
492 } else {
493 phy = DPIO_PHY1;
494 assert_pll_disabled(dev_priv, PIPE_C);
495 }
496
497 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
498 ~PHY_COM_LANE_RESET_DEASSERT(phy));
499
500 vlv_set_power_well(dev_priv, power_well, false);
501}
502
503static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
504 struct i915_power_well *power_well)
505{
506 enum pipe pipe = power_well->data;
507 bool enabled;
508 u32 state, ctrl;
509
510 mutex_lock(&dev_priv->rps.hw_lock);
511
512 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
513 /*
514 * We only ever set the power-on and power-gate states, anything
515 * else is unexpected.
516 */
517 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
518 enabled = state == DP_SSS_PWR_ON(pipe);
519
520 /*
521 * A transient state at this point would mean some unexpected party
522 * is poking at the power controls too.
523 */
524 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
525 WARN_ON(ctrl << 16 != state);
526
527 mutex_unlock(&dev_priv->rps.hw_lock);
528
529 return enabled;
530}
531
532static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
533 struct i915_power_well *power_well,
534 bool enable)
535{
536 enum pipe pipe = power_well->data;
537 u32 state;
538 u32 ctrl;
539
540 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
541
542 mutex_lock(&dev_priv->rps.hw_lock);
543
544#define COND \
545 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
546
547 if (COND)
548 goto out;
549
550 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
551 ctrl &= ~DP_SSC_MASK(pipe);
552 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
553 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
554
555 if (wait_for(COND, 100))
556 DRM_ERROR("timout setting power well state %08x (%08x)\n",
557 state,
558 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
559
560#undef COND
561
562out:
563 mutex_unlock(&dev_priv->rps.hw_lock);
564}
565
566static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
567 struct i915_power_well *power_well)
568{
569 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
570}
571
572static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
573 struct i915_power_well *power_well)
574{
575 WARN_ON_ONCE(power_well->data != PIPE_A &&
576 power_well->data != PIPE_B &&
577 power_well->data != PIPE_C);
578
579 chv_set_pipe_power_well(dev_priv, power_well, true);
580}
581
582static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
583 struct i915_power_well *power_well)
584{
585 WARN_ON_ONCE(power_well->data != PIPE_A &&
586 power_well->data != PIPE_B &&
587 power_well->data != PIPE_C);
588
589 chv_set_pipe_power_well(dev_priv, power_well, false);
baa4e575
VS		 590
591 if (power_well->data == PIPE_A)
592 vlv_power_sequencer_reset(dev_priv);
9c065a7d
DV		 593}
594
595static void check_power_well_state(struct drm_i915_private *dev_priv,
596 struct i915_power_well *power_well)
597{
598 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
599
600 if (power_well->always_on || !i915.disable_power_well) {
601 if (!enabled)
602 goto mismatch;
603
604 return;
605 }
606
607 if (enabled != (power_well->count > 0))
608 goto mismatch;
609
610 return;
611
612mismatch:
613 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
614 power_well->name, power_well->always_on, enabled,
615 power_well->count, i915.disable_power_well);
616}
617
e4e7684f
DV		 618/**
619 * intel_display_power_get - grab a power domain reference
620 * @dev_priv: i915 device instance
621 * @domain: power domain to reference
622 *
623 * This function grabs a power domain reference for @domain and ensures that the
624 * power domain and all its parents are powered up. Therefore users should only
625 * grab a reference to the innermost power domain they need.
626 *
627 * Any power domain reference obtained by this function must have a symmetric
628 * call to intel_display_power_put() to release the reference again.
629 */
9c065a7d
DV		 630void intel_display_power_get(struct drm_i915_private *dev_priv,
631 enum intel_display_power_domain domain)
632{
633 struct i915_power_domains *power_domains;
634 struct i915_power_well *power_well;
635 int i;
636
637 intel_runtime_pm_get(dev_priv);
638
639 power_domains = &dev_priv->power_domains;
640
641 mutex_lock(&power_domains->lock);
642
643 for_each_power_well(i, power_well, BIT(domain), power_domains) {
644 if (!power_well->count++) {
645 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
646 power_well->ops->enable(dev_priv, power_well);
647 power_well->hw_enabled = true;
648 }
649
650 check_power_well_state(dev_priv, power_well);
651 }
652
653 power_domains->domain_use_count[domain]++;
654
655 mutex_unlock(&power_domains->lock);
656}
657
e4e7684f
DV		 658/**
659 * intel_display_power_put - release a power domain reference
660 * @dev_priv: i915 device instance
661 * @domain: power domain to reference
662 *
663 * This function drops the power domain reference obtained by
664 * intel_display_power_get() and might power down the corresponding hardware
665 * block right away if this is the last reference.
666 */
9c065a7d
DV		 667void intel_display_power_put(struct drm_i915_private *dev_priv,
668 enum intel_display_power_domain domain)
669{
670 struct i915_power_domains *power_domains;
671 struct i915_power_well *power_well;
672 int i;
673
674 power_domains = &dev_priv->power_domains;
675
676 mutex_lock(&power_domains->lock);
677
678 WARN_ON(!power_domains->domain_use_count[domain]);
679 power_domains->domain_use_count[domain]--;
680
681 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
682 WARN_ON(!power_well->count);
683
684 if (!--power_well->count && i915.disable_power_well) {
685 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
686 power_well->hw_enabled = false;
687 power_well->ops->disable(dev_priv, power_well);
688 }
689
690 check_power_well_state(dev_priv, power_well);
691 }
692
693 mutex_unlock(&power_domains->lock);
694
695 intel_runtime_pm_put(dev_priv);
696}
697
698#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
699
700#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
701 BIT(POWER_DOMAIN_PIPE_A) | \
702 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
703 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
704 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
705 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
706 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
707 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
708 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
709 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
710 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
711 BIT(POWER_DOMAIN_PORT_CRT) | \
712 BIT(POWER_DOMAIN_PLLS) | \
713 BIT(POWER_DOMAIN_INIT))
714#define HSW_DISPLAY_POWER_DOMAINS ( \
715 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
716 BIT(POWER_DOMAIN_INIT))
717
718#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
719 HSW_ALWAYS_ON_POWER_DOMAINS | \
720 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
721#define BDW_DISPLAY_POWER_DOMAINS ( \
722 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
723 BIT(POWER_DOMAIN_INIT))
724
725#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
726#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
727
728#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
729 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
730 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
731 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
732 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
733 BIT(POWER_DOMAIN_PORT_CRT) | \
734 BIT(POWER_DOMAIN_INIT))
735
736#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
737 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
738 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
739 BIT(POWER_DOMAIN_INIT))
740
741#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
742 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
743 BIT(POWER_DOMAIN_INIT))
744
745#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
746 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
747 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
748 BIT(POWER_DOMAIN_INIT))
749
750#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
751 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
752 BIT(POWER_DOMAIN_INIT))
753
754#define CHV_PIPE_A_POWER_DOMAINS ( \
755 BIT(POWER_DOMAIN_PIPE_A) | \
756 BIT(POWER_DOMAIN_INIT))
757
758#define CHV_PIPE_B_POWER_DOMAINS ( \
759 BIT(POWER_DOMAIN_PIPE_B) | \
760 BIT(POWER_DOMAIN_INIT))
761
762#define CHV_PIPE_C_POWER_DOMAINS ( \
763 BIT(POWER_DOMAIN_PIPE_C) | \
764 BIT(POWER_DOMAIN_INIT))
765
766#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
767 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
768 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
769 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
770 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
771 BIT(POWER_DOMAIN_INIT))
772
773#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
774 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
775 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
776 BIT(POWER_DOMAIN_INIT))
777
778#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
779 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
780 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
781 BIT(POWER_DOMAIN_INIT))
782
783#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
784 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
785 BIT(POWER_DOMAIN_INIT))
786
787static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
788 .sync_hw = i9xx_always_on_power_well_noop,
789 .enable = i9xx_always_on_power_well_noop,
790 .disable = i9xx_always_on_power_well_noop,
791 .is_enabled = i9xx_always_on_power_well_enabled,
792};
793
794static const struct i915_power_well_ops chv_pipe_power_well_ops = {
795 .sync_hw = chv_pipe_power_well_sync_hw,
796 .enable = chv_pipe_power_well_enable,
797 .disable = chv_pipe_power_well_disable,
798 .is_enabled = chv_pipe_power_well_enabled,
799};
800
801static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
802 .sync_hw = vlv_power_well_sync_hw,
803 .enable = chv_dpio_cmn_power_well_enable,
804 .disable = chv_dpio_cmn_power_well_disable,
805 .is_enabled = vlv_power_well_enabled,
806};
807
808static struct i915_power_well i9xx_always_on_power_well[] = {
809 {
810 .name = "always-on",
811 .always_on = 1,
812 .domains = POWER_DOMAIN_MASK,
813 .ops = &i9xx_always_on_power_well_ops,
814 },
815};
816
817static const struct i915_power_well_ops hsw_power_well_ops = {
818 .sync_hw = hsw_power_well_sync_hw,
819 .enable = hsw_power_well_enable,
820 .disable = hsw_power_well_disable,
821 .is_enabled = hsw_power_well_enabled,
822};
823
824static struct i915_power_well hsw_power_wells[] = {
825 {
826 .name = "always-on",
827 .always_on = 1,
828 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
829 .ops = &i9xx_always_on_power_well_ops,
830 },
831 {
832 .name = "display",
833 .domains = HSW_DISPLAY_POWER_DOMAINS,
834 .ops = &hsw_power_well_ops,
835 },
836};
837
838static struct i915_power_well bdw_power_wells[] = {
839 {
840 .name = "always-on",
841 .always_on = 1,
842 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
843 .ops = &i9xx_always_on_power_well_ops,
844 },
845 {
846 .name = "display",
847 .domains = BDW_DISPLAY_POWER_DOMAINS,
848 .ops = &hsw_power_well_ops,
849 },
850};
851
852static const struct i915_power_well_ops vlv_display_power_well_ops = {
853 .sync_hw = vlv_power_well_sync_hw,
854 .enable = vlv_display_power_well_enable,
855 .disable = vlv_display_power_well_disable,
856 .is_enabled = vlv_power_well_enabled,
857};
858
859static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
860 .sync_hw = vlv_power_well_sync_hw,
861 .enable = vlv_dpio_cmn_power_well_enable,
862 .disable = vlv_dpio_cmn_power_well_disable,
863 .is_enabled = vlv_power_well_enabled,
864};
865
866static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
867 .sync_hw = vlv_power_well_sync_hw,
868 .enable = vlv_power_well_enable,
869 .disable = vlv_power_well_disable,
870 .is_enabled = vlv_power_well_enabled,
871};
872
873static struct i915_power_well vlv_power_wells[] = {
874 {
875 .name = "always-on",
876 .always_on = 1,
877 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
878 .ops = &i9xx_always_on_power_well_ops,
879 },
880 {
881 .name = "display",
882 .domains = VLV_DISPLAY_POWER_DOMAINS,
883 .data = PUNIT_POWER_WELL_DISP2D,
884 .ops = &vlv_display_power_well_ops,
885 },
886 {
887 .name = "dpio-tx-b-01",
888 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
889 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
890 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
891 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
892 .ops = &vlv_dpio_power_well_ops,
893 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
894 },
895 {
896 .name = "dpio-tx-b-23",
897 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
898 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
899 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
900 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
901 .ops = &vlv_dpio_power_well_ops,
902 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
903 },
904 {
905 .name = "dpio-tx-c-01",
906 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
907 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
908 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
909 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
910 .ops = &vlv_dpio_power_well_ops,
911 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
912 },
913 {
914 .name = "dpio-tx-c-23",
915 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
916 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
917 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
918 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
919 .ops = &vlv_dpio_power_well_ops,
920 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
921 },
922 {
923 .name = "dpio-common",
924 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
925 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
926 .ops = &vlv_dpio_cmn_power_well_ops,
927 },
928};
929
930static struct i915_power_well chv_power_wells[] = {
931 {
932 .name = "always-on",
933 .always_on = 1,
934 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
935 .ops = &i9xx_always_on_power_well_ops,
936 },
937#if 0
938 {
939 .name = "display",
940 .domains = VLV_DISPLAY_POWER_DOMAINS,
941 .data = PUNIT_POWER_WELL_DISP2D,
942 .ops = &vlv_display_power_well_ops,
943 },
baa4e575 944#endif
9c065a7d
DV		 945 {
946 .name = "pipe-a",
baa4e575
VS		 947 /*
948 * FIXME: pipe A power well seems to be the new disp2d well.
949 * At least all registers seem to be housed there. Figure
950 * out if this a a temporary situation in pre-production
951 * hardware or a permanent state of affairs.
952 */
953 .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS,
9c065a7d
DV		 954 .data = PIPE_A,
955 .ops = &chv_pipe_power_well_ops,
956 },
baa4e575 957#if 0
9c065a7d
DV		 958 {
959 .name = "pipe-b",
960 .domains = CHV_PIPE_B_POWER_DOMAINS,
961 .data = PIPE_B,
962 .ops = &chv_pipe_power_well_ops,
963 },
964 {
965 .name = "pipe-c",
966 .domains = CHV_PIPE_C_POWER_DOMAINS,
967 .data = PIPE_C,
968 .ops = &chv_pipe_power_well_ops,
969 },
970#endif
971 {
972 .name = "dpio-common-bc",
973 /*
974 * XXX: cmnreset for one PHY seems to disturb the other.
975 * As a workaround keep both powered on at the same
976 * time for now.
977 */
978 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
979 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
980 .ops = &chv_dpio_cmn_power_well_ops,
981 },
982 {
983 .name = "dpio-common-d",
984 /*
985 * XXX: cmnreset for one PHY seems to disturb the other.
986 * As a workaround keep both powered on at the same
987 * time for now.
988 */
989 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
990 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
991 .ops = &chv_dpio_cmn_power_well_ops,
992 },
993#if 0
994 {
995 .name = "dpio-tx-b-01",
996 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
997 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
998 .ops = &vlv_dpio_power_well_ops,
999 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1000 },
1001 {
1002 .name = "dpio-tx-b-23",
1003 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1004 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
1005 .ops = &vlv_dpio_power_well_ops,
1006 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1007 },
1008 {
1009 .name = "dpio-tx-c-01",
1010 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1011 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1012 .ops = &vlv_dpio_power_well_ops,
1013 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1014 },
1015 {
1016 .name = "dpio-tx-c-23",
1017 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1018 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1019 .ops = &vlv_dpio_power_well_ops,
1020 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1021 },
1022 {
1023 .name = "dpio-tx-d-01",
1024 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1025 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1026 .ops = &vlv_dpio_power_well_ops,
1027 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
1028 },
1029 {
1030 .name = "dpio-tx-d-23",
1031 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
1032 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
1033 .ops = &vlv_dpio_power_well_ops,
1034 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
1035 },
1036#endif
1037};
1038
1039static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1040 enum punit_power_well power_well_id)
1041{
1042 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1043 struct i915_power_well *power_well;
1044 int i;
1045
1046 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1047 if (power_well->data == power_well_id)
1048 return power_well;
1049 }
1050
1051 return NULL;
1052}
1053
1054#define set_power_wells(power_domains, __power_wells) ({ \
1055 (power_domains)->power_wells = (__power_wells); \
1056 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1057})
1058
e4e7684f
DV		 1059/**
1060 * intel_power_domains_init - initializes the power domain structures
1061 * @dev_priv: i915 device instance
1062 *
1063 * Initializes the power domain structures for @dev_priv depending upon the
1064 * supported platform.
1065 */
9c065a7d
DV		 1066int intel_power_domains_init(struct drm_i915_private *dev_priv)
1067{
1068 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1069
1070 mutex_init(&power_domains->lock);
1071
1072 /*
1073 * The enabling order will be from lower to higher indexed wells,
1074 * the disabling order is reversed.
1075 */
1076 if (IS_HASWELL(dev_priv->dev)) {
1077 set_power_wells(power_domains, hsw_power_wells);
1078 hsw_pwr = power_domains;
1079 } else if (IS_BROADWELL(dev_priv->dev)) {
1080 set_power_wells(power_domains, bdw_power_wells);
1081 hsw_pwr = power_domains;
1082 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1083 set_power_wells(power_domains, chv_power_wells);
1084 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1085 set_power_wells(power_domains, vlv_power_wells);
1086 } else {
1087 set_power_wells(power_domains, i9xx_always_on_power_well);
1088 }
1089
1090 return 0;
1091}
1092
41373cd5
DV		 1093static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1094{
1095 struct drm_device *dev = dev_priv->dev;
1096 struct device *device = &dev->pdev->dev;
1097
1098 if (!HAS_RUNTIME_PM(dev))
1099 return;
1100
1101 if (!intel_enable_rc6(dev))
1102 return;
1103
1104 /* Make sure we're not suspended first. */
1105 pm_runtime_get_sync(device);
1106 pm_runtime_disable(device);
1107}
1108
e4e7684f
DV		 1109/**
1110 * intel_power_domains_fini - finalizes the power domain structures
1111 * @dev_priv: i915 device instance
1112 *
1113 * Finalizes the power domain structures for @dev_priv depending upon the
1114 * supported platform. This function also disables runtime pm and ensures that
1115 * the device stays powered up so that the driver can be reloaded.
1116 */
f458ebbc 1117void intel_power_domains_fini(struct drm_i915_private *dev_priv)
9c065a7d 1118{
41373cd5
DV		 1119 intel_runtime_pm_disable(dev_priv);
1120
f458ebbc
DV		 1121 /* The i915.ko module is still not prepared to be loaded when
1122 * the power well is not enabled, so just enable it in case
1123 * we're going to unload/reload. */
1124 intel_display_set_init_power(dev_priv, true);
1125
9c065a7d
DV		 1126 hsw_pwr = NULL;
1127}
1128
1129static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1130{
1131 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1132 struct i915_power_well *power_well;
1133 int i;
1134
1135 mutex_lock(&power_domains->lock);
1136 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1137 power_well->ops->sync_hw(dev_priv, power_well);
1138 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1139 power_well);
1140 }
1141 mutex_unlock(&power_domains->lock);
1142}
1143
1144static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1145{
1146 struct i915_power_well *cmn =
1147 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1148 struct i915_power_well *disp2d =
1149 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1150
9c065a7d 1151 /* If the display might be already active skip this */
5d93a6e5
VS		 1152 if (cmn->ops->is_enabled(dev_priv, cmn) &&
1153 disp2d->ops->is_enabled(dev_priv, disp2d) &&
9c065a7d
DV		 1154 I915_READ(DPIO_CTL) & DPIO_CMNRST)
1155 return;
1156
1157 DRM_DEBUG_KMS("toggling display PHY side reset\n");
1158
1159 /* cmnlane needs DPLL registers */
1160 disp2d->ops->enable(dev_priv, disp2d);
1161
1162 /*
1163 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1164 * Need to assert and de-assert PHY SB reset by gating the
1165 * common lane power, then un-gating it.
1166 * Simply ungating isn't enough to reset the PHY enough to get
1167 * ports and lanes running.
1168 */
1169 cmn->ops->disable(dev_priv, cmn);
1170}
1171
e4e7684f
DV		 1172/**
1173 * intel_power_domains_init_hw - initialize hardware power domain state
1174 * @dev_priv: i915 device instance
1175 *
1176 * This function initializes the hardware power domain state and enables all
1177 * power domains using intel_display_set_init_power().
1178 */
9c065a7d
DV		 1179void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
1180{
1181 struct drm_device *dev = dev_priv->dev;
1182 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1183
1184 power_domains->initializing = true;
1185
1186 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
1187 mutex_lock(&power_domains->lock);
1188 vlv_cmnlane_wa(dev_priv);
1189 mutex_unlock(&power_domains->lock);
1190 }
1191
1192 /* For now, we need the power well to be always enabled. */
1193 intel_display_set_init_power(dev_priv, true);
1194 intel_power_domains_resume(dev_priv);
1195 power_domains->initializing = false;
1196}
1197
e4e7684f
DV		 1198/**
1199 * intel_aux_display_runtime_get - grab an auxilliary power domain reference
1200 * @dev_priv: i915 device instance
1201 *
1202 * This function grabs a power domain reference for the auxiliary power domain
1203 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
1204 * parents are powered up. Therefore users should only grab a reference to the
1205 * innermost power domain they need.
1206 *
1207 * Any power domain reference obtained by this function must have a symmetric
1208 * call to intel_aux_display_runtime_put() to release the reference again.
1209 */
9c065a7d
DV		 1210void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
1211{
1212 intel_runtime_pm_get(dev_priv);
1213}
1214
e4e7684f
DV		 1215/**
1216 * intel_aux_display_runtime_put - release an auxilliary power domain reference
1217 * @dev_priv: i915 device instance
1218 *
1219 * This function drops the auxilliary power domain reference obtained by
1220 * intel_aux_display_runtime_get() and might power down the corresponding
1221 * hardware block right away if this is the last reference.
1222 */
9c065a7d
DV		 1223void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
1224{
1225 intel_runtime_pm_put(dev_priv);
1226}
1227
e4e7684f
DV		 1228/**
1229 * intel_runtime_pm_get - grab a runtime pm reference
1230 * @dev_priv: i915 device instance
1231 *
1232 * This function grabs a device-level runtime pm reference (mostly used for GEM
1233 * code to ensure the GTT or GT is on) and ensures that it is powered up.
1234 *
1235 * Any runtime pm reference obtained by this function must have a symmetric
1236 * call to intel_runtime_pm_put() to release the reference again.
1237 */
9c065a7d
DV		 1238void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
1239{
1240 struct drm_device *dev = dev_priv->dev;
1241 struct device *device = &dev->pdev->dev;
1242
1243 if (!HAS_RUNTIME_PM(dev))
1244 return;
1245
1246 pm_runtime_get_sync(device);
1247 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
1248}
1249
e4e7684f
DV		 1250/**
1251 * intel_runtime_pm_get_noresume - grab a runtime pm reference
1252 * @dev_priv: i915 device instance
1253 *
1254 * This function grabs a device-level runtime pm reference (mostly used for GEM
1255 * code to ensure the GTT or GT is on).
1256 *
1257 * It will _not_ power up the device but instead only check that it's powered
1258 * on. Therefore it is only valid to call this functions from contexts where
1259 * the device is known to be powered up and where trying to power it up would
1260 * result in hilarity and deadlocks. That pretty much means only the system
1261 * suspend/resume code where this is used to grab runtime pm references for
1262 * delayed setup down in work items.
1263 *
1264 * Any runtime pm reference obtained by this function must have a symmetric
1265 * call to intel_runtime_pm_put() to release the reference again.
1266 */
9c065a7d
DV		 1267void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
1268{
1269 struct drm_device *dev = dev_priv->dev;
1270 struct device *device = &dev->pdev->dev;
1271
1272 if (!HAS_RUNTIME_PM(dev))
1273 return;
1274
1275 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
1276 pm_runtime_get_noresume(device);
1277}
1278
e4e7684f
DV		 1279/**
1280 * intel_runtime_pm_put - release a runtime pm reference
1281 * @dev_priv: i915 device instance
1282 *
1283 * This function drops the device-level runtime pm reference obtained by
1284 * intel_runtime_pm_get() and might power down the corresponding
1285 * hardware block right away if this is the last reference.
1286 */
9c065a7d
DV		 1287void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
1288{
1289 struct drm_device *dev = dev_priv->dev;
1290 struct device *device = &dev->pdev->dev;
1291
1292 if (!HAS_RUNTIME_PM(dev))
1293 return;
1294
1295 pm_runtime_mark_last_busy(device);
1296 pm_runtime_put_autosuspend(device);
1297}
1298
e4e7684f
DV		 1299/**
1300 * intel_runtime_pm_enable - enable runtime pm
1301 * @dev_priv: i915 device instance
1302 *
1303 * This function enables runtime pm at the end of the driver load sequence.
1304 *
1305 * Note that this function does currently not enable runtime pm for the
1306 * subordinate display power domains. That is only done on the first modeset
1307 * using intel_display_set_init_power().
1308 */
f458ebbc 1309void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
9c065a7d
DV		 1310{
1311 struct drm_device *dev = dev_priv->dev;
1312 struct device *device = &dev->pdev->dev;
1313
1314 if (!HAS_RUNTIME_PM(dev))
1315 return;
1316
1317 pm_runtime_set_active(device);
1318
1319 /*
1320 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
1321 * requirement.
1322 */
1323 if (!intel_enable_rc6(dev)) {
1324 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
1325 return;
1326 }
1327
1328 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
1329 pm_runtime_mark_last_busy(device);
1330 pm_runtime_use_autosuspend(device);
1331
1332 pm_runtime_put_autosuspend(device);
1333}
1334
9c065a7d
DV		 1335/* Display audio driver power well request */
1336int i915_request_power_well(void)
1337{
1338 struct drm_i915_private *dev_priv;
1339
1340 if (!hsw_pwr)
1341 return -ENODEV;
1342
1343 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
1344 power_domains);
1345 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1346 return 0;
1347}
1348EXPORT_SYMBOL_GPL(i915_request_power_well);
1349
1350/* Display audio driver power well release */
1351int i915_release_power_well(void)
1352{
1353 struct drm_i915_private *dev_priv;
1354
1355 if (!hsw_pwr)
1356 return -ENODEV;
1357
1358 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
1359 power_domains);
1360 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1361 return 0;
1362}
1363EXPORT_SYMBOL_GPL(i915_release_power_well);
1364
1365/*
1366 * Private interface for the audio driver to get CDCLK in kHz.
1367 *
1368 * Caller must request power well using i915_request_power_well() prior to
1369 * making the call.
1370 */
1371int i915_get_cdclk_freq(void)
1372{
1373 struct drm_i915_private *dev_priv;
1374
1375 if (!hsw_pwr)
1376 return -ENODEV;
1377
1378 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
1379 power_domains);
1380
1381 return intel_ddi_get_cdclk_freq(dev_priv);
1382}
1383EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
Linux kernel - Deliverables
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