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drm/i915: Add CHV PHY LDO power sanity checks
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
CommitLineData
9c065a7d
DV		 1/*
2 * Copyright © 2012-2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
26 *
27 */
28
29#include <linux/pm_runtime.h>
30#include <linux/vgaarb.h>
31
32#include "i915_drv.h"
33#include "intel_drv.h"
9c065a7d 34
e4e7684f
DV		 35/**
36 * DOC: runtime pm
37 *
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
43 *
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
50 */
51
f75a1985
SS		 52#define GEN9_ENABLE_DC5(dev) 0
53#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
dc174300 54
9c065a7d
DV		 55#define for_each_power_well(i, power_well, domain_mask, power_domains) \
56 for (i = 0; \
57 i < (power_domains)->power_well_count && \
58 ((power_well) = &(power_domains)->power_wells[i]); \
59 i++) \
60 if ((power_well)->domains & (domain_mask))
61
62#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
63 for (i = (power_domains)->power_well_count - 1; \
64 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
65 i--) \
66 if ((power_well)->domains & (domain_mask))
67
5aefb239
SS		 68bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
69 int power_well_id);
70
e8ca9320
DL		 71static void intel_power_well_enable(struct drm_i915_private *dev_priv,
72 struct i915_power_well *power_well)
73{
74 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
75 power_well->ops->enable(dev_priv, power_well);
76 power_well->hw_enabled = true;
77}
78
dcddab3a
DL		 79static void intel_power_well_disable(struct drm_i915_private *dev_priv,
80 struct i915_power_well *power_well)
81{
82 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
83 power_well->hw_enabled = false;
84 power_well->ops->disable(dev_priv, power_well);
85}
86
e4e7684f 87/*
9c065a7d
DV		 88 * We should only use the power well if we explicitly asked the hardware to
89 * enable it, so check if it's enabled and also check if we've requested it to
90 * be enabled.
91 */
92static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
93 struct i915_power_well *power_well)
94{
95 return I915_READ(HSW_PWR_WELL_DRIVER) ==
96 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
97}
98
e4e7684f
DV		 99/**
100 * __intel_display_power_is_enabled - unlocked check for a power domain
101 * @dev_priv: i915 device instance
102 * @domain: power domain to check
103 *
104 * This is the unlocked version of intel_display_power_is_enabled() and should
105 * only be used from error capture and recovery code where deadlocks are
106 * possible.
107 *
108 * Returns:
109 * True when the power domain is enabled, false otherwise.
110 */
f458ebbc
DV		 111bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
112 enum intel_display_power_domain domain)
9c065a7d
DV		 113{
114 struct i915_power_domains *power_domains;
115 struct i915_power_well *power_well;
116 bool is_enabled;
117 int i;
118
119 if (dev_priv->pm.suspended)
120 return false;
121
122 power_domains = &dev_priv->power_domains;
123
124 is_enabled = true;
125
126 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
127 if (power_well->always_on)
128 continue;
129
130 if (!power_well->hw_enabled) {
131 is_enabled = false;
132 break;
133 }
134 }
135
136 return is_enabled;
137}
138
e4e7684f 139/**
f61ccae3 140 * intel_display_power_is_enabled - check for a power domain
e4e7684f
DV		 141 * @dev_priv: i915 device instance
142 * @domain: power domain to check
143 *
144 * This function can be used to check the hw power domain state. It is mostly
145 * used in hardware state readout functions. Everywhere else code should rely
146 * upon explicit power domain reference counting to ensure that the hardware
147 * block is powered up before accessing it.
148 *
149 * Callers must hold the relevant modesetting locks to ensure that concurrent
150 * threads can't disable the power well while the caller tries to read a few
151 * registers.
152 *
153 * Returns:
154 * True when the power domain is enabled, false otherwise.
155 */
f458ebbc
DV		 156bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
157 enum intel_display_power_domain domain)
9c065a7d
DV		 158{
159 struct i915_power_domains *power_domains;
160 bool ret;
161
162 power_domains = &dev_priv->power_domains;
163
164 mutex_lock(&power_domains->lock);
f458ebbc 165 ret = __intel_display_power_is_enabled(dev_priv, domain);
9c065a7d
DV		 166 mutex_unlock(&power_domains->lock);
167
168 return ret;
169}
170
e4e7684f
DV		 171/**
172 * intel_display_set_init_power - set the initial power domain state
173 * @dev_priv: i915 device instance
174 * @enable: whether to enable or disable the initial power domain state
175 *
176 * For simplicity our driver load/unload and system suspend/resume code assumes
177 * that all power domains are always enabled. This functions controls the state
178 * of this little hack. While the initial power domain state is enabled runtime
179 * pm is effectively disabled.
180 */
d9bc89d9
DV		 181void intel_display_set_init_power(struct drm_i915_private *dev_priv,
182 bool enable)
183{
184 if (dev_priv->power_domains.init_power_on == enable)
185 return;
186
187 if (enable)
188 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
189 else
190 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
191
192 dev_priv->power_domains.init_power_on = enable;
193}
194
9c065a7d
DV		 195/*
196 * Starting with Haswell, we have a "Power Down Well" that can be turned off
197 * when not needed anymore. We have 4 registers that can request the power well
198 * to be enabled, and it will only be disabled if none of the registers is
199 * requesting it to be enabled.
200 */
201static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
202{
203 struct drm_device *dev = dev_priv->dev;
204
205 /*
206 * After we re-enable the power well, if we touch VGA register 0x3d5
207 * we'll get unclaimed register interrupts. This stops after we write
208 * anything to the VGA MSR register. The vgacon module uses this
209 * register all the time, so if we unbind our driver and, as a
210 * consequence, bind vgacon, we'll get stuck in an infinite loop at
211 * console_unlock(). So make here we touch the VGA MSR register, making
212 * sure vgacon can keep working normally without triggering interrupts
213 * and error messages.
214 */
215 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
216 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
217 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
218
25400392 219 if (IS_BROADWELL(dev))
4c6c03be
DL		 220 gen8_irq_power_well_post_enable(dev_priv,
221 1 << PIPE_C | 1 << PIPE_B);
9c065a7d
DV		 222}
223
d14c0343
DL		 224static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
225 struct i915_power_well *power_well)
226{
227 struct drm_device *dev = dev_priv->dev;
228
229 /*
230 * After we re-enable the power well, if we touch VGA register 0x3d5
231 * we'll get unclaimed register interrupts. This stops after we write
232 * anything to the VGA MSR register. The vgacon module uses this
233 * register all the time, so if we unbind our driver and, as a
234 * consequence, bind vgacon, we'll get stuck in an infinite loop at
235 * console_unlock(). So make here we touch the VGA MSR register, making
236 * sure vgacon can keep working normally without triggering interrupts
237 * and error messages.
238 */
239 if (power_well->data == SKL_DISP_PW_2) {
240 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
241 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
242 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
243
244 gen8_irq_power_well_post_enable(dev_priv,
245 1 << PIPE_C | 1 << PIPE_B);
246 }
247
1d2b9526
DL		 248 if (power_well->data == SKL_DISP_PW_1) {
249 intel_prepare_ddi(dev);
d14c0343 250 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
1d2b9526 251 }
d14c0343
DL		 252}
253
9c065a7d
DV		 254static void hsw_set_power_well(struct drm_i915_private *dev_priv,
255 struct i915_power_well *power_well, bool enable)
256{
257 bool is_enabled, enable_requested;
258 uint32_t tmp;
259
260 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
261 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
262 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
263
264 if (enable) {
265 if (!enable_requested)
266 I915_WRITE(HSW_PWR_WELL_DRIVER,
267 HSW_PWR_WELL_ENABLE_REQUEST);
268
269 if (!is_enabled) {
270 DRM_DEBUG_KMS("Enabling power well\n");
271 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
272 HSW_PWR_WELL_STATE_ENABLED), 20))
273 DRM_ERROR("Timeout enabling power well\n");
6d729bff 274 hsw_power_well_post_enable(dev_priv);
9c065a7d
DV		 275 }
276
9c065a7d
DV		 277 } else {
278 if (enable_requested) {
279 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
280 POSTING_READ(HSW_PWR_WELL_DRIVER);
281 DRM_DEBUG_KMS("Requesting to disable the power well\n");
282 }
283 }
284}
285
94dd5138
S		 286#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
287 BIT(POWER_DOMAIN_TRANSCODER_A) | \
288 BIT(POWER_DOMAIN_PIPE_B) | \
289 BIT(POWER_DOMAIN_TRANSCODER_B) | \
290 BIT(POWER_DOMAIN_PIPE_C) | \
291 BIT(POWER_DOMAIN_TRANSCODER_C) | \
292 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
293 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
294 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
295 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
296 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
297 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
298 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
299 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
300 BIT(POWER_DOMAIN_AUX_B) | \
301 BIT(POWER_DOMAIN_AUX_C) | \
302 BIT(POWER_DOMAIN_AUX_D) | \
303 BIT(POWER_DOMAIN_AUDIO) | \
304 BIT(POWER_DOMAIN_VGA) | \
305 BIT(POWER_DOMAIN_INIT))
306#define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
307 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
308 BIT(POWER_DOMAIN_PLLS) | \
309 BIT(POWER_DOMAIN_PIPE_A) | \
310 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
311 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
312 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
313 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
314 BIT(POWER_DOMAIN_AUX_A) | \
315 BIT(POWER_DOMAIN_INIT))
316#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
317 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
318 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
319 BIT(POWER_DOMAIN_INIT))
320#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
321 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
322 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
323 BIT(POWER_DOMAIN_INIT))
324#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
325 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
326 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
327 BIT(POWER_DOMAIN_INIT))
328#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
329 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
330 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
331 BIT(POWER_DOMAIN_INIT))
332#define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \
aeaa2122 333 SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
6222709d 334 BIT(POWER_DOMAIN_PLLS) | \
aeaa2122 335 BIT(POWER_DOMAIN_INIT))
94dd5138
S		 336#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
337 (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
338 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
339 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \
340 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \
341 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \
342 SKL_DISPLAY_DDI_D_POWER_DOMAINS | \
343 SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \
344 BIT(POWER_DOMAIN_INIT))
345
0b4a2a36
S		 346#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
347 BIT(POWER_DOMAIN_TRANSCODER_A) | \
348 BIT(POWER_DOMAIN_PIPE_B) | \
349 BIT(POWER_DOMAIN_TRANSCODER_B) | \
350 BIT(POWER_DOMAIN_PIPE_C) | \
351 BIT(POWER_DOMAIN_TRANSCODER_C) | \
352 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
353 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
354 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
355 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
356 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
357 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
358 BIT(POWER_DOMAIN_AUX_B) | \
359 BIT(POWER_DOMAIN_AUX_C) | \
360 BIT(POWER_DOMAIN_AUDIO) | \
361 BIT(POWER_DOMAIN_VGA) | \
362 BIT(POWER_DOMAIN_INIT))
363#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
364 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
365 BIT(POWER_DOMAIN_PIPE_A) | \
366 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
367 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
368 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
369 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
370 BIT(POWER_DOMAIN_AUX_A) | \
371 BIT(POWER_DOMAIN_PLLS) | \
372 BIT(POWER_DOMAIN_INIT))
373#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
374 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
375 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
376 BIT(POWER_DOMAIN_INIT))
377
664326f8
SK		 378static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
379{
380 struct drm_device *dev = dev_priv->dev;
381
382 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
383 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
384 "DC9 already programmed to be enabled.\n");
385 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
386 "DC5 still not disabled to enable DC9.\n");
387 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
388 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
389
390 /*
391 * TODO: check for the following to verify the conditions to enter DC9
392 * state are satisfied:
393 * 1] Check relevant display engine registers to verify if mode set
394 * disable sequence was followed.
395 * 2] Check if display uninitialize sequence is initialized.
396 */
397}
398
399static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
400{
401 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
402 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
403 "DC9 already programmed to be disabled.\n");
404 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
405 "DC5 still not disabled.\n");
406
407 /*
408 * TODO: check for the following to verify DC9 state was indeed
409 * entered before programming to disable it:
410 * 1] Check relevant display engine registers to verify if mode
411 * set disable sequence was followed.
412 * 2] Check if display uninitialize sequence is initialized.
413 */
414}
415
416void bxt_enable_dc9(struct drm_i915_private *dev_priv)
417{
418 uint32_t val;
419
420 assert_can_enable_dc9(dev_priv);
421
422 DRM_DEBUG_KMS("Enabling DC9\n");
423
424 val = I915_READ(DC_STATE_EN);
425 val |= DC_STATE_EN_DC9;
426 I915_WRITE(DC_STATE_EN, val);
427 POSTING_READ(DC_STATE_EN);
428}
429
430void bxt_disable_dc9(struct drm_i915_private *dev_priv)
431{
432 uint32_t val;
433
434 assert_can_disable_dc9(dev_priv);
435
436 DRM_DEBUG_KMS("Disabling DC9\n");
437
438 val = I915_READ(DC_STATE_EN);
439 val &= ~DC_STATE_EN_DC9;
440 I915_WRITE(DC_STATE_EN, val);
441 POSTING_READ(DC_STATE_EN);
442}
443
6b457d31
SK		 444static void gen9_set_dc_state_debugmask_memory_up(
445 struct drm_i915_private *dev_priv)
446{
447 uint32_t val;
448
449 /* The below bit doesn't need to be cleared ever afterwards */
450 val = I915_READ(DC_STATE_DEBUG);
451 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
452 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
453 I915_WRITE(DC_STATE_DEBUG, val);
454 POSTING_READ(DC_STATE_DEBUG);
455 }
456}
457
5aefb239 458static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
dc174300 459{
6b457d31 460 struct drm_device *dev = dev_priv->dev;
5aefb239
SS		 461 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
462 SKL_DISP_PW_2);
463
464 WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
465 WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
466 WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n");
467
468 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
469 "DC5 already programmed to be enabled.\n");
470 WARN(dev_priv->pm.suspended,
471 "DC5 cannot be enabled, if platform is runtime-suspended.\n");
472
473 assert_csr_loaded(dev_priv);
474}
475
476static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
477{
478 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
479 SKL_DISP_PW_2);
93c7cb6c
SS		 480 /*
481 * During initialization, the firmware may not be loaded yet.
482 * We still want to make sure that the DC enabling flag is cleared.
483 */
484 if (dev_priv->power_domains.initializing)
485 return;
5aefb239
SS		 486
487 WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
488 WARN(dev_priv->pm.suspended,
489 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
490}
491
492static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
493{
6b457d31
SK		 494 uint32_t val;
495
5aefb239 496 assert_can_enable_dc5(dev_priv);
6b457d31
SK		 497
498 DRM_DEBUG_KMS("Enabling DC5\n");
499
500 gen9_set_dc_state_debugmask_memory_up(dev_priv);
501
502 val = I915_READ(DC_STATE_EN);
503 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
504 val |= DC_STATE_EN_UPTO_DC5;
505 I915_WRITE(DC_STATE_EN, val);
506 POSTING_READ(DC_STATE_EN);
dc174300
SS		 507}
508
509static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
510{
6b457d31
SK		 511 uint32_t val;
512
5aefb239 513 assert_can_disable_dc5(dev_priv);
6b457d31
SK		 514
515 DRM_DEBUG_KMS("Disabling DC5\n");
516
517 val = I915_READ(DC_STATE_EN);
518 val &= ~DC_STATE_EN_UPTO_DC5;
519 I915_WRITE(DC_STATE_EN, val);
520 POSTING_READ(DC_STATE_EN);
dc174300
SS		 521}
522
93c7cb6c 523static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
f75a1985 524{
74b4f371 525 struct drm_device *dev = dev_priv->dev;
93c7cb6c
SS		 526
527 WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
528 WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
529 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
530 "Backlight is not disabled.\n");
531 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
532 "DC6 already programmed to be enabled.\n");
533
534 assert_csr_loaded(dev_priv);
535}
536
537static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
538{
539 /*
540 * During initialization, the firmware may not be loaded yet.
541 * We still want to make sure that the DC enabling flag is cleared.
542 */
543 if (dev_priv->power_domains.initializing)
544 return;
545
546 assert_csr_loaded(dev_priv);
547 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
548 "DC6 already programmed to be disabled.\n");
549}
550
551static void skl_enable_dc6(struct drm_i915_private *dev_priv)
552{
74b4f371
SK		 553 uint32_t val;
554
93c7cb6c 555 assert_can_enable_dc6(dev_priv);
74b4f371
SK		 556
557 DRM_DEBUG_KMS("Enabling DC6\n");
558
559 gen9_set_dc_state_debugmask_memory_up(dev_priv);
560
561 val = I915_READ(DC_STATE_EN);
562 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
563 val |= DC_STATE_EN_UPTO_DC6;
564 I915_WRITE(DC_STATE_EN, val);
565 POSTING_READ(DC_STATE_EN);
f75a1985
SS		 566}
567
568static void skl_disable_dc6(struct drm_i915_private *dev_priv)
569{
74b4f371
SK		 570 uint32_t val;
571
93c7cb6c 572 assert_can_disable_dc6(dev_priv);
74b4f371
SK		 573
574 DRM_DEBUG_KMS("Disabling DC6\n");
575
576 val = I915_READ(DC_STATE_EN);
577 val &= ~DC_STATE_EN_UPTO_DC6;
578 I915_WRITE(DC_STATE_EN, val);
579 POSTING_READ(DC_STATE_EN);
f75a1985
SS		 580}
581
94dd5138
S		 582static void skl_set_power_well(struct drm_i915_private *dev_priv,
583 struct i915_power_well *power_well, bool enable)
584{
dc174300 585 struct drm_device *dev = dev_priv->dev;
94dd5138
S		 586 uint32_t tmp, fuse_status;
587 uint32_t req_mask, state_mask;
2a51835f 588 bool is_enabled, enable_requested, check_fuse_status = false;
94dd5138
S		 589
590 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
591 fuse_status = I915_READ(SKL_FUSE_STATUS);
592
593 switch (power_well->data) {
594 case SKL_DISP_PW_1:
595 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
596 SKL_FUSE_PG0_DIST_STATUS), 1)) {
597 DRM_ERROR("PG0 not enabled\n");
598 return;
599 }
600 break;
601 case SKL_DISP_PW_2:
602 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
603 DRM_ERROR("PG1 in disabled state\n");
604 return;
605 }
606 break;
607 case SKL_DISP_PW_DDI_A_E:
608 case SKL_DISP_PW_DDI_B:
609 case SKL_DISP_PW_DDI_C:
610 case SKL_DISP_PW_DDI_D:
611 case SKL_DISP_PW_MISC_IO:
612 break;
613 default:
614 WARN(1, "Unknown power well %lu\n", power_well->data);
615 return;
616 }
617
618 req_mask = SKL_POWER_WELL_REQ(power_well->data);
2a51835f 619 enable_requested = tmp & req_mask;
94dd5138 620 state_mask = SKL_POWER_WELL_STATE(power_well->data);
2a51835f 621 is_enabled = tmp & state_mask;
94dd5138
S		 622
623 if (enable) {
2a51835f 624 if (!enable_requested) {
dc174300
SS		 625 WARN((tmp & state_mask) &&
626 !I915_READ(HSW_PWR_WELL_BIOS),
627 "Invalid for power well status to be enabled, unless done by the BIOS, \
628 when request is to disable!\n");
f75a1985
SS		 629 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
630 power_well->data == SKL_DISP_PW_2) {
631 if (SKL_ENABLE_DC6(dev)) {
632 skl_disable_dc6(dev_priv);
633 /*
634 * DDI buffer programming unnecessary during driver-load/resume
635 * as it's already done during modeset initialization then.
636 * It's also invalid here as encoder list is still uninitialized.
637 */
638 if (!dev_priv->power_domains.initializing)
639 intel_prepare_ddi(dev);
640 } else {
641 gen9_disable_dc5(dev_priv);
642 }
643 }
94dd5138 644 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
94dd5138
S		 645 }
646
2a51835f 647 if (!is_enabled) {
510e6fdd 648 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
94dd5138
S		 649 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
650 state_mask), 1))
651 DRM_ERROR("%s enable timeout\n",
652 power_well->name);
653 check_fuse_status = true;
654 }
655 } else {
2a51835f 656 if (enable_requested) {
94dd5138
S		 657 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
658 POSTING_READ(HSW_PWR_WELL_DRIVER);
659 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
dc174300 660
f75a1985 661 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
dc174300
SS		 662 power_well->data == SKL_DISP_PW_2) {
663 enum csr_state state;
f75a1985
SS		 664 /* TODO: wait for a completion event or
665 * similar here instead of busy
666 * waiting using wait_for function.
667 */
dc174300
SS		 668 wait_for((state = intel_csr_load_status_get(dev_priv)) !=
669 FW_UNINITIALIZED, 1000);
670 if (state != FW_LOADED)
671 DRM_ERROR("CSR firmware not ready (%d)\n",
672 state);
673 else
f75a1985
SS		 674 if (SKL_ENABLE_DC6(dev))
675 skl_enable_dc6(dev_priv);
676 else
677 gen9_enable_dc5(dev_priv);
dc174300 678 }
94dd5138
S		 679 }
680 }
681
682 if (check_fuse_status) {
683 if (power_well->data == SKL_DISP_PW_1) {
684 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
685 SKL_FUSE_PG1_DIST_STATUS), 1))
686 DRM_ERROR("PG1 distributing status timeout\n");
687 } else if (power_well->data == SKL_DISP_PW_2) {
688 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
689 SKL_FUSE_PG2_DIST_STATUS), 1))
690 DRM_ERROR("PG2 distributing status timeout\n");
691 }
692 }
d14c0343
DL		 693
694 if (enable && !is_enabled)
695 skl_power_well_post_enable(dev_priv, power_well);
94dd5138
S		 696}
697
9c065a7d
DV		 698static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
699 struct i915_power_well *power_well)
700{
701 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
702
703 /*
704 * We're taking over the BIOS, so clear any requests made by it since
705 * the driver is in charge now.
706 */
707 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
708 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
709}
710
711static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
712 struct i915_power_well *power_well)
713{
714 hsw_set_power_well(dev_priv, power_well, true);
715}
716
717static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
718 struct i915_power_well *power_well)
719{
720 hsw_set_power_well(dev_priv, power_well, false);
721}
722
94dd5138
S		 723static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
724 struct i915_power_well *power_well)
725{
726 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
727 SKL_POWER_WELL_STATE(power_well->data);
728
729 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
730}
731
732static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
733 struct i915_power_well *power_well)
734{
735 skl_set_power_well(dev_priv, power_well, power_well->count > 0);
736
737 /* Clear any request made by BIOS as driver is taking over */
738 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
739}
740
741static void skl_power_well_enable(struct drm_i915_private *dev_priv,
742 struct i915_power_well *power_well)
743{
744 skl_set_power_well(dev_priv, power_well, true);
745}
746
747static void skl_power_well_disable(struct drm_i915_private *dev_priv,
748 struct i915_power_well *power_well)
749{
750 skl_set_power_well(dev_priv, power_well, false);
751}
752
9c065a7d
DV		 753static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
754 struct i915_power_well *power_well)
755{
756}
757
758static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
759 struct i915_power_well *power_well)
760{
761 return true;
762}
763
764static void vlv_set_power_well(struct drm_i915_private *dev_priv,
765 struct i915_power_well *power_well, bool enable)
766{
767 enum punit_power_well power_well_id = power_well->data;
768 u32 mask;
769 u32 state;
770 u32 ctrl;
771
772 mask = PUNIT_PWRGT_MASK(power_well_id);
773 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
774 PUNIT_PWRGT_PWR_GATE(power_well_id);
775
776 mutex_lock(&dev_priv->rps.hw_lock);
777
778#define COND \
779 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
780
781 if (COND)
782 goto out;
783
784 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
785 ctrl &= ~mask;
786 ctrl |= state;
787 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
788
789 if (wait_for(COND, 100))
7e35ab88 790 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
DV		 791 state,
792 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
793
794#undef COND
795
796out:
797 mutex_unlock(&dev_priv->rps.hw_lock);
798}
799
800static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
801 struct i915_power_well *power_well)
802{
803 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
804}
805
806static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
807 struct i915_power_well *power_well)
808{
809 vlv_set_power_well(dev_priv, power_well, true);
810}
811
812static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
813 struct i915_power_well *power_well)
814{
815 vlv_set_power_well(dev_priv, power_well, false);
816}
817
818static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
819 struct i915_power_well *power_well)
820{
821 int power_well_id = power_well->data;
822 bool enabled = false;
823 u32 mask;
824 u32 state;
825 u32 ctrl;
826
827 mask = PUNIT_PWRGT_MASK(power_well_id);
828 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
829
830 mutex_lock(&dev_priv->rps.hw_lock);
831
832 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
833 /*
834 * We only ever set the power-on and power-gate states, anything
835 * else is unexpected.
836 */
837 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
838 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
839 if (state == ctrl)
840 enabled = true;
841
842 /*
843 * A transient state at this point would mean some unexpected party
844 * is poking at the power controls too.
845 */
846 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
847 WARN_ON(ctrl != state);
848
849 mutex_unlock(&dev_priv->rps.hw_lock);
850
851 return enabled;
852}
853
2be7d540 854static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
9c065a7d 855{
5a8fbb7d
VS		 856 enum pipe pipe;
857
858 /*
859 * Enable the CRI clock source so we can get at the
860 * display and the reference clock for VGA
861 * hotplug / manual detection. Supposedly DSI also
862 * needs the ref clock up and running.
863 *
864 * CHV DPLL B/C have some issues if VGA mode is enabled.
865 */
866 for_each_pipe(dev_priv->dev, pipe) {
867 u32 val = I915_READ(DPLL(pipe));
868
869 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
870 if (pipe != PIPE_A)
871 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
872
873 I915_WRITE(DPLL(pipe), val);
874 }
9c065a7d
DV		 875
876 spin_lock_irq(&dev_priv->irq_lock);
877 valleyview_enable_display_irqs(dev_priv);
878 spin_unlock_irq(&dev_priv->irq_lock);
879
880 /*
881 * During driver initialization/resume we can avoid restoring the
882 * part of the HW/SW state that will be inited anyway explicitly.
883 */
884 if (dev_priv->power_domains.initializing)
885 return;
886
b963291c 887 intel_hpd_init(dev_priv);
9c065a7d
DV		 888
889 i915_redisable_vga_power_on(dev_priv->dev);
890}
891
2be7d540
VS		 892static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
893{
894 spin_lock_irq(&dev_priv->irq_lock);
895 valleyview_disable_display_irqs(dev_priv);
896 spin_unlock_irq(&dev_priv->irq_lock);
897
898 vlv_power_sequencer_reset(dev_priv);
899}
900
901static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
902 struct i915_power_well *power_well)
903{
904 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
905
906 vlv_set_power_well(dev_priv, power_well, true);
907
908 vlv_display_power_well_init(dev_priv);
909}
910
9c065a7d
DV		 911static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
912 struct i915_power_well *power_well)
913{
914 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
915
2be7d540 916 vlv_display_power_well_deinit(dev_priv);
9c065a7d
DV		 917
918 vlv_set_power_well(dev_priv, power_well, false);
9c065a7d
DV		 919}
920
921static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
922 struct i915_power_well *power_well)
923{
924 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
925
5a8fbb7d 926 /* since ref/cri clock was enabled */
9c065a7d
DV		 927 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
928
929 vlv_set_power_well(dev_priv, power_well, true);
930
931 /*
932 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
933 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
934 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
935 * b. The other bits such as sfr settings / modesel may all
936 * be set to 0.
937 *
938 * This should only be done on init and resume from S3 with
939 * both PLLs disabled, or we risk losing DPIO and PLL
940 * synchronization.
941 */
942 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
943}
944
945static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
946 struct i915_power_well *power_well)
947{
948 enum pipe pipe;
949
950 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
951
952 for_each_pipe(dev_priv, pipe)
953 assert_pll_disabled(dev_priv, pipe);
954
955 /* Assert common reset */
956 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
957
958 vlv_set_power_well(dev_priv, power_well, false);
959}
960
30142273
VS		 961#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
962
963static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
964 int power_well_id)
965{
966 struct i915_power_domains *power_domains = &dev_priv->power_domains;
967 struct i915_power_well *power_well;
968 int i;
969
970 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
971 if (power_well->data == power_well_id)
972 return power_well;
973 }
974
975 return NULL;
976}
977
978#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
979
980static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
981{
982 struct i915_power_well *cmn_bc =
983 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
984 struct i915_power_well *cmn_d =
985 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
986 u32 phy_control = dev_priv->chv_phy_control;
987 u32 phy_status = 0;
988 u32 tmp;
989
990 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
991 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
992
993 /* this assumes override is only used to enable lanes */
994 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
995 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
996
997 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
998 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
999
1000 /* CL1 is on whenever anything is on in either channel */
1001 if (BITS_SET(phy_control,
1002 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1003 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1004 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1005
1006 /*
1007 * The DPLLB check accounts for the pipe B + port A usage
1008 * with CL2 powered up but all the lanes in the second channel
1009 * powered down.
1010 */
1011 if (BITS_SET(phy_control,
1012 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1013 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1014 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1015
1016 if (BITS_SET(phy_control,
1017 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1018 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1019 if (BITS_SET(phy_control,
1020 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1021 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1022
1023 if (BITS_SET(phy_control,
1024 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1025 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1026 if (BITS_SET(phy_control,
1027 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1028 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1029 }
1030
1031 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1032 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1033
1034 /* this assumes override is only used to enable lanes */
1035 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1036 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1037
1038 if (BITS_SET(phy_control,
1039 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1040 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1041
1042 if (BITS_SET(phy_control,
1043 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1044 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1045 if (BITS_SET(phy_control,
1046 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1047 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1048 }
1049
1050 /*
1051 * The PHY may be busy with some initial calibration and whatnot,
1052 * so the power state can take a while to actually change.
1053 */
1054 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS)) == phy_status, 10))
1055 WARN(phy_status != tmp,
1056 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1057 tmp, phy_status, dev_priv->chv_phy_control);
1058}
1059
1060#undef BITS_SET
1061
9c065a7d
DV		 1062static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1063 struct i915_power_well *power_well)
1064{
1065 enum dpio_phy phy;
e0fce78f
VS		 1066 enum pipe pipe;
1067 uint32_t tmp;
9c065a7d
DV		 1068
1069 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1070 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1071
e0fce78f
VS		 1072 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1073 pipe = PIPE_A;
9c065a7d 1074 phy = DPIO_PHY0;
e0fce78f
VS		 1075 } else {
1076 pipe = PIPE_C;
9c065a7d 1077 phy = DPIO_PHY1;
e0fce78f 1078 }
5a8fbb7d
VS		 1079
1080 /* since ref/cri clock was enabled */
9c065a7d
DV		 1081 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1082 vlv_set_power_well(dev_priv, power_well, true);
1083
1084 /* Poll for phypwrgood signal */
1085 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1086 DRM_ERROR("Display PHY %d is not power up\n", phy);
1087
e0fce78f
VS		 1088 mutex_lock(&dev_priv->sb_lock);
1089
1090 /* Enable dynamic power down */
1091 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
ee279218
VS		 1092 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1093 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
e0fce78f
VS		 1094 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1095
1096 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1097 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1098 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1099 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
3e288786
VS		 1100 } else {
1101 /*
1102 * Force the non-existing CL2 off. BXT does this
1103 * too, so maybe it saves some power even though
1104 * CL2 doesn't exist?
1105 */
1106 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1107 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1108 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
e0fce78f
VS		 1109 }
1110
1111 mutex_unlock(&dev_priv->sb_lock);
1112
70722468
VS		 1113 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1114 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
e0fce78f
VS		 1115
1116 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1117 phy, dev_priv->chv_phy_control);
30142273
VS		 1118
1119 assert_chv_phy_status(dev_priv);
9c065a7d
DV		 1120}
1121
1122static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1123 struct i915_power_well *power_well)
1124{
1125 enum dpio_phy phy;
1126
1127 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1128 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1129
1130 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1131 phy = DPIO_PHY0;
1132 assert_pll_disabled(dev_priv, PIPE_A);
1133 assert_pll_disabled(dev_priv, PIPE_B);
1134 } else {
1135 phy = DPIO_PHY1;
1136 assert_pll_disabled(dev_priv, PIPE_C);
1137 }
1138
70722468
VS		 1139 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1140 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
9c065a7d
DV		 1141
1142 vlv_set_power_well(dev_priv, power_well, false);
e0fce78f
VS		 1143
1144 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1145 phy, dev_priv->chv_phy_control);
30142273
VS		 1146
1147 assert_chv_phy_status(dev_priv);
e0fce78f
VS		 1148}
1149
6669e39f
VS		 1150static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1151 enum dpio_channel ch, bool override, unsigned int mask)
1152{
1153 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1154 u32 reg, val, expected, actual;
1155
1156 if (ch == DPIO_CH0)
1157 reg = _CHV_CMN_DW0_CH0;
1158 else
1159 reg = _CHV_CMN_DW6_CH1;
1160
1161 mutex_lock(&dev_priv->sb_lock);
1162 val = vlv_dpio_read(dev_priv, pipe, reg);
1163 mutex_unlock(&dev_priv->sb_lock);
1164
1165 /*
1166 * This assumes !override is only used when the port is disabled.
1167 * All lanes should power down even without the override when
1168 * the port is disabled.
1169 */
1170 if (!override || mask == 0xf) {
1171 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1172 /*
1173 * If CH1 common lane is not active anymore
1174 * (eg. for pipe B DPLL) the entire channel will
1175 * shut down, which causes the common lane registers
1176 * to read as 0. That means we can't actually check
1177 * the lane power down status bits, but as the entire
1178 * register reads as 0 it's a good indication that the
1179 * channel is indeed entirely powered down.
1180 */
1181 if (ch == DPIO_CH1 && val == 0)
1182 expected = 0;
1183 } else if (mask != 0x0) {
1184 expected = DPIO_ANYDL_POWERDOWN;
1185 } else {
1186 expected = 0;
1187 }
1188
1189 if (ch == DPIO_CH0)
1190 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1191 else
1192 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1193 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1194
1195 WARN(actual != expected,
1196 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1197 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1198 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1199 reg, val);
1200}
1201
b0b33846
VS		 1202bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1203 enum dpio_channel ch, bool override)
1204{
1205 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1206 bool was_override;
1207
1208 mutex_lock(&power_domains->lock);
1209
1210 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1211
1212 if (override == was_override)
1213 goto out;
1214
1215 if (override)
1216 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1217 else
1218 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1219
1220 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1221
1222 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1223 phy, ch, dev_priv->chv_phy_control);
1224
30142273
VS		 1225 assert_chv_phy_status(dev_priv);
1226
b0b33846
VS		 1227out:
1228 mutex_unlock(&power_domains->lock);
1229
1230 return was_override;
1231}
1232
e0fce78f
VS		 1233void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1234 bool override, unsigned int mask)
1235{
1236 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1237 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1238 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1239 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1240
1241 mutex_lock(&power_domains->lock);
1242
1243 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1244 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1245
1246 if (override)
1247 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1248 else
1249 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1250
1251 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1252
1253 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1254 phy, ch, mask, dev_priv->chv_phy_control);
1255
30142273
VS		 1256 assert_chv_phy_status(dev_priv);
1257
6669e39f
VS		 1258 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1259
e0fce78f 1260 mutex_unlock(&power_domains->lock);
9c065a7d
DV		 1261}
1262
1263static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1264 struct i915_power_well *power_well)
1265{
1266 enum pipe pipe = power_well->data;
1267 bool enabled;
1268 u32 state, ctrl;
1269
1270 mutex_lock(&dev_priv->rps.hw_lock);
1271
1272 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1273 /*
1274 * We only ever set the power-on and power-gate states, anything
1275 * else is unexpected.
1276 */
1277 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1278 enabled = state == DP_SSS_PWR_ON(pipe);
1279
1280 /*
1281 * A transient state at this point would mean some unexpected party
1282 * is poking at the power controls too.
1283 */
1284 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1285 WARN_ON(ctrl << 16 != state);
1286
1287 mutex_unlock(&dev_priv->rps.hw_lock);
1288
1289 return enabled;
1290}
1291
1292static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1293 struct i915_power_well *power_well,
1294 bool enable)
1295{
1296 enum pipe pipe = power_well->data;
1297 u32 state;
1298 u32 ctrl;
1299
1300 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1301
1302 mutex_lock(&dev_priv->rps.hw_lock);
1303
1304#define COND \
1305 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1306
1307 if (COND)
1308 goto out;
1309
1310 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1311 ctrl &= ~DP_SSC_MASK(pipe);
1312 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1313 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1314
1315 if (wait_for(COND, 100))
7e35ab88 1316 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
DV		 1317 state,
1318 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1319
1320#undef COND
1321
1322out:
1323 mutex_unlock(&dev_priv->rps.hw_lock);
1324}
1325
1326static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1327 struct i915_power_well *power_well)
1328{
8fcd5cd8
VS		 1329 WARN_ON_ONCE(power_well->data != PIPE_A);
1330
9c065a7d
DV		 1331 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1332}
1333
1334static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1335 struct i915_power_well *power_well)
1336{
8fcd5cd8 1337 WARN_ON_ONCE(power_well->data != PIPE_A);
9c065a7d
DV		 1338
1339 chv_set_pipe_power_well(dev_priv, power_well, true);
afd6275d 1340
2be7d540 1341 vlv_display_power_well_init(dev_priv);
9c065a7d
DV		 1342}
1343
1344static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1345 struct i915_power_well *power_well)
1346{
8fcd5cd8
VS		 1347 WARN_ON_ONCE(power_well->data != PIPE_A);
1348
2be7d540 1349 vlv_display_power_well_deinit(dev_priv);
afd6275d 1350
9c065a7d
DV		 1351 chv_set_pipe_power_well(dev_priv, power_well, false);
1352}
1353
e4e7684f
DV		 1354/**
1355 * intel_display_power_get - grab a power domain reference
1356 * @dev_priv: i915 device instance
1357 * @domain: power domain to reference
1358 *
1359 * This function grabs a power domain reference for @domain and ensures that the
1360 * power domain and all its parents are powered up. Therefore users should only
1361 * grab a reference to the innermost power domain they need.
1362 *
1363 * Any power domain reference obtained by this function must have a symmetric
1364 * call to intel_display_power_put() to release the reference again.
1365 */
9c065a7d
DV		 1366void intel_display_power_get(struct drm_i915_private *dev_priv,
1367 enum intel_display_power_domain domain)
1368{
1369 struct i915_power_domains *power_domains;
1370 struct i915_power_well *power_well;
1371 int i;
1372
1373 intel_runtime_pm_get(dev_priv);
1374
1375 power_domains = &dev_priv->power_domains;
1376
1377 mutex_lock(&power_domains->lock);
1378
1379 for_each_power_well(i, power_well, BIT(domain), power_domains) {
e8ca9320
DL		 1380 if (!power_well->count++)
1381 intel_power_well_enable(dev_priv, power_well);
9c065a7d
DV		 1382 }
1383
1384 power_domains->domain_use_count[domain]++;
1385
1386 mutex_unlock(&power_domains->lock);
1387}
1388
e4e7684f
DV		 1389/**
1390 * intel_display_power_put - release a power domain reference
1391 * @dev_priv: i915 device instance
1392 * @domain: power domain to reference
1393 *
1394 * This function drops the power domain reference obtained by
1395 * intel_display_power_get() and might power down the corresponding hardware
1396 * block right away if this is the last reference.
1397 */
9c065a7d
DV		 1398void intel_display_power_put(struct drm_i915_private *dev_priv,
1399 enum intel_display_power_domain domain)
1400{
1401 struct i915_power_domains *power_domains;
1402 struct i915_power_well *power_well;
1403 int i;
1404
1405 power_domains = &dev_priv->power_domains;
1406
1407 mutex_lock(&power_domains->lock);
1408
1409 WARN_ON(!power_domains->domain_use_count[domain]);
1410 power_domains->domain_use_count[domain]--;
1411
1412 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1413 WARN_ON(!power_well->count);
1414
dcddab3a
DL		 1415 if (!--power_well->count && i915.disable_power_well)
1416 intel_power_well_disable(dev_priv, power_well);
9c065a7d
DV		 1417 }
1418
1419 mutex_unlock(&power_domains->lock);
1420
1421 intel_runtime_pm_put(dev_priv);
1422}
1423
9c065a7d
DV		 1424#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1425 BIT(POWER_DOMAIN_PIPE_A) | \
1426 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
1427 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
1428 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
1429 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1430 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1431 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1432 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1433 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1434 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1435 BIT(POWER_DOMAIN_PORT_CRT) | \
1436 BIT(POWER_DOMAIN_PLLS) | \
1407121a
S		 1437 BIT(POWER_DOMAIN_AUX_A) | \
1438 BIT(POWER_DOMAIN_AUX_B) | \
1439 BIT(POWER_DOMAIN_AUX_C) | \
1440 BIT(POWER_DOMAIN_AUX_D) | \
9c065a7d
DV		 1441 BIT(POWER_DOMAIN_INIT))
1442#define HSW_DISPLAY_POWER_DOMAINS ( \
1443 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1444 BIT(POWER_DOMAIN_INIT))
1445
1446#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1447 HSW_ALWAYS_ON_POWER_DOMAINS | \
1448 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1449#define BDW_DISPLAY_POWER_DOMAINS ( \
1450 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1451 BIT(POWER_DOMAIN_INIT))
1452
1453#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1454#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1455
1456#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1457 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1458 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1459 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1460 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1461 BIT(POWER_DOMAIN_PORT_CRT) | \
1407121a
S		 1462 BIT(POWER_DOMAIN_AUX_B) | \
1463 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1464 BIT(POWER_DOMAIN_INIT))
1465
1466#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1467 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1468 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1407121a 1469 BIT(POWER_DOMAIN_AUX_B) | \
9c065a7d
DV		 1470 BIT(POWER_DOMAIN_INIT))
1471
1472#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1473 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1407121a 1474 BIT(POWER_DOMAIN_AUX_B) | \
9c065a7d
DV		 1475 BIT(POWER_DOMAIN_INIT))
1476
1477#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1478 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1479 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1407121a 1480 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1481 BIT(POWER_DOMAIN_INIT))
1482
1483#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1484 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1407121a 1485 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1486 BIT(POWER_DOMAIN_INIT))
1487
9c065a7d
DV		 1488#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1489 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1490 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1491 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1492 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1407121a
S		 1493 BIT(POWER_DOMAIN_AUX_B) | \
1494 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1495 BIT(POWER_DOMAIN_INIT))
1496
1497#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1498 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1499 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1407121a 1500 BIT(POWER_DOMAIN_AUX_D) | \
9c065a7d
DV		 1501 BIT(POWER_DOMAIN_INIT))
1502
9c065a7d
DV		 1503static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1504 .sync_hw = i9xx_always_on_power_well_noop,
1505 .enable = i9xx_always_on_power_well_noop,
1506 .disable = i9xx_always_on_power_well_noop,
1507 .is_enabled = i9xx_always_on_power_well_enabled,
1508};
1509
1510static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1511 .sync_hw = chv_pipe_power_well_sync_hw,
1512 .enable = chv_pipe_power_well_enable,
1513 .disable = chv_pipe_power_well_disable,
1514 .is_enabled = chv_pipe_power_well_enabled,
1515};
1516
1517static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1518 .sync_hw = vlv_power_well_sync_hw,
1519 .enable = chv_dpio_cmn_power_well_enable,
1520 .disable = chv_dpio_cmn_power_well_disable,
1521 .is_enabled = vlv_power_well_enabled,
1522};
1523
1524static struct i915_power_well i9xx_always_on_power_well[] = {
1525 {
1526 .name = "always-on",
1527 .always_on = 1,
1528 .domains = POWER_DOMAIN_MASK,
1529 .ops = &i9xx_always_on_power_well_ops,
1530 },
1531};
1532
1533static const struct i915_power_well_ops hsw_power_well_ops = {
1534 .sync_hw = hsw_power_well_sync_hw,
1535 .enable = hsw_power_well_enable,
1536 .disable = hsw_power_well_disable,
1537 .is_enabled = hsw_power_well_enabled,
1538};
1539
94dd5138
S		 1540static const struct i915_power_well_ops skl_power_well_ops = {
1541 .sync_hw = skl_power_well_sync_hw,
1542 .enable = skl_power_well_enable,
1543 .disable = skl_power_well_disable,
1544 .is_enabled = skl_power_well_enabled,
1545};
1546
9c065a7d
DV		 1547static struct i915_power_well hsw_power_wells[] = {
1548 {
1549 .name = "always-on",
1550 .always_on = 1,
1551 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1552 .ops = &i9xx_always_on_power_well_ops,
1553 },
1554 {
1555 .name = "display",
1556 .domains = HSW_DISPLAY_POWER_DOMAINS,
1557 .ops = &hsw_power_well_ops,
1558 },
1559};
1560
1561static struct i915_power_well bdw_power_wells[] = {
1562 {
1563 .name = "always-on",
1564 .always_on = 1,
1565 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1566 .ops = &i9xx_always_on_power_well_ops,
1567 },
1568 {
1569 .name = "display",
1570 .domains = BDW_DISPLAY_POWER_DOMAINS,
1571 .ops = &hsw_power_well_ops,
1572 },
1573};
1574
1575static const struct i915_power_well_ops vlv_display_power_well_ops = {
1576 .sync_hw = vlv_power_well_sync_hw,
1577 .enable = vlv_display_power_well_enable,
1578 .disable = vlv_display_power_well_disable,
1579 .is_enabled = vlv_power_well_enabled,
1580};
1581
1582static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1583 .sync_hw = vlv_power_well_sync_hw,
1584 .enable = vlv_dpio_cmn_power_well_enable,
1585 .disable = vlv_dpio_cmn_power_well_disable,
1586 .is_enabled = vlv_power_well_enabled,
1587};
1588
1589static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1590 .sync_hw = vlv_power_well_sync_hw,
1591 .enable = vlv_power_well_enable,
1592 .disable = vlv_power_well_disable,
1593 .is_enabled = vlv_power_well_enabled,
1594};
1595
1596static struct i915_power_well vlv_power_wells[] = {
1597 {
1598 .name = "always-on",
1599 .always_on = 1,
1600 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1601 .ops = &i9xx_always_on_power_well_ops,
1602 },
1603 {
1604 .name = "display",
1605 .domains = VLV_DISPLAY_POWER_DOMAINS,
1606 .data = PUNIT_POWER_WELL_DISP2D,
1607 .ops = &vlv_display_power_well_ops,
1608 },
1609 {
1610 .name = "dpio-tx-b-01",
1611 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1612 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1613 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1614 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1615 .ops = &vlv_dpio_power_well_ops,
1616 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1617 },
1618 {
1619 .name = "dpio-tx-b-23",
1620 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1621 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1622 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1623 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1624 .ops = &vlv_dpio_power_well_ops,
1625 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1626 },
1627 {
1628 .name = "dpio-tx-c-01",
1629 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1630 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1631 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1632 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1633 .ops = &vlv_dpio_power_well_ops,
1634 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1635 },
1636 {
1637 .name = "dpio-tx-c-23",
1638 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1639 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1640 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1641 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1642 .ops = &vlv_dpio_power_well_ops,
1643 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1644 },
1645 {
1646 .name = "dpio-common",
1647 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1648 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1649 .ops = &vlv_dpio_cmn_power_well_ops,
1650 },
1651};
1652
1653static struct i915_power_well chv_power_wells[] = {
1654 {
1655 .name = "always-on",
1656 .always_on = 1,
1657 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1658 .ops = &i9xx_always_on_power_well_ops,
1659 },
9c065a7d
DV		 1660 {
1661 .name = "display",
baa4e575 1662 /*
fde61e4b
VS		 1663 * Pipe A power well is the new disp2d well. Pipe B and C
1664 * power wells don't actually exist. Pipe A power well is
1665 * required for any pipe to work.
baa4e575 1666 */
fde61e4b 1667 .domains = VLV_DISPLAY_POWER_DOMAINS,
9c065a7d
DV		 1668 .data = PIPE_A,
1669 .ops = &chv_pipe_power_well_ops,
1670 },
9c065a7d
DV		 1671 {
1672 .name = "dpio-common-bc",
71849b67 1673 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
9c065a7d
DV		 1674 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1675 .ops = &chv_dpio_cmn_power_well_ops,
1676 },
1677 {
1678 .name = "dpio-common-d",
71849b67 1679 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
9c065a7d
DV		 1680 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1681 .ops = &chv_dpio_cmn_power_well_ops,
1682 },
9c065a7d
DV		 1683};
1684
5aefb239
SS		 1685bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1686 int power_well_id)
1687{
1688 struct i915_power_well *power_well;
1689 bool ret;
1690
1691 power_well = lookup_power_well(dev_priv, power_well_id);
1692 ret = power_well->ops->is_enabled(dev_priv, power_well);
1693
1694 return ret;
1695}
1696
94dd5138
S		 1697static struct i915_power_well skl_power_wells[] = {
1698 {
1699 .name = "always-on",
1700 .always_on = 1,
1701 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1702 .ops = &i9xx_always_on_power_well_ops,
1703 },
1704 {
1705 .name = "power well 1",
1706 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1707 .ops = &skl_power_well_ops,
1708 .data = SKL_DISP_PW_1,
1709 },
1710 {
1711 .name = "MISC IO power well",
1712 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1713 .ops = &skl_power_well_ops,
1714 .data = SKL_DISP_PW_MISC_IO,
1715 },
1716 {
1717 .name = "power well 2",
1718 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1719 .ops = &skl_power_well_ops,
1720 .data = SKL_DISP_PW_2,
1721 },
1722 {
1723 .name = "DDI A/E power well",
1724 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1725 .ops = &skl_power_well_ops,
1726 .data = SKL_DISP_PW_DDI_A_E,
1727 },
1728 {
1729 .name = "DDI B power well",
1730 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1731 .ops = &skl_power_well_ops,
1732 .data = SKL_DISP_PW_DDI_B,
1733 },
1734 {
1735 .name = "DDI C power well",
1736 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1737 .ops = &skl_power_well_ops,
1738 .data = SKL_DISP_PW_DDI_C,
1739 },
1740 {
1741 .name = "DDI D power well",
1742 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1743 .ops = &skl_power_well_ops,
1744 .data = SKL_DISP_PW_DDI_D,
1745 },
1746};
1747
0b4a2a36
S		 1748static struct i915_power_well bxt_power_wells[] = {
1749 {
1750 .name = "always-on",
1751 .always_on = 1,
1752 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1753 .ops = &i9xx_always_on_power_well_ops,
1754 },
1755 {
1756 .name = "power well 1",
1757 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1758 .ops = &skl_power_well_ops,
1759 .data = SKL_DISP_PW_1,
1760 },
1761 {
1762 .name = "power well 2",
1763 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1764 .ops = &skl_power_well_ops,
1765 .data = SKL_DISP_PW_2,
1766 }
1767};
1768
9c065a7d
DV		 1769#define set_power_wells(power_domains, __power_wells) ({ \
1770 (power_domains)->power_wells = (__power_wells); \
1771 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1772})
1773
e4e7684f
DV		 1774/**
1775 * intel_power_domains_init - initializes the power domain structures
1776 * @dev_priv: i915 device instance
1777 *
1778 * Initializes the power domain structures for @dev_priv depending upon the
1779 * supported platform.
1780 */
9c065a7d
DV		 1781int intel_power_domains_init(struct drm_i915_private *dev_priv)
1782{
1783 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1784
1785 mutex_init(&power_domains->lock);
1786
1787 /*
1788 * The enabling order will be from lower to higher indexed wells,
1789 * the disabling order is reversed.
1790 */
1791 if (IS_HASWELL(dev_priv->dev)) {
1792 set_power_wells(power_domains, hsw_power_wells);
9c065a7d
DV		 1793 } else if (IS_BROADWELL(dev_priv->dev)) {
1794 set_power_wells(power_domains, bdw_power_wells);
94dd5138
S		 1795 } else if (IS_SKYLAKE(dev_priv->dev)) {
1796 set_power_wells(power_domains, skl_power_wells);
0b4a2a36
S		 1797 } else if (IS_BROXTON(dev_priv->dev)) {
1798 set_power_wells(power_domains, bxt_power_wells);
9c065a7d
DV		 1799 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1800 set_power_wells(power_domains, chv_power_wells);
1801 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1802 set_power_wells(power_domains, vlv_power_wells);
1803 } else {
1804 set_power_wells(power_domains, i9xx_always_on_power_well);
1805 }
1806
1807 return 0;
1808}
1809
41373cd5
DV		 1810static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1811{
1812 struct drm_device *dev = dev_priv->dev;
1813 struct device *device = &dev->pdev->dev;
1814
1815 if (!HAS_RUNTIME_PM(dev))
1816 return;
1817
1818 if (!intel_enable_rc6(dev))
1819 return;
1820
1821 /* Make sure we're not suspended first. */
1822 pm_runtime_get_sync(device);
1823 pm_runtime_disable(device);
1824}
1825
e4e7684f
DV		 1826/**
1827 * intel_power_domains_fini - finalizes the power domain structures
1828 * @dev_priv: i915 device instance
1829 *
1830 * Finalizes the power domain structures for @dev_priv depending upon the
1831 * supported platform. This function also disables runtime pm and ensures that
1832 * the device stays powered up so that the driver can be reloaded.
1833 */
f458ebbc 1834void intel_power_domains_fini(struct drm_i915_private *dev_priv)
9c065a7d 1835{
41373cd5
DV		 1836 intel_runtime_pm_disable(dev_priv);
1837
f458ebbc
DV		 1838 /* The i915.ko module is still not prepared to be loaded when
1839 * the power well is not enabled, so just enable it in case
1840 * we're going to unload/reload. */
1841 intel_display_set_init_power(dev_priv, true);
9c065a7d
DV		 1842}
1843
1844static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1845{
1846 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1847 struct i915_power_well *power_well;
1848 int i;
1849
1850 mutex_lock(&power_domains->lock);
1851 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1852 power_well->ops->sync_hw(dev_priv, power_well);
1853 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1854 power_well);
1855 }
1856 mutex_unlock(&power_domains->lock);
1857}
1858
70722468
VS		 1859static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1860{
1861 struct i915_power_well *cmn_bc =
1862 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1863 struct i915_power_well *cmn_d =
1864 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1865
1866 /*
1867 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1868 * workaround never ever read DISPLAY_PHY_CONTROL, and
1869 * instead maintain a shadow copy ourselves. Use the actual
e0fce78f
VS		 1870 * power well state and lane status to reconstruct the
1871 * expected initial value.
70722468
VS		 1872 */
1873 dev_priv->chv_phy_control =
bc284542
VS		 1874 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1875 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
e0fce78f
VS		 1876 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1877 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1878 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1879
1880 /*
1881 * If all lanes are disabled we leave the override disabled
1882 * with all power down bits cleared to match the state we
1883 * would use after disabling the port. Otherwise enable the
1884 * override and set the lane powerdown bits accding to the
1885 * current lane status.
1886 */
1887 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1888 uint32_t status = I915_READ(DPLL(PIPE_A));
1889 unsigned int mask;
1890
1891 mask = status & DPLL_PORTB_READY_MASK;
1892 if (mask == 0xf)
1893 mask = 0x0;
1894 else
1895 dev_priv->chv_phy_control |=
1896 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1897
1898 dev_priv->chv_phy_control |=
1899 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1900
1901 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1902 if (mask == 0xf)
1903 mask = 0x0;
1904 else
1905 dev_priv->chv_phy_control |=
1906 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1907
1908 dev_priv->chv_phy_control |=
1909 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1910
70722468 1911 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
e0fce78f
VS		 1912 }
1913
1914 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1915 uint32_t status = I915_READ(DPIO_PHY_STATUS);
1916 unsigned int mask;
1917
1918 mask = status & DPLL_PORTD_READY_MASK;
1919
1920 if (mask == 0xf)
1921 mask = 0x0;
1922 else
1923 dev_priv->chv_phy_control |=
1924 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1925
1926 dev_priv->chv_phy_control |=
1927 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1928
70722468 1929 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
e0fce78f
VS		 1930 }
1931
1932 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1933
1934 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
1935 dev_priv->chv_phy_control);
70722468
VS		 1936}
1937
9c065a7d
DV		 1938static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1939{
1940 struct i915_power_well *cmn =
1941 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1942 struct i915_power_well *disp2d =
1943 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1944
9c065a7d 1945 /* If the display might be already active skip this */
5d93a6e5
VS		 1946 if (cmn->ops->is_enabled(dev_priv, cmn) &&
1947 disp2d->ops->is_enabled(dev_priv, disp2d) &&
9c065a7d
DV		 1948 I915_READ(DPIO_CTL) & DPIO_CMNRST)
1949 return;
1950
1951 DRM_DEBUG_KMS("toggling display PHY side reset\n");
1952
1953 /* cmnlane needs DPLL registers */
1954 disp2d->ops->enable(dev_priv, disp2d);
1955
1956 /*
1957 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1958 * Need to assert and de-assert PHY SB reset by gating the
1959 * common lane power, then un-gating it.
1960 * Simply ungating isn't enough to reset the PHY enough to get
1961 * ports and lanes running.
1962 */
1963 cmn->ops->disable(dev_priv, cmn);
1964}
1965
e4e7684f
DV		 1966/**
1967 * intel_power_domains_init_hw - initialize hardware power domain state
1968 * @dev_priv: i915 device instance
1969 *
1970 * This function initializes the hardware power domain state and enables all
1971 * power domains using intel_display_set_init_power().
1972 */
9c065a7d
DV		 1973void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
1974{
1975 struct drm_device *dev = dev_priv->dev;
1976 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1977
1978 power_domains->initializing = true;
1979
70722468 1980 if (IS_CHERRYVIEW(dev)) {
770effb1 1981 mutex_lock(&power_domains->lock);
70722468 1982 chv_phy_control_init(dev_priv);
770effb1 1983 mutex_unlock(&power_domains->lock);
70722468 1984 } else if (IS_VALLEYVIEW(dev)) {
9c065a7d
DV		 1985 mutex_lock(&power_domains->lock);
1986 vlv_cmnlane_wa(dev_priv);
1987 mutex_unlock(&power_domains->lock);
1988 }
1989
1990 /* For now, we need the power well to be always enabled. */
1991 intel_display_set_init_power(dev_priv, true);
1992 intel_power_domains_resume(dev_priv);
1993 power_domains->initializing = false;
1994}
1995
e4e7684f 1996/**
ca2b1403 1997 * intel_aux_display_runtime_get - grab an auxiliary power domain reference
e4e7684f
DV		 1998 * @dev_priv: i915 device instance
1999 *
2000 * This function grabs a power domain reference for the auxiliary power domain
2001 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
2002 * parents are powered up. Therefore users should only grab a reference to the
2003 * innermost power domain they need.
2004 *
2005 * Any power domain reference obtained by this function must have a symmetric
2006 * call to intel_aux_display_runtime_put() to release the reference again.
2007 */
9c065a7d
DV		 2008void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
2009{
2010 intel_runtime_pm_get(dev_priv);
2011}
2012
e4e7684f 2013/**
ca2b1403 2014 * intel_aux_display_runtime_put - release an auxiliary power domain reference
e4e7684f
DV		 2015 * @dev_priv: i915 device instance
2016 *
ca2b1403 2017 * This function drops the auxiliary power domain reference obtained by
e4e7684f
DV		 2018 * intel_aux_display_runtime_get() and might power down the corresponding
2019 * hardware block right away if this is the last reference.
2020 */
9c065a7d
DV		 2021void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
2022{
2023 intel_runtime_pm_put(dev_priv);
2024}
2025
e4e7684f
DV		 2026/**
2027 * intel_runtime_pm_get - grab a runtime pm reference
2028 * @dev_priv: i915 device instance
2029 *
2030 * This function grabs a device-level runtime pm reference (mostly used for GEM
2031 * code to ensure the GTT or GT is on) and ensures that it is powered up.
2032 *
2033 * Any runtime pm reference obtained by this function must have a symmetric
2034 * call to intel_runtime_pm_put() to release the reference again.
2035 */
9c065a7d
DV		 2036void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2037{
2038 struct drm_device *dev = dev_priv->dev;
2039 struct device *device = &dev->pdev->dev;
2040
2041 if (!HAS_RUNTIME_PM(dev))
2042 return;
2043
2044 pm_runtime_get_sync(device);
2045 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
2046}
2047
e4e7684f
DV		 2048/**
2049 * intel_runtime_pm_get_noresume - grab a runtime pm reference
2050 * @dev_priv: i915 device instance
2051 *
2052 * This function grabs a device-level runtime pm reference (mostly used for GEM
2053 * code to ensure the GTT or GT is on).
2054 *
2055 * It will _not_ power up the device but instead only check that it's powered
2056 * on. Therefore it is only valid to call this functions from contexts where
2057 * the device is known to be powered up and where trying to power it up would
2058 * result in hilarity and deadlocks. That pretty much means only the system
2059 * suspend/resume code where this is used to grab runtime pm references for
2060 * delayed setup down in work items.
2061 *
2062 * Any runtime pm reference obtained by this function must have a symmetric
2063 * call to intel_runtime_pm_put() to release the reference again.
2064 */
9c065a7d
DV		 2065void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2066{
2067 struct drm_device *dev = dev_priv->dev;
2068 struct device *device = &dev->pdev->dev;
2069
2070 if (!HAS_RUNTIME_PM(dev))
2071 return;
2072
2073 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
2074 pm_runtime_get_noresume(device);
2075}
2076
e4e7684f
DV		 2077/**
2078 * intel_runtime_pm_put - release a runtime pm reference
2079 * @dev_priv: i915 device instance
2080 *
2081 * This function drops the device-level runtime pm reference obtained by
2082 * intel_runtime_pm_get() and might power down the corresponding
2083 * hardware block right away if this is the last reference.
2084 */
9c065a7d
DV		 2085void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2086{
2087 struct drm_device *dev = dev_priv->dev;
2088 struct device *device = &dev->pdev->dev;
2089
2090 if (!HAS_RUNTIME_PM(dev))
2091 return;
2092
2093 pm_runtime_mark_last_busy(device);
2094 pm_runtime_put_autosuspend(device);
2095}
2096
e4e7684f
DV		 2097/**
2098 * intel_runtime_pm_enable - enable runtime pm
2099 * @dev_priv: i915 device instance
2100 *
2101 * This function enables runtime pm at the end of the driver load sequence.
2102 *
2103 * Note that this function does currently not enable runtime pm for the
2104 * subordinate display power domains. That is only done on the first modeset
2105 * using intel_display_set_init_power().
2106 */
f458ebbc 2107void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
9c065a7d
DV		 2108{
2109 struct drm_device *dev = dev_priv->dev;
2110 struct device *device = &dev->pdev->dev;
2111
2112 if (!HAS_RUNTIME_PM(dev))
2113 return;
2114
2115 pm_runtime_set_active(device);
2116
2117 /*
2118 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
2119 * requirement.
2120 */
2121 if (!intel_enable_rc6(dev)) {
2122 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
2123 return;
2124 }
2125
2126 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2127 pm_runtime_mark_last_busy(device);
2128 pm_runtime_use_autosuspend(device);
2129
2130 pm_runtime_put_autosuspend(device);
2131}
2132
Linux kernel - Deliverables
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