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drm/i915: export error state ref handling
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
19d415a2 83 * intel_sdvo_get_capabilities()
e2f0ba97 84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
890f3359 205static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 206{
4ef69c7a 207 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
212 return container_of(intel_attached_encoder(connector),
213 struct intel_sdvo, base);
214}
215
615fb93f
CW		 216static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
217{
218 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
219}
220
fb7a46f3 221static bool
ea5b213a 222intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 223static bool
224intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
225 struct intel_sdvo_connector *intel_sdvo_connector,
226 int type);
227static bool
228intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
229 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 230
79e53945
JB		 231/**
232 * Writes the SDVOB or SDVOC with the given value, but always writes both
233 * SDVOB and SDVOC to work around apparent hardware issues (according to
234 * comments in the BIOS).
235 */
ea5b213a 236static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 237{
4ef69c7a 238 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 239 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 240 u32 bval = val, cval = val;
241 int i;
242
ea5b213a
CW		 243 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
244 I915_WRITE(intel_sdvo->sdvo_reg, val);
245 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 246 return;
247 }
248
e2debe91
PZ		 249 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
250 cval = I915_READ(GEN3_SDVOC);
251 else
252 bval = I915_READ(GEN3_SDVOB);
253
79e53945
JB		 254 /*
255 * Write the registers twice for luck. Sometimes,
256 * writing them only once doesn't appear to 'stick'.
257 * The BIOS does this too. Yay, magic
258 */
259 for (i = 0; i < 2; i++)
260 {
e2debe91
PZ		 261 I915_WRITE(GEN3_SDVOB, bval);
262 I915_READ(GEN3_SDVOB);
263 I915_WRITE(GEN3_SDVOC, cval);
264 I915_READ(GEN3_SDVOC);
79e53945
JB		 265 }
266}
267
32aad86f 268static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 269{
79e53945
JB		 270 struct i2c_msg msgs[] = {
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = 0,
274 .len = 1,
e957d772 275 .buf = &addr,
79e53945
JB		 276 },
277 {
e957d772 278 .addr = intel_sdvo->slave_addr,
79e53945
JB		 279 .flags = I2C_M_RD,
280 .len = 1,
e957d772 281 .buf = ch,
79e53945
JB		 282 }
283 };
32aad86f 284 int ret;
79e53945 285
f899fc64 286 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 287 return true;
79e53945 288
8a4c47f3 289 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 290 return false;
291}
292
79e53945
JB		 293#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
294/** Mapping of command numbers to names, for debug output */
005568be 295static const struct _sdvo_cmd_name {
e2f0ba97 296 u8 cmd;
2e88e40b 297 const char *name;
79e53945 298} sdvo_cmd_names[] = {
0206e353
AJ		 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
342
343 /* Add the op code for SDVO enhancements */
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
388
389 /* HDMI op code */
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 410};
411
eef4eacb 412#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 413
ea5b213a 414static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 415 const void *args, int args_len)
79e53945 416{
79e53945
JB		 417 int i;
418
8a4c47f3 419 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 420 SDVO_NAME(intel_sdvo), cmd);
79e53945 421 for (i = 0; i < args_len; i++)
342dc382 422 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 423 for (; i < 8; i++)
342dc382 424 DRM_LOG_KMS(" ");
04ad327f 425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 426 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 427 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 428 break;
429 }
430 }
04ad327f 431 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 432 DRM_LOG_KMS("(%02X)", cmd);
433 DRM_LOG_KMS("\n");
79e53945 434}
79e53945 435
e957d772
CW		 436static const char *cmd_status_names[] = {
437 "Power on",
438 "Success",
439 "Not supported",
440 "Invalid arg",
441 "Pending",
442 "Target not specified",
443 "Scaling not supported"
444};
445
32aad86f
CW		 446static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
447 const void *args, int args_len)
79e53945 448{
3bf3f452
BW		 449 u8 *buf, status;
450 struct i2c_msg *msgs;
451 int i, ret = true;
452
0274df3e 453 /* Would be simpler to allocate both in one go ? */
5c67eeb6 454 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 455 if (!buf)
456 return false;
457
458 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 459 if (!msgs) {
460 kfree(buf);
3bf3f452 461 return false;
0274df3e 462 }
79e53945 463
ea5b213a 464 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 465
466 for (i = 0; i < args_len; i++) {
e957d772
CW		 467 msgs[i].addr = intel_sdvo->slave_addr;
468 msgs[i].flags = 0;
469 msgs[i].len = 2;
470 msgs[i].buf = buf + 2 *i;
471 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
472 buf[2*i + 1] = ((u8*)args)[i];
473 }
474 msgs[i].addr = intel_sdvo->slave_addr;
475 msgs[i].flags = 0;
476 msgs[i].len = 2;
477 msgs[i].buf = buf + 2*i;
478 buf[2*i + 0] = SDVO_I2C_OPCODE;
479 buf[2*i + 1] = cmd;
480
481 /* the following two are to read the response */
482 status = SDVO_I2C_CMD_STATUS;
483 msgs[i+1].addr = intel_sdvo->slave_addr;
484 msgs[i+1].flags = 0;
485 msgs[i+1].len = 1;
486 msgs[i+1].buf = &status;
487
488 msgs[i+2].addr = intel_sdvo->slave_addr;
489 msgs[i+2].flags = I2C_M_RD;
490 msgs[i+2].len = 1;
491 msgs[i+2].buf = &status;
492
493 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
494 if (ret < 0) {
495 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 496 ret = false;
497 goto out;
e957d772
CW		 498 }
499 if (ret != i+3) {
500 /* failure in I2C transfer */
501 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 502 ret = false;
e957d772
CW		 503 }
504
3bf3f452
BW		 505out:
506 kfree(msgs);
507 kfree(buf);
508 return ret;
79e53945
JB		 509}
510
b5c616a7
CW		 511static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
512 void *response, int response_len)
79e53945 513{
fc37381c 514 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 515 u8 status;
33b52961 516 int i;
79e53945 517
d121a5d2
CW		 518 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
519
b5c616a7
CW		 520 /*
521 * The documentation states that all commands will be
522 * processed within 15µs, and that we need only poll
523 * the status byte a maximum of 3 times in order for the
524 * command to be complete.
525 *
526 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 527 *
528 * Also beware that the first response by many devices is to
529 * reply PENDING and stall for time. TVs are notorious for
530 * requiring longer than specified to complete their replies.
531 * Originally (in the DDX long ago), the delay was only ever 15ms
532 * with an additional delay of 30ms applied for TVs added later after
533 * many experiments. To accommodate both sets of delays, we do a
534 * sequence of slow checks if the device is falling behind and fails
535 * to reply within 5*15µs.
b5c616a7 536 */
d121a5d2
CW		 537 if (!intel_sdvo_read_byte(intel_sdvo,
538 SDVO_I2C_CMD_STATUS,
539 &status))
540 goto log_fail;
541
fc37381c
CW		 542 while (status == SDVO_CMD_STATUS_PENDING && --retry) {
543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
b5c616a7
CW		 548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
d121a5d2
CW		 551 goto log_fail;
552 }
b5c616a7 553
79e53945 554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 556 else
342dc382 557 DRM_LOG_KMS("(??? %d)", status);
79e53945 558
b5c616a7
CW		 559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
79e53945 561
b5c616a7
CW		 562 /* Read the command response */
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
e957d772 568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 569 }
b5c616a7 570 DRM_LOG_KMS("\n");
b5c616a7 571 return true;
79e53945 572
b5c616a7 573log_fail:
d121a5d2 574 DRM_LOG_KMS("... failed\n");
b5c616a7 575 return false;
79e53945
JB		 576}
577
b358d0a6 578static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 579{
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586}
587
e957d772
CW		 588static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
79e53945 590{
d121a5d2 591 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
79e53945
JB		 595}
596
32aad86f 597static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 598{
d121a5d2
CW		 599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 603}
79e53945 604
32aad86f
CW		 605static bool
606intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607{
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
79e53945 610
32aad86f
CW		 611 return intel_sdvo_read_response(intel_sdvo, value, len);
612}
79e53945 613
32aad86f
CW		 614static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615{
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
79e53945
JB		 620}
621
622/**
623 * Return whether each input is trained.
624 *
625 * This function is making an assumption about the layout of the response,
626 * which should be checked against the docs.
627 */
ea5b213a 628static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 629{
630 struct intel_sdvo_get_trained_inputs_response response;
79e53945 631
1a3665c8 632 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
79e53945
JB		 635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640}
641
ea5b213a 642static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 643 u16 outputs)
644{
32aad86f
CW		 645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
79e53945
JB		 648}
649
4ac41f47
DV		 650static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652{
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656}
657
ea5b213a 658static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 659 int mode)
660{
32aad86f 661 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
32aad86f
CW		 678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 680}
681
ea5b213a 682static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int *clock_min,
684 int *clock_max)
685{
686 struct intel_sdvo_pixel_clock_range clocks;
79e53945 687
1a3665c8 688 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
79e53945
JB		 692 return false;
693
694 /* Convert the values from units of 10 kHz to kHz. */
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
79e53945
JB		 697 return true;
698}
699
ea5b213a 700static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 701 u16 outputs)
702{
32aad86f
CW		 703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
79e53945
JB		 706}
707
ea5b213a 708static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 709 struct intel_sdvo_dtd *dtd)
710{
32aad86f
CW		 711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 713}
714
045ac3b5
JB		 715static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
716 struct intel_sdvo_dtd *dtd)
717{
718 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
720}
721
ea5b213a 722static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 723 struct intel_sdvo_dtd *dtd)
724{
ea5b213a 725 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 726 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
727}
728
ea5b213a 729static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 730 struct intel_sdvo_dtd *dtd)
731{
ea5b213a 732 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 733 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
734}
735
045ac3b5
JB		 736static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
737 struct intel_sdvo_dtd *dtd)
738{
739 return intel_sdvo_get_timing(intel_sdvo,
740 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
741}
742
e2f0ba97 743static bool
ea5b213a 744intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 745 uint16_t clock,
746 uint16_t width,
747 uint16_t height)
748{
749 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 750
e642c6f1 751 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 752 args.clock = clock;
753 args.width = width;
754 args.height = height;
e642c6f1 755 args.interlace = 0;
12682a97 756
ea5b213a
CW		 757 if (intel_sdvo->is_lvds &&
758 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
759 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 760 args.scaled = 1;
761
32aad86f
CW		 762 return intel_sdvo_set_value(intel_sdvo,
763 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
764 &args, sizeof(args));
e2f0ba97
JB		 765}
766
ea5b213a 767static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 768 struct intel_sdvo_dtd *dtd)
769{
1a3665c8
CW		 770 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
771 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 772 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
773 &dtd->part1, sizeof(dtd->part1)) &&
774 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
775 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 776}
79e53945 777
ea5b213a 778static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 779{
32aad86f 780 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 781}
782
e2f0ba97 783static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 784 const struct drm_display_mode *mode)
79e53945 785{
e2f0ba97
JB		 786 uint16_t width, height;
787 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
788 uint16_t h_sync_offset, v_sync_offset;
6651819b 789 int mode_clock;
79e53945 790
c6ebd4c0
DV		 791 width = mode->hdisplay;
792 height = mode->vdisplay;
79e53945
JB		 793
794 /* do some mode translations */
c6ebd4c0
DV		 795 h_blank_len = mode->htotal - mode->hdisplay;
796 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 797
c6ebd4c0
DV		 798 v_blank_len = mode->vtotal - mode->vdisplay;
799 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 800
c6ebd4c0
DV		 801 h_sync_offset = mode->hsync_start - mode->hdisplay;
802 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 803
6651819b 804 mode_clock = mode->clock;
6651819b
DV		 805 mode_clock /= 10;
806 dtd->part1.clock = mode_clock;
807
e2f0ba97
JB		 808 dtd->part1.h_active = width & 0xff;
809 dtd->part1.h_blank = h_blank_len & 0xff;
810 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 811 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 812 dtd->part1.v_active = height & 0xff;
813 dtd->part1.v_blank = v_blank_len & 0xff;
814 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 815 ((v_blank_len >> 8) & 0xf);
816
171a9e96 817 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 818 dtd->part2.h_sync_width = h_sync_len & 0xff;
819 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 820 (v_sync_len & 0xf);
e2f0ba97 821 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 822 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
823 ((v_sync_len & 0x30) >> 4);
824
e2f0ba97 825 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 826 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
827 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 828 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 829 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 830 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 831 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 832
833 dtd->part2.sdvo_flags = 0;
834 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
835 dtd->part2.reserved = 0;
836}
837
838static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 839 const struct intel_sdvo_dtd *dtd)
e2f0ba97 840{
e2f0ba97
JB		 841 mode->hdisplay = dtd->part1.h_active;
842 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
843 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 844 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 845 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
846 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
847 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
848 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
849
850 mode->vdisplay = dtd->part1.v_active;
851 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
852 mode->vsync_start = mode->vdisplay;
853 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 854 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 855 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
856 mode->vsync_end = mode->vsync_start +
857 (dtd->part2.v_sync_off_width & 0xf);
858 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
859 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
860 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
861
862 mode->clock = dtd->part1.clock * 10;
863
171a9e96 864 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 865 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
866 mode->flags |= DRM_MODE_FLAG_INTERLACE;
867 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 868 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 869 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 870 mode->flags |= DRM_MODE_FLAG_PVSYNC;
871}
872
e27d8538 873static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 874{
e27d8538 875 struct intel_sdvo_encode encode;
e2f0ba97 876
1a3665c8 877 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 878 return intel_sdvo_get_value(intel_sdvo,
879 SDVO_CMD_GET_SUPP_ENCODE,
880 &encode, sizeof(encode));
e2f0ba97
JB		 881}
882
ea5b213a 883static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 884 uint8_t mode)
e2f0ba97 885{
32aad86f 886 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 887}
888
ea5b213a 889static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 890 uint8_t mode)
891{
32aad86f 892 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 893}
894
895#if 0
ea5b213a 896static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 897{
898 int i, j;
899 uint8_t set_buf_index[2];
900 uint8_t av_split;
901 uint8_t buf_size;
902 uint8_t buf[48];
903 uint8_t *pos;
904
32aad86f 905 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 906
907 for (i = 0; i <= av_split; i++) {
908 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 909 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 910 set_buf_index, 2);
c751ce4f
EA		 911 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
912 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 913
914 pos = buf;
915 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 916 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 917 NULL, 0);
c751ce4f 918 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 919 pos += 8;
920 }
921 }
922}
923#endif
924
b6e0e543
DV		 925static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
926 unsigned if_index, uint8_t tx_rate,
927 uint8_t *data, unsigned length)
928{
929 uint8_t set_buf_index[2] = { if_index, 0 };
930 uint8_t hbuf_size, tmp[8];
931 int i;
932
933 if (!intel_sdvo_set_value(intel_sdvo,
934 SDVO_CMD_SET_HBUF_INDEX,
935 set_buf_index, 2))
936 return false;
937
938 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
939 &hbuf_size, 1))
940 return false;
941
942 /* Buffer size is 0 based, hooray! */
943 hbuf_size++;
944
945 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
946 if_index, length, hbuf_size);
947
948 for (i = 0; i < hbuf_size; i += 8) {
949 memset(tmp, 0, 8);
950 if (i < length)
951 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
952
953 if (!intel_sdvo_set_value(intel_sdvo,
954 SDVO_CMD_SET_HBUF_DATA,
955 tmp, 8))
956 return false;
957 }
958
959 return intel_sdvo_set_value(intel_sdvo,
960 SDVO_CMD_SET_HBUF_TXRATE,
961 &tx_rate, 1);
962}
963
abedc077
VS		 964static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
965 const struct drm_display_mode *adjusted_mode)
e2f0ba97
JB		 966{
967 struct dip_infoframe avi_if = {
968 .type = DIP_TYPE_AVI,
3c17fe4b 969 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 970 .len = DIP_LEN_AVI,
971 };
81014b9d 972 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
50f3b016 973 struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
3c17fe4b 974
abedc077 975 if (intel_sdvo->rgb_quant_range_selectable) {
50f3b016 976 if (intel_crtc->config.limited_color_range)
abedc077
VS		 977 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
978 else
979 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
980 }
981
96b219fa
VS		 982 avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
983
3c17fe4b
DH		 984 intel_dip_infoframe_csum(&avi_if);
985
81014b9d
DV		 986 /* sdvo spec says that the ecc is handled by the hw, and it looks like
987 * we must not send the ecc field, either. */
988 memcpy(sdvo_data, &avi_if, 3);
989 sdvo_data[3] = avi_if.checksum;
990 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
991
b6e0e543
DV		 992 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
993 SDVO_HBUF_TX_VSYNC,
994 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 995}
996
32aad86f 997static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 998{
ce6feabd 999 struct intel_sdvo_tv_format format;
40039750 1000 uint32_t format_map;
ce6feabd 1001
40039750 1002 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1003 memset(&format, 0, sizeof(format));
32aad86f 1004 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1005
32aad86f
CW		 1006 BUILD_BUG_ON(sizeof(format) != 6);
1007 return intel_sdvo_set_value(intel_sdvo,
1008 SDVO_CMD_SET_TV_FORMAT,
1009 &format, sizeof(format));
7026d4ac
ZW		 1010}
1011
32aad86f
CW		 1012static bool
1013intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1014 const struct drm_display_mode *mode)
e2f0ba97 1015{
32aad86f 1016 struct intel_sdvo_dtd output_dtd;
79e53945 1017
32aad86f
CW		 1018 if (!intel_sdvo_set_target_output(intel_sdvo,
1019 intel_sdvo->attached_output))
1020 return false;
e2f0ba97 1021
32aad86f
CW		 1022 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1023 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1024 return false;
e2f0ba97 1025
32aad86f
CW		 1026 return true;
1027}
1028
c9a29698
DV		 1029/* Asks the sdvo controller for the preferred input mode given the output mode.
1030 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1031static bool
c9a29698 1032intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1033 const struct drm_display_mode *mode,
c9a29698 1034 struct drm_display_mode *adjusted_mode)
32aad86f 1035{
c9a29698
DV		 1036 struct intel_sdvo_dtd input_dtd;
1037
32aad86f
CW		 1038 /* Reset the input timing to the screen. Assume always input 0. */
1039 if (!intel_sdvo_set_target_input(intel_sdvo))
1040 return false;
e2f0ba97 1041
32aad86f
CW		 1042 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1043 mode->clock / 10,
1044 mode->hdisplay,
1045 mode->vdisplay))
1046 return false;
e2f0ba97 1047
32aad86f 1048 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1049 &input_dtd))
32aad86f 1050 return false;
e2f0ba97 1051
c9a29698 1052 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1053 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1054
32aad86f
CW		 1055 return true;
1056}
12682a97 1057
70484559
DV		 1058static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1059{
1060 unsigned dotclock = pipe_config->adjusted_mode.clock;
1061 struct dpll *clock = &pipe_config->dpll;
1062
1063 /* SDVO TV has fixed PLL values depend on its clock range,
1064 this mirrors vbios setting. */
1065 if (dotclock >= 100000 && dotclock < 140500) {
1066 clock->p1 = 2;
1067 clock->p2 = 10;
1068 clock->n = 3;
1069 clock->m1 = 16;
1070 clock->m2 = 8;
1071 } else if (dotclock >= 140500 && dotclock <= 200000) {
1072 clock->p1 = 1;
1073 clock->p2 = 10;
1074 clock->n = 6;
1075 clock->m1 = 12;
1076 clock->m2 = 8;
1077 } else {
1078 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1079 }
1080
1081 pipe_config->clock_set = true;
1082}
1083
6cc5f341
DV		 1084static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1085 struct intel_crtc_config *pipe_config)
32aad86f 1086{
6cc5f341
DV		 1087 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1088 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1089 struct drm_display_mode *mode = &pipe_config->requested_mode;
12682a97 1090
5d2d38dd
DV		 1091 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1092 pipe_config->pipe_bpp = 8*3;
1093
5bfe2ac0
DV		 1094 if (HAS_PCH_SPLIT(encoder->base.dev))
1095 pipe_config->has_pch_encoder = true;
1096
32aad86f
CW		 1097 /* We need to construct preferred input timings based on our
1098 * output timings. To do that, we have to set the output
1099 * timings, even though this isn't really the right place in
1100 * the sequence to do it. Oh well.
1101 */
1102 if (intel_sdvo->is_tv) {
1103 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1104 return false;
12682a97 1105
c9a29698
DV		 1106 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1107 mode,
1108 adjusted_mode);
09ede541 1109 pipe_config->sdvo_tv_clock = true;
ea5b213a 1110 } else if (intel_sdvo->is_lvds) {
32aad86f 1111 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1112 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1113 return false;
12682a97 1114
c9a29698
DV		 1115 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1116 mode,
1117 adjusted_mode);
e2f0ba97 1118 }
32aad86f
CW		 1119
1120 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1121 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1122 */
6cc5f341
DV		 1123 pipe_config->pixel_multiplier =
1124 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1125 adjusted_mode->clock *= pipe_config->pixel_multiplier;
32aad86f 1126
55bc60db
VS		 1127 if (intel_sdvo->color_range_auto) {
1128 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1129 /* FIXME: This bit is only valid when using TMDS encoding and 8
1130 * bit per color mode. */
55bc60db 1131 if (intel_sdvo->has_hdmi_monitor &&
18316c8c 1132 drm_match_cea_mode(adjusted_mode) > 1)
4f3a8bc7 1133 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1134 else
1135 intel_sdvo->color_range = 0;
1136 }
1137
3685a8f3 1138 if (intel_sdvo->color_range)
50f3b016 1139 pipe_config->limited_color_range = true;
3685a8f3 1140
70484559
DV		 1141 /* Clock computation needs to happen after pixel multiplier. */
1142 if (intel_sdvo->is_tv)
1143 i9xx_adjust_sdvo_tv_clock(pipe_config);
1144
e2f0ba97
JB		 1145 return true;
1146}
1147
6cc5f341 1148static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
e2f0ba97 1149{
6cc5f341 1150 struct drm_device *dev = intel_encoder->base.dev;
e2f0ba97 1151 struct drm_i915_private *dev_priv = dev->dev_private;
6cc5f341 1152 struct drm_crtc *crtc = intel_encoder->base.crtc;
e2f0ba97 1153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 1154 struct drm_display_mode *adjusted_mode =
1155 &intel_crtc->config.adjusted_mode;
1156 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
1157 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
6c9547ff 1158 u32 sdvox;
e2f0ba97 1159 struct intel_sdvo_in_out_map in_out;
6651819b 1160 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1161 int rate;
e2f0ba97
JB		 1162
1163 if (!mode)
1164 return;
1165
1166 /* First, set the input mapping for the first input to our controlled
1167 * output. This is only correct if we're a single-input device, in
1168 * which case the first input is the output from the appropriate SDVO
1169 * channel on the motherboard. In a two-input device, the first input
1170 * will be SDVOB and the second SDVOC.
1171 */
ea5b213a 1172 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1173 in_out.in1 = 0;
1174
c74696b9
PR		 1175 intel_sdvo_set_value(intel_sdvo,
1176 SDVO_CMD_SET_IN_OUT_MAP,
1177 &in_out, sizeof(in_out));
e2f0ba97 1178
6c9547ff
CW		 1179 /* Set the output timings to the screen */
1180 if (!intel_sdvo_set_target_output(intel_sdvo,
1181 intel_sdvo->attached_output))
1182 return;
e2f0ba97 1183
6651819b
DV		 1184 /* lvds has a special fixed output timing. */
1185 if (intel_sdvo->is_lvds)
1186 intel_sdvo_get_dtd_from_mode(&output_dtd,
1187 intel_sdvo->sdvo_lvds_fixed_mode);
1188 else
1189 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1190 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1191 DRM_INFO("Setting output timings on %s failed\n",
1192 SDVO_NAME(intel_sdvo));
79e53945
JB		 1193
1194 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1195 if (!intel_sdvo_set_target_input(intel_sdvo))
1196 return;
79e53945 1197
97aaf910
CW		 1198 if (intel_sdvo->has_hdmi_monitor) {
1199 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1200 intel_sdvo_set_colorimetry(intel_sdvo,
1201 SDVO_COLORIMETRY_RGB256);
abedc077 1202 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1203 } else
1204 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1205
6c9547ff
CW		 1206 if (intel_sdvo->is_tv &&
1207 !intel_sdvo_set_tv_format(intel_sdvo))
1208 return;
e2f0ba97 1209
6651819b
DV		 1210 /* We have tried to get input timing in mode_fixup, and filled into
1211 * adjusted_mode.
1212 */
1213 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
e751823d
EE		 1214 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1215 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1216 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1217 DRM_INFO("Setting input timings on %s failed\n",
1218 SDVO_NAME(intel_sdvo));
79e53945 1219
6cc5f341 1220 switch (intel_crtc->config.pixel_multiplier) {
6c9547ff 1221 default:
ef1b460d 1222 WARN(1, "unknown pixel mutlipler specified\n");
32aad86f
CW		 1223 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1224 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1225 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1226 }
32aad86f
CW		 1227 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1228 return;
79e53945
JB		 1229
1230 /* Set the SDVO control regs. */
a6c45cf0 1231 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1232 /* The real mode polarity is set by the SDVO commands, using
1233 * struct intel_sdvo_dtd. */
1234 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1235 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1236 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1237 if (INTEL_INFO(dev)->gen < 5)
1238 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1239 } else {
6c9547ff 1240 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1241 switch (intel_sdvo->sdvo_reg) {
e2debe91 1242 case GEN3_SDVOB:
e2f0ba97
JB		 1243 sdvox &= SDVOB_PRESERVE_MASK;
1244 break;
e2debe91 1245 case GEN3_SDVOC:
e2f0ba97
JB		 1246 sdvox &= SDVOC_PRESERVE_MASK;
1247 break;
1248 }
1249 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1250 }
3573c410
PZ		 1251
1252 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
dc0fa718 1253 sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
3573c410 1254 else
dc0fa718 1255 sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
3573c410 1256
da79de97 1257 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1258 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1259
a6c45cf0 1260 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1261 /* done in crtc_mode_set as the dpll_md reg must be written early */
1262 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1263 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1264 } else {
6cc5f341
DV		 1265 sdvox |= (intel_crtc->config.pixel_multiplier - 1)
1266 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1267 }
1268
6714afb1
CW		 1269 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1270 INTEL_INFO(dev)->gen < 5)
12682a97 1271 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1272 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1273}
1274
4ac41f47 1275static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1276{
4ac41f47
DV		 1277 struct intel_sdvo_connector *intel_sdvo_connector =
1278 to_intel_sdvo_connector(&connector->base);
1279 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1280 u16 active_outputs = 0;
4ac41f47
DV		 1281
1282 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1283
1284 if (active_outputs & intel_sdvo_connector->output_flag)
1285 return true;
1286 else
1287 return false;
1288}
1289
1290static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1291 enum pipe *pipe)
1292{
1293 struct drm_device *dev = encoder->base.dev;
79e53945 1294 struct drm_i915_private *dev_priv = dev->dev_private;
4ac41f47 1295 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
2f28c50b 1296 u16 active_outputs = 0;
4ac41f47
DV		 1297 u32 tmp;
1298
1299 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1300 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1301
7a7d1fb7 1302 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1303 return false;
1304
1305 if (HAS_PCH_CPT(dev))
1306 *pipe = PORT_TO_PIPE_CPT(tmp);
1307 else
1308 *pipe = PORT_TO_PIPE(tmp);
1309
1310 return true;
1311}
1312
045ac3b5
JB		 1313static void intel_sdvo_get_config(struct intel_encoder *encoder,
1314 struct intel_crtc_config *pipe_config)
1315{
6c49f241
DV		 1316 struct drm_device *dev = encoder->base.dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
045ac3b5
JB		 1318 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1319 struct intel_sdvo_dtd dtd;
6c49f241
DV		 1320 int encoder_pixel_multiplier = 0;
1321 u32 flags = 0, sdvox;
1322 u8 val;
045ac3b5
JB		 1323 bool ret;
1324
1325 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1326 if (!ret) {
bb760063
DV		 1327 /* Some sdvo encoders are not spec compliant and don't
1328 * implement the mandatory get_timings function. */
045ac3b5 1329 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1330 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1331 } else {
1332 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1333 flags |= DRM_MODE_FLAG_PHSYNC;
1334 else
1335 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1336
bb760063
DV		 1337 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1338 flags |= DRM_MODE_FLAG_PVSYNC;
1339 else
1340 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1341 }
1342
045ac3b5 1343 pipe_config->adjusted_mode.flags |= flags;
045ac3b5 1344
fdafa9e2
DV		 1345 /*
1346 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1347 * the sdvo port register, on all other platforms it is part of the dpll
1348 * state. Since the general pipe state readout happens before the
1349 * encoder->get_config we so already have a valid pixel multplier on all
1350 * other platfroms.
1351 */
6c49f241
DV		 1352 if (IS_I915G(dev) || IS_I915GM(dev)) {
1353 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1354 pipe_config->pixel_multiplier =
1355 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1356 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1357 }
045ac3b5 1358
6c49f241
DV		 1359 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1360 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
1361 switch (val) {
1362 case SDVO_CLOCK_RATE_MULT_1X:
1363 encoder_pixel_multiplier = 1;
1364 break;
1365 case SDVO_CLOCK_RATE_MULT_2X:
1366 encoder_pixel_multiplier = 2;
1367 break;
1368 case SDVO_CLOCK_RATE_MULT_4X:
1369 encoder_pixel_multiplier = 4;
1370 break;
1371 }
fdafa9e2 1372
6c49f241
DV		 1373 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1374 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1375 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1376}
1377
ce22c320
DV		 1378static void intel_disable_sdvo(struct intel_encoder *encoder)
1379{
1380 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1381 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1382 u32 temp;
1383
1384 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1385 if (0)
1386 intel_sdvo_set_encoder_power_state(intel_sdvo,
1387 DRM_MODE_DPMS_OFF);
1388
1389 temp = I915_READ(intel_sdvo->sdvo_reg);
1390 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1391 /* HW workaround for IBX, we need to move the port to
1392 * transcoder A before disabling it. */
1393 if (HAS_PCH_IBX(encoder->base.dev)) {
1394 struct drm_crtc *crtc = encoder->base.crtc;
1395 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1396
1397 if (temp & SDVO_PIPE_B_SELECT) {
1398 temp &= ~SDVO_PIPE_B_SELECT;
1399 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1400 POSTING_READ(intel_sdvo->sdvo_reg);
1401
1402 /* Again we need to write this twice. */
1403 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1404 POSTING_READ(intel_sdvo->sdvo_reg);
1405
1406 /* Transcoder selection bits only update
1407 * effectively on vblank. */
1408 if (crtc)
1409 intel_wait_for_vblank(encoder->base.dev, pipe);
1410 else
1411 msleep(50);
1412 }
1413 }
1414
ce22c320
DV		 1415 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1416 }
1417}
1418
1419static void intel_enable_sdvo(struct intel_encoder *encoder)
1420{
1421 struct drm_device *dev = encoder->base.dev;
1422 struct drm_i915_private *dev_priv = dev->dev_private;
1423 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1424 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1425 u32 temp;
ce22c320
DV		 1426 bool input1, input2;
1427 int i;
1428 u8 status;
1429
1430 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1431 if ((temp & SDVO_ENABLE) == 0) {
1432 /* HW workaround for IBX, we need to move the port
dc0fa718
PZ		 1433 * to transcoder A before disabling it, so restore it here. */
1434 if (HAS_PCH_IBX(dev))
1435 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
776ca7cf 1436
ce22c320 1437 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1438 }
ce22c320
DV		 1439 for (i = 0; i < 2; i++)
1440 intel_wait_for_vblank(dev, intel_crtc->pipe);
1441
1442 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1443 /* Warn if the device reported failure to sync.
1444 * A lot of SDVO devices fail to notify of sync, but it's
1445 * a given it the status is a success, we succeeded.
1446 */
1447 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1448 DRM_DEBUG_KMS("First %s output reported failure to "
1449 "sync\n", SDVO_NAME(intel_sdvo));
1450 }
1451
1452 if (0)
1453 intel_sdvo_set_encoder_power_state(intel_sdvo,
1454 DRM_MODE_DPMS_ON);
1455 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1456}
1457
6b1c087b 1458/* Special dpms function to support cloning between dvo/sdvo/crt. */
b2cabb0e 1459static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1460{
b2cabb0e
DV		 1461 struct drm_crtc *crtc;
1462 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1463
1464 /* dvo supports only 2 dpms states. */
1465 if (mode != DRM_MODE_DPMS_ON)
1466 mode = DRM_MODE_DPMS_OFF;
1467
1468 if (mode == connector->dpms)
1469 return;
1470
1471 connector->dpms = mode;
1472
1473 /* Only need to change hw state when actually enabled */
1474 crtc = intel_sdvo->base.base.crtc;
1475 if (!crtc) {
1476 intel_sdvo->base.connectors_active = false;
1477 return;
1478 }
79e53945 1479
6b1c087b
JN		 1480 /* We set active outputs manually below in case pipe dpms doesn't change
1481 * due to cloning. */
79e53945 1482 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1483 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1484 if (0)
ea5b213a 1485 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1486
b2cabb0e
DV		 1487 intel_sdvo->base.connectors_active = false;
1488
1489 intel_crtc_update_dpms(crtc);
79e53945 1490 } else {
b2cabb0e
DV		 1491 intel_sdvo->base.connectors_active = true;
1492
1493 intel_crtc_update_dpms(crtc);
79e53945
JB		 1494
1495 if (0)
ea5b213a
CW		 1496 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1497 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1498 }
0a91ca29 1499
b980514c 1500 intel_modeset_check_state(connector->dev);
79e53945
JB		 1501}
1502
79e53945
JB		 1503static int intel_sdvo_mode_valid(struct drm_connector *connector,
1504 struct drm_display_mode *mode)
1505{
df0e9248 1506 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1507
1508 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1509 return MODE_NO_DBLESCAN;
1510
ea5b213a 1511 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1512 return MODE_CLOCK_LOW;
1513
ea5b213a 1514 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1515 return MODE_CLOCK_HIGH;
1516
8545423a 1517 if (intel_sdvo->is_lvds) {
ea5b213a 1518 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1519 return MODE_PANEL;
1520
ea5b213a 1521 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1522 return MODE_PANEL;
1523 }
1524
79e53945
JB		 1525 return MODE_OK;
1526}
1527
ea5b213a 1528static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1529{
1a3665c8 1530 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1531 if (!intel_sdvo_get_value(intel_sdvo,
1532 SDVO_CMD_GET_DEVICE_CAPS,
1533 caps, sizeof(*caps)))
1534 return false;
1535
1536 DRM_DEBUG_KMS("SDVO capabilities:\n"
1537 " vendor_id: %d\n"
1538 " device_id: %d\n"
1539 " device_rev_id: %d\n"
1540 " sdvo_version_major: %d\n"
1541 " sdvo_version_minor: %d\n"
1542 " sdvo_inputs_mask: %d\n"
1543 " smooth_scaling: %d\n"
1544 " sharp_scaling: %d\n"
1545 " up_scaling: %d\n"
1546 " down_scaling: %d\n"
1547 " stall_support: %d\n"
1548 " output_flags: %d\n",
1549 caps->vendor_id,
1550 caps->device_id,
1551 caps->device_rev_id,
1552 caps->sdvo_version_major,
1553 caps->sdvo_version_minor,
1554 caps->sdvo_inputs_mask,
1555 caps->smooth_scaling,
1556 caps->sharp_scaling,
1557 caps->up_scaling,
1558 caps->down_scaling,
1559 caps->stall_support,
1560 caps->output_flags);
1561
1562 return true;
79e53945
JB		 1563}
1564
5fa7ac9c 1565static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1566{
768b107e 1567 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1568 uint16_t hotplug;
79e53945 1569
768b107e
DV		 1570 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1571 * on the line. */
1572 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1573 return 0;
768b107e 1574
5fa7ac9c
JN		 1575 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1576 &hotplug, sizeof(hotplug)))
1577 return 0;
768b107e 1578
5fa7ac9c 1579 return hotplug;
79e53945
JB		 1580}
1581
cc68c81a 1582static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1583{
cc68c81a 1584 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1585
5fa7ac9c
JN		 1586 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1587 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1588}
1589
fb7a46f3 1590static bool
ea5b213a 1591intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1592{
bc65212c 1593 /* Is there more than one type of output? */
2294488d 1594 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1595}
1596
f899fc64 1597static struct edid *
e957d772 1598intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1599{
e957d772
CW		 1600 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1601 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1602}
1603
ff482d83
CW		 1604/* Mac mini hack -- use the same DDC as the analog connector */
1605static struct edid *
1606intel_sdvo_get_analog_edid(struct drm_connector *connector)
1607{
f899fc64 1608 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1609
0c1dab89 1610 return drm_get_edid(connector,
3bd7d909 1611 intel_gmbus_get_adapter(dev_priv,
41aa3448 1612 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1613}
1614
c43b5634 1615static enum drm_connector_status
8bf38485 1616intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1617{
df0e9248 1618 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1619 enum drm_connector_status status;
1620 struct edid *edid;
9dff6af8 1621
e957d772 1622 edid = intel_sdvo_get_edid(connector);
57cdaf90 1623
ea5b213a 1624 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1625 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1626
7c3f0a27
ZY		 1627 /*
1628 * Don't use the 1 as the argument of DDC bus switch to get
1629 * the EDID. It is used for SDVO SPD ROM.
1630 */
9d1a903d 1631 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1632 intel_sdvo->ddc_bus = ddc;
1633 edid = intel_sdvo_get_edid(connector);
1634 if (edid)
7c3f0a27 1635 break;
7c3f0a27 1636 }
e957d772
CW		 1637 /*
1638 * If we found the EDID on the other bus,
1639 * assume that is the correct DDC bus.
1640 */
1641 if (edid == NULL)
1642 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1643 }
9d1a903d
CW		 1644
1645 /*
1646 * When there is no edid and no monitor is connected with VGA
1647 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1648 */
ff482d83
CW		 1649 if (edid == NULL)
1650 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1651
2f551c84 1652 status = connector_status_unknown;
9dff6af8 1653 if (edid != NULL) {
149c36a3 1654 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1655 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1656 status = connector_status_connected;
da79de97
CW		 1657 if (intel_sdvo->is_hdmi) {
1658 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1659 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1660 intel_sdvo->rgb_quant_range_selectable =
1661 drm_rgb_quant_range_selectable(edid);
da79de97 1662 }
13946743
CW		 1663 } else
1664 status = connector_status_disconnected;
9d1a903d
CW		 1665 kfree(edid);
1666 }
7f36e7ed
CW		 1667
1668 if (status == connector_status_connected) {
1669 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1670 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1671 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1672 }
1673
2b8d33f7 1674 return status;
9dff6af8
ML		 1675}
1676
52220085
CW		 1677static bool
1678intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1679 struct edid *edid)
1680{
1681 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1682 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1683
1684 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1685 connector_is_digital, monitor_is_digital);
1686 return connector_is_digital == monitor_is_digital;
1687}
1688
7b334fcb 1689static enum drm_connector_status
930a9e28 1690intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1691{
fb7a46f3 1692 uint16_t response;
df0e9248 1693 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1694 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1695 enum drm_connector_status ret;
79e53945 1696
fc37381c
CW		 1697 if (!intel_sdvo_get_value(intel_sdvo,
1698 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1699 &response, 2))
32aad86f 1700 return connector_status_unknown;
79e53945 1701
e957d772
CW		 1702 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1703 response & 0xff, response >> 8,
1704 intel_sdvo_connector->output_flag);
e2f0ba97 1705
fb7a46f3 1706 if (response == 0)
79e53945 1707 return connector_status_disconnected;
fb7a46f3 1708
ea5b213a 1709 intel_sdvo->attached_output = response;
14571b4c 1710
97aaf910
CW		 1711 intel_sdvo->has_hdmi_monitor = false;
1712 intel_sdvo->has_hdmi_audio = false;
abedc077 1713 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1714
615fb93f 1715 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1716 ret = connector_status_disconnected;
13946743 1717 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1718 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1719 else {
1720 struct edid *edid;
1721
1722 /* if we have an edid check it matches the connection */
1723 edid = intel_sdvo_get_edid(connector);
1724 if (edid == NULL)
1725 edid = intel_sdvo_get_analog_edid(connector);
1726 if (edid != NULL) {
52220085
CW		 1727 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1728 edid))
13946743 1729 ret = connector_status_connected;
52220085
CW		 1730 else
1731 ret = connector_status_disconnected;
1732
13946743
CW		 1733 kfree(edid);
1734 } else
1735 ret = connector_status_connected;
1736 }
14571b4c
ZW		 1737
1738 /* May update encoder flag for like clock for SDVO TV, etc.*/
1739 if (ret == connector_status_connected) {
ea5b213a
CW		 1740 intel_sdvo->is_tv = false;
1741 intel_sdvo->is_lvds = false;
14571b4c 1742
09ede541 1743 if (response & SDVO_TV_MASK)
ea5b213a 1744 intel_sdvo->is_tv = true;
14571b4c 1745 if (response & SDVO_LVDS_MASK)
8545423a 1746 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1747 }
14571b4c
ZW		 1748
1749 return ret;
79e53945
JB		 1750}
1751
e2f0ba97 1752static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1753{
ff482d83 1754 struct edid *edid;
79e53945
JB		 1755
1756 /* set the bus switch and get the modes */
e957d772 1757 edid = intel_sdvo_get_edid(connector);
79e53945 1758
57cdaf90
KP		 1759 /*
1760 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1761 * link between analog and digital outputs. So, if the regular SDVO
1762 * DDC fails, check to see if the analog output is disconnected, in
1763 * which case we'll look there for the digital DDC data.
e2f0ba97 1764 */
f899fc64
CW		 1765 if (edid == NULL)
1766 edid = intel_sdvo_get_analog_edid(connector);
1767
ff482d83 1768 if (edid != NULL) {
52220085
CW		 1769 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1770 edid)) {
0c1dab89
CW		 1771 drm_mode_connector_update_edid_property(connector, edid);
1772 drm_add_edid_modes(connector, edid);
1773 }
13946743 1774
ff482d83 1775 kfree(edid);
e2f0ba97 1776 }
e2f0ba97
JB		 1777}
1778
1779/*
1780 * Set of SDVO TV modes.
1781 * Note! This is in reply order (see loop in get_tv_modes).
1782 * XXX: all 60Hz refresh?
1783 */
b1f559ec 1784static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1785 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1786 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1787 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1788 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1789 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1790 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1791 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1792 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1794 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1795 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1797 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1798 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1800 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1801 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1802 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1803 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1804 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1806 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1807 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1808 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1809 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1810 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1812 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1813 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1815 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1816 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1818 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1819 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1821 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1822 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1824 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1825 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1827 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1828 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1830 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1831 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1833 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1834 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1836 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1837 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1839 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1840 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1842};
1843
1844static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1845{
df0e9248 1846 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1847 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1848 uint32_t reply = 0, format_map = 0;
1849 int i;
e2f0ba97
JB		 1850
1851 /* Read the list of supported input resolutions for the selected TV
1852 * format.
1853 */
40039750 1854 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1855 memcpy(&tv_res, &format_map,
32aad86f 1856 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1857
32aad86f
CW		 1858 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1859 return;
ce6feabd 1860
32aad86f 1861 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1862 if (!intel_sdvo_write_cmd(intel_sdvo,
1863 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1864 &tv_res, sizeof(tv_res)))
1865 return;
1866 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1867 return;
1868
1869 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1870 if (reply & (1 << i)) {
1871 struct drm_display_mode *nmode;
1872 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1873 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1874 if (nmode)
1875 drm_mode_probed_add(connector, nmode);
1876 }
e2f0ba97
JB		 1877}
1878
7086c87f
ML		 1879static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1880{
df0e9248 1881 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1882 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1883 struct drm_display_mode *newmode;
7086c87f
ML		 1884
1885 /*
c3456fb3 1886 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 1887 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 1888 */
41aa3448 1889 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1890 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1891 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1892 if (newmode != NULL) {
1893 /* Guarantee the mode is preferred */
1894 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1895 DRM_MODE_TYPE_DRIVER);
1896 drm_mode_probed_add(connector, newmode);
1897 }
1898 }
12682a97 1899
4300a0f8
DA		 1900 /*
1901 * Attempt to get the mode list from DDC.
1902 * Assume that the preferred modes are
1903 * arranged in priority order.
1904 */
1905 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1906
12682a97 1907 list_for_each_entry(newmode, &connector->probed_modes, head) {
1908 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1909 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1910 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1911
8545423a 1912 intel_sdvo->is_lvds = true;
12682a97 1913 break;
1914 }
1915 }
1916
7086c87f
ML		 1917}
1918
e2f0ba97
JB		 1919static int intel_sdvo_get_modes(struct drm_connector *connector)
1920{
615fb93f 1921 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1922
615fb93f 1923 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1924 intel_sdvo_get_tv_modes(connector);
615fb93f 1925 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1926 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1927 else
1928 intel_sdvo_get_ddc_modes(connector);
1929
32aad86f 1930 return !list_empty(&connector->probed_modes);
79e53945
JB		 1931}
1932
fcc8d672
CW		 1933static void
1934intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1935{
615fb93f 1936 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1937 struct drm_device *dev = connector->dev;
1938
c5521706
CW		 1939 if (intel_sdvo_connector->left)
1940 drm_property_destroy(dev, intel_sdvo_connector->left);
1941 if (intel_sdvo_connector->right)
1942 drm_property_destroy(dev, intel_sdvo_connector->right);
1943 if (intel_sdvo_connector->top)
1944 drm_property_destroy(dev, intel_sdvo_connector->top);
1945 if (intel_sdvo_connector->bottom)
1946 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1947 if (intel_sdvo_connector->hpos)
1948 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1949 if (intel_sdvo_connector->vpos)
1950 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1951 if (intel_sdvo_connector->saturation)
1952 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1953 if (intel_sdvo_connector->contrast)
1954 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1955 if (intel_sdvo_connector->hue)
1956 drm_property_destroy(dev, intel_sdvo_connector->hue);
1957 if (intel_sdvo_connector->sharpness)
1958 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1959 if (intel_sdvo_connector->flicker_filter)
1960 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1961 if (intel_sdvo_connector->flicker_filter_2d)
1962 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1963 if (intel_sdvo_connector->flicker_filter_adaptive)
1964 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1965 if (intel_sdvo_connector->tv_luma_filter)
1966 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1967 if (intel_sdvo_connector->tv_chroma_filter)
1968 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1969 if (intel_sdvo_connector->dot_crawl)
1970 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1971 if (intel_sdvo_connector->brightness)
1972 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1973}
1974
79e53945
JB		 1975static void intel_sdvo_destroy(struct drm_connector *connector)
1976{
615fb93f 1977 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1978
c5521706 1979 if (intel_sdvo_connector->tv_format)
ce6feabd 1980 drm_property_destroy(connector->dev,
c5521706 1981 intel_sdvo_connector->tv_format);
b9219c5e 1982
d2a82a6f 1983 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1984 drm_sysfs_connector_remove(connector);
1985 drm_connector_cleanup(connector);
4b745b1e 1986 kfree(intel_sdvo_connector);
79e53945
JB		 1987}
1988
1aad7ac0
CW		 1989static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1990{
1991 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1992 struct edid *edid;
1993 bool has_audio = false;
1994
1995 if (!intel_sdvo->is_hdmi)
1996 return false;
1997
1998 edid = intel_sdvo_get_edid(connector);
1999 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2000 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 2001 kfree(edid);
1aad7ac0
CW		 2002
2003 return has_audio;
2004}
2005
ce6feabd
ZY		 2006static int
2007intel_sdvo_set_property(struct drm_connector *connector,
2008 struct drm_property *property,
2009 uint64_t val)
2010{
df0e9248 2011 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 2012 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 2013 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 2014 uint16_t temp_value;
32aad86f
CW		 2015 uint8_t cmd;
2016 int ret;
ce6feabd 2017
662595df 2018 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 2019 if (ret)
2020 return ret;
ce6feabd 2021
3f43c48d 2022 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2023 int i = val;
2024 bool has_audio;
2025
2026 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 2027 return 0;
2028
1aad7ac0 2029 intel_sdvo_connector->force_audio = i;
7f36e7ed 2030
c3e5f67b 2031 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2032 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2033 else
c3e5f67b 2034 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 2035
1aad7ac0 2036 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 2037 return 0;
7f36e7ed 2038
1aad7ac0 2039 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 2040 goto done;
2041 }
2042
e953fd7b 2043 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2044 bool old_auto = intel_sdvo->color_range_auto;
2045 uint32_t old_range = intel_sdvo->color_range;
2046
55bc60db
VS		 2047 switch (val) {
2048 case INTEL_BROADCAST_RGB_AUTO:
2049 intel_sdvo->color_range_auto = true;
2050 break;
2051 case INTEL_BROADCAST_RGB_FULL:
2052 intel_sdvo->color_range_auto = false;
2053 intel_sdvo->color_range = 0;
2054 break;
2055 case INTEL_BROADCAST_RGB_LIMITED:
2056 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 2057 /* FIXME: this bit is only valid when using TMDS
2058 * encoding and 8 bit per color mode. */
2059 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 2060 break;
2061 default:
2062 return -EINVAL;
2063 }
ae4edb80
DV		 2064
2065 if (old_auto == intel_sdvo->color_range_auto &&
2066 old_range == intel_sdvo->color_range)
2067 return 0;
2068
7f36e7ed
CW		 2069 goto done;
2070 }
2071
c5521706
CW		 2072#define CHECK_PROPERTY(name, NAME) \
2073 if (intel_sdvo_connector->name == property) { \
2074 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2075 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2076 cmd = SDVO_CMD_SET_##NAME; \
2077 intel_sdvo_connector->cur_##name = temp_value; \
2078 goto set_value; \
2079 }
2080
2081 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 2082 if (val >= TV_FORMAT_NUM)
2083 return -EINVAL;
2084
40039750 2085 if (intel_sdvo->tv_format_index ==
615fb93f 2086 intel_sdvo_connector->tv_format_supported[val])
32aad86f 2087 return 0;
ce6feabd 2088
40039750 2089 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 2090 goto done;
32aad86f 2091 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2092 temp_value = val;
c5521706 2093 if (intel_sdvo_connector->left == property) {
662595df 2094 drm_object_property_set_value(&connector->base,
c5521706 2095 intel_sdvo_connector->right, val);
615fb93f 2096 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2097 return 0;
b9219c5e 2098
615fb93f
CW		 2099 intel_sdvo_connector->left_margin = temp_value;
2100 intel_sdvo_connector->right_margin = temp_value;
2101 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2102 intel_sdvo_connector->left_margin;
b9219c5e 2103 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2104 goto set_value;
2105 } else if (intel_sdvo_connector->right == property) {
662595df 2106 drm_object_property_set_value(&connector->base,
c5521706 2107 intel_sdvo_connector->left, val);
615fb93f 2108 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2109 return 0;
b9219c5e 2110
615fb93f
CW		 2111 intel_sdvo_connector->left_margin = temp_value;
2112 intel_sdvo_connector->right_margin = temp_value;
2113 temp_value = intel_sdvo_connector->max_hscan -
2114 intel_sdvo_connector->left_margin;
b9219c5e 2115 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2116 goto set_value;
2117 } else if (intel_sdvo_connector->top == property) {
662595df 2118 drm_object_property_set_value(&connector->base,
c5521706 2119 intel_sdvo_connector->bottom, val);
615fb93f 2120 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2121 return 0;
b9219c5e 2122
615fb93f
CW		 2123 intel_sdvo_connector->top_margin = temp_value;
2124 intel_sdvo_connector->bottom_margin = temp_value;
2125 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2126 intel_sdvo_connector->top_margin;
b9219c5e 2127 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2128 goto set_value;
2129 } else if (intel_sdvo_connector->bottom == property) {
662595df 2130 drm_object_property_set_value(&connector->base,
c5521706 2131 intel_sdvo_connector->top, val);
615fb93f 2132 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2133 return 0;
2134
615fb93f
CW		 2135 intel_sdvo_connector->top_margin = temp_value;
2136 intel_sdvo_connector->bottom_margin = temp_value;
2137 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2138 intel_sdvo_connector->top_margin;
b9219c5e 2139 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2140 goto set_value;
2141 }
2142 CHECK_PROPERTY(hpos, HPOS)
2143 CHECK_PROPERTY(vpos, VPOS)
2144 CHECK_PROPERTY(saturation, SATURATION)
2145 CHECK_PROPERTY(contrast, CONTRAST)
2146 CHECK_PROPERTY(hue, HUE)
2147 CHECK_PROPERTY(brightness, BRIGHTNESS)
2148 CHECK_PROPERTY(sharpness, SHARPNESS)
2149 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2150 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2151 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2152 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2153 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2154 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2155 }
b9219c5e 2156
c5521706 2157 return -EINVAL; /* unknown property */
b9219c5e 2158
c5521706
CW		 2159set_value:
2160 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2161 return -EIO;
b9219c5e 2162
b9219c5e 2163
c5521706 2164done:
c0c36b94
CW		 2165 if (intel_sdvo->base.base.crtc)
2166 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2167
32aad86f 2168 return 0;
c5521706 2169#undef CHECK_PROPERTY
ce6feabd
ZY		 2170}
2171
79e53945 2172static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2173 .dpms = intel_sdvo_dpms,
79e53945
JB		 2174 .detect = intel_sdvo_detect,
2175 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2176 .set_property = intel_sdvo_set_property,
79e53945
JB		 2177 .destroy = intel_sdvo_destroy,
2178};
2179
2180static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2181 .get_modes = intel_sdvo_get_modes,
2182 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2183 .best_encoder = intel_best_encoder,
79e53945
JB		 2184};
2185
b358d0a6 2186static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2187{
890f3359 2188 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 2189
ea5b213a 2190 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2191 drm_mode_destroy(encoder->dev,
ea5b213a 2192 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2193
e957d772 2194 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2195 intel_encoder_destroy(encoder);
79e53945
JB		 2196}
2197
2198static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2199 .destroy = intel_sdvo_enc_destroy,
2200};
2201
b66d8424
CW		 2202static void
2203intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2204{
2205 uint16_t mask = 0;
2206 unsigned int num_bits;
2207
2208 /* Make a mask of outputs less than or equal to our own priority in the
2209 * list.
2210 */
2211 switch (sdvo->controlled_output) {
2212 case SDVO_OUTPUT_LVDS1:
2213 mask |= SDVO_OUTPUT_LVDS1;
2214 case SDVO_OUTPUT_LVDS0:
2215 mask |= SDVO_OUTPUT_LVDS0;
2216 case SDVO_OUTPUT_TMDS1:
2217 mask |= SDVO_OUTPUT_TMDS1;
2218 case SDVO_OUTPUT_TMDS0:
2219 mask |= SDVO_OUTPUT_TMDS0;
2220 case SDVO_OUTPUT_RGB1:
2221 mask |= SDVO_OUTPUT_RGB1;
2222 case SDVO_OUTPUT_RGB0:
2223 mask |= SDVO_OUTPUT_RGB0;
2224 break;
2225 }
2226
2227 /* Count bits to find what number we are in the priority list. */
2228 mask &= sdvo->caps.output_flags;
2229 num_bits = hweight16(mask);
2230 /* If more than 3 outputs, default to DDC bus 3 for now. */
2231 if (num_bits > 3)
2232 num_bits = 3;
2233
2234 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2235 sdvo->ddc_bus = 1 << num_bits;
2236}
79e53945 2237
e2f0ba97
JB		 2238/**
2239 * Choose the appropriate DDC bus for control bus switch command for this
2240 * SDVO output based on the controlled output.
2241 *
2242 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2243 * outputs, then LVDS outputs.
2244 */
2245static void
b1083333 2246intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2247 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2248{
b1083333 2249 struct sdvo_device_mapping *mapping;
e2f0ba97 2250
eef4eacb 2251 if (sdvo->is_sdvob)
b1083333
AJ		 2252 mapping = &(dev_priv->sdvo_mappings[0]);
2253 else
2254 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2255
b66d8424
CW		 2256 if (mapping->initialized)
2257 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2258 else
2259 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2260}
2261
e957d772
CW		 2262static void
2263intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2264 struct intel_sdvo *sdvo, u32 reg)
2265{
2266 struct sdvo_device_mapping *mapping;
46eb3036 2267 u8 pin;
e957d772 2268
eef4eacb 2269 if (sdvo->is_sdvob)
e957d772
CW		 2270 mapping = &dev_priv->sdvo_mappings[0];
2271 else
2272 mapping = &dev_priv->sdvo_mappings[1];
2273
6cb1612a 2274 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2275 pin = mapping->i2c_pin;
6cb1612a
JN		 2276 else
2277 pin = GMBUS_PORT_DPB;
e957d772 2278
6cb1612a
JN		 2279 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2280
2281 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2282 * our code totally fails once we start using gmbus. Hence fall back to
2283 * bit banging for now. */
2284 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2285}
2286
fbfcc4f3
JN		 2287/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2288static void
2289intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2290{
2291 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2292}
2293
e2f0ba97 2294static bool
e27d8538 2295intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2296{
97aaf910 2297 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2298}
2299
714605e4 2300static u8
eef4eacb 2301intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2302{
2303 struct drm_i915_private *dev_priv = dev->dev_private;
2304 struct sdvo_device_mapping *my_mapping, *other_mapping;
2305
eef4eacb 2306 if (sdvo->is_sdvob) {
714605e4 2307 my_mapping = &dev_priv->sdvo_mappings[0];
2308 other_mapping = &dev_priv->sdvo_mappings[1];
2309 } else {
2310 my_mapping = &dev_priv->sdvo_mappings[1];
2311 other_mapping = &dev_priv->sdvo_mappings[0];
2312 }
2313
2314 /* If the BIOS described our SDVO device, take advantage of it. */
2315 if (my_mapping->slave_addr)
2316 return my_mapping->slave_addr;
2317
2318 /* If the BIOS only described a different SDVO device, use the
2319 * address that it isn't using.
2320 */
2321 if (other_mapping->slave_addr) {
2322 if (other_mapping->slave_addr == 0x70)
2323 return 0x72;
2324 else
2325 return 0x70;
2326 }
2327
2328 /* No SDVO device info is found for another DVO port,
2329 * so use mapping assumption we had before BIOS parsing.
2330 */
eef4eacb 2331 if (sdvo->is_sdvob)
714605e4 2332 return 0x70;
2333 else
2334 return 0x72;
2335}
2336
14571b4c 2337static void
df0e9248
CW		 2338intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2339 struct intel_sdvo *encoder)
14571b4c 2340{
df0e9248
CW		 2341 drm_connector_init(encoder->base.base.dev,
2342 &connector->base.base,
2343 &intel_sdvo_connector_funcs,
2344 connector->base.base.connector_type);
6070a4a9 2345
df0e9248
CW		 2346 drm_connector_helper_add(&connector->base.base,
2347 &intel_sdvo_connector_helper_funcs);
14571b4c 2348
8f4839e2 2349 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2350 connector->base.base.doublescan_allowed = 0;
2351 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2352 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2353
df0e9248
CW		 2354 intel_connector_attach_encoder(&connector->base, &encoder->base);
2355 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2356}
6070a4a9 2357
7f36e7ed 2358static void
55bc60db
VS		 2359intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2360 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2361{
2362 struct drm_device *dev = connector->base.base.dev;
2363
3f43c48d 2364 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2365 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2366 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2367 intel_sdvo->color_range_auto = true;
2368 }
7f36e7ed
CW		 2369}
2370
fb7a46f3 2371static bool
ea5b213a 2372intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2373{
4ef69c7a 2374 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2375 struct drm_connector *connector;
cc68c81a 2376 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2377 struct intel_connector *intel_connector;
615fb93f 2378 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2379
615fb93f
CW		 2380 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2381 if (!intel_sdvo_connector)
14571b4c
ZW		 2382 return false;
2383
14571b4c 2384 if (device == 0) {
ea5b213a 2385 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2386 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2387 } else if (device == 1) {
ea5b213a 2388 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2389 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2390 }
2391
615fb93f 2392 intel_connector = &intel_sdvo_connector->base;
14571b4c 2393 connector = &intel_connector->base;
5fa7ac9c
JN		 2394 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2395 intel_sdvo_connector->output_flag) {
5fa7ac9c 2396 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2397 /* Some SDVO devices have one-shot hotplug interrupts.
2398 * Ensure that they get re-enabled when an interrupt happens.
2399 */
2400 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2401 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2402 } else {
821450c6 2403 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2404 }
14571b4c
ZW		 2405 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2406 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2407
e27d8538 2408 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2409 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2410 intel_sdvo->is_hdmi = true;
14571b4c 2411 }
14571b4c 2412
df0e9248 2413 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221 2414 if (intel_sdvo->is_hdmi)
55bc60db 2415 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2416
2417 return true;
2418}
2419
2420static bool
ea5b213a 2421intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2422{
4ef69c7a
CW		 2423 struct drm_encoder *encoder = &intel_sdvo->base.base;
2424 struct drm_connector *connector;
2425 struct intel_connector *intel_connector;
2426 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2427
615fb93f
CW		 2428 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2429 if (!intel_sdvo_connector)
2430 return false;
14571b4c 2431
615fb93f 2432 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2433 connector = &intel_connector->base;
2434 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2435 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2436
4ef69c7a
CW		 2437 intel_sdvo->controlled_output |= type;
2438 intel_sdvo_connector->output_flag = type;
14571b4c 2439
4ef69c7a 2440 intel_sdvo->is_tv = true;
14571b4c 2441
df0e9248 2442 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2443
4ef69c7a 2444 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2445 goto err;
14571b4c 2446
4ef69c7a 2447 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2448 goto err;
14571b4c 2449
4ef69c7a 2450 return true;
32aad86f
CW		 2451
2452err:
123d5c01 2453 intel_sdvo_destroy(connector);
32aad86f 2454 return false;
14571b4c
ZW		 2455}
2456
2457static bool
ea5b213a 2458intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2459{
4ef69c7a
CW		 2460 struct drm_encoder *encoder = &intel_sdvo->base.base;
2461 struct drm_connector *connector;
2462 struct intel_connector *intel_connector;
2463 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2464
615fb93f
CW		 2465 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2466 if (!intel_sdvo_connector)
2467 return false;
14571b4c 2468
615fb93f 2469 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2470 connector = &intel_connector->base;
821450c6 2471 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2472 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2473 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2474
2475 if (device == 0) {
2476 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2477 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2478 } else if (device == 1) {
2479 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2480 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2481 }
2482
df0e9248
CW		 2483 intel_sdvo_connector_init(intel_sdvo_connector,
2484 intel_sdvo);
4ef69c7a 2485 return true;
14571b4c
ZW		 2486}
2487
2488static bool
ea5b213a 2489intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2490{
4ef69c7a
CW		 2491 struct drm_encoder *encoder = &intel_sdvo->base.base;
2492 struct drm_connector *connector;
2493 struct intel_connector *intel_connector;
2494 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2495
615fb93f
CW		 2496 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2497 if (!intel_sdvo_connector)
2498 return false;
14571b4c 2499
615fb93f
CW		 2500 intel_connector = &intel_sdvo_connector->base;
2501 connector = &intel_connector->base;
4ef69c7a
CW		 2502 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2503 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2504
2505 if (device == 0) {
2506 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2507 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2508 } else if (device == 1) {
2509 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2510 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2511 }
2512
df0e9248 2513 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2514 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2515 goto err;
2516
2517 return true;
2518
2519err:
123d5c01 2520 intel_sdvo_destroy(connector);
32aad86f 2521 return false;
14571b4c
ZW		 2522}
2523
2524static bool
ea5b213a 2525intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2526{
ea5b213a 2527 intel_sdvo->is_tv = false;
ea5b213a 2528 intel_sdvo->is_lvds = false;
fb7a46f3 2529
14571b4c 2530 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2531
14571b4c 2532 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2533 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2534 return false;
2535
2536 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2537 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2538 return false;
2539
2540 /* TV has no XXX1 function block */
a1f4b7ff 2541 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2542 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2543 return false;
2544
2545 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2546 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2547 return false;
fb7a46f3 2548
a0b1c7a5
CW		 2549 if (flags & SDVO_OUTPUT_YPRPB0)
2550 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2551 return false;
2552
14571b4c 2553 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2554 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2555 return false;
2556
2557 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2558 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2559 return false;
2560
2561 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2562 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2563 return false;
2564
2565 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2566 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2567 return false;
fb7a46f3 2568
14571b4c 2569 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2570 unsigned char bytes[2];
2571
ea5b213a
CW		 2572 intel_sdvo->controlled_output = 0;
2573 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2574 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2575 SDVO_NAME(intel_sdvo),
51c8b407 2576 bytes[0], bytes[1]);
14571b4c 2577 return false;
fb7a46f3 2578 }
27f8227b 2579 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2580
14571b4c 2581 return true;
fb7a46f3 2582}
2583
d0ddfbd3
JN		 2584static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2585{
2586 struct drm_device *dev = intel_sdvo->base.base.dev;
2587 struct drm_connector *connector, *tmp;
2588
2589 list_for_each_entry_safe(connector, tmp,
2590 &dev->mode_config.connector_list, head) {
2591 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2592 intel_sdvo_destroy(connector);
2593 }
2594}
2595
32aad86f
CW		 2596static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2597 struct intel_sdvo_connector *intel_sdvo_connector,
2598 int type)
ce6feabd 2599{
4ef69c7a 2600 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2601 struct intel_sdvo_tv_format format;
2602 uint32_t format_map, i;
ce6feabd 2603
32aad86f
CW		 2604 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2605 return false;
ce6feabd 2606
1a3665c8 2607 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2608 if (!intel_sdvo_get_value(intel_sdvo,
2609 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2610 &format, sizeof(format)))
2611 return false;
ce6feabd 2612
32aad86f 2613 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2614
2615 if (format_map == 0)
32aad86f 2616 return false;
ce6feabd 2617
615fb93f 2618 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2619 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2620 if (format_map & (1 << i))
2621 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2622
2623
c5521706 2624 intel_sdvo_connector->tv_format =
32aad86f
CW		 2625 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2626 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2627 if (!intel_sdvo_connector->tv_format)
fcc8d672 2628 return false;
ce6feabd 2629
615fb93f 2630 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2631 drm_property_add_enum(
c5521706 2632 intel_sdvo_connector->tv_format, i,
40039750 2633 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2634
40039750 2635 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2636 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2637 intel_sdvo_connector->tv_format, 0);
32aad86f 2638 return true;
ce6feabd
ZY		 2639
2640}
2641
c5521706
CW		 2642#define ENHANCEMENT(name, NAME) do { \
2643 if (enhancements.name) { \
2644 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2645 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2646 return false; \
2647 intel_sdvo_connector->max_##name = data_value[0]; \
2648 intel_sdvo_connector->cur_##name = response; \
2649 intel_sdvo_connector->name = \
d9bc3c02 2650 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2651 if (!intel_sdvo_connector->name) return false; \
662595df 2652 drm_object_attach_property(&connector->base, \
c5521706
CW		 2653 intel_sdvo_connector->name, \
2654 intel_sdvo_connector->cur_##name); \
2655 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2656 data_value[0], data_value[1], response); \
2657 } \
0206e353 2658} while (0)
c5521706
CW		 2659
2660static bool
2661intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2662 struct intel_sdvo_connector *intel_sdvo_connector,
2663 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2664{
4ef69c7a 2665 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2666 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2667 uint16_t response, data_value[2];
2668
c5521706
CW		 2669 /* when horizontal overscan is supported, Add the left/right property */
2670 if (enhancements.overscan_h) {
2671 if (!intel_sdvo_get_value(intel_sdvo,
2672 SDVO_CMD_GET_MAX_OVERSCAN_H,
2673 &data_value, 4))
2674 return false;
32aad86f 2675
c5521706
CW		 2676 if (!intel_sdvo_get_value(intel_sdvo,
2677 SDVO_CMD_GET_OVERSCAN_H,
2678 &response, 2))
2679 return false;
fcc8d672 2680
c5521706
CW		 2681 intel_sdvo_connector->max_hscan = data_value[0];
2682 intel_sdvo_connector->left_margin = data_value[0] - response;
2683 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2684 intel_sdvo_connector->left =
d9bc3c02 2685 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2686 if (!intel_sdvo_connector->left)
2687 return false;
fcc8d672 2688
662595df 2689 drm_object_attach_property(&connector->base,
c5521706
CW		 2690 intel_sdvo_connector->left,
2691 intel_sdvo_connector->left_margin);
fcc8d672 2692
c5521706 2693 intel_sdvo_connector->right =
d9bc3c02 2694 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2695 if (!intel_sdvo_connector->right)
2696 return false;
32aad86f 2697
662595df 2698 drm_object_attach_property(&connector->base,
c5521706
CW		 2699 intel_sdvo_connector->right,
2700 intel_sdvo_connector->right_margin);
2701 DRM_DEBUG_KMS("h_overscan: max %d, "
2702 "default %d, current %d\n",
2703 data_value[0], data_value[1], response);
2704 }
32aad86f 2705
c5521706
CW		 2706 if (enhancements.overscan_v) {
2707 if (!intel_sdvo_get_value(intel_sdvo,
2708 SDVO_CMD_GET_MAX_OVERSCAN_V,
2709 &data_value, 4))
2710 return false;
fcc8d672 2711
c5521706
CW		 2712 if (!intel_sdvo_get_value(intel_sdvo,
2713 SDVO_CMD_GET_OVERSCAN_V,
2714 &response, 2))
2715 return false;
32aad86f 2716
c5521706
CW		 2717 intel_sdvo_connector->max_vscan = data_value[0];
2718 intel_sdvo_connector->top_margin = data_value[0] - response;
2719 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2720 intel_sdvo_connector->top =
d9bc3c02
SH		 2721 drm_property_create_range(dev, 0,
2722 "top_margin", 0, data_value[0]);
c5521706
CW		 2723 if (!intel_sdvo_connector->top)
2724 return false;
32aad86f 2725
662595df 2726 drm_object_attach_property(&connector->base,
c5521706
CW		 2727 intel_sdvo_connector->top,
2728 intel_sdvo_connector->top_margin);
fcc8d672 2729
c5521706 2730 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2731 drm_property_create_range(dev, 0,
2732 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2733 if (!intel_sdvo_connector->bottom)
2734 return false;
32aad86f 2735
662595df 2736 drm_object_attach_property(&connector->base,
c5521706
CW		 2737 intel_sdvo_connector->bottom,
2738 intel_sdvo_connector->bottom_margin);
2739 DRM_DEBUG_KMS("v_overscan: max %d, "
2740 "default %d, current %d\n",
2741 data_value[0], data_value[1], response);
2742 }
32aad86f 2743
c5521706
CW		 2744 ENHANCEMENT(hpos, HPOS);
2745 ENHANCEMENT(vpos, VPOS);
2746 ENHANCEMENT(saturation, SATURATION);
2747 ENHANCEMENT(contrast, CONTRAST);
2748 ENHANCEMENT(hue, HUE);
2749 ENHANCEMENT(sharpness, SHARPNESS);
2750 ENHANCEMENT(brightness, BRIGHTNESS);
2751 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2752 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2753 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2754 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2755 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2756
e044218a
CW		 2757 if (enhancements.dot_crawl) {
2758 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2759 return false;
2760
2761 intel_sdvo_connector->max_dot_crawl = 1;
2762 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2763 intel_sdvo_connector->dot_crawl =
d9bc3c02 2764 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2765 if (!intel_sdvo_connector->dot_crawl)
2766 return false;
2767
662595df 2768 drm_object_attach_property(&connector->base,
e044218a
CW		 2769 intel_sdvo_connector->dot_crawl,
2770 intel_sdvo_connector->cur_dot_crawl);
2771 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2772 }
2773
c5521706
CW		 2774 return true;
2775}
32aad86f 2776
c5521706
CW		 2777static bool
2778intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2779 struct intel_sdvo_connector *intel_sdvo_connector,
2780 struct intel_sdvo_enhancements_reply enhancements)
2781{
4ef69c7a 2782 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2783 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2784 uint16_t response, data_value[2];
32aad86f 2785
c5521706 2786 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2787
c5521706
CW		 2788 return true;
2789}
2790#undef ENHANCEMENT
32aad86f 2791
c5521706
CW		 2792static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2793 struct intel_sdvo_connector *intel_sdvo_connector)
2794{
2795 union {
2796 struct intel_sdvo_enhancements_reply reply;
2797 uint16_t response;
2798 } enhancements;
32aad86f 2799
1a3665c8
CW		 2800 BUILD_BUG_ON(sizeof(enhancements) != 2);
2801
cf9a2f3a
CW		 2802 enhancements.response = 0;
2803 intel_sdvo_get_value(intel_sdvo,
2804 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2805 &enhancements, sizeof(enhancements));
c5521706
CW		 2806 if (enhancements.response == 0) {
2807 DRM_DEBUG_KMS("No enhancement is supported\n");
2808 return true;
b9219c5e 2809 }
32aad86f 2810
c5521706
CW		 2811 if (IS_TV(intel_sdvo_connector))
2812 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2813 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2814 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2815 else
2816 return true;
e957d772
CW		 2817}
2818
2819static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2820 struct i2c_msg *msgs,
2821 int num)
2822{
2823 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2824
e957d772
CW		 2825 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2826 return -EIO;
2827
2828 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2829}
2830
2831static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2832{
2833 struct intel_sdvo *sdvo = adapter->algo_data;
2834 return sdvo->i2c->algo->functionality(sdvo->i2c);
2835}
2836
2837static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2838 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2839 .functionality = intel_sdvo_ddc_proxy_func
2840};
2841
2842static bool
2843intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2844 struct drm_device *dev)
2845{
2846 sdvo->ddc.owner = THIS_MODULE;
2847 sdvo->ddc.class = I2C_CLASS_DDC;
2848 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2849 sdvo->ddc.dev.parent = &dev->pdev->dev;
2850 sdvo->ddc.algo_data = sdvo;
2851 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2852
2853 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2854}
2855
eef4eacb 2856bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2857{
b01f2c3a 2858 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2859 struct intel_encoder *intel_encoder;
ea5b213a 2860 struct intel_sdvo *intel_sdvo;
79e53945 2861 int i;
ea5b213a
CW		 2862 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2863 if (!intel_sdvo)
7d57382e 2864 return false;
79e53945 2865
56184e3d 2866 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2867 intel_sdvo->is_sdvob = is_sdvob;
2868 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2869 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2870 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2871 goto err_i2c_bus;
e957d772 2872
56184e3d 2873 /* encoder type will be decided later */
ea5b213a 2874 intel_encoder = &intel_sdvo->base;
21d40d37 2875 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2876 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2877
79e53945
JB		 2878 /* Read the regs to test if we can talk to the device */
2879 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2880 u8 byte;
2881
2882 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2883 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2884 SDVO_NAME(intel_sdvo));
f899fc64 2885 goto err;
79e53945
JB		 2886 }
2887 }
2888
6cc5f341 2889 intel_encoder->compute_config = intel_sdvo_compute_config;
ce22c320 2890 intel_encoder->disable = intel_disable_sdvo;
6cc5f341 2891 intel_encoder->mode_set = intel_sdvo_mode_set;
ce22c320 2892 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2893 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 2894 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 2895
af901ca1 2896 /* In default case sdvo lvds is false */
32aad86f 2897 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2898 goto err;
79e53945 2899
ea5b213a
CW		 2900 if (intel_sdvo_output_setup(intel_sdvo,
2901 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2902 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2903 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 2904 /* Output_setup can leave behind connectors! */
2905 goto err_output;
79e53945
JB		 2906 }
2907
7ba220ce
CW		 2908 /* Only enable the hotplug irq if we need it, to work around noisy
2909 * hotplug lines.
2910 */
2911 if (intel_sdvo->hotplug_active) {
2912 intel_encoder->hpd_pin =
2913 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
2914 }
2915
e506d6fd
DV		 2916 /*
2917 * Cloning SDVO with anything is often impossible, since the SDVO
2918 * encoder can request a special input timing mode. And even if that's
2919 * not the case we have evidence that cloning a plain unscaled mode with
2920 * VGA doesn't really work. Furthermore the cloning flags are way too
2921 * simplistic anyway to express such constraints, so just give up on
2922 * cloning for SDVO encoders.
2923 */
2924 intel_sdvo->base.cloneable = false;
2925
ea5b213a 2926 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2927
79e53945 2928 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2929 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 2930 goto err_output;
79e53945 2931
32aad86f
CW		 2932 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2933 &intel_sdvo->pixel_clock_min,
2934 &intel_sdvo->pixel_clock_max))
d0ddfbd3 2935 goto err_output;
79e53945 2936
8a4c47f3 2937 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2938 "clock range %dMHz - %dMHz, "
2939 "input 1: %c, input 2: %c, "
2940 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2941 SDVO_NAME(intel_sdvo),
2942 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2943 intel_sdvo->caps.device_rev_id,
2944 intel_sdvo->pixel_clock_min / 1000,
2945 intel_sdvo->pixel_clock_max / 1000,
2946 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2947 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2948 /* check currently supported outputs */
ea5b213a 2949 intel_sdvo->caps.output_flags &
79e53945 2950 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2951 intel_sdvo->caps.output_flags &
79e53945 2952 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2953 return true;
79e53945 2954
d0ddfbd3
JN		 2955err_output:
2956 intel_sdvo_output_cleanup(intel_sdvo);
2957
f899fc64 2958err:
373a3cf7 2959 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2960 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2961err_i2c_bus:
2962 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2963 kfree(intel_sdvo);
79e53945 2964
7d57382e 2965 return false;
79e53945 2966}
Linux kernel - Deliverables
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