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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
79e53945 | 30 | #include <linux/delay.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 | 32 | #include <drm/drmP.h> |
c6f95f27 | 33 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
34 | #include <drm/drm_crtc.h> |
35 | #include <drm/drm_edid.h> | |
ea5b213a | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 JB |
38 | #include "i915_drv.h" |
39 | #include "intel_sdvo_regs.h" | |
40 | ||
14571b4c ZW |
41 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
42 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) | |
43 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) | |
a0b1c7a5 | 44 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
14571b4c ZW |
45 | |
46 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ | |
0206e353 | 47 | SDVO_TV_MASK) |
14571b4c ZW |
48 | |
49 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) | |
13946743 | 50 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
14571b4c | 51 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
32aad86f | 52 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
52220085 | 53 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
14571b4c | 54 | |
79e53945 | 55 | |
4d9194de | 56 | static const char * const tv_format_names[] = { |
ce6feabd ZY |
57 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
58 | "PAL_B" , "PAL_D" , "PAL_G" , | |
59 | "PAL_H" , "PAL_I" , "PAL_M" , | |
60 | "PAL_N" , "PAL_NC" , "PAL_60" , | |
61 | "SECAM_B" , "SECAM_D" , "SECAM_G" , | |
62 | "SECAM_K" , "SECAM_K1", "SECAM_L" , | |
63 | "SECAM_60" | |
64 | }; | |
65 | ||
53abb679 | 66 | #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) |
ce6feabd | 67 | |
ea5b213a CW |
68 | struct intel_sdvo { |
69 | struct intel_encoder base; | |
70 | ||
f899fc64 | 71 | struct i2c_adapter *i2c; |
f9c10a9b | 72 | u8 slave_addr; |
e2f0ba97 | 73 | |
e957d772 CW |
74 | struct i2c_adapter ddc; |
75 | ||
e2f0ba97 | 76 | /* Register for the SDVO device: SDVOB or SDVOC */ |
f0f59a00 | 77 | i915_reg_t sdvo_reg; |
79e53945 | 78 | |
e2f0ba97 JB |
79 | /* Active outputs controlled by this SDVO output */ |
80 | uint16_t controlled_output; | |
79e53945 | 81 | |
e2f0ba97 JB |
82 | /* |
83 | * Capabilities of the SDVO device returned by | |
19d415a2 | 84 | * intel_sdvo_get_capabilities() |
e2f0ba97 | 85 | */ |
79e53945 | 86 | struct intel_sdvo_caps caps; |
e2f0ba97 JB |
87 | |
88 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
79e53945 JB |
89 | int pixel_clock_min, pixel_clock_max; |
90 | ||
fb7a46f3 | 91 | /* |
92 | * For multiple function SDVO device, | |
93 | * this is for current attached outputs. | |
94 | */ | |
95 | uint16_t attached_output; | |
96 | ||
cc68c81a SF |
97 | /* |
98 | * Hotplug activation bits for this device | |
99 | */ | |
5fa7ac9c | 100 | uint16_t hotplug_active; |
cc68c81a | 101 | |
e953fd7b CW |
102 | /** |
103 | * This is used to select the color range of RBG outputs in HDMI mode. | |
104 | * It is only valid when using TMDS encoding and 8 bit per color mode. | |
105 | */ | |
106 | uint32_t color_range; | |
55bc60db | 107 | bool color_range_auto; |
e953fd7b | 108 | |
7949dd47 VS |
109 | /** |
110 | * HDMI user specified aspect ratio | |
111 | */ | |
112 | enum hdmi_picture_aspect aspect_ratio; | |
113 | ||
e2f0ba97 JB |
114 | /** |
115 | * This is set if we're going to treat the device as TV-out. | |
116 | * | |
117 | * While we have these nice friendly flags for output types that ought | |
118 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
119 | * shows up as RGB1 (VGA). | |
120 | */ | |
121 | bool is_tv; | |
122 | ||
2a5c0832 | 123 | enum port port; |
eef4eacb | 124 | |
ce6feabd | 125 | /* This is for current tv format name */ |
40039750 | 126 | int tv_format_index; |
ce6feabd | 127 | |
e2f0ba97 JB |
128 | /** |
129 | * This is set if we treat the device as HDMI, instead of DVI. | |
130 | */ | |
131 | bool is_hdmi; | |
da79de97 CW |
132 | bool has_hdmi_monitor; |
133 | bool has_hdmi_audio; | |
abedc077 | 134 | bool rgb_quant_range_selectable; |
12682a97 | 135 | |
7086c87f | 136 | /** |
6c9547ff CW |
137 | * This is set if we detect output of sdvo device as LVDS and |
138 | * have a valid fixed mode to use with the panel. | |
7086c87f ML |
139 | */ |
140 | bool is_lvds; | |
e2f0ba97 | 141 | |
12682a97 | 142 | /** |
143 | * This is sdvo fixed pannel mode pointer | |
144 | */ | |
145 | struct drm_display_mode *sdvo_lvds_fixed_mode; | |
146 | ||
c751ce4f | 147 | /* DDC bus used by this SDVO encoder */ |
e2f0ba97 | 148 | uint8_t ddc_bus; |
e751823d EE |
149 | |
150 | /* | |
151 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd | |
152 | */ | |
153 | uint8_t dtd_sdvo_flags; | |
14571b4c ZW |
154 | }; |
155 | ||
156 | struct intel_sdvo_connector { | |
615fb93f CW |
157 | struct intel_connector base; |
158 | ||
14571b4c ZW |
159 | /* Mark the type of connector */ |
160 | uint16_t output_flag; | |
161 | ||
c3e5f67b | 162 | enum hdmi_force_audio force_audio; |
7f36e7ed | 163 | |
14571b4c | 164 | /* This contains all current supported TV format */ |
40039750 | 165 | u8 tv_format_supported[TV_FORMAT_NUM]; |
14571b4c | 166 | int format_supported_num; |
c5521706 | 167 | struct drm_property *tv_format; |
14571b4c | 168 | |
b9219c5e | 169 | /* add the property for the SDVO-TV */ |
c5521706 CW |
170 | struct drm_property *left; |
171 | struct drm_property *right; | |
172 | struct drm_property *top; | |
173 | struct drm_property *bottom; | |
174 | struct drm_property *hpos; | |
175 | struct drm_property *vpos; | |
176 | struct drm_property *contrast; | |
177 | struct drm_property *saturation; | |
178 | struct drm_property *hue; | |
179 | struct drm_property *sharpness; | |
180 | struct drm_property *flicker_filter; | |
181 | struct drm_property *flicker_filter_adaptive; | |
182 | struct drm_property *flicker_filter_2d; | |
183 | struct drm_property *tv_chroma_filter; | |
184 | struct drm_property *tv_luma_filter; | |
e044218a | 185 | struct drm_property *dot_crawl; |
b9219c5e ZY |
186 | |
187 | /* add the property for the SDVO-TV/LVDS */ | |
c5521706 | 188 | struct drm_property *brightness; |
b9219c5e ZY |
189 | |
190 | /* Add variable to record current setting for the above property */ | |
191 | u32 left_margin, right_margin, top_margin, bottom_margin; | |
c5521706 | 192 | |
b9219c5e ZY |
193 | /* this is to get the range of margin.*/ |
194 | u32 max_hscan, max_vscan; | |
195 | u32 max_hpos, cur_hpos; | |
196 | u32 max_vpos, cur_vpos; | |
197 | u32 cur_brightness, max_brightness; | |
198 | u32 cur_contrast, max_contrast; | |
199 | u32 cur_saturation, max_saturation; | |
200 | u32 cur_hue, max_hue; | |
c5521706 CW |
201 | u32 cur_sharpness, max_sharpness; |
202 | u32 cur_flicker_filter, max_flicker_filter; | |
203 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; | |
204 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; | |
205 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; | |
206 | u32 cur_tv_luma_filter, max_tv_luma_filter; | |
e044218a | 207 | u32 cur_dot_crawl, max_dot_crawl; |
79e53945 JB |
208 | }; |
209 | ||
8aca63aa | 210 | static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) |
ea5b213a | 211 | { |
8aca63aa | 212 | return container_of(encoder, struct intel_sdvo, base); |
ea5b213a CW |
213 | } |
214 | ||
df0e9248 CW |
215 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
216 | { | |
8aca63aa | 217 | return to_sdvo(intel_attached_encoder(connector)); |
df0e9248 CW |
218 | } |
219 | ||
615fb93f CW |
220 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
221 | { | |
222 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); | |
223 | } | |
224 | ||
fb7a46f3 | 225 | static bool |
ea5b213a | 226 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
32aad86f CW |
227 | static bool |
228 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | |
229 | struct intel_sdvo_connector *intel_sdvo_connector, | |
230 | int type); | |
231 | static bool | |
232 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, | |
233 | struct intel_sdvo_connector *intel_sdvo_connector); | |
fb7a46f3 | 234 | |
79e53945 JB |
235 | /** |
236 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
237 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
238 | * comments in the BIOS). | |
239 | */ | |
ea5b213a | 240 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
79e53945 | 241 | { |
4ef69c7a | 242 | struct drm_device *dev = intel_sdvo->base.base.dev; |
fac5e23e | 243 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 JB |
244 | u32 bval = val, cval = val; |
245 | int i; | |
246 | ||
2a5c0832 | 247 | if (HAS_PCH_SPLIT(dev_priv)) { |
ea5b213a | 248 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
abab6311 | 249 | POSTING_READ(intel_sdvo->sdvo_reg); |
e8504ee2 VS |
250 | /* |
251 | * HW workaround, need to write this twice for issue | |
252 | * that may result in first write getting masked. | |
253 | */ | |
254 | if (HAS_PCH_IBX(dev)) { | |
255 | I915_WRITE(intel_sdvo->sdvo_reg, val); | |
256 | POSTING_READ(intel_sdvo->sdvo_reg); | |
257 | } | |
461ed3ca ZY |
258 | return; |
259 | } | |
260 | ||
2a5c0832 | 261 | if (intel_sdvo->port == PORT_B) |
e2debe91 PZ |
262 | cval = I915_READ(GEN3_SDVOC); |
263 | else | |
264 | bval = I915_READ(GEN3_SDVOB); | |
265 | ||
79e53945 JB |
266 | /* |
267 | * Write the registers twice for luck. Sometimes, | |
268 | * writing them only once doesn't appear to 'stick'. | |
269 | * The BIOS does this too. Yay, magic | |
270 | */ | |
271 | for (i = 0; i < 2; i++) | |
272 | { | |
e2debe91 | 273 | I915_WRITE(GEN3_SDVOB, bval); |
abab6311 | 274 | POSTING_READ(GEN3_SDVOB); |
e2debe91 | 275 | I915_WRITE(GEN3_SDVOC, cval); |
abab6311 | 276 | POSTING_READ(GEN3_SDVOC); |
79e53945 JB |
277 | } |
278 | } | |
279 | ||
32aad86f | 280 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
79e53945 | 281 | { |
79e53945 JB |
282 | struct i2c_msg msgs[] = { |
283 | { | |
e957d772 | 284 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
285 | .flags = 0, |
286 | .len = 1, | |
e957d772 | 287 | .buf = &addr, |
79e53945 JB |
288 | }, |
289 | { | |
e957d772 | 290 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
291 | .flags = I2C_M_RD, |
292 | .len = 1, | |
e957d772 | 293 | .buf = ch, |
79e53945 JB |
294 | } |
295 | }; | |
32aad86f | 296 | int ret; |
79e53945 | 297 | |
f899fc64 | 298 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
79e53945 | 299 | return true; |
79e53945 | 300 | |
8a4c47f3 | 301 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
79e53945 JB |
302 | return false; |
303 | } | |
304 | ||
79e53945 JB |
305 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
306 | /** Mapping of command numbers to names, for debug output */ | |
005568be | 307 | static const struct _sdvo_cmd_name { |
e2f0ba97 | 308 | u8 cmd; |
2e88e40b | 309 | const char *name; |
79e53945 | 310 | } sdvo_cmd_names[] = { |
0206e353 AJ |
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), | |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), | |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), | |
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
354 | ||
355 | /* Add the op code for SDVO enhancements */ | |
356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), | |
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), | |
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), | |
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), | |
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), | |
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), | |
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), | |
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), | |
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), | |
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), | |
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), | |
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), | |
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), | |
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), | |
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), | |
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), | |
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), | |
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), | |
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), | |
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), | |
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), | |
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), | |
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), | |
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), | |
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), | |
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), | |
382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), | |
383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), | |
384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), | |
385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), | |
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), | |
387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), | |
388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), | |
389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), | |
390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), | |
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), | |
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), | |
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), | |
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), | |
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), | |
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), | |
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), | |
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), | |
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), | |
400 | ||
401 | /* HDMI op code */ | |
402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
409 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
410 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
411 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
412 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
413 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
414 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
415 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
416 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
417 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
418 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
419 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
420 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
421 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
79e53945 JB |
422 | }; |
423 | ||
2a5c0832 | 424 | #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") |
79e53945 | 425 | |
ea5b213a | 426 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
32aad86f | 427 | const void *args, int args_len) |
79e53945 | 428 | { |
84fcb469 DV |
429 | int i, pos = 0; |
430 | #define BUF_LEN 256 | |
431 | char buffer[BUF_LEN]; | |
432 | ||
433 | #define BUF_PRINT(args...) \ | |
434 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) | |
435 | ||
79e53945 | 436 | |
84fcb469 DV |
437 | for (i = 0; i < args_len; i++) { |
438 | BUF_PRINT("%02X ", ((u8 *)args)[i]); | |
439 | } | |
440 | for (; i < 8; i++) { | |
441 | BUF_PRINT(" "); | |
442 | } | |
04ad327f | 443 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
79e53945 | 444 | if (cmd == sdvo_cmd_names[i].cmd) { |
84fcb469 | 445 | BUF_PRINT("(%s)", sdvo_cmd_names[i].name); |
79e53945 JB |
446 | break; |
447 | } | |
448 | } | |
84fcb469 DV |
449 | if (i == ARRAY_SIZE(sdvo_cmd_names)) { |
450 | BUF_PRINT("(%02X)", cmd); | |
451 | } | |
452 | BUG_ON(pos >= BUF_LEN - 1); | |
453 | #undef BUF_PRINT | |
454 | #undef BUF_LEN | |
455 | ||
456 | DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); | |
79e53945 | 457 | } |
79e53945 | 458 | |
4d9194de | 459 | static const char * const cmd_status_names[] = { |
e957d772 CW |
460 | "Power on", |
461 | "Success", | |
462 | "Not supported", | |
463 | "Invalid arg", | |
464 | "Pending", | |
465 | "Target not specified", | |
466 | "Scaling not supported" | |
467 | }; | |
468 | ||
32aad86f CW |
469 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
470 | const void *args, int args_len) | |
79e53945 | 471 | { |
3bf3f452 BW |
472 | u8 *buf, status; |
473 | struct i2c_msg *msgs; | |
474 | int i, ret = true; | |
475 | ||
0274df3e | 476 | /* Would be simpler to allocate both in one go ? */ |
5c67eeb6 | 477 | buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); |
3bf3f452 BW |
478 | if (!buf) |
479 | return false; | |
480 | ||
481 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); | |
0274df3e AC |
482 | if (!msgs) { |
483 | kfree(buf); | |
3bf3f452 | 484 | return false; |
0274df3e | 485 | } |
79e53945 | 486 | |
ea5b213a | 487 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
79e53945 JB |
488 | |
489 | for (i = 0; i < args_len; i++) { | |
e957d772 CW |
490 | msgs[i].addr = intel_sdvo->slave_addr; |
491 | msgs[i].flags = 0; | |
492 | msgs[i].len = 2; | |
493 | msgs[i].buf = buf + 2 *i; | |
494 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; | |
495 | buf[2*i + 1] = ((u8*)args)[i]; | |
496 | } | |
497 | msgs[i].addr = intel_sdvo->slave_addr; | |
498 | msgs[i].flags = 0; | |
499 | msgs[i].len = 2; | |
500 | msgs[i].buf = buf + 2*i; | |
501 | buf[2*i + 0] = SDVO_I2C_OPCODE; | |
502 | buf[2*i + 1] = cmd; | |
503 | ||
504 | /* the following two are to read the response */ | |
505 | status = SDVO_I2C_CMD_STATUS; | |
506 | msgs[i+1].addr = intel_sdvo->slave_addr; | |
507 | msgs[i+1].flags = 0; | |
508 | msgs[i+1].len = 1; | |
509 | msgs[i+1].buf = &status; | |
510 | ||
511 | msgs[i+2].addr = intel_sdvo->slave_addr; | |
512 | msgs[i+2].flags = I2C_M_RD; | |
513 | msgs[i+2].len = 1; | |
514 | msgs[i+2].buf = &status; | |
515 | ||
516 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); | |
517 | if (ret < 0) { | |
518 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); | |
3bf3f452 BW |
519 | ret = false; |
520 | goto out; | |
e957d772 CW |
521 | } |
522 | if (ret != i+3) { | |
523 | /* failure in I2C transfer */ | |
524 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); | |
3bf3f452 | 525 | ret = false; |
e957d772 CW |
526 | } |
527 | ||
3bf3f452 BW |
528 | out: |
529 | kfree(msgs); | |
530 | kfree(buf); | |
531 | return ret; | |
79e53945 JB |
532 | } |
533 | ||
b5c616a7 CW |
534 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
535 | void *response, int response_len) | |
79e53945 | 536 | { |
fc37381c | 537 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
b5c616a7 | 538 | u8 status; |
84fcb469 DV |
539 | int i, pos = 0; |
540 | #define BUF_LEN 256 | |
541 | char buffer[BUF_LEN]; | |
79e53945 | 542 | |
d121a5d2 | 543 | |
b5c616a7 CW |
544 | /* |
545 | * The documentation states that all commands will be | |
546 | * processed within 15µs, and that we need only poll | |
547 | * the status byte a maximum of 3 times in order for the | |
548 | * command to be complete. | |
549 | * | |
550 | * Check 5 times in case the hardware failed to read the docs. | |
fc37381c CW |
551 | * |
552 | * Also beware that the first response by many devices is to | |
553 | * reply PENDING and stall for time. TVs are notorious for | |
554 | * requiring longer than specified to complete their replies. | |
555 | * Originally (in the DDX long ago), the delay was only ever 15ms | |
556 | * with an additional delay of 30ms applied for TVs added later after | |
557 | * many experiments. To accommodate both sets of delays, we do a | |
558 | * sequence of slow checks if the device is falling behind and fails | |
559 | * to reply within 5*15µs. | |
b5c616a7 | 560 | */ |
d121a5d2 CW |
561 | if (!intel_sdvo_read_byte(intel_sdvo, |
562 | SDVO_I2C_CMD_STATUS, | |
563 | &status)) | |
564 | goto log_fail; | |
565 | ||
1ad87e72 | 566 | while ((status == SDVO_CMD_STATUS_PENDING || |
46a3f4a3 | 567 | status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { |
fc37381c CW |
568 | if (retry < 10) |
569 | msleep(15); | |
570 | else | |
571 | udelay(15); | |
572 | ||
b5c616a7 CW |
573 | if (!intel_sdvo_read_byte(intel_sdvo, |
574 | SDVO_I2C_CMD_STATUS, | |
575 | &status)) | |
d121a5d2 CW |
576 | goto log_fail; |
577 | } | |
b5c616a7 | 578 | |
84fcb469 DV |
579 | #define BUF_PRINT(args...) \ |
580 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) | |
581 | ||
79e53945 | 582 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
84fcb469 | 583 | BUF_PRINT("(%s)", cmd_status_names[status]); |
79e53945 | 584 | else |
84fcb469 | 585 | BUF_PRINT("(??? %d)", status); |
79e53945 | 586 | |
b5c616a7 CW |
587 | if (status != SDVO_CMD_STATUS_SUCCESS) |
588 | goto log_fail; | |
79e53945 | 589 | |
b5c616a7 CW |
590 | /* Read the command response */ |
591 | for (i = 0; i < response_len; i++) { | |
592 | if (!intel_sdvo_read_byte(intel_sdvo, | |
593 | SDVO_I2C_RETURN_0 + i, | |
594 | &((u8 *)response)[i])) | |
595 | goto log_fail; | |
84fcb469 | 596 | BUF_PRINT(" %02X", ((u8 *)response)[i]); |
b5c616a7 | 597 | } |
84fcb469 DV |
598 | BUG_ON(pos >= BUF_LEN - 1); |
599 | #undef BUF_PRINT | |
600 | #undef BUF_LEN | |
601 | ||
602 | DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); | |
b5c616a7 | 603 | return true; |
79e53945 | 604 | |
b5c616a7 | 605 | log_fail: |
84fcb469 | 606 | DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); |
b5c616a7 | 607 | return false; |
79e53945 JB |
608 | } |
609 | ||
5e7234c9 | 610 | static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) |
79e53945 | 611 | { |
aad941d5 | 612 | if (adjusted_mode->crtc_clock >= 100000) |
79e53945 | 613 | return 1; |
aad941d5 | 614 | else if (adjusted_mode->crtc_clock >= 50000) |
79e53945 JB |
615 | return 2; |
616 | else | |
617 | return 4; | |
618 | } | |
619 | ||
e957d772 CW |
620 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
621 | u8 ddc_bus) | |
79e53945 | 622 | { |
d121a5d2 | 623 | /* This must be the immediately preceding write before the i2c xfer */ |
e957d772 CW |
624 | return intel_sdvo_write_cmd(intel_sdvo, |
625 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, | |
626 | &ddc_bus, 1); | |
79e53945 JB |
627 | } |
628 | ||
32aad86f | 629 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
79e53945 | 630 | { |
d121a5d2 CW |
631 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
632 | return false; | |
633 | ||
634 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); | |
32aad86f | 635 | } |
79e53945 | 636 | |
32aad86f CW |
637 | static bool |
638 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) | |
639 | { | |
640 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) | |
641 | return false; | |
79e53945 | 642 | |
32aad86f CW |
643 | return intel_sdvo_read_response(intel_sdvo, value, len); |
644 | } | |
79e53945 | 645 | |
32aad86f CW |
646 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
647 | { | |
648 | struct intel_sdvo_set_target_input_args targets = {0}; | |
649 | return intel_sdvo_set_value(intel_sdvo, | |
650 | SDVO_CMD_SET_TARGET_INPUT, | |
651 | &targets, sizeof(targets)); | |
79e53945 JB |
652 | } |
653 | ||
654 | /** | |
655 | * Return whether each input is trained. | |
656 | * | |
657 | * This function is making an assumption about the layout of the response, | |
658 | * which should be checked against the docs. | |
659 | */ | |
ea5b213a | 660 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
79e53945 JB |
661 | { |
662 | struct intel_sdvo_get_trained_inputs_response response; | |
79e53945 | 663 | |
1a3665c8 | 664 | BUILD_BUG_ON(sizeof(response) != 1); |
32aad86f CW |
665 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
666 | &response, sizeof(response))) | |
79e53945 JB |
667 | return false; |
668 | ||
669 | *input_1 = response.input0_trained; | |
670 | *input_2 = response.input1_trained; | |
671 | return true; | |
672 | } | |
673 | ||
ea5b213a | 674 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
675 | u16 outputs) |
676 | { | |
32aad86f CW |
677 | return intel_sdvo_set_value(intel_sdvo, |
678 | SDVO_CMD_SET_ACTIVE_OUTPUTS, | |
679 | &outputs, sizeof(outputs)); | |
79e53945 JB |
680 | } |
681 | ||
4ac41f47 DV |
682 | static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
683 | u16 *outputs) | |
684 | { | |
685 | return intel_sdvo_get_value(intel_sdvo, | |
686 | SDVO_CMD_GET_ACTIVE_OUTPUTS, | |
687 | outputs, sizeof(*outputs)); | |
688 | } | |
689 | ||
ea5b213a | 690 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
691 | int mode) |
692 | { | |
32aad86f | 693 | u8 state = SDVO_ENCODER_STATE_ON; |
79e53945 JB |
694 | |
695 | switch (mode) { | |
696 | case DRM_MODE_DPMS_ON: | |
697 | state = SDVO_ENCODER_STATE_ON; | |
698 | break; | |
699 | case DRM_MODE_DPMS_STANDBY: | |
700 | state = SDVO_ENCODER_STATE_STANDBY; | |
701 | break; | |
702 | case DRM_MODE_DPMS_SUSPEND: | |
703 | state = SDVO_ENCODER_STATE_SUSPEND; | |
704 | break; | |
705 | case DRM_MODE_DPMS_OFF: | |
706 | state = SDVO_ENCODER_STATE_OFF; | |
707 | break; | |
708 | } | |
709 | ||
32aad86f CW |
710 | return intel_sdvo_set_value(intel_sdvo, |
711 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); | |
79e53945 JB |
712 | } |
713 | ||
ea5b213a | 714 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
715 | int *clock_min, |
716 | int *clock_max) | |
717 | { | |
718 | struct intel_sdvo_pixel_clock_range clocks; | |
79e53945 | 719 | |
1a3665c8 | 720 | BUILD_BUG_ON(sizeof(clocks) != 4); |
32aad86f CW |
721 | if (!intel_sdvo_get_value(intel_sdvo, |
722 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
723 | &clocks, sizeof(clocks))) | |
79e53945 JB |
724 | return false; |
725 | ||
726 | /* Convert the values from units of 10 kHz to kHz. */ | |
727 | *clock_min = clocks.min * 10; | |
728 | *clock_max = clocks.max * 10; | |
79e53945 JB |
729 | return true; |
730 | } | |
731 | ||
ea5b213a | 732 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
733 | u16 outputs) |
734 | { | |
32aad86f CW |
735 | return intel_sdvo_set_value(intel_sdvo, |
736 | SDVO_CMD_SET_TARGET_OUTPUT, | |
737 | &outputs, sizeof(outputs)); | |
79e53945 JB |
738 | } |
739 | ||
ea5b213a | 740 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
79e53945 JB |
741 | struct intel_sdvo_dtd *dtd) |
742 | { | |
32aad86f CW |
743 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
744 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
79e53945 JB |
745 | } |
746 | ||
045ac3b5 JB |
747 | static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
748 | struct intel_sdvo_dtd *dtd) | |
749 | { | |
750 | return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && | |
751 | intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
752 | } | |
753 | ||
ea5b213a | 754 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
755 | struct intel_sdvo_dtd *dtd) |
756 | { | |
ea5b213a | 757 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
758 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
759 | } | |
760 | ||
ea5b213a | 761 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
762 | struct intel_sdvo_dtd *dtd) |
763 | { | |
ea5b213a | 764 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
765 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
766 | } | |
767 | ||
045ac3b5 JB |
768 | static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, |
769 | struct intel_sdvo_dtd *dtd) | |
770 | { | |
771 | return intel_sdvo_get_timing(intel_sdvo, | |
772 | SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); | |
773 | } | |
774 | ||
e2f0ba97 | 775 | static bool |
ea5b213a | 776 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
777 | uint16_t clock, |
778 | uint16_t width, | |
779 | uint16_t height) | |
780 | { | |
781 | struct intel_sdvo_preferred_input_timing_args args; | |
e2f0ba97 | 782 | |
e642c6f1 | 783 | memset(&args, 0, sizeof(args)); |
e2f0ba97 JB |
784 | args.clock = clock; |
785 | args.width = width; | |
786 | args.height = height; | |
e642c6f1 | 787 | args.interlace = 0; |
12682a97 | 788 | |
ea5b213a CW |
789 | if (intel_sdvo->is_lvds && |
790 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || | |
791 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) | |
12682a97 | 792 | args.scaled = 1; |
793 | ||
32aad86f CW |
794 | return intel_sdvo_set_value(intel_sdvo, |
795 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, | |
796 | &args, sizeof(args)); | |
e2f0ba97 JB |
797 | } |
798 | ||
ea5b213a | 799 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
800 | struct intel_sdvo_dtd *dtd) |
801 | { | |
1a3665c8 CW |
802 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
803 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); | |
32aad86f CW |
804 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
805 | &dtd->part1, sizeof(dtd->part1)) && | |
806 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
807 | &dtd->part2, sizeof(dtd->part2)); | |
e2f0ba97 | 808 | } |
79e53945 | 809 | |
ea5b213a | 810 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
79e53945 | 811 | { |
32aad86f | 812 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
79e53945 JB |
813 | } |
814 | ||
e2f0ba97 | 815 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
32aad86f | 816 | const struct drm_display_mode *mode) |
79e53945 | 817 | { |
e2f0ba97 JB |
818 | uint16_t width, height; |
819 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
820 | uint16_t h_sync_offset, v_sync_offset; | |
6651819b | 821 | int mode_clock; |
79e53945 | 822 | |
1c4a814e DV |
823 | memset(dtd, 0, sizeof(*dtd)); |
824 | ||
c6ebd4c0 DV |
825 | width = mode->hdisplay; |
826 | height = mode->vdisplay; | |
79e53945 JB |
827 | |
828 | /* do some mode translations */ | |
c6ebd4c0 DV |
829 | h_blank_len = mode->htotal - mode->hdisplay; |
830 | h_sync_len = mode->hsync_end - mode->hsync_start; | |
79e53945 | 831 | |
c6ebd4c0 DV |
832 | v_blank_len = mode->vtotal - mode->vdisplay; |
833 | v_sync_len = mode->vsync_end - mode->vsync_start; | |
79e53945 | 834 | |
c6ebd4c0 DV |
835 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
836 | v_sync_offset = mode->vsync_start - mode->vdisplay; | |
79e53945 | 837 | |
6651819b | 838 | mode_clock = mode->clock; |
6651819b DV |
839 | mode_clock /= 10; |
840 | dtd->part1.clock = mode_clock; | |
841 | ||
e2f0ba97 JB |
842 | dtd->part1.h_active = width & 0xff; |
843 | dtd->part1.h_blank = h_blank_len & 0xff; | |
844 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
79e53945 | 845 | ((h_blank_len >> 8) & 0xf); |
e2f0ba97 JB |
846 | dtd->part1.v_active = height & 0xff; |
847 | dtd->part1.v_blank = v_blank_len & 0xff; | |
848 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
79e53945 JB |
849 | ((v_blank_len >> 8) & 0xf); |
850 | ||
171a9e96 | 851 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
e2f0ba97 JB |
852 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
853 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
79e53945 | 854 | (v_sync_len & 0xf); |
e2f0ba97 | 855 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
79e53945 JB |
856 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
857 | ((v_sync_len & 0x30) >> 4); | |
858 | ||
e2f0ba97 | 859 | dtd->part2.dtd_flags = 0x18; |
59d92bfa DV |
860 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
861 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; | |
79e53945 | 862 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
59d92bfa | 863 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
79e53945 | 864 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
59d92bfa | 865 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
e2f0ba97 | 866 | |
e2f0ba97 | 867 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
e2f0ba97 JB |
868 | } |
869 | ||
1c4a814e | 870 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, |
32aad86f | 871 | const struct intel_sdvo_dtd *dtd) |
e2f0ba97 | 872 | { |
1c4a814e DV |
873 | struct drm_display_mode mode = {}; |
874 | ||
875 | mode.hdisplay = dtd->part1.h_active; | |
876 | mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
877 | mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; | |
878 | mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; | |
879 | mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; | |
880 | mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
881 | mode.htotal = mode.hdisplay + dtd->part1.h_blank; | |
882 | mode.htotal += (dtd->part1.h_high & 0xf) << 8; | |
883 | ||
884 | mode.vdisplay = dtd->part1.v_active; | |
885 | mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
886 | mode.vsync_start = mode.vdisplay; | |
887 | mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
888 | mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; | |
889 | mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; | |
890 | mode.vsync_end = mode.vsync_start + | |
e2f0ba97 | 891 | (dtd->part2.v_sync_off_width & 0xf); |
1c4a814e DV |
892 | mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
893 | mode.vtotal = mode.vdisplay + dtd->part1.v_blank; | |
894 | mode.vtotal += (dtd->part1.v_high & 0xf) << 8; | |
e2f0ba97 | 895 | |
1c4a814e | 896 | mode.clock = dtd->part1.clock * 10; |
e2f0ba97 | 897 | |
59d92bfa | 898 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
1c4a814e | 899 | mode.flags |= DRM_MODE_FLAG_INTERLACE; |
59d92bfa | 900 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
1c4a814e | 901 | mode.flags |= DRM_MODE_FLAG_PHSYNC; |
3cea210f | 902 | else |
1c4a814e | 903 | mode.flags |= DRM_MODE_FLAG_NHSYNC; |
59d92bfa | 904 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
1c4a814e | 905 | mode.flags |= DRM_MODE_FLAG_PVSYNC; |
3cea210f | 906 | else |
1c4a814e DV |
907 | mode.flags |= DRM_MODE_FLAG_NVSYNC; |
908 | ||
909 | drm_mode_set_crtcinfo(&mode, 0); | |
910 | ||
911 | drm_mode_copy(pmode, &mode); | |
e2f0ba97 JB |
912 | } |
913 | ||
e27d8538 | 914 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
e2f0ba97 | 915 | { |
e27d8538 | 916 | struct intel_sdvo_encode encode; |
e2f0ba97 | 917 | |
1a3665c8 | 918 | BUILD_BUG_ON(sizeof(encode) != 2); |
e27d8538 CW |
919 | return intel_sdvo_get_value(intel_sdvo, |
920 | SDVO_CMD_GET_SUPP_ENCODE, | |
921 | &encode, sizeof(encode)); | |
e2f0ba97 JB |
922 | } |
923 | ||
ea5b213a | 924 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
c751ce4f | 925 | uint8_t mode) |
e2f0ba97 | 926 | { |
32aad86f | 927 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
e2f0ba97 JB |
928 | } |
929 | ||
ea5b213a | 930 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
931 | uint8_t mode) |
932 | { | |
32aad86f | 933 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
e2f0ba97 JB |
934 | } |
935 | ||
936 | #if 0 | |
ea5b213a | 937 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
e2f0ba97 JB |
938 | { |
939 | int i, j; | |
940 | uint8_t set_buf_index[2]; | |
941 | uint8_t av_split; | |
942 | uint8_t buf_size; | |
943 | uint8_t buf[48]; | |
944 | uint8_t *pos; | |
945 | ||
32aad86f | 946 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
e2f0ba97 JB |
947 | |
948 | for (i = 0; i <= av_split; i++) { | |
949 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
c751ce4f | 950 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
e2f0ba97 | 951 | set_buf_index, 2); |
c751ce4f EA |
952 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
953 | intel_sdvo_read_response(encoder, &buf_size, 1); | |
e2f0ba97 JB |
954 | |
955 | pos = buf; | |
956 | for (j = 0; j <= buf_size; j += 8) { | |
c751ce4f | 957 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
e2f0ba97 | 958 | NULL, 0); |
c751ce4f | 959 | intel_sdvo_read_response(encoder, pos, 8); |
e2f0ba97 JB |
960 | pos += 8; |
961 | } | |
962 | } | |
963 | } | |
964 | #endif | |
965 | ||
b6e0e543 DV |
966 | static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
967 | unsigned if_index, uint8_t tx_rate, | |
fff63867 | 968 | const uint8_t *data, unsigned length) |
b6e0e543 DV |
969 | { |
970 | uint8_t set_buf_index[2] = { if_index, 0 }; | |
971 | uint8_t hbuf_size, tmp[8]; | |
972 | int i; | |
973 | ||
974 | if (!intel_sdvo_set_value(intel_sdvo, | |
975 | SDVO_CMD_SET_HBUF_INDEX, | |
976 | set_buf_index, 2)) | |
977 | return false; | |
978 | ||
979 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, | |
980 | &hbuf_size, 1)) | |
981 | return false; | |
982 | ||
983 | /* Buffer size is 0 based, hooray! */ | |
984 | hbuf_size++; | |
985 | ||
986 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", | |
987 | if_index, length, hbuf_size); | |
988 | ||
989 | for (i = 0; i < hbuf_size; i += 8) { | |
990 | memset(tmp, 0, 8); | |
991 | if (i < length) | |
992 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); | |
993 | ||
994 | if (!intel_sdvo_set_value(intel_sdvo, | |
995 | SDVO_CMD_SET_HBUF_DATA, | |
996 | tmp, 8)) | |
997 | return false; | |
998 | } | |
999 | ||
1000 | return intel_sdvo_set_value(intel_sdvo, | |
1001 | SDVO_CMD_SET_HBUF_TXRATE, | |
1002 | &tx_rate, 1); | |
1003 | } | |
1004 | ||
abedc077 VS |
1005 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
1006 | const struct drm_display_mode *adjusted_mode) | |
e2f0ba97 | 1007 | { |
15dcd350 DL |
1008 | uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; |
1009 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; | |
1010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1011 | union hdmi_infoframe frame; | |
1012 | int ret; | |
1013 | ssize_t len; | |
1014 | ||
1015 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, | |
1016 | adjusted_mode); | |
1017 | if (ret < 0) { | |
1018 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
1019 | return false; | |
1020 | } | |
3c17fe4b | 1021 | |
abedc077 | 1022 | if (intel_sdvo->rgb_quant_range_selectable) { |
6e3c9717 | 1023 | if (intel_crtc->config->limited_color_range) |
15dcd350 DL |
1024 | frame.avi.quantization_range = |
1025 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 1026 | else |
15dcd350 DL |
1027 | frame.avi.quantization_range = |
1028 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
1029 | } |
1030 | ||
15dcd350 DL |
1031 | len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); |
1032 | if (len < 0) | |
1033 | return false; | |
81014b9d | 1034 | |
b6e0e543 DV |
1035 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, |
1036 | SDVO_HBUF_TX_VSYNC, | |
1037 | sdvo_data, sizeof(sdvo_data)); | |
e2f0ba97 JB |
1038 | } |
1039 | ||
32aad86f | 1040 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
7026d4ac | 1041 | { |
ce6feabd | 1042 | struct intel_sdvo_tv_format format; |
40039750 | 1043 | uint32_t format_map; |
ce6feabd | 1044 | |
40039750 | 1045 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1046 | memset(&format, 0, sizeof(format)); |
32aad86f | 1047 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
ce6feabd | 1048 | |
32aad86f CW |
1049 | BUILD_BUG_ON(sizeof(format) != 6); |
1050 | return intel_sdvo_set_value(intel_sdvo, | |
1051 | SDVO_CMD_SET_TV_FORMAT, | |
1052 | &format, sizeof(format)); | |
7026d4ac ZW |
1053 | } |
1054 | ||
32aad86f CW |
1055 | static bool |
1056 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, | |
e811f5ae | 1057 | const struct drm_display_mode *mode) |
e2f0ba97 | 1058 | { |
32aad86f | 1059 | struct intel_sdvo_dtd output_dtd; |
79e53945 | 1060 | |
32aad86f CW |
1061 | if (!intel_sdvo_set_target_output(intel_sdvo, |
1062 | intel_sdvo->attached_output)) | |
1063 | return false; | |
e2f0ba97 | 1064 | |
32aad86f CW |
1065 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
1066 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) | |
1067 | return false; | |
e2f0ba97 | 1068 | |
32aad86f CW |
1069 | return true; |
1070 | } | |
1071 | ||
c9a29698 DV |
1072 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
1073 | * Unfortunately we have to set up the full output mode to do that. */ | |
32aad86f | 1074 | static bool |
c9a29698 | 1075 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
e811f5ae | 1076 | const struct drm_display_mode *mode, |
c9a29698 | 1077 | struct drm_display_mode *adjusted_mode) |
32aad86f | 1078 | { |
c9a29698 DV |
1079 | struct intel_sdvo_dtd input_dtd; |
1080 | ||
32aad86f CW |
1081 | /* Reset the input timing to the screen. Assume always input 0. */ |
1082 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
1083 | return false; | |
e2f0ba97 | 1084 | |
32aad86f CW |
1085 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
1086 | mode->clock / 10, | |
1087 | mode->hdisplay, | |
1088 | mode->vdisplay)) | |
1089 | return false; | |
e2f0ba97 | 1090 | |
32aad86f | 1091 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
c9a29698 | 1092 | &input_dtd)) |
32aad86f | 1093 | return false; |
e2f0ba97 | 1094 | |
c9a29698 | 1095 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
e751823d | 1096 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
79e53945 | 1097 | |
32aad86f CW |
1098 | return true; |
1099 | } | |
12682a97 | 1100 | |
5cec258b | 1101 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) |
70484559 | 1102 | { |
3c52f4eb | 1103 | unsigned dotclock = pipe_config->port_clock; |
70484559 DV |
1104 | struct dpll *clock = &pipe_config->dpll; |
1105 | ||
1106 | /* SDVO TV has fixed PLL values depend on its clock range, | |
1107 | this mirrors vbios setting. */ | |
1108 | if (dotclock >= 100000 && dotclock < 140500) { | |
1109 | clock->p1 = 2; | |
1110 | clock->p2 = 10; | |
1111 | clock->n = 3; | |
1112 | clock->m1 = 16; | |
1113 | clock->m2 = 8; | |
1114 | } else if (dotclock >= 140500 && dotclock <= 200000) { | |
1115 | clock->p1 = 1; | |
1116 | clock->p2 = 10; | |
1117 | clock->n = 6; | |
1118 | clock->m1 = 12; | |
1119 | clock->m2 = 8; | |
1120 | } else { | |
1121 | WARN(1, "SDVO TV clock out of range: %i\n", dotclock); | |
1122 | } | |
1123 | ||
1124 | pipe_config->clock_set = true; | |
1125 | } | |
1126 | ||
6cc5f341 | 1127 | static bool intel_sdvo_compute_config(struct intel_encoder *encoder, |
5cec258b | 1128 | struct intel_crtc_state *pipe_config) |
32aad86f | 1129 | { |
8aca63aa | 1130 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
2d112de7 ACO |
1131 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1132 | struct drm_display_mode *mode = &pipe_config->base.mode; | |
12682a97 | 1133 | |
5d2d38dd DV |
1134 | DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); |
1135 | pipe_config->pipe_bpp = 8*3; | |
1136 | ||
5bfe2ac0 DV |
1137 | if (HAS_PCH_SPLIT(encoder->base.dev)) |
1138 | pipe_config->has_pch_encoder = true; | |
1139 | ||
32aad86f CW |
1140 | /* We need to construct preferred input timings based on our |
1141 | * output timings. To do that, we have to set the output | |
1142 | * timings, even though this isn't really the right place in | |
1143 | * the sequence to do it. Oh well. | |
1144 | */ | |
1145 | if (intel_sdvo->is_tv) { | |
1146 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) | |
1147 | return false; | |
12682a97 | 1148 | |
c9a29698 DV |
1149 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1150 | mode, | |
1151 | adjusted_mode); | |
09ede541 | 1152 | pipe_config->sdvo_tv_clock = true; |
ea5b213a | 1153 | } else if (intel_sdvo->is_lvds) { |
32aad86f | 1154 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
6c9547ff | 1155 | intel_sdvo->sdvo_lvds_fixed_mode)) |
e2f0ba97 | 1156 | return false; |
12682a97 | 1157 | |
c9a29698 DV |
1158 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1159 | mode, | |
1160 | adjusted_mode); | |
e2f0ba97 | 1161 | } |
32aad86f CW |
1162 | |
1163 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
6c9547ff | 1164 | * SDVO device will factor out the multiplier during mode_set. |
32aad86f | 1165 | */ |
6cc5f341 DV |
1166 | pipe_config->pixel_multiplier = |
1167 | intel_sdvo_get_pixel_multiplier(adjusted_mode); | |
32aad86f | 1168 | |
9f04003e DV |
1169 | pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; |
1170 | ||
55bc60db VS |
1171 | if (intel_sdvo->color_range_auto) { |
1172 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
4f3a8bc7 PZ |
1173 | /* FIXME: This bit is only valid when using TMDS encoding and 8 |
1174 | * bit per color mode. */ | |
9f04003e | 1175 | if (pipe_config->has_hdmi_sink && |
18316c8c | 1176 | drm_match_cea_mode(adjusted_mode) > 1) |
69f5acc8 DV |
1177 | pipe_config->limited_color_range = true; |
1178 | } else { | |
9f04003e | 1179 | if (pipe_config->has_hdmi_sink && |
69f5acc8 DV |
1180 | intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) |
1181 | pipe_config->limited_color_range = true; | |
55bc60db VS |
1182 | } |
1183 | ||
70484559 DV |
1184 | /* Clock computation needs to happen after pixel multiplier. */ |
1185 | if (intel_sdvo->is_tv) | |
1186 | i9xx_adjust_sdvo_tv_clock(pipe_config); | |
1187 | ||
7949dd47 VS |
1188 | /* Set user selected PAR to incoming mode's member */ |
1189 | if (intel_sdvo->is_hdmi) | |
1190 | adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio; | |
1191 | ||
e2f0ba97 JB |
1192 | return true; |
1193 | } | |
1194 | ||
192d47a6 | 1195 | static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) |
e2f0ba97 | 1196 | { |
6cc5f341 | 1197 | struct drm_device *dev = intel_encoder->base.dev; |
fac5e23e | 1198 | struct drm_i915_private *dev_priv = to_i915(dev); |
eeb47937 | 1199 | struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); |
7c5f93b0 | 1200 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
6e3c9717 | 1201 | struct drm_display_mode *mode = &crtc->config->base.mode; |
8aca63aa | 1202 | struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); |
6c9547ff | 1203 | u32 sdvox; |
e2f0ba97 | 1204 | struct intel_sdvo_in_out_map in_out; |
6651819b | 1205 | struct intel_sdvo_dtd input_dtd, output_dtd; |
6c9547ff | 1206 | int rate; |
e2f0ba97 JB |
1207 | |
1208 | if (!mode) | |
1209 | return; | |
1210 | ||
1211 | /* First, set the input mapping for the first input to our controlled | |
1212 | * output. This is only correct if we're a single-input device, in | |
1213 | * which case the first input is the output from the appropriate SDVO | |
1214 | * channel on the motherboard. In a two-input device, the first input | |
1215 | * will be SDVOB and the second SDVOC. | |
1216 | */ | |
ea5b213a | 1217 | in_out.in0 = intel_sdvo->attached_output; |
e2f0ba97 JB |
1218 | in_out.in1 = 0; |
1219 | ||
c74696b9 PR |
1220 | intel_sdvo_set_value(intel_sdvo, |
1221 | SDVO_CMD_SET_IN_OUT_MAP, | |
1222 | &in_out, sizeof(in_out)); | |
e2f0ba97 | 1223 | |
6c9547ff CW |
1224 | /* Set the output timings to the screen */ |
1225 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1226 | intel_sdvo->attached_output)) | |
1227 | return; | |
e2f0ba97 | 1228 | |
6651819b DV |
1229 | /* lvds has a special fixed output timing. */ |
1230 | if (intel_sdvo->is_lvds) | |
1231 | intel_sdvo_get_dtd_from_mode(&output_dtd, | |
1232 | intel_sdvo->sdvo_lvds_fixed_mode); | |
1233 | else | |
1234 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); | |
c8d4bb54 DV |
1235 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
1236 | DRM_INFO("Setting output timings on %s failed\n", | |
1237 | SDVO_NAME(intel_sdvo)); | |
79e53945 JB |
1238 | |
1239 | /* Set the input timing to the screen. Assume always input 0. */ | |
32aad86f CW |
1240 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
1241 | return; | |
79e53945 | 1242 | |
6e3c9717 | 1243 | if (crtc->config->has_hdmi_sink) { |
97aaf910 CW |
1244 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
1245 | intel_sdvo_set_colorimetry(intel_sdvo, | |
1246 | SDVO_COLORIMETRY_RGB256); | |
abedc077 | 1247 | intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); |
97aaf910 CW |
1248 | } else |
1249 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); | |
7026d4ac | 1250 | |
6c9547ff CW |
1251 | if (intel_sdvo->is_tv && |
1252 | !intel_sdvo_set_tv_format(intel_sdvo)) | |
1253 | return; | |
e2f0ba97 | 1254 | |
6651819b | 1255 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
eeb47937 | 1256 | |
e751823d EE |
1257 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) |
1258 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; | |
c8d4bb54 DV |
1259 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
1260 | DRM_INFO("Setting input timings on %s failed\n", | |
1261 | SDVO_NAME(intel_sdvo)); | |
79e53945 | 1262 | |
6e3c9717 | 1263 | switch (crtc->config->pixel_multiplier) { |
6c9547ff | 1264 | default: |
fd0753cf | 1265 | WARN(1, "unknown pixel multiplier specified\n"); |
32aad86f CW |
1266 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
1267 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; | |
1268 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; | |
79e53945 | 1269 | } |
32aad86f CW |
1270 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
1271 | return; | |
79e53945 JB |
1272 | |
1273 | /* Set the SDVO control regs. */ | |
a6c45cf0 | 1274 | if (INTEL_INFO(dev)->gen >= 4) { |
ba68e086 PZ |
1275 | /* The real mode polarity is set by the SDVO commands, using |
1276 | * struct intel_sdvo_dtd. */ | |
1277 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; | |
6e3c9717 | 1278 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
69f5acc8 | 1279 | sdvox |= HDMI_COLOR_RANGE_16_235; |
6714afb1 CW |
1280 | if (INTEL_INFO(dev)->gen < 5) |
1281 | sdvox |= SDVO_BORDER_ENABLE; | |
e2f0ba97 | 1282 | } else { |
6c9547ff | 1283 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
2a5c0832 | 1284 | if (intel_sdvo->port == PORT_B) |
e2f0ba97 | 1285 | sdvox &= SDVOB_PRESERVE_MASK; |
2a5c0832 | 1286 | else |
e2f0ba97 | 1287 | sdvox &= SDVOC_PRESERVE_MASK; |
e2f0ba97 JB |
1288 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
1289 | } | |
3573c410 PZ |
1290 | |
1291 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) | |
eeb47937 | 1292 | sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
3573c410 | 1293 | else |
eeb47937 | 1294 | sdvox |= SDVO_PIPE_SEL(crtc->pipe); |
3573c410 | 1295 | |
da79de97 | 1296 | if (intel_sdvo->has_hdmi_audio) |
6c9547ff | 1297 | sdvox |= SDVO_AUDIO_ENABLE; |
79e53945 | 1298 | |
a6c45cf0 | 1299 | if (INTEL_INFO(dev)->gen >= 4) { |
e2f0ba97 JB |
1300 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1301 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1302 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
79e53945 | 1303 | } else { |
6e3c9717 | 1304 | sdvox |= (crtc->config->pixel_multiplier - 1) |
6cc5f341 | 1305 | << SDVO_PORT_MULTIPLY_SHIFT; |
79e53945 JB |
1306 | } |
1307 | ||
6714afb1 CW |
1308 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
1309 | INTEL_INFO(dev)->gen < 5) | |
12682a97 | 1310 | sdvox |= SDVO_STALL_SELECT; |
ea5b213a | 1311 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
79e53945 JB |
1312 | } |
1313 | ||
4ac41f47 | 1314 | static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
79e53945 | 1315 | { |
4ac41f47 DV |
1316 | struct intel_sdvo_connector *intel_sdvo_connector = |
1317 | to_intel_sdvo_connector(&connector->base); | |
1318 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); | |
2f28c50b | 1319 | u16 active_outputs = 0; |
4ac41f47 DV |
1320 | |
1321 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); | |
1322 | ||
1323 | if (active_outputs & intel_sdvo_connector->output_flag) | |
1324 | return true; | |
1325 | else | |
1326 | return false; | |
1327 | } | |
1328 | ||
1329 | static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, | |
1330 | enum pipe *pipe) | |
1331 | { | |
1332 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1333 | struct drm_i915_private *dev_priv = to_i915(dev); |
8aca63aa | 1334 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
2f28c50b | 1335 | u16 active_outputs = 0; |
4ac41f47 DV |
1336 | u32 tmp; |
1337 | ||
1338 | tmp = I915_READ(intel_sdvo->sdvo_reg); | |
7a7d1fb7 | 1339 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
4ac41f47 | 1340 | |
7a7d1fb7 | 1341 | if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) |
4ac41f47 DV |
1342 | return false; |
1343 | ||
1344 | if (HAS_PCH_CPT(dev)) | |
1345 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
1346 | else | |
1347 | *pipe = PORT_TO_PIPE(tmp); | |
1348 | ||
1349 | return true; | |
1350 | } | |
1351 | ||
045ac3b5 | 1352 | static void intel_sdvo_get_config(struct intel_encoder *encoder, |
5cec258b | 1353 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 1354 | { |
6c49f241 | 1355 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1356 | struct drm_i915_private *dev_priv = to_i915(dev); |
8aca63aa | 1357 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
045ac3b5 | 1358 | struct intel_sdvo_dtd dtd; |
6c49f241 | 1359 | int encoder_pixel_multiplier = 0; |
18442d08 | 1360 | int dotclock; |
6c49f241 DV |
1361 | u32 flags = 0, sdvox; |
1362 | u8 val; | |
045ac3b5 JB |
1363 | bool ret; |
1364 | ||
b5a9fa09 DV |
1365 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
1366 | ||
045ac3b5 JB |
1367 | ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); |
1368 | if (!ret) { | |
bb760063 DV |
1369 | /* Some sdvo encoders are not spec compliant and don't |
1370 | * implement the mandatory get_timings function. */ | |
045ac3b5 | 1371 | DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); |
bb760063 DV |
1372 | pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; |
1373 | } else { | |
1374 | if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) | |
1375 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1376 | else | |
1377 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1378 | |
bb760063 DV |
1379 | if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
1380 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1381 | else | |
1382 | flags |= DRM_MODE_FLAG_NVSYNC; | |
045ac3b5 JB |
1383 | } |
1384 | ||
2d112de7 | 1385 | pipe_config->base.adjusted_mode.flags |= flags; |
045ac3b5 | 1386 | |
fdafa9e2 DV |
1387 | /* |
1388 | * pixel multiplier readout is tricky: Only on i915g/gm it is stored in | |
1389 | * the sdvo port register, on all other platforms it is part of the dpll | |
1390 | * state. Since the general pipe state readout happens before the | |
1391 | * encoder->get_config we so already have a valid pixel multplier on all | |
1392 | * other platfroms. | |
1393 | */ | |
6c49f241 | 1394 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
6c49f241 DV |
1395 | pipe_config->pixel_multiplier = |
1396 | ((sdvox & SDVO_PORT_MULTIPLY_MASK) | |
1397 | >> SDVO_PORT_MULTIPLY_SHIFT) + 1; | |
1398 | } | |
045ac3b5 | 1399 | |
2b85886a | 1400 | dotclock = pipe_config->port_clock; |
e3b247da | 1401 | |
2b85886a VS |
1402 | if (pipe_config->pixel_multiplier) |
1403 | dotclock /= pipe_config->pixel_multiplier; | |
18442d08 | 1404 | |
2d112de7 | 1405 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
18442d08 | 1406 | |
6c49f241 | 1407 | /* Cross check the port pixel multiplier with the sdvo encoder state. */ |
53b91408 DL |
1408 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, |
1409 | &val, 1)) { | |
1410 | switch (val) { | |
1411 | case SDVO_CLOCK_RATE_MULT_1X: | |
1412 | encoder_pixel_multiplier = 1; | |
1413 | break; | |
1414 | case SDVO_CLOCK_RATE_MULT_2X: | |
1415 | encoder_pixel_multiplier = 2; | |
1416 | break; | |
1417 | case SDVO_CLOCK_RATE_MULT_4X: | |
1418 | encoder_pixel_multiplier = 4; | |
1419 | break; | |
1420 | } | |
6c49f241 | 1421 | } |
fdafa9e2 | 1422 | |
b5a9fa09 DV |
1423 | if (sdvox & HDMI_COLOR_RANGE_16_235) |
1424 | pipe_config->limited_color_range = true; | |
1425 | ||
9f04003e DV |
1426 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, |
1427 | &val, 1)) { | |
1428 | if (val == SDVO_ENCODE_HDMI) | |
1429 | pipe_config->has_hdmi_sink = true; | |
1430 | } | |
1431 | ||
6c49f241 DV |
1432 | WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, |
1433 | "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", | |
1434 | pipe_config->pixel_multiplier, encoder_pixel_multiplier); | |
045ac3b5 JB |
1435 | } |
1436 | ||
ce22c320 DV |
1437 | static void intel_disable_sdvo(struct intel_encoder *encoder) |
1438 | { | |
fac5e23e | 1439 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
8aca63aa | 1440 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
1612c8bd | 1441 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
ce22c320 DV |
1442 | u32 temp; |
1443 | ||
1444 | intel_sdvo_set_active_outputs(intel_sdvo, 0); | |
1445 | if (0) | |
1446 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1447 | DRM_MODE_DPMS_OFF); | |
1448 | ||
1449 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
776ca7cf | 1450 | |
1612c8bd VS |
1451 | temp &= ~SDVO_ENABLE; |
1452 | intel_sdvo_write_sdvox(intel_sdvo, temp); | |
1453 | ||
1454 | /* | |
1455 | * HW workaround for IBX, we need to move the port | |
1456 | * to transcoder A after disabling it to allow the | |
1457 | * matching DP port to be enabled on transcoder A. | |
1458 | */ | |
1459 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { | |
0c241d5b VS |
1460 | /* |
1461 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1462 | * doing the workaround. Sweep them under the rug. | |
1463 | */ | |
1464 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1465 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1466 | ||
1612c8bd VS |
1467 | temp &= ~SDVO_PIPE_B_SELECT; |
1468 | temp |= SDVO_ENABLE; | |
1469 | intel_sdvo_write_sdvox(intel_sdvo, temp); | |
1470 | ||
1471 | temp &= ~SDVO_ENABLE; | |
1472 | intel_sdvo_write_sdvox(intel_sdvo, temp); | |
0c241d5b | 1473 | |
91c8a326 | 1474 | intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); |
0c241d5b VS |
1475 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
1476 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
ce22c320 DV |
1477 | } |
1478 | } | |
1479 | ||
3c65d1d1 VS |
1480 | static void pch_disable_sdvo(struct intel_encoder *encoder) |
1481 | { | |
1482 | } | |
1483 | ||
1484 | static void pch_post_disable_sdvo(struct intel_encoder *encoder) | |
1485 | { | |
1486 | intel_disable_sdvo(encoder); | |
1487 | } | |
1488 | ||
ce22c320 DV |
1489 | static void intel_enable_sdvo(struct intel_encoder *encoder) |
1490 | { | |
1491 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1492 | struct drm_i915_private *dev_priv = to_i915(dev); |
8aca63aa | 1493 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
ce22c320 | 1494 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 1495 | u32 temp; |
ce22c320 DV |
1496 | bool input1, input2; |
1497 | int i; | |
d0a7b6de | 1498 | bool success; |
ce22c320 DV |
1499 | |
1500 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
3c65d1d1 VS |
1501 | temp |= SDVO_ENABLE; |
1502 | intel_sdvo_write_sdvox(intel_sdvo, temp); | |
776ca7cf | 1503 | |
ce22c320 DV |
1504 | for (i = 0; i < 2; i++) |
1505 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1506 | ||
d0a7b6de | 1507 | success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
ce22c320 DV |
1508 | /* Warn if the device reported failure to sync. |
1509 | * A lot of SDVO devices fail to notify of sync, but it's | |
1510 | * a given it the status is a success, we succeeded. | |
1511 | */ | |
d0a7b6de | 1512 | if (success && !input1) { |
ce22c320 DV |
1513 | DRM_DEBUG_KMS("First %s output reported failure to " |
1514 | "sync\n", SDVO_NAME(intel_sdvo)); | |
1515 | } | |
1516 | ||
1517 | if (0) | |
1518 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1519 | DRM_MODE_DPMS_ON); | |
1520 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
1521 | } | |
1522 | ||
c19de8eb DL |
1523 | static enum drm_mode_status |
1524 | intel_sdvo_mode_valid(struct drm_connector *connector, | |
1525 | struct drm_display_mode *mode) | |
79e53945 | 1526 | { |
df0e9248 | 1527 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
24b23882 | 1528 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
79e53945 JB |
1529 | |
1530 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1531 | return MODE_NO_DBLESCAN; | |
1532 | ||
ea5b213a | 1533 | if (intel_sdvo->pixel_clock_min > mode->clock) |
79e53945 JB |
1534 | return MODE_CLOCK_LOW; |
1535 | ||
ea5b213a | 1536 | if (intel_sdvo->pixel_clock_max < mode->clock) |
79e53945 JB |
1537 | return MODE_CLOCK_HIGH; |
1538 | ||
24b23882 MK |
1539 | if (mode->clock > max_dotclk) |
1540 | return MODE_CLOCK_HIGH; | |
1541 | ||
8545423a | 1542 | if (intel_sdvo->is_lvds) { |
ea5b213a | 1543 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
12682a97 | 1544 | return MODE_PANEL; |
1545 | ||
ea5b213a | 1546 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
12682a97 | 1547 | return MODE_PANEL; |
1548 | } | |
1549 | ||
79e53945 JB |
1550 | return MODE_OK; |
1551 | } | |
1552 | ||
ea5b213a | 1553 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
79e53945 | 1554 | { |
1a3665c8 | 1555 | BUILD_BUG_ON(sizeof(*caps) != 8); |
e957d772 CW |
1556 | if (!intel_sdvo_get_value(intel_sdvo, |
1557 | SDVO_CMD_GET_DEVICE_CAPS, | |
1558 | caps, sizeof(*caps))) | |
1559 | return false; | |
1560 | ||
1561 | DRM_DEBUG_KMS("SDVO capabilities:\n" | |
1562 | " vendor_id: %d\n" | |
1563 | " device_id: %d\n" | |
1564 | " device_rev_id: %d\n" | |
1565 | " sdvo_version_major: %d\n" | |
1566 | " sdvo_version_minor: %d\n" | |
1567 | " sdvo_inputs_mask: %d\n" | |
1568 | " smooth_scaling: %d\n" | |
1569 | " sharp_scaling: %d\n" | |
1570 | " up_scaling: %d\n" | |
1571 | " down_scaling: %d\n" | |
1572 | " stall_support: %d\n" | |
1573 | " output_flags: %d\n", | |
1574 | caps->vendor_id, | |
1575 | caps->device_id, | |
1576 | caps->device_rev_id, | |
1577 | caps->sdvo_version_major, | |
1578 | caps->sdvo_version_minor, | |
1579 | caps->sdvo_inputs_mask, | |
1580 | caps->smooth_scaling, | |
1581 | caps->sharp_scaling, | |
1582 | caps->up_scaling, | |
1583 | caps->down_scaling, | |
1584 | caps->stall_support, | |
1585 | caps->output_flags); | |
1586 | ||
1587 | return true; | |
79e53945 JB |
1588 | } |
1589 | ||
5fa7ac9c | 1590 | static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
79e53945 | 1591 | { |
768b107e | 1592 | struct drm_device *dev = intel_sdvo->base.base.dev; |
5fa7ac9c | 1593 | uint16_t hotplug; |
79e53945 | 1594 | |
1d83d957 VS |
1595 | if (!I915_HAS_HOTPLUG(dev)) |
1596 | return 0; | |
1597 | ||
768b107e DV |
1598 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
1599 | * on the line. */ | |
1600 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
5fa7ac9c | 1601 | return 0; |
768b107e | 1602 | |
5fa7ac9c JN |
1603 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
1604 | &hotplug, sizeof(hotplug))) | |
1605 | return 0; | |
768b107e | 1606 | |
5fa7ac9c | 1607 | return hotplug; |
79e53945 JB |
1608 | } |
1609 | ||
cc68c81a | 1610 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
79e53945 | 1611 | { |
8aca63aa | 1612 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
79e53945 | 1613 | |
5fa7ac9c JN |
1614 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, |
1615 | &intel_sdvo->hotplug_active, 2); | |
79e53945 JB |
1616 | } |
1617 | ||
fb7a46f3 | 1618 | static bool |
ea5b213a | 1619 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
fb7a46f3 | 1620 | { |
bc65212c | 1621 | /* Is there more than one type of output? */ |
2294488d | 1622 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
fb7a46f3 | 1623 | } |
1624 | ||
f899fc64 | 1625 | static struct edid * |
e957d772 | 1626 | intel_sdvo_get_edid(struct drm_connector *connector) |
f899fc64 | 1627 | { |
e957d772 CW |
1628 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
1629 | return drm_get_edid(connector, &sdvo->ddc); | |
f899fc64 CW |
1630 | } |
1631 | ||
ff482d83 CW |
1632 | /* Mac mini hack -- use the same DDC as the analog connector */ |
1633 | static struct edid * | |
1634 | intel_sdvo_get_analog_edid(struct drm_connector *connector) | |
1635 | { | |
fac5e23e | 1636 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
ff482d83 | 1637 | |
0c1dab89 | 1638 | return drm_get_edid(connector, |
3bd7d909 | 1639 | intel_gmbus_get_adapter(dev_priv, |
41aa3448 | 1640 | dev_priv->vbt.crt_ddc_pin)); |
ff482d83 CW |
1641 | } |
1642 | ||
c43b5634 | 1643 | static enum drm_connector_status |
8bf38485 | 1644 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
9dff6af8 | 1645 | { |
df0e9248 | 1646 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
9d1a903d CW |
1647 | enum drm_connector_status status; |
1648 | struct edid *edid; | |
9dff6af8 | 1649 | |
e957d772 | 1650 | edid = intel_sdvo_get_edid(connector); |
57cdaf90 | 1651 | |
ea5b213a | 1652 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
e957d772 | 1653 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
9d1a903d | 1654 | |
7c3f0a27 ZY |
1655 | /* |
1656 | * Don't use the 1 as the argument of DDC bus switch to get | |
1657 | * the EDID. It is used for SDVO SPD ROM. | |
1658 | */ | |
9d1a903d | 1659 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
e957d772 CW |
1660 | intel_sdvo->ddc_bus = ddc; |
1661 | edid = intel_sdvo_get_edid(connector); | |
1662 | if (edid) | |
7c3f0a27 | 1663 | break; |
7c3f0a27 | 1664 | } |
e957d772 CW |
1665 | /* |
1666 | * If we found the EDID on the other bus, | |
1667 | * assume that is the correct DDC bus. | |
1668 | */ | |
1669 | if (edid == NULL) | |
1670 | intel_sdvo->ddc_bus = saved_ddc; | |
7c3f0a27 | 1671 | } |
9d1a903d CW |
1672 | |
1673 | /* | |
1674 | * When there is no edid and no monitor is connected with VGA | |
1675 | * port, try to use the CRT ddc to read the EDID for DVI-connector. | |
57cdaf90 | 1676 | */ |
ff482d83 CW |
1677 | if (edid == NULL) |
1678 | edid = intel_sdvo_get_analog_edid(connector); | |
149c36a3 | 1679 | |
2f551c84 | 1680 | status = connector_status_unknown; |
9dff6af8 | 1681 | if (edid != NULL) { |
149c36a3 | 1682 | /* DDC bus is shared, match EDID to connector type */ |
9d1a903d CW |
1683 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
1684 | status = connector_status_connected; | |
da79de97 CW |
1685 | if (intel_sdvo->is_hdmi) { |
1686 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); | |
1687 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); | |
abedc077 VS |
1688 | intel_sdvo->rgb_quant_range_selectable = |
1689 | drm_rgb_quant_range_selectable(edid); | |
da79de97 | 1690 | } |
13946743 CW |
1691 | } else |
1692 | status = connector_status_disconnected; | |
9d1a903d CW |
1693 | kfree(edid); |
1694 | } | |
7f36e7ed CW |
1695 | |
1696 | if (status == connector_status_connected) { | |
1697 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
c3e5f67b DV |
1698 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
1699 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); | |
7f36e7ed CW |
1700 | } |
1701 | ||
2b8d33f7 | 1702 | return status; |
9dff6af8 ML |
1703 | } |
1704 | ||
52220085 CW |
1705 | static bool |
1706 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, | |
1707 | struct edid *edid) | |
1708 | { | |
1709 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); | |
1710 | bool connector_is_digital = !!IS_DIGITAL(sdvo); | |
1711 | ||
1712 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", | |
1713 | connector_is_digital, monitor_is_digital); | |
1714 | return connector_is_digital == monitor_is_digital; | |
1715 | } | |
1716 | ||
7b334fcb | 1717 | static enum drm_connector_status |
930a9e28 | 1718 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 1719 | { |
fb7a46f3 | 1720 | uint16_t response; |
df0e9248 | 1721 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1722 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
14571b4c | 1723 | enum drm_connector_status ret; |
79e53945 | 1724 | |
164c8598 | 1725 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1726 | connector->base.id, connector->name); |
164c8598 | 1727 | |
fc37381c CW |
1728 | if (!intel_sdvo_get_value(intel_sdvo, |
1729 | SDVO_CMD_GET_ATTACHED_DISPLAYS, | |
1730 | &response, 2)) | |
32aad86f | 1731 | return connector_status_unknown; |
79e53945 | 1732 | |
e957d772 CW |
1733 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
1734 | response & 0xff, response >> 8, | |
1735 | intel_sdvo_connector->output_flag); | |
e2f0ba97 | 1736 | |
fb7a46f3 | 1737 | if (response == 0) |
79e53945 | 1738 | return connector_status_disconnected; |
fb7a46f3 | 1739 | |
ea5b213a | 1740 | intel_sdvo->attached_output = response; |
14571b4c | 1741 | |
97aaf910 CW |
1742 | intel_sdvo->has_hdmi_monitor = false; |
1743 | intel_sdvo->has_hdmi_audio = false; | |
abedc077 | 1744 | intel_sdvo->rgb_quant_range_selectable = false; |
97aaf910 | 1745 | |
615fb93f | 1746 | if ((intel_sdvo_connector->output_flag & response) == 0) |
14571b4c | 1747 | ret = connector_status_disconnected; |
13946743 | 1748 | else if (IS_TMDS(intel_sdvo_connector)) |
8bf38485 | 1749 | ret = intel_sdvo_tmds_sink_detect(connector); |
13946743 CW |
1750 | else { |
1751 | struct edid *edid; | |
1752 | ||
1753 | /* if we have an edid check it matches the connection */ | |
1754 | edid = intel_sdvo_get_edid(connector); | |
1755 | if (edid == NULL) | |
1756 | edid = intel_sdvo_get_analog_edid(connector); | |
1757 | if (edid != NULL) { | |
52220085 CW |
1758 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
1759 | edid)) | |
13946743 | 1760 | ret = connector_status_connected; |
52220085 CW |
1761 | else |
1762 | ret = connector_status_disconnected; | |
1763 | ||
13946743 CW |
1764 | kfree(edid); |
1765 | } else | |
1766 | ret = connector_status_connected; | |
1767 | } | |
14571b4c ZW |
1768 | |
1769 | /* May update encoder flag for like clock for SDVO TV, etc.*/ | |
1770 | if (ret == connector_status_connected) { | |
ea5b213a CW |
1771 | intel_sdvo->is_tv = false; |
1772 | intel_sdvo->is_lvds = false; | |
14571b4c | 1773 | |
09ede541 | 1774 | if (response & SDVO_TV_MASK) |
ea5b213a | 1775 | intel_sdvo->is_tv = true; |
14571b4c | 1776 | if (response & SDVO_LVDS_MASK) |
8545423a | 1777 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
fb7a46f3 | 1778 | } |
14571b4c ZW |
1779 | |
1780 | return ret; | |
79e53945 JB |
1781 | } |
1782 | ||
e2f0ba97 | 1783 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
79e53945 | 1784 | { |
ff482d83 | 1785 | struct edid *edid; |
79e53945 | 1786 | |
46a3f4a3 | 1787 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1788 | connector->base.id, connector->name); |
46a3f4a3 | 1789 | |
79e53945 | 1790 | /* set the bus switch and get the modes */ |
e957d772 | 1791 | edid = intel_sdvo_get_edid(connector); |
79e53945 | 1792 | |
57cdaf90 KP |
1793 | /* |
1794 | * Mac mini hack. On this device, the DVI-I connector shares one DDC | |
1795 | * link between analog and digital outputs. So, if the regular SDVO | |
1796 | * DDC fails, check to see if the analog output is disconnected, in | |
1797 | * which case we'll look there for the digital DDC data. | |
e2f0ba97 | 1798 | */ |
f899fc64 CW |
1799 | if (edid == NULL) |
1800 | edid = intel_sdvo_get_analog_edid(connector); | |
1801 | ||
ff482d83 | 1802 | if (edid != NULL) { |
52220085 CW |
1803 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
1804 | edid)) { | |
0c1dab89 CW |
1805 | drm_mode_connector_update_edid_property(connector, edid); |
1806 | drm_add_edid_modes(connector, edid); | |
1807 | } | |
13946743 | 1808 | |
ff482d83 | 1809 | kfree(edid); |
e2f0ba97 | 1810 | } |
e2f0ba97 JB |
1811 | } |
1812 | ||
1813 | /* | |
1814 | * Set of SDVO TV modes. | |
1815 | * Note! This is in reply order (see loop in get_tv_modes). | |
1816 | * XXX: all 60Hz refresh? | |
1817 | */ | |
b1f559ec | 1818 | static const struct drm_display_mode sdvo_tv_modes[] = { |
7026d4ac ZW |
1819 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1820 | 416, 0, 200, 201, 232, 233, 0, | |
e2f0ba97 | 1821 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1822 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1823 | 416, 0, 240, 241, 272, 273, 0, | |
e2f0ba97 | 1824 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1825 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1826 | 496, 0, 300, 301, 332, 333, 0, | |
e2f0ba97 | 1827 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1828 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1829 | 736, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1830 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1831 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1832 | 736, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1833 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1834 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1835 | 736, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1836 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1837 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1838 | 800, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1839 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1840 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1841 | 800, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1842 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1843 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1844 | 816, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1845 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1846 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1847 | 816, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1848 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1849 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1850 | 816, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1851 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1852 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1853 | 816, 0, 540, 541, 572, 573, 0, | |
e2f0ba97 | 1854 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1855 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1856 | 816, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1857 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1858 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1859 | 864, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1860 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1861 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1862 | 896, 0, 600, 601, 632, 633, 0, | |
e2f0ba97 | 1863 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1864 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1865 | 928, 0, 624, 625, 656, 657, 0, | |
e2f0ba97 | 1866 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1867 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1868 | 1016, 0, 766, 767, 798, 799, 0, | |
e2f0ba97 | 1869 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1870 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1871 | 1120, 0, 768, 769, 800, 801, 0, | |
e2f0ba97 | 1872 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1873 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1874 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
e2f0ba97 JB |
1875 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1876 | }; | |
1877 | ||
1878 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1879 | { | |
df0e9248 | 1880 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7026d4ac | 1881 | struct intel_sdvo_sdtv_resolution_request tv_res; |
ce6feabd ZY |
1882 | uint32_t reply = 0, format_map = 0; |
1883 | int i; | |
e2f0ba97 | 1884 | |
46a3f4a3 | 1885 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1886 | connector->base.id, connector->name); |
46a3f4a3 | 1887 | |
e2f0ba97 JB |
1888 | /* Read the list of supported input resolutions for the selected TV |
1889 | * format. | |
1890 | */ | |
40039750 | 1891 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1892 | memcpy(&tv_res, &format_map, |
32aad86f | 1893 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
ce6feabd | 1894 | |
32aad86f CW |
1895 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
1896 | return; | |
ce6feabd | 1897 | |
32aad86f | 1898 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
e957d772 CW |
1899 | if (!intel_sdvo_write_cmd(intel_sdvo, |
1900 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, | |
32aad86f CW |
1901 | &tv_res, sizeof(tv_res))) |
1902 | return; | |
1903 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) | |
e2f0ba97 JB |
1904 | return; |
1905 | ||
1906 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
7026d4ac ZW |
1907 | if (reply & (1 << i)) { |
1908 | struct drm_display_mode *nmode; | |
1909 | nmode = drm_mode_duplicate(connector->dev, | |
32aad86f | 1910 | &sdvo_tv_modes[i]); |
7026d4ac ZW |
1911 | if (nmode) |
1912 | drm_mode_probed_add(connector, nmode); | |
1913 | } | |
e2f0ba97 JB |
1914 | } |
1915 | ||
7086c87f ML |
1916 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1917 | { | |
df0e9248 | 1918 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
fac5e23e | 1919 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
12682a97 | 1920 | struct drm_display_mode *newmode; |
7086c87f | 1921 | |
46a3f4a3 | 1922 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1923 | connector->base.id, connector->name); |
46a3f4a3 | 1924 | |
7086c87f | 1925 | /* |
c3456fb3 | 1926 | * Fetch modes from VBT. For SDVO prefer the VBT mode since some |
4300a0f8 | 1927 | * SDVO->LVDS transcoders can't cope with the EDID mode. |
7086c87f | 1928 | */ |
41aa3448 | 1929 | if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { |
7086c87f | 1930 | newmode = drm_mode_duplicate(connector->dev, |
41aa3448 | 1931 | dev_priv->vbt.sdvo_lvds_vbt_mode); |
7086c87f ML |
1932 | if (newmode != NULL) { |
1933 | /* Guarantee the mode is preferred */ | |
1934 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1935 | DRM_MODE_TYPE_DRIVER); | |
1936 | drm_mode_probed_add(connector, newmode); | |
1937 | } | |
1938 | } | |
12682a97 | 1939 | |
4300a0f8 DA |
1940 | /* |
1941 | * Attempt to get the mode list from DDC. | |
1942 | * Assume that the preferred modes are | |
1943 | * arranged in priority order. | |
1944 | */ | |
1945 | intel_ddc_get_modes(connector, &intel_sdvo->ddc); | |
1946 | ||
12682a97 | 1947 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
1948 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
ea5b213a | 1949 | intel_sdvo->sdvo_lvds_fixed_mode = |
12682a97 | 1950 | drm_mode_duplicate(connector->dev, newmode); |
6c9547ff | 1951 | |
8545423a | 1952 | intel_sdvo->is_lvds = true; |
12682a97 | 1953 | break; |
1954 | } | |
1955 | } | |
7086c87f ML |
1956 | } |
1957 | ||
e2f0ba97 JB |
1958 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1959 | { | |
615fb93f | 1960 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e2f0ba97 | 1961 | |
615fb93f | 1962 | if (IS_TV(intel_sdvo_connector)) |
e2f0ba97 | 1963 | intel_sdvo_get_tv_modes(connector); |
615fb93f | 1964 | else if (IS_LVDS(intel_sdvo_connector)) |
7086c87f | 1965 | intel_sdvo_get_lvds_modes(connector); |
e2f0ba97 JB |
1966 | else |
1967 | intel_sdvo_get_ddc_modes(connector); | |
1968 | ||
32aad86f | 1969 | return !list_empty(&connector->probed_modes); |
79e53945 JB |
1970 | } |
1971 | ||
1972 | static void intel_sdvo_destroy(struct drm_connector *connector) | |
1973 | { | |
615fb93f | 1974 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
79e53945 | 1975 | |
79e53945 | 1976 | drm_connector_cleanup(connector); |
4b745b1e | 1977 | kfree(intel_sdvo_connector); |
79e53945 JB |
1978 | } |
1979 | ||
1aad7ac0 CW |
1980 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
1981 | { | |
1982 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
1983 | struct edid *edid; | |
1984 | bool has_audio = false; | |
1985 | ||
1986 | if (!intel_sdvo->is_hdmi) | |
1987 | return false; | |
1988 | ||
1989 | edid = intel_sdvo_get_edid(connector); | |
1990 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1991 | has_audio = drm_detect_monitor_audio(edid); | |
38ab8a20 | 1992 | kfree(edid); |
1aad7ac0 CW |
1993 | |
1994 | return has_audio; | |
1995 | } | |
1996 | ||
ce6feabd ZY |
1997 | static int |
1998 | intel_sdvo_set_property(struct drm_connector *connector, | |
1999 | struct drm_property *property, | |
2000 | uint64_t val) | |
2001 | { | |
df0e9248 | 2002 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 2003 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
fac5e23e | 2004 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
b9219c5e | 2005 | uint16_t temp_value; |
32aad86f CW |
2006 | uint8_t cmd; |
2007 | int ret; | |
ce6feabd | 2008 | |
662595df | 2009 | ret = drm_object_property_set_value(&connector->base, property, val); |
32aad86f CW |
2010 | if (ret) |
2011 | return ret; | |
ce6feabd | 2012 | |
3f43c48d | 2013 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2014 | int i = val; |
2015 | bool has_audio; | |
2016 | ||
2017 | if (i == intel_sdvo_connector->force_audio) | |
7f36e7ed CW |
2018 | return 0; |
2019 | ||
1aad7ac0 | 2020 | intel_sdvo_connector->force_audio = i; |
7f36e7ed | 2021 | |
c3e5f67b | 2022 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
2023 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
2024 | else | |
c3e5f67b | 2025 | has_audio = (i == HDMI_AUDIO_ON); |
7f36e7ed | 2026 | |
1aad7ac0 | 2027 | if (has_audio == intel_sdvo->has_hdmi_audio) |
7f36e7ed | 2028 | return 0; |
7f36e7ed | 2029 | |
1aad7ac0 | 2030 | intel_sdvo->has_hdmi_audio = has_audio; |
7f36e7ed CW |
2031 | goto done; |
2032 | } | |
2033 | ||
e953fd7b | 2034 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
2035 | bool old_auto = intel_sdvo->color_range_auto; |
2036 | uint32_t old_range = intel_sdvo->color_range; | |
2037 | ||
55bc60db VS |
2038 | switch (val) { |
2039 | case INTEL_BROADCAST_RGB_AUTO: | |
2040 | intel_sdvo->color_range_auto = true; | |
2041 | break; | |
2042 | case INTEL_BROADCAST_RGB_FULL: | |
2043 | intel_sdvo->color_range_auto = false; | |
2044 | intel_sdvo->color_range = 0; | |
2045 | break; | |
2046 | case INTEL_BROADCAST_RGB_LIMITED: | |
2047 | intel_sdvo->color_range_auto = false; | |
4f3a8bc7 PZ |
2048 | /* FIXME: this bit is only valid when using TMDS |
2049 | * encoding and 8 bit per color mode. */ | |
2050 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; | |
55bc60db VS |
2051 | break; |
2052 | default: | |
2053 | return -EINVAL; | |
2054 | } | |
ae4edb80 DV |
2055 | |
2056 | if (old_auto == intel_sdvo->color_range_auto && | |
2057 | old_range == intel_sdvo->color_range) | |
2058 | return 0; | |
2059 | ||
7f36e7ed CW |
2060 | goto done; |
2061 | } | |
2062 | ||
7949dd47 VS |
2063 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
2064 | switch (val) { | |
2065 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
2066 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
2067 | break; | |
2068 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
2069 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
2070 | break; | |
2071 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
2072 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
2073 | break; | |
2074 | default: | |
2075 | return -EINVAL; | |
2076 | } | |
2077 | goto done; | |
2078 | } | |
2079 | ||
c5521706 CW |
2080 | #define CHECK_PROPERTY(name, NAME) \ |
2081 | if (intel_sdvo_connector->name == property) { \ | |
2082 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ | |
2083 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ | |
2084 | cmd = SDVO_CMD_SET_##NAME; \ | |
2085 | intel_sdvo_connector->cur_##name = temp_value; \ | |
2086 | goto set_value; \ | |
2087 | } | |
2088 | ||
2089 | if (property == intel_sdvo_connector->tv_format) { | |
32aad86f CW |
2090 | if (val >= TV_FORMAT_NUM) |
2091 | return -EINVAL; | |
2092 | ||
40039750 | 2093 | if (intel_sdvo->tv_format_index == |
615fb93f | 2094 | intel_sdvo_connector->tv_format_supported[val]) |
32aad86f | 2095 | return 0; |
ce6feabd | 2096 | |
40039750 | 2097 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
c5521706 | 2098 | goto done; |
32aad86f | 2099 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
b9219c5e | 2100 | temp_value = val; |
c5521706 | 2101 | if (intel_sdvo_connector->left == property) { |
662595df | 2102 | drm_object_property_set_value(&connector->base, |
c5521706 | 2103 | intel_sdvo_connector->right, val); |
615fb93f | 2104 | if (intel_sdvo_connector->left_margin == temp_value) |
32aad86f | 2105 | return 0; |
b9219c5e | 2106 | |
615fb93f CW |
2107 | intel_sdvo_connector->left_margin = temp_value; |
2108 | intel_sdvo_connector->right_margin = temp_value; | |
2109 | temp_value = intel_sdvo_connector->max_hscan - | |
c5521706 | 2110 | intel_sdvo_connector->left_margin; |
b9219c5e | 2111 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2112 | goto set_value; |
2113 | } else if (intel_sdvo_connector->right == property) { | |
662595df | 2114 | drm_object_property_set_value(&connector->base, |
c5521706 | 2115 | intel_sdvo_connector->left, val); |
615fb93f | 2116 | if (intel_sdvo_connector->right_margin == temp_value) |
32aad86f | 2117 | return 0; |
b9219c5e | 2118 | |
615fb93f CW |
2119 | intel_sdvo_connector->left_margin = temp_value; |
2120 | intel_sdvo_connector->right_margin = temp_value; | |
2121 | temp_value = intel_sdvo_connector->max_hscan - | |
2122 | intel_sdvo_connector->left_margin; | |
b9219c5e | 2123 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2124 | goto set_value; |
2125 | } else if (intel_sdvo_connector->top == property) { | |
662595df | 2126 | drm_object_property_set_value(&connector->base, |
c5521706 | 2127 | intel_sdvo_connector->bottom, val); |
615fb93f | 2128 | if (intel_sdvo_connector->top_margin == temp_value) |
32aad86f | 2129 | return 0; |
b9219c5e | 2130 | |
615fb93f CW |
2131 | intel_sdvo_connector->top_margin = temp_value; |
2132 | intel_sdvo_connector->bottom_margin = temp_value; | |
2133 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2134 | intel_sdvo_connector->top_margin; |
b9219c5e | 2135 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2136 | goto set_value; |
2137 | } else if (intel_sdvo_connector->bottom == property) { | |
662595df | 2138 | drm_object_property_set_value(&connector->base, |
c5521706 | 2139 | intel_sdvo_connector->top, val); |
615fb93f | 2140 | if (intel_sdvo_connector->bottom_margin == temp_value) |
32aad86f CW |
2141 | return 0; |
2142 | ||
615fb93f CW |
2143 | intel_sdvo_connector->top_margin = temp_value; |
2144 | intel_sdvo_connector->bottom_margin = temp_value; | |
2145 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2146 | intel_sdvo_connector->top_margin; |
b9219c5e | 2147 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2148 | goto set_value; |
2149 | } | |
2150 | CHECK_PROPERTY(hpos, HPOS) | |
2151 | CHECK_PROPERTY(vpos, VPOS) | |
2152 | CHECK_PROPERTY(saturation, SATURATION) | |
2153 | CHECK_PROPERTY(contrast, CONTRAST) | |
2154 | CHECK_PROPERTY(hue, HUE) | |
2155 | CHECK_PROPERTY(brightness, BRIGHTNESS) | |
2156 | CHECK_PROPERTY(sharpness, SHARPNESS) | |
2157 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) | |
2158 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) | |
2159 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) | |
2160 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) | |
2161 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) | |
e044218a | 2162 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
c5521706 | 2163 | } |
b9219c5e | 2164 | |
c5521706 | 2165 | return -EINVAL; /* unknown property */ |
b9219c5e | 2166 | |
c5521706 CW |
2167 | set_value: |
2168 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) | |
2169 | return -EIO; | |
b9219c5e | 2170 | |
b9219c5e | 2171 | |
c5521706 | 2172 | done: |
c0c36b94 CW |
2173 | if (intel_sdvo->base.base.crtc) |
2174 | intel_crtc_restore_mode(intel_sdvo->base.base.crtc); | |
c5521706 | 2175 | |
32aad86f | 2176 | return 0; |
c5521706 | 2177 | #undef CHECK_PROPERTY |
ce6feabd ZY |
2178 | } |
2179 | ||
7a418e34 CW |
2180 | static int |
2181 | intel_sdvo_connector_register(struct drm_connector *connector) | |
2182 | { | |
2183 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); | |
1ebaa0b9 CW |
2184 | int ret; |
2185 | ||
2186 | ret = intel_connector_register(connector); | |
2187 | if (ret) | |
2188 | return ret; | |
7a418e34 CW |
2189 | |
2190 | return sysfs_create_link(&connector->kdev->kobj, | |
2191 | &sdvo->ddc.dev.kobj, | |
2192 | sdvo->ddc.dev.kobj.name); | |
2193 | } | |
2194 | ||
c191eca1 CW |
2195 | static void |
2196 | intel_sdvo_connector_unregister(struct drm_connector *connector) | |
2197 | { | |
2198 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); | |
2199 | ||
2200 | sysfs_remove_link(&connector->kdev->kobj, | |
2201 | sdvo->ddc.dev.kobj.name); | |
2202 | intel_connector_unregister(connector); | |
2203 | } | |
2204 | ||
79e53945 | 2205 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
4d688a2a | 2206 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 JB |
2207 | .detect = intel_sdvo_detect, |
2208 | .fill_modes = drm_helper_probe_single_connector_modes, | |
ce6feabd | 2209 | .set_property = intel_sdvo_set_property, |
2545e4a6 | 2210 | .atomic_get_property = intel_connector_atomic_get_property, |
7a418e34 | 2211 | .late_register = intel_sdvo_connector_register, |
c191eca1 | 2212 | .early_unregister = intel_sdvo_connector_unregister, |
79e53945 | 2213 | .destroy = intel_sdvo_destroy, |
c6f95f27 | 2214 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 2215 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
2216 | }; |
2217 | ||
2218 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
2219 | .get_modes = intel_sdvo_get_modes, | |
2220 | .mode_valid = intel_sdvo_mode_valid, | |
79e53945 JB |
2221 | }; |
2222 | ||
b358d0a6 | 2223 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 2224 | { |
8aca63aa | 2225 | struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); |
d2a82a6f | 2226 | |
ea5b213a | 2227 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
d2a82a6f | 2228 | drm_mode_destroy(encoder->dev, |
ea5b213a | 2229 | intel_sdvo->sdvo_lvds_fixed_mode); |
d2a82a6f | 2230 | |
e957d772 | 2231 | i2c_del_adapter(&intel_sdvo->ddc); |
ea5b213a | 2232 | intel_encoder_destroy(encoder); |
79e53945 JB |
2233 | } |
2234 | ||
2235 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
2236 | .destroy = intel_sdvo_enc_destroy, | |
2237 | }; | |
2238 | ||
b66d8424 CW |
2239 | static void |
2240 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) | |
2241 | { | |
2242 | uint16_t mask = 0; | |
2243 | unsigned int num_bits; | |
2244 | ||
2245 | /* Make a mask of outputs less than or equal to our own priority in the | |
2246 | * list. | |
2247 | */ | |
2248 | switch (sdvo->controlled_output) { | |
2249 | case SDVO_OUTPUT_LVDS1: | |
2250 | mask |= SDVO_OUTPUT_LVDS1; | |
2251 | case SDVO_OUTPUT_LVDS0: | |
2252 | mask |= SDVO_OUTPUT_LVDS0; | |
2253 | case SDVO_OUTPUT_TMDS1: | |
2254 | mask |= SDVO_OUTPUT_TMDS1; | |
2255 | case SDVO_OUTPUT_TMDS0: | |
2256 | mask |= SDVO_OUTPUT_TMDS0; | |
2257 | case SDVO_OUTPUT_RGB1: | |
2258 | mask |= SDVO_OUTPUT_RGB1; | |
2259 | case SDVO_OUTPUT_RGB0: | |
2260 | mask |= SDVO_OUTPUT_RGB0; | |
2261 | break; | |
2262 | } | |
2263 | ||
2264 | /* Count bits to find what number we are in the priority list. */ | |
2265 | mask &= sdvo->caps.output_flags; | |
2266 | num_bits = hweight16(mask); | |
2267 | /* If more than 3 outputs, default to DDC bus 3 for now. */ | |
2268 | if (num_bits > 3) | |
2269 | num_bits = 3; | |
2270 | ||
2271 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
2272 | sdvo->ddc_bus = 1 << num_bits; | |
2273 | } | |
79e53945 | 2274 | |
e2f0ba97 JB |
2275 | /** |
2276 | * Choose the appropriate DDC bus for control bus switch command for this | |
2277 | * SDVO output based on the controlled output. | |
2278 | * | |
2279 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
2280 | * outputs, then LVDS outputs. | |
2281 | */ | |
2282 | static void | |
b1083333 | 2283 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
8bd864b8 | 2284 | struct intel_sdvo *sdvo) |
e2f0ba97 | 2285 | { |
b1083333 | 2286 | struct sdvo_device_mapping *mapping; |
e2f0ba97 | 2287 | |
2a5c0832 | 2288 | if (sdvo->port == PORT_B) |
9d6c875d | 2289 | mapping = &dev_priv->vbt.sdvo_mappings[0]; |
b1083333 | 2290 | else |
9d6c875d | 2291 | mapping = &dev_priv->vbt.sdvo_mappings[1]; |
e2f0ba97 | 2292 | |
b66d8424 CW |
2293 | if (mapping->initialized) |
2294 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); | |
2295 | else | |
2296 | intel_sdvo_guess_ddc_bus(sdvo); | |
e2f0ba97 JB |
2297 | } |
2298 | ||
e957d772 CW |
2299 | static void |
2300 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, | |
8bd864b8 | 2301 | struct intel_sdvo *sdvo) |
e957d772 CW |
2302 | { |
2303 | struct sdvo_device_mapping *mapping; | |
46eb3036 | 2304 | u8 pin; |
e957d772 | 2305 | |
2a5c0832 | 2306 | if (sdvo->port == PORT_B) |
9d6c875d | 2307 | mapping = &dev_priv->vbt.sdvo_mappings[0]; |
e957d772 | 2308 | else |
9d6c875d | 2309 | mapping = &dev_priv->vbt.sdvo_mappings[1]; |
e957d772 | 2310 | |
88ac7939 JN |
2311 | if (mapping->initialized && |
2312 | intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) | |
e957d772 | 2313 | pin = mapping->i2c_pin; |
6cb1612a | 2314 | else |
988c7015 | 2315 | pin = GMBUS_PIN_DPB; |
e957d772 | 2316 | |
6cb1612a JN |
2317 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
2318 | ||
2319 | /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow | |
2320 | * our code totally fails once we start using gmbus. Hence fall back to | |
2321 | * bit banging for now. */ | |
2322 | intel_gmbus_force_bit(sdvo->i2c, true); | |
e957d772 CW |
2323 | } |
2324 | ||
fbfcc4f3 JN |
2325 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
2326 | static void | |
2327 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) | |
2328 | { | |
2329 | intel_gmbus_force_bit(sdvo->i2c, false); | |
e957d772 CW |
2330 | } |
2331 | ||
e2f0ba97 | 2332 | static bool |
e27d8538 | 2333 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
e2f0ba97 | 2334 | { |
97aaf910 | 2335 | return intel_sdvo_check_supp_encode(intel_sdvo); |
e2f0ba97 JB |
2336 | } |
2337 | ||
714605e4 | 2338 | static u8 |
eef4eacb | 2339 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
714605e4 | 2340 | { |
fac5e23e | 2341 | struct drm_i915_private *dev_priv = to_i915(dev); |
714605e4 | 2342 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
2343 | ||
2a5c0832 | 2344 | if (sdvo->port == PORT_B) { |
9d6c875d JN |
2345 | my_mapping = &dev_priv->vbt.sdvo_mappings[0]; |
2346 | other_mapping = &dev_priv->vbt.sdvo_mappings[1]; | |
714605e4 | 2347 | } else { |
9d6c875d JN |
2348 | my_mapping = &dev_priv->vbt.sdvo_mappings[1]; |
2349 | other_mapping = &dev_priv->vbt.sdvo_mappings[0]; | |
714605e4 | 2350 | } |
2351 | ||
2352 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
2353 | if (my_mapping->slave_addr) | |
2354 | return my_mapping->slave_addr; | |
2355 | ||
2356 | /* If the BIOS only described a different SDVO device, use the | |
2357 | * address that it isn't using. | |
2358 | */ | |
2359 | if (other_mapping->slave_addr) { | |
2360 | if (other_mapping->slave_addr == 0x70) | |
2361 | return 0x72; | |
2362 | else | |
2363 | return 0x70; | |
2364 | } | |
2365 | ||
2366 | /* No SDVO device info is found for another DVO port, | |
2367 | * so use mapping assumption we had before BIOS parsing. | |
2368 | */ | |
2a5c0832 | 2369 | if (sdvo->port == PORT_B) |
714605e4 | 2370 | return 0x70; |
2371 | else | |
2372 | return 0x72; | |
2373 | } | |
2374 | ||
c393454d | 2375 | static int |
df0e9248 CW |
2376 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
2377 | struct intel_sdvo *encoder) | |
14571b4c | 2378 | { |
c393454d ID |
2379 | struct drm_connector *drm_connector; |
2380 | int ret; | |
2381 | ||
2382 | drm_connector = &connector->base.base; | |
2383 | ret = drm_connector_init(encoder->base.base.dev, | |
2384 | drm_connector, | |
df0e9248 CW |
2385 | &intel_sdvo_connector_funcs, |
2386 | connector->base.base.connector_type); | |
c393454d ID |
2387 | if (ret < 0) |
2388 | return ret; | |
6070a4a9 | 2389 | |
c393454d | 2390 | drm_connector_helper_add(drm_connector, |
df0e9248 | 2391 | &intel_sdvo_connector_helper_funcs); |
14571b4c | 2392 | |
8f4839e2 | 2393 | connector->base.base.interlace_allowed = 1; |
df0e9248 CW |
2394 | connector->base.base.doublescan_allowed = 0; |
2395 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; | |
4ac41f47 | 2396 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
14571b4c | 2397 | |
df0e9248 | 2398 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
c393454d ID |
2399 | |
2400 | return 0; | |
14571b4c | 2401 | } |
6070a4a9 | 2402 | |
7f36e7ed | 2403 | static void |
55bc60db VS |
2404 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
2405 | struct intel_sdvo_connector *connector) | |
7f36e7ed CW |
2406 | { |
2407 | struct drm_device *dev = connector->base.base.dev; | |
2408 | ||
3f43c48d | 2409 | intel_attach_force_audio_property(&connector->base.base); |
55bc60db | 2410 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { |
e953fd7b | 2411 | intel_attach_broadcast_rgb_property(&connector->base.base); |
55bc60db VS |
2412 | intel_sdvo->color_range_auto = true; |
2413 | } | |
7949dd47 VS |
2414 | intel_attach_aspect_ratio_property(&connector->base.base); |
2415 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
7f36e7ed CW |
2416 | } |
2417 | ||
08d9bc92 ACO |
2418 | static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) |
2419 | { | |
2420 | struct intel_sdvo_connector *sdvo_connector; | |
2421 | ||
2422 | sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); | |
2423 | if (!sdvo_connector) | |
2424 | return NULL; | |
2425 | ||
2426 | if (intel_connector_init(&sdvo_connector->base) < 0) { | |
2427 | kfree(sdvo_connector); | |
2428 | return NULL; | |
2429 | } | |
2430 | ||
2431 | return sdvo_connector; | |
2432 | } | |
2433 | ||
fb7a46f3 | 2434 | static bool |
ea5b213a | 2435 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
fb7a46f3 | 2436 | { |
4ef69c7a | 2437 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
14571b4c | 2438 | struct drm_connector *connector; |
cc68c81a | 2439 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
14571b4c | 2440 | struct intel_connector *intel_connector; |
615fb93f | 2441 | struct intel_sdvo_connector *intel_sdvo_connector; |
14571b4c | 2442 | |
46a3f4a3 CW |
2443 | DRM_DEBUG_KMS("initialising DVI device %d\n", device); |
2444 | ||
08d9bc92 | 2445 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f | 2446 | if (!intel_sdvo_connector) |
14571b4c ZW |
2447 | return false; |
2448 | ||
14571b4c | 2449 | if (device == 0) { |
ea5b213a | 2450 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
615fb93f | 2451 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
14571b4c | 2452 | } else if (device == 1) { |
ea5b213a | 2453 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
615fb93f | 2454 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
14571b4c ZW |
2455 | } |
2456 | ||
615fb93f | 2457 | intel_connector = &intel_sdvo_connector->base; |
14571b4c | 2458 | connector = &intel_connector->base; |
5fa7ac9c JN |
2459 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
2460 | intel_sdvo_connector->output_flag) { | |
5fa7ac9c | 2461 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
cc68c81a SF |
2462 | /* Some SDVO devices have one-shot hotplug interrupts. |
2463 | * Ensure that they get re-enabled when an interrupt happens. | |
2464 | */ | |
2465 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; | |
3a2fb2c3 | 2466 | intel_sdvo_enable_hotplug(intel_encoder); |
5fa7ac9c | 2467 | } else { |
821450c6 | 2468 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
5fa7ac9c | 2469 | } |
14571b4c ZW |
2470 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
2471 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; | |
2472 | ||
e27d8538 | 2473 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
14571b4c | 2474 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
e27d8538 | 2475 | intel_sdvo->is_hdmi = true; |
14571b4c | 2476 | } |
14571b4c | 2477 | |
c393454d ID |
2478 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2479 | kfree(intel_sdvo_connector); | |
2480 | return false; | |
2481 | } | |
2482 | ||
f797d221 | 2483 | if (intel_sdvo->is_hdmi) |
55bc60db | 2484 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
14571b4c ZW |
2485 | |
2486 | return true; | |
2487 | } | |
2488 | ||
2489 | static bool | |
ea5b213a | 2490 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
14571b4c | 2491 | { |
4ef69c7a CW |
2492 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2493 | struct drm_connector *connector; | |
2494 | struct intel_connector *intel_connector; | |
2495 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2496 | |
46a3f4a3 CW |
2497 | DRM_DEBUG_KMS("initialising TV type %d\n", type); |
2498 | ||
08d9bc92 | 2499 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f CW |
2500 | if (!intel_sdvo_connector) |
2501 | return false; | |
14571b4c | 2502 | |
615fb93f | 2503 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a CW |
2504 | connector = &intel_connector->base; |
2505 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | |
2506 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
14571b4c | 2507 | |
4ef69c7a CW |
2508 | intel_sdvo->controlled_output |= type; |
2509 | intel_sdvo_connector->output_flag = type; | |
14571b4c | 2510 | |
4ef69c7a | 2511 | intel_sdvo->is_tv = true; |
14571b4c | 2512 | |
c393454d ID |
2513 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2514 | kfree(intel_sdvo_connector); | |
2515 | return false; | |
2516 | } | |
14571b4c | 2517 | |
4ef69c7a | 2518 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
32aad86f | 2519 | goto err; |
14571b4c | 2520 | |
4ef69c7a | 2521 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f | 2522 | goto err; |
14571b4c | 2523 | |
4ef69c7a | 2524 | return true; |
32aad86f CW |
2525 | |
2526 | err: | |
123d5c01 | 2527 | intel_sdvo_destroy(connector); |
32aad86f | 2528 | return false; |
14571b4c ZW |
2529 | } |
2530 | ||
2531 | static bool | |
ea5b213a | 2532 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2533 | { |
4ef69c7a CW |
2534 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2535 | struct drm_connector *connector; | |
2536 | struct intel_connector *intel_connector; | |
2537 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2538 | |
46a3f4a3 CW |
2539 | DRM_DEBUG_KMS("initialising analog device %d\n", device); |
2540 | ||
8ce7da47 | 2541 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f CW |
2542 | if (!intel_sdvo_connector) |
2543 | return false; | |
14571b4c | 2544 | |
615fb93f | 2545 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a | 2546 | connector = &intel_connector->base; |
821450c6 | 2547 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
4ef69c7a CW |
2548 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
2549 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
2550 | ||
2551 | if (device == 0) { | |
2552 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; | |
2553 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; | |
2554 | } else if (device == 1) { | |
2555 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; | |
2556 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; | |
2557 | } | |
2558 | ||
c393454d ID |
2559 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2560 | kfree(intel_sdvo_connector); | |
2561 | return false; | |
2562 | } | |
2563 | ||
4ef69c7a | 2564 | return true; |
14571b4c ZW |
2565 | } |
2566 | ||
2567 | static bool | |
ea5b213a | 2568 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2569 | { |
4ef69c7a CW |
2570 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2571 | struct drm_connector *connector; | |
2572 | struct intel_connector *intel_connector; | |
2573 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2574 | |
46a3f4a3 CW |
2575 | DRM_DEBUG_KMS("initialising LVDS device %d\n", device); |
2576 | ||
08d9bc92 | 2577 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f CW |
2578 | if (!intel_sdvo_connector) |
2579 | return false; | |
14571b4c | 2580 | |
615fb93f CW |
2581 | intel_connector = &intel_sdvo_connector->base; |
2582 | connector = &intel_connector->base; | |
4ef69c7a CW |
2583 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
2584 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2585 | ||
2586 | if (device == 0) { | |
2587 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; | |
2588 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; | |
2589 | } else if (device == 1) { | |
2590 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; | |
2591 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; | |
2592 | } | |
2593 | ||
c393454d ID |
2594 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2595 | kfree(intel_sdvo_connector); | |
2596 | return false; | |
2597 | } | |
2598 | ||
4ef69c7a | 2599 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f CW |
2600 | goto err; |
2601 | ||
2602 | return true; | |
2603 | ||
2604 | err: | |
123d5c01 | 2605 | intel_sdvo_destroy(connector); |
32aad86f | 2606 | return false; |
14571b4c ZW |
2607 | } |
2608 | ||
2609 | static bool | |
ea5b213a | 2610 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
14571b4c | 2611 | { |
ea5b213a | 2612 | intel_sdvo->is_tv = false; |
ea5b213a | 2613 | intel_sdvo->is_lvds = false; |
fb7a46f3 | 2614 | |
14571b4c | 2615 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
fb7a46f3 | 2616 | |
14571b4c | 2617 | if (flags & SDVO_OUTPUT_TMDS0) |
ea5b213a | 2618 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
14571b4c ZW |
2619 | return false; |
2620 | ||
2621 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) | |
ea5b213a | 2622 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
14571b4c ZW |
2623 | return false; |
2624 | ||
2625 | /* TV has no XXX1 function block */ | |
a1f4b7ff | 2626 | if (flags & SDVO_OUTPUT_SVID0) |
ea5b213a | 2627 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
14571b4c ZW |
2628 | return false; |
2629 | ||
2630 | if (flags & SDVO_OUTPUT_CVBS0) | |
ea5b213a | 2631 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
14571b4c | 2632 | return false; |
fb7a46f3 | 2633 | |
a0b1c7a5 CW |
2634 | if (flags & SDVO_OUTPUT_YPRPB0) |
2635 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) | |
2636 | return false; | |
2637 | ||
14571b4c | 2638 | if (flags & SDVO_OUTPUT_RGB0) |
ea5b213a | 2639 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
14571b4c ZW |
2640 | return false; |
2641 | ||
2642 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) | |
ea5b213a | 2643 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
14571b4c ZW |
2644 | return false; |
2645 | ||
2646 | if (flags & SDVO_OUTPUT_LVDS0) | |
ea5b213a | 2647 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
14571b4c ZW |
2648 | return false; |
2649 | ||
2650 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) | |
ea5b213a | 2651 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
14571b4c | 2652 | return false; |
fb7a46f3 | 2653 | |
14571b4c | 2654 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
fb7a46f3 | 2655 | unsigned char bytes[2]; |
2656 | ||
ea5b213a CW |
2657 | intel_sdvo->controlled_output = 0; |
2658 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); | |
51c8b407 | 2659 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
ea5b213a | 2660 | SDVO_NAME(intel_sdvo), |
51c8b407 | 2661 | bytes[0], bytes[1]); |
14571b4c | 2662 | return false; |
fb7a46f3 | 2663 | } |
27f8227b | 2664 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
fb7a46f3 | 2665 | |
14571b4c | 2666 | return true; |
fb7a46f3 | 2667 | } |
2668 | ||
d0ddfbd3 JN |
2669 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
2670 | { | |
2671 | struct drm_device *dev = intel_sdvo->base.base.dev; | |
2672 | struct drm_connector *connector, *tmp; | |
2673 | ||
2674 | list_for_each_entry_safe(connector, tmp, | |
2675 | &dev->mode_config.connector_list, head) { | |
d9255d57 | 2676 | if (intel_attached_encoder(connector) == &intel_sdvo->base) { |
34ea3d38 | 2677 | drm_connector_unregister(connector); |
d0ddfbd3 | 2678 | intel_sdvo_destroy(connector); |
d9255d57 | 2679 | } |
d0ddfbd3 JN |
2680 | } |
2681 | } | |
2682 | ||
32aad86f CW |
2683 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2684 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2685 | int type) | |
ce6feabd | 2686 | { |
4ef69c7a | 2687 | struct drm_device *dev = intel_sdvo->base.base.dev; |
ce6feabd ZY |
2688 | struct intel_sdvo_tv_format format; |
2689 | uint32_t format_map, i; | |
ce6feabd | 2690 | |
32aad86f CW |
2691 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
2692 | return false; | |
ce6feabd | 2693 | |
1a3665c8 | 2694 | BUILD_BUG_ON(sizeof(format) != 6); |
32aad86f CW |
2695 | if (!intel_sdvo_get_value(intel_sdvo, |
2696 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, | |
2697 | &format, sizeof(format))) | |
2698 | return false; | |
ce6feabd | 2699 | |
32aad86f | 2700 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
ce6feabd ZY |
2701 | |
2702 | if (format_map == 0) | |
32aad86f | 2703 | return false; |
ce6feabd | 2704 | |
615fb93f | 2705 | intel_sdvo_connector->format_supported_num = 0; |
ce6feabd | 2706 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
40039750 CW |
2707 | if (format_map & (1 << i)) |
2708 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; | |
ce6feabd ZY |
2709 | |
2710 | ||
c5521706 | 2711 | intel_sdvo_connector->tv_format = |
32aad86f CW |
2712 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
2713 | "mode", intel_sdvo_connector->format_supported_num); | |
c5521706 | 2714 | if (!intel_sdvo_connector->tv_format) |
fcc8d672 | 2715 | return false; |
ce6feabd | 2716 | |
615fb93f | 2717 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
ce6feabd | 2718 | drm_property_add_enum( |
c5521706 | 2719 | intel_sdvo_connector->tv_format, i, |
40039750 | 2720 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
ce6feabd | 2721 | |
40039750 | 2722 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
662595df | 2723 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
c5521706 | 2724 | intel_sdvo_connector->tv_format, 0); |
32aad86f | 2725 | return true; |
ce6feabd ZY |
2726 | |
2727 | } | |
2728 | ||
c5521706 CW |
2729 | #define ENHANCEMENT(name, NAME) do { \ |
2730 | if (enhancements.name) { \ | |
2731 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ | |
2732 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ | |
2733 | return false; \ | |
2734 | intel_sdvo_connector->max_##name = data_value[0]; \ | |
2735 | intel_sdvo_connector->cur_##name = response; \ | |
2736 | intel_sdvo_connector->name = \ | |
d9bc3c02 | 2737 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
c5521706 | 2738 | if (!intel_sdvo_connector->name) return false; \ |
662595df | 2739 | drm_object_attach_property(&connector->base, \ |
c5521706 CW |
2740 | intel_sdvo_connector->name, \ |
2741 | intel_sdvo_connector->cur_##name); \ | |
2742 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ | |
2743 | data_value[0], data_value[1], response); \ | |
2744 | } \ | |
0206e353 | 2745 | } while (0) |
c5521706 CW |
2746 | |
2747 | static bool | |
2748 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, | |
2749 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2750 | struct intel_sdvo_enhancements_reply enhancements) | |
b9219c5e | 2751 | { |
4ef69c7a | 2752 | struct drm_device *dev = intel_sdvo->base.base.dev; |
32aad86f | 2753 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
b9219c5e ZY |
2754 | uint16_t response, data_value[2]; |
2755 | ||
c5521706 CW |
2756 | /* when horizontal overscan is supported, Add the left/right property */ |
2757 | if (enhancements.overscan_h) { | |
2758 | if (!intel_sdvo_get_value(intel_sdvo, | |
2759 | SDVO_CMD_GET_MAX_OVERSCAN_H, | |
2760 | &data_value, 4)) | |
2761 | return false; | |
32aad86f | 2762 | |
c5521706 CW |
2763 | if (!intel_sdvo_get_value(intel_sdvo, |
2764 | SDVO_CMD_GET_OVERSCAN_H, | |
2765 | &response, 2)) | |
2766 | return false; | |
fcc8d672 | 2767 | |
c5521706 CW |
2768 | intel_sdvo_connector->max_hscan = data_value[0]; |
2769 | intel_sdvo_connector->left_margin = data_value[0] - response; | |
2770 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; | |
2771 | intel_sdvo_connector->left = | |
d9bc3c02 | 2772 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
c5521706 CW |
2773 | if (!intel_sdvo_connector->left) |
2774 | return false; | |
fcc8d672 | 2775 | |
662595df | 2776 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2777 | intel_sdvo_connector->left, |
2778 | intel_sdvo_connector->left_margin); | |
fcc8d672 | 2779 | |
c5521706 | 2780 | intel_sdvo_connector->right = |
d9bc3c02 | 2781 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
c5521706 CW |
2782 | if (!intel_sdvo_connector->right) |
2783 | return false; | |
32aad86f | 2784 | |
662595df | 2785 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2786 | intel_sdvo_connector->right, |
2787 | intel_sdvo_connector->right_margin); | |
2788 | DRM_DEBUG_KMS("h_overscan: max %d, " | |
2789 | "default %d, current %d\n", | |
2790 | data_value[0], data_value[1], response); | |
2791 | } | |
32aad86f | 2792 | |
c5521706 CW |
2793 | if (enhancements.overscan_v) { |
2794 | if (!intel_sdvo_get_value(intel_sdvo, | |
2795 | SDVO_CMD_GET_MAX_OVERSCAN_V, | |
2796 | &data_value, 4)) | |
2797 | return false; | |
fcc8d672 | 2798 | |
c5521706 CW |
2799 | if (!intel_sdvo_get_value(intel_sdvo, |
2800 | SDVO_CMD_GET_OVERSCAN_V, | |
2801 | &response, 2)) | |
2802 | return false; | |
32aad86f | 2803 | |
c5521706 CW |
2804 | intel_sdvo_connector->max_vscan = data_value[0]; |
2805 | intel_sdvo_connector->top_margin = data_value[0] - response; | |
2806 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; | |
2807 | intel_sdvo_connector->top = | |
d9bc3c02 SH |
2808 | drm_property_create_range(dev, 0, |
2809 | "top_margin", 0, data_value[0]); | |
c5521706 CW |
2810 | if (!intel_sdvo_connector->top) |
2811 | return false; | |
32aad86f | 2812 | |
662595df | 2813 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2814 | intel_sdvo_connector->top, |
2815 | intel_sdvo_connector->top_margin); | |
fcc8d672 | 2816 | |
c5521706 | 2817 | intel_sdvo_connector->bottom = |
d9bc3c02 SH |
2818 | drm_property_create_range(dev, 0, |
2819 | "bottom_margin", 0, data_value[0]); | |
c5521706 CW |
2820 | if (!intel_sdvo_connector->bottom) |
2821 | return false; | |
32aad86f | 2822 | |
662595df | 2823 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2824 | intel_sdvo_connector->bottom, |
2825 | intel_sdvo_connector->bottom_margin); | |
2826 | DRM_DEBUG_KMS("v_overscan: max %d, " | |
2827 | "default %d, current %d\n", | |
2828 | data_value[0], data_value[1], response); | |
2829 | } | |
32aad86f | 2830 | |
c5521706 CW |
2831 | ENHANCEMENT(hpos, HPOS); |
2832 | ENHANCEMENT(vpos, VPOS); | |
2833 | ENHANCEMENT(saturation, SATURATION); | |
2834 | ENHANCEMENT(contrast, CONTRAST); | |
2835 | ENHANCEMENT(hue, HUE); | |
2836 | ENHANCEMENT(sharpness, SHARPNESS); | |
2837 | ENHANCEMENT(brightness, BRIGHTNESS); | |
2838 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); | |
2839 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); | |
2840 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); | |
2841 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); | |
2842 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); | |
fcc8d672 | 2843 | |
e044218a CW |
2844 | if (enhancements.dot_crawl) { |
2845 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) | |
2846 | return false; | |
2847 | ||
2848 | intel_sdvo_connector->max_dot_crawl = 1; | |
2849 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; | |
2850 | intel_sdvo_connector->dot_crawl = | |
d9bc3c02 | 2851 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
e044218a CW |
2852 | if (!intel_sdvo_connector->dot_crawl) |
2853 | return false; | |
2854 | ||
662595df | 2855 | drm_object_attach_property(&connector->base, |
e044218a CW |
2856 | intel_sdvo_connector->dot_crawl, |
2857 | intel_sdvo_connector->cur_dot_crawl); | |
2858 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); | |
2859 | } | |
2860 | ||
c5521706 CW |
2861 | return true; |
2862 | } | |
32aad86f | 2863 | |
c5521706 CW |
2864 | static bool |
2865 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, | |
2866 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2867 | struct intel_sdvo_enhancements_reply enhancements) | |
2868 | { | |
4ef69c7a | 2869 | struct drm_device *dev = intel_sdvo->base.base.dev; |
c5521706 CW |
2870 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
2871 | uint16_t response, data_value[2]; | |
32aad86f | 2872 | |
c5521706 | 2873 | ENHANCEMENT(brightness, BRIGHTNESS); |
fcc8d672 | 2874 | |
c5521706 CW |
2875 | return true; |
2876 | } | |
2877 | #undef ENHANCEMENT | |
32aad86f | 2878 | |
c5521706 CW |
2879 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
2880 | struct intel_sdvo_connector *intel_sdvo_connector) | |
2881 | { | |
2882 | union { | |
2883 | struct intel_sdvo_enhancements_reply reply; | |
2884 | uint16_t response; | |
2885 | } enhancements; | |
32aad86f | 2886 | |
1a3665c8 CW |
2887 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
2888 | ||
cf9a2f3a CW |
2889 | enhancements.response = 0; |
2890 | intel_sdvo_get_value(intel_sdvo, | |
2891 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, | |
2892 | &enhancements, sizeof(enhancements)); | |
c5521706 CW |
2893 | if (enhancements.response == 0) { |
2894 | DRM_DEBUG_KMS("No enhancement is supported\n"); | |
2895 | return true; | |
b9219c5e | 2896 | } |
32aad86f | 2897 | |
c5521706 CW |
2898 | if (IS_TV(intel_sdvo_connector)) |
2899 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); | |
0206e353 | 2900 | else if (IS_LVDS(intel_sdvo_connector)) |
c5521706 CW |
2901 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2902 | else | |
2903 | return true; | |
e957d772 CW |
2904 | } |
2905 | ||
2906 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, | |
2907 | struct i2c_msg *msgs, | |
2908 | int num) | |
2909 | { | |
2910 | struct intel_sdvo *sdvo = adapter->algo_data; | |
fcc8d672 | 2911 | |
e957d772 CW |
2912 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
2913 | return -EIO; | |
2914 | ||
2915 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); | |
2916 | } | |
2917 | ||
2918 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) | |
2919 | { | |
2920 | struct intel_sdvo *sdvo = adapter->algo_data; | |
2921 | return sdvo->i2c->algo->functionality(sdvo->i2c); | |
2922 | } | |
2923 | ||
2924 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { | |
2925 | .master_xfer = intel_sdvo_ddc_proxy_xfer, | |
2926 | .functionality = intel_sdvo_ddc_proxy_func | |
2927 | }; | |
2928 | ||
2929 | static bool | |
2930 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, | |
2931 | struct drm_device *dev) | |
2932 | { | |
52a05c30 DW |
2933 | struct pci_dev *pdev = dev->pdev; |
2934 | ||
e957d772 CW |
2935 | sdvo->ddc.owner = THIS_MODULE; |
2936 | sdvo->ddc.class = I2C_CLASS_DDC; | |
2937 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); | |
52a05c30 | 2938 | sdvo->ddc.dev.parent = &pdev->dev; |
e957d772 CW |
2939 | sdvo->ddc.algo_data = sdvo; |
2940 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; | |
2941 | ||
2942 | return i2c_add_adapter(&sdvo->ddc) == 0; | |
b9219c5e ZY |
2943 | } |
2944 | ||
2a5c0832 VS |
2945 | static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, |
2946 | enum port port) | |
2947 | { | |
2948 | if (HAS_PCH_SPLIT(dev_priv)) | |
2949 | WARN_ON(port != PORT_B); | |
2950 | else | |
2951 | WARN_ON(port != PORT_B && port != PORT_C); | |
2952 | } | |
2953 | ||
f0f59a00 VS |
2954 | bool intel_sdvo_init(struct drm_device *dev, |
2955 | i915_reg_t sdvo_reg, enum port port) | |
79e53945 | 2956 | { |
fac5e23e | 2957 | struct drm_i915_private *dev_priv = to_i915(dev); |
21d40d37 | 2958 | struct intel_encoder *intel_encoder; |
ea5b213a | 2959 | struct intel_sdvo *intel_sdvo; |
79e53945 | 2960 | int i; |
2a5c0832 VS |
2961 | |
2962 | assert_sdvo_port_valid(dev_priv, port); | |
2963 | ||
b14c5679 | 2964 | intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); |
ea5b213a | 2965 | if (!intel_sdvo) |
7d57382e | 2966 | return false; |
79e53945 | 2967 | |
56184e3d | 2968 | intel_sdvo->sdvo_reg = sdvo_reg; |
2a5c0832 | 2969 | intel_sdvo->port = port; |
eef4eacb | 2970 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; |
8bd864b8 | 2971 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); |
fbfcc4f3 JN |
2972 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) |
2973 | goto err_i2c_bus; | |
e957d772 | 2974 | |
56184e3d | 2975 | /* encoder type will be decided later */ |
ea5b213a | 2976 | intel_encoder = &intel_sdvo->base; |
21d40d37 | 2977 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
13a3d91f | 2978 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0, |
580d8ed5 | 2979 | "SDVO %c", port_name(port)); |
79e53945 | 2980 | |
79e53945 JB |
2981 | /* Read the regs to test if we can talk to the device */ |
2982 | for (i = 0; i < 0x40; i++) { | |
f899fc64 CW |
2983 | u8 byte; |
2984 | ||
2985 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { | |
eef4eacb DV |
2986 | DRM_DEBUG_KMS("No SDVO device found on %s\n", |
2987 | SDVO_NAME(intel_sdvo)); | |
f899fc64 | 2988 | goto err; |
79e53945 JB |
2989 | } |
2990 | } | |
2991 | ||
6cc5f341 | 2992 | intel_encoder->compute_config = intel_sdvo_compute_config; |
3c65d1d1 VS |
2993 | if (HAS_PCH_SPLIT(dev)) { |
2994 | intel_encoder->disable = pch_disable_sdvo; | |
2995 | intel_encoder->post_disable = pch_post_disable_sdvo; | |
2996 | } else { | |
2997 | intel_encoder->disable = intel_disable_sdvo; | |
2998 | } | |
192d47a6 | 2999 | intel_encoder->pre_enable = intel_sdvo_pre_enable; |
ce22c320 | 3000 | intel_encoder->enable = intel_enable_sdvo; |
4ac41f47 | 3001 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
045ac3b5 | 3002 | intel_encoder->get_config = intel_sdvo_get_config; |
ce22c320 | 3003 | |
af901ca1 | 3004 | /* In default case sdvo lvds is false */ |
32aad86f | 3005 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
f899fc64 | 3006 | goto err; |
79e53945 | 3007 | |
ea5b213a CW |
3008 | if (intel_sdvo_output_setup(intel_sdvo, |
3009 | intel_sdvo->caps.output_flags) != true) { | |
eef4eacb DV |
3010 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
3011 | SDVO_NAME(intel_sdvo)); | |
d0ddfbd3 JN |
3012 | /* Output_setup can leave behind connectors! */ |
3013 | goto err_output; | |
79e53945 JB |
3014 | } |
3015 | ||
7ba220ce CW |
3016 | /* Only enable the hotplug irq if we need it, to work around noisy |
3017 | * hotplug lines. | |
3018 | */ | |
3019 | if (intel_sdvo->hotplug_active) { | |
2a5c0832 VS |
3020 | if (intel_sdvo->port == PORT_B) |
3021 | intel_encoder->hpd_pin = HPD_SDVO_B; | |
3022 | else | |
3023 | intel_encoder->hpd_pin = HPD_SDVO_C; | |
7ba220ce CW |
3024 | } |
3025 | ||
e506d6fd DV |
3026 | /* |
3027 | * Cloning SDVO with anything is often impossible, since the SDVO | |
3028 | * encoder can request a special input timing mode. And even if that's | |
3029 | * not the case we have evidence that cloning a plain unscaled mode with | |
3030 | * VGA doesn't really work. Furthermore the cloning flags are way too | |
3031 | * simplistic anyway to express such constraints, so just give up on | |
3032 | * cloning for SDVO encoders. | |
3033 | */ | |
bc079e8b | 3034 | intel_sdvo->base.cloneable = 0; |
e506d6fd | 3035 | |
8bd864b8 | 3036 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); |
e2f0ba97 | 3037 | |
79e53945 | 3038 | /* Set the input timing to the screen. Assume always input 0. */ |
32aad86f | 3039 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
d0ddfbd3 | 3040 | goto err_output; |
79e53945 | 3041 | |
32aad86f CW |
3042 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
3043 | &intel_sdvo->pixel_clock_min, | |
3044 | &intel_sdvo->pixel_clock_max)) | |
d0ddfbd3 | 3045 | goto err_output; |
79e53945 | 3046 | |
8a4c47f3 | 3047 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
342dc382 | 3048 | "clock range %dMHz - %dMHz, " |
3049 | "input 1: %c, input 2: %c, " | |
3050 | "output 1: %c, output 2: %c\n", | |
ea5b213a CW |
3051 | SDVO_NAME(intel_sdvo), |
3052 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, | |
3053 | intel_sdvo->caps.device_rev_id, | |
3054 | intel_sdvo->pixel_clock_min / 1000, | |
3055 | intel_sdvo->pixel_clock_max / 1000, | |
3056 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
3057 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
342dc382 | 3058 | /* check currently supported outputs */ |
ea5b213a | 3059 | intel_sdvo->caps.output_flags & |
79e53945 | 3060 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
ea5b213a | 3061 | intel_sdvo->caps.output_flags & |
79e53945 | 3062 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
7d57382e | 3063 | return true; |
79e53945 | 3064 | |
d0ddfbd3 JN |
3065 | err_output: |
3066 | intel_sdvo_output_cleanup(intel_sdvo); | |
3067 | ||
f899fc64 | 3068 | err: |
373a3cf7 | 3069 | drm_encoder_cleanup(&intel_encoder->base); |
e957d772 | 3070 | i2c_del_adapter(&intel_sdvo->ddc); |
fbfcc4f3 JN |
3071 | err_i2c_bus: |
3072 | intel_sdvo_unselect_i2c_bus(intel_sdvo); | |
ea5b213a | 3073 | kfree(intel_sdvo); |
79e53945 | 3074 | |
7d57382e | 3075 | return false; |
79e53945 | 3076 | } |