projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Drivers: i915: Fix all space related issues.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 52
79e53945 53
2e88e40b 54static const char *tv_format_names[] = {
ce6feabd
ZY		 55 "NTSC_M" , "NTSC_J" , "NTSC_443",
56 "PAL_B" , "PAL_D" , "PAL_G" ,
57 "PAL_H" , "PAL_I" , "PAL_M" ,
58 "PAL_N" , "PAL_NC" , "PAL_60" ,
59 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
60 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
61 "SECAM_60"
62};
63
64#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
65
ea5b213a
CW		 66struct intel_sdvo {
67 struct intel_encoder base;
68
f899fc64 69 struct i2c_adapter *i2c;
f9c10a9b 70 u8 slave_addr;
e2f0ba97 71
e957d772
CW		 72 struct i2c_adapter ddc;
73
e2f0ba97 74 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 75 int sdvo_reg;
79e53945 76
e2f0ba97
JB		 77 /* Active outputs controlled by this SDVO output */
78 uint16_t controlled_output;
79e53945 79
e2f0ba97
JB		 80 /*
81 * Capabilities of the SDVO device returned by
82 * i830_sdvo_get_capabilities()
83 */
79e53945 84 struct intel_sdvo_caps caps;
e2f0ba97
JB		 85
86 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 87 int pixel_clock_min, pixel_clock_max;
88
fb7a46f3 89 /*
90 * For multiple function SDVO device,
91 * this is for current attached outputs.
92 */
93 uint16_t attached_output;
94
e953fd7b
CW		 95 /**
96 * This is used to select the color range of RBG outputs in HDMI mode.
97 * It is only valid when using TMDS encoding and 8 bit per color mode.
98 */
99 uint32_t color_range;
100
e2f0ba97
JB		 101 /**
102 * This is set if we're going to treat the device as TV-out.
103 *
104 * While we have these nice friendly flags for output types that ought
105 * to decide this for us, the S-Video output on our HDMI+S-Video card
106 * shows up as RGB1 (VGA).
107 */
108 bool is_tv;
109
ce6feabd 110 /* This is for current tv format name */
40039750 111 int tv_format_index;
ce6feabd 112
e2f0ba97
JB		 113 /**
114 * This is set if we treat the device as HDMI, instead of DVI.
115 */
116 bool is_hdmi;
da79de97
CW		 117 bool has_hdmi_monitor;
118 bool has_hdmi_audio;
12682a97 119
7086c87f 120 /**
6c9547ff
CW		 121 * This is set if we detect output of sdvo device as LVDS and
122 * have a valid fixed mode to use with the panel.
7086c87f
ML		 123 */
124 bool is_lvds;
e2f0ba97 125
12682a97 126 /**
127 * This is sdvo fixed pannel mode pointer
128 */
129 struct drm_display_mode *sdvo_lvds_fixed_mode;
130
c751ce4f 131 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 132 uint8_t ddc_bus;
133
6c9547ff
CW		 134 /* Input timings for adjusted_mode */
135 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 136};
137
138struct intel_sdvo_connector {
615fb93f
CW		 139 struct intel_connector base;
140
14571b4c
ZW		 141 /* Mark the type of connector */
142 uint16_t output_flag;
143
7f36e7ed
CW		 144 int force_audio;
145
14571b4c 146 /* This contains all current supported TV format */
40039750 147 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 148 int format_supported_num;
c5521706 149 struct drm_property *tv_format;
14571b4c 150
b9219c5e 151 /* add the property for the SDVO-TV */
c5521706
CW		 152 struct drm_property *left;
153 struct drm_property *right;
154 struct drm_property *top;
155 struct drm_property *bottom;
156 struct drm_property *hpos;
157 struct drm_property *vpos;
158 struct drm_property *contrast;
159 struct drm_property *saturation;
160 struct drm_property *hue;
161 struct drm_property *sharpness;
162 struct drm_property *flicker_filter;
163 struct drm_property *flicker_filter_adaptive;
164 struct drm_property *flicker_filter_2d;
165 struct drm_property *tv_chroma_filter;
166 struct drm_property *tv_luma_filter;
e044218a 167 struct drm_property *dot_crawl;
b9219c5e
ZY		 168
169 /* add the property for the SDVO-TV/LVDS */
c5521706 170 struct drm_property *brightness;
b9219c5e
ZY		 171
172 /* Add variable to record current setting for the above property */
173 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 174
b9219c5e
ZY		 175 /* this is to get the range of margin.*/
176 u32 max_hscan, max_vscan;
177 u32 max_hpos, cur_hpos;
178 u32 max_vpos, cur_vpos;
179 u32 cur_brightness, max_brightness;
180 u32 cur_contrast, max_contrast;
181 u32 cur_saturation, max_saturation;
182 u32 cur_hue, max_hue;
c5521706
CW		 183 u32 cur_sharpness, max_sharpness;
184 u32 cur_flicker_filter, max_flicker_filter;
185 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
186 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
187 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
188 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 189 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 190};
191
890f3359 192static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 193{
4ef69c7a 194 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 195}
196
df0e9248
CW		 197static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
198{
199 return container_of(intel_attached_encoder(connector),
200 struct intel_sdvo, base);
201}
202
615fb93f
CW		 203static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
204{
205 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
206}
207
fb7a46f3 208static bool
ea5b213a 209intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 210static bool
211intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
212 struct intel_sdvo_connector *intel_sdvo_connector,
213 int type);
214static bool
215intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
216 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 217
79e53945
JB		 218/**
219 * Writes the SDVOB or SDVOC with the given value, but always writes both
220 * SDVOB and SDVOC to work around apparent hardware issues (according to
221 * comments in the BIOS).
222 */
ea5b213a 223static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 224{
4ef69c7a 225 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 226 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 227 u32 bval = val, cval = val;
228 int i;
229
ea5b213a
CW		 230 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
231 I915_WRITE(intel_sdvo->sdvo_reg, val);
232 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 233 return;
234 }
235
ea5b213a 236 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 237 cval = I915_READ(SDVOC);
238 } else {
239 bval = I915_READ(SDVOB);
240 }
241 /*
242 * Write the registers twice for luck. Sometimes,
243 * writing them only once doesn't appear to 'stick'.
244 * The BIOS does this too. Yay, magic
245 */
246 for (i = 0; i < 2; i++)
247 {
248 I915_WRITE(SDVOB, bval);
249 I915_READ(SDVOB);
250 I915_WRITE(SDVOC, cval);
251 I915_READ(SDVOC);
252 }
253}
254
32aad86f 255static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 256{
79e53945
JB		 257 struct i2c_msg msgs[] = {
258 {
e957d772 259 .addr = intel_sdvo->slave_addr,
79e53945
JB		 260 .flags = 0,
261 .len = 1,
e957d772 262 .buf = &addr,
79e53945
JB		 263 },
264 {
e957d772 265 .addr = intel_sdvo->slave_addr,
79e53945
JB		 266 .flags = I2C_M_RD,
267 .len = 1,
e957d772 268 .buf = ch,
79e53945
JB		 269 }
270 };
32aad86f 271 int ret;
79e53945 272
f899fc64 273 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 274 return true;
79e53945 275
8a4c47f3 276 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 277 return false;
278}
279
79e53945
JB		 280#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
281/** Mapping of command numbers to names, for debug output */
005568be 282static const struct _sdvo_cmd_name {
e2f0ba97 283 u8 cmd;
2e88e40b 284 const char *name;
79e53945 285} sdvo_cmd_names[] = {
0206e353
AJ		 286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
329
330 /* Add the op code for SDVO enhancements */
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
375
376 /* HDMI op code */
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 397};
398
461ed3ca 399#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 400#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 401
ea5b213a 402static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 403 const void *args, int args_len)
79e53945 404{
79e53945
JB		 405 int i;
406
8a4c47f3 407 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 408 SDVO_NAME(intel_sdvo), cmd);
79e53945 409 for (i = 0; i < args_len; i++)
342dc382 410 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 411 for (; i < 8; i++)
342dc382 412 DRM_LOG_KMS(" ");
04ad327f 413 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 414 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 415 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 416 break;
417 }
418 }
04ad327f 419 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 420 DRM_LOG_KMS("(%02X)", cmd);
421 DRM_LOG_KMS("\n");
79e53945 422}
79e53945 423
e957d772
CW		 424static const char *cmd_status_names[] = {
425 "Power on",
426 "Success",
427 "Not supported",
428 "Invalid arg",
429 "Pending",
430 "Target not specified",
431 "Scaling not supported"
432};
433
32aad86f
CW		 434static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
435 const void *args, int args_len)
79e53945 436{
e957d772
CW		 437 u8 buf[args_len*2 + 2], status;
438 struct i2c_msg msgs[args_len + 3];
439 int i, ret;
79e53945 440
ea5b213a 441 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 442
443 for (i = 0; i < args_len; i++) {
e957d772
CW		 444 msgs[i].addr = intel_sdvo->slave_addr;
445 msgs[i].flags = 0;
446 msgs[i].len = 2;
447 msgs[i].buf = buf + 2 *i;
448 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
449 buf[2*i + 1] = ((u8*)args)[i];
450 }
451 msgs[i].addr = intel_sdvo->slave_addr;
452 msgs[i].flags = 0;
453 msgs[i].len = 2;
454 msgs[i].buf = buf + 2*i;
455 buf[2*i + 0] = SDVO_I2C_OPCODE;
456 buf[2*i + 1] = cmd;
457
458 /* the following two are to read the response */
459 status = SDVO_I2C_CMD_STATUS;
460 msgs[i+1].addr = intel_sdvo->slave_addr;
461 msgs[i+1].flags = 0;
462 msgs[i+1].len = 1;
463 msgs[i+1].buf = &status;
464
465 msgs[i+2].addr = intel_sdvo->slave_addr;
466 msgs[i+2].flags = I2C_M_RD;
467 msgs[i+2].len = 1;
468 msgs[i+2].buf = &status;
469
470 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
471 if (ret < 0) {
472 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
473 return false;
474 }
475 if (ret != i+3) {
476 /* failure in I2C transfer */
477 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
478 return false;
479 }
480
e957d772 481 return true;
79e53945
JB		 482}
483
b5c616a7
CW		 484static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
485 void *response, int response_len)
79e53945 486{
b5c616a7
CW		 487 u8 retry = 5;
488 u8 status;
33b52961 489 int i;
79e53945 490
d121a5d2
CW		 491 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
492
b5c616a7
CW		 493 /*
494 * The documentation states that all commands will be
495 * processed within 15µs, and that we need only poll
496 * the status byte a maximum of 3 times in order for the
497 * command to be complete.
498 *
499 * Check 5 times in case the hardware failed to read the docs.
500 */
d121a5d2
CW		 501 if (!intel_sdvo_read_byte(intel_sdvo,
502 SDVO_I2C_CMD_STATUS,
503 &status))
504 goto log_fail;
505
506 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
507 udelay(15);
b5c616a7
CW		 508 if (!intel_sdvo_read_byte(intel_sdvo,
509 SDVO_I2C_CMD_STATUS,
510 &status))
d121a5d2
CW		 511 goto log_fail;
512 }
b5c616a7 513
79e53945 514 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 515 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 516 else
342dc382 517 DRM_LOG_KMS("(??? %d)", status);
79e53945 518
b5c616a7
CW		 519 if (status != SDVO_CMD_STATUS_SUCCESS)
520 goto log_fail;
79e53945 521
b5c616a7
CW		 522 /* Read the command response */
523 for (i = 0; i < response_len; i++) {
524 if (!intel_sdvo_read_byte(intel_sdvo,
525 SDVO_I2C_RETURN_0 + i,
526 &((u8 *)response)[i]))
527 goto log_fail;
e957d772 528 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 529 }
b5c616a7 530 DRM_LOG_KMS("\n");
b5c616a7 531 return true;
79e53945 532
b5c616a7 533log_fail:
d121a5d2 534 DRM_LOG_KMS("... failed\n");
b5c616a7 535 return false;
79e53945
JB		 536}
537
b358d0a6 538static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 539{
540 if (mode->clock >= 100000)
541 return 1;
542 else if (mode->clock >= 50000)
543 return 2;
544 else
545 return 4;
546}
547
e957d772
CW		 548static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
549 u8 ddc_bus)
79e53945 550{
d121a5d2 551 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 552 return intel_sdvo_write_cmd(intel_sdvo,
553 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
554 &ddc_bus, 1);
79e53945
JB		 555}
556
32aad86f 557static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 558{
d121a5d2
CW		 559 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
560 return false;
561
562 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 563}
79e53945 564
32aad86f
CW		 565static bool
566intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
567{
568 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
569 return false;
79e53945 570
32aad86f
CW		 571 return intel_sdvo_read_response(intel_sdvo, value, len);
572}
79e53945 573
32aad86f
CW		 574static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
575{
576 struct intel_sdvo_set_target_input_args targets = {0};
577 return intel_sdvo_set_value(intel_sdvo,
578 SDVO_CMD_SET_TARGET_INPUT,
579 &targets, sizeof(targets));
79e53945
JB		 580}
581
582/**
583 * Return whether each input is trained.
584 *
585 * This function is making an assumption about the layout of the response,
586 * which should be checked against the docs.
587 */
ea5b213a 588static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 589{
590 struct intel_sdvo_get_trained_inputs_response response;
79e53945 591
1a3665c8 592 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 593 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
594 &response, sizeof(response)))
79e53945
JB		 595 return false;
596
597 *input_1 = response.input0_trained;
598 *input_2 = response.input1_trained;
599 return true;
600}
601
ea5b213a 602static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 603 u16 outputs)
604{
32aad86f
CW		 605 return intel_sdvo_set_value(intel_sdvo,
606 SDVO_CMD_SET_ACTIVE_OUTPUTS,
607 &outputs, sizeof(outputs));
79e53945
JB		 608}
609
ea5b213a 610static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 611 int mode)
612{
32aad86f 613 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 614
615 switch (mode) {
616 case DRM_MODE_DPMS_ON:
617 state = SDVO_ENCODER_STATE_ON;
618 break;
619 case DRM_MODE_DPMS_STANDBY:
620 state = SDVO_ENCODER_STATE_STANDBY;
621 break;
622 case DRM_MODE_DPMS_SUSPEND:
623 state = SDVO_ENCODER_STATE_SUSPEND;
624 break;
625 case DRM_MODE_DPMS_OFF:
626 state = SDVO_ENCODER_STATE_OFF;
627 break;
628 }
629
32aad86f
CW		 630 return intel_sdvo_set_value(intel_sdvo,
631 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 632}
633
ea5b213a 634static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 635 int *clock_min,
636 int *clock_max)
637{
638 struct intel_sdvo_pixel_clock_range clocks;
79e53945 639
1a3665c8 640 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 641 if (!intel_sdvo_get_value(intel_sdvo,
642 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
643 &clocks, sizeof(clocks)))
79e53945
JB		 644 return false;
645
646 /* Convert the values from units of 10 kHz to kHz. */
647 *clock_min = clocks.min * 10;
648 *clock_max = clocks.max * 10;
79e53945
JB		 649 return true;
650}
651
ea5b213a 652static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 653 u16 outputs)
654{
32aad86f
CW		 655 return intel_sdvo_set_value(intel_sdvo,
656 SDVO_CMD_SET_TARGET_OUTPUT,
657 &outputs, sizeof(outputs));
79e53945
JB		 658}
659
ea5b213a 660static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 661 struct intel_sdvo_dtd *dtd)
662{
32aad86f
CW		 663 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
664 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 665}
666
ea5b213a 667static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 668 struct intel_sdvo_dtd *dtd)
669{
ea5b213a 670 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 671 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
672}
673
ea5b213a 674static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 675 struct intel_sdvo_dtd *dtd)
676{
ea5b213a 677 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 678 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
679}
680
e2f0ba97 681static bool
ea5b213a 682intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 683 uint16_t clock,
684 uint16_t width,
685 uint16_t height)
686{
687 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 688
e642c6f1 689 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 690 args.clock = clock;
691 args.width = width;
692 args.height = height;
e642c6f1 693 args.interlace = 0;
12682a97 694
ea5b213a
CW		 695 if (intel_sdvo->is_lvds &&
696 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
697 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 698 args.scaled = 1;
699
32aad86f
CW		 700 return intel_sdvo_set_value(intel_sdvo,
701 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
702 &args, sizeof(args));
e2f0ba97
JB		 703}
704
ea5b213a 705static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 706 struct intel_sdvo_dtd *dtd)
707{
1a3665c8
CW		 708 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
709 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 710 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
711 &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
713 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 714}
79e53945 715
ea5b213a 716static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 717{
32aad86f 718 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 719}
720
e2f0ba97 721static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 722 const struct drm_display_mode *mode)
79e53945 723{
e2f0ba97
JB		 724 uint16_t width, height;
725 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
726 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 727
728 width = mode->crtc_hdisplay;
729 height = mode->crtc_vdisplay;
730
731 /* do some mode translations */
732 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
733 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
734
735 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
736 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
737
738 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
739 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
740
e2f0ba97
JB		 741 dtd->part1.clock = mode->clock / 10;
742 dtd->part1.h_active = width & 0xff;
743 dtd->part1.h_blank = h_blank_len & 0xff;
744 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 745 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 746 dtd->part1.v_active = height & 0xff;
747 dtd->part1.v_blank = v_blank_len & 0xff;
748 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 749 ((v_blank_len >> 8) & 0xf);
750
171a9e96 751 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 752 dtd->part2.h_sync_width = h_sync_len & 0xff;
753 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 754 (v_sync_len & 0xf);
e2f0ba97 755 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 756 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
757 ((v_sync_len & 0x30) >> 4);
758
e2f0ba97 759 dtd->part2.dtd_flags = 0x18;
79e53945 760 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 761 dtd->part2.dtd_flags |= 0x2;
79e53945 762 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 763 dtd->part2.dtd_flags |= 0x4;
764
765 dtd->part2.sdvo_flags = 0;
766 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
767 dtd->part2.reserved = 0;
768}
769
770static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 771 const struct intel_sdvo_dtd *dtd)
e2f0ba97 772{
e2f0ba97
JB		 773 mode->hdisplay = dtd->part1.h_active;
774 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
775 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 776 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 777 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
778 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
779 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
780 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
781
782 mode->vdisplay = dtd->part1.v_active;
783 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
784 mode->vsync_start = mode->vdisplay;
785 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 786 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 787 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
788 mode->vsync_end = mode->vsync_start +
789 (dtd->part2.v_sync_off_width & 0xf);
790 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
791 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
792 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
793
794 mode->clock = dtd->part1.clock * 10;
795
171a9e96 796 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 797 if (dtd->part2.dtd_flags & 0x2)
798 mode->flags |= DRM_MODE_FLAG_PHSYNC;
799 if (dtd->part2.dtd_flags & 0x4)
800 mode->flags |= DRM_MODE_FLAG_PVSYNC;
801}
802
e27d8538 803static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 804{
e27d8538 805 struct intel_sdvo_encode encode;
e2f0ba97 806
1a3665c8 807 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 808 return intel_sdvo_get_value(intel_sdvo,
809 SDVO_CMD_GET_SUPP_ENCODE,
810 &encode, sizeof(encode));
e2f0ba97
JB		 811}
812
ea5b213a 813static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 814 uint8_t mode)
e2f0ba97 815{
32aad86f 816 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 817}
818
ea5b213a 819static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 820 uint8_t mode)
821{
32aad86f 822 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 823}
824
825#if 0
ea5b213a 826static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 827{
828 int i, j;
829 uint8_t set_buf_index[2];
830 uint8_t av_split;
831 uint8_t buf_size;
832 uint8_t buf[48];
833 uint8_t *pos;
834
32aad86f 835 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 836
837 for (i = 0; i <= av_split; i++) {
838 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 839 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 840 set_buf_index, 2);
c751ce4f
EA		 841 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
842 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 843
844 pos = buf;
845 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 846 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 847 NULL, 0);
c751ce4f 848 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 849 pos += 8;
850 }
851 }
852}
853#endif
854
3c17fe4b 855static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 856{
857 struct dip_infoframe avi_if = {
858 .type = DIP_TYPE_AVI,
3c17fe4b 859 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 860 .len = DIP_LEN_AVI,
861 };
3c17fe4b
DH		 862 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
863 uint8_t set_buf_index[2] = { 1, 0 };
864 uint64_t *data = (uint64_t *)&avi_if;
865 unsigned i;
866
867 intel_dip_infoframe_csum(&avi_if);
868
d121a5d2
CW		 869 if (!intel_sdvo_set_value(intel_sdvo,
870 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 871 set_buf_index, 2))
872 return false;
873
874 for (i = 0; i < sizeof(avi_if); i += 8) {
d121a5d2
CW		 875 if (!intel_sdvo_set_value(intel_sdvo,
876 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 877 data, 8))
878 return false;
879 data++;
880 }
e2f0ba97 881
d121a5d2
CW		 882 return intel_sdvo_set_value(intel_sdvo,
883 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 884 &tx_rate, 1);
e2f0ba97
JB		 885}
886
32aad86f 887static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 888{
ce6feabd 889 struct intel_sdvo_tv_format format;
40039750 890 uint32_t format_map;
ce6feabd 891
40039750 892 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 893 memset(&format, 0, sizeof(format));
32aad86f 894 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 895
32aad86f
CW		 896 BUILD_BUG_ON(sizeof(format) != 6);
897 return intel_sdvo_set_value(intel_sdvo,
898 SDVO_CMD_SET_TV_FORMAT,
899 &format, sizeof(format));
7026d4ac
ZW		 900}
901
32aad86f
CW		 902static bool
903intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
904 struct drm_display_mode *mode)
e2f0ba97 905{
32aad86f 906 struct intel_sdvo_dtd output_dtd;
79e53945 907
32aad86f
CW		 908 if (!intel_sdvo_set_target_output(intel_sdvo,
909 intel_sdvo->attached_output))
910 return false;
e2f0ba97 911
32aad86f
CW		 912 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
913 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
914 return false;
e2f0ba97 915
32aad86f
CW		 916 return true;
917}
918
919static bool
920intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
921 struct drm_display_mode *mode,
922 struct drm_display_mode *adjusted_mode)
923{
32aad86f
CW		 924 /* Reset the input timing to the screen. Assume always input 0. */
925 if (!intel_sdvo_set_target_input(intel_sdvo))
926 return false;
e2f0ba97 927
32aad86f
CW		 928 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
929 mode->clock / 10,
930 mode->hdisplay,
931 mode->vdisplay))
932 return false;
e2f0ba97 933
32aad86f 934 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 935 &intel_sdvo->input_dtd))
32aad86f 936 return false;
e2f0ba97 937
6c9547ff 938 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 939
32aad86f 940 drm_mode_set_crtcinfo(adjusted_mode, 0);
32aad86f
CW		 941 return true;
942}
12682a97 943
32aad86f
CW		 944static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
945 struct drm_display_mode *mode,
946 struct drm_display_mode *adjusted_mode)
947{
890f3359 948 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 949 int multiplier;
12682a97 950
32aad86f
CW		 951 /* We need to construct preferred input timings based on our
952 * output timings. To do that, we have to set the output
953 * timings, even though this isn't really the right place in
954 * the sequence to do it. Oh well.
955 */
956 if (intel_sdvo->is_tv) {
957 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
958 return false;
12682a97 959
c74696b9
PR		 960 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
961 mode,
962 adjusted_mode);
ea5b213a 963 } else if (intel_sdvo->is_lvds) {
32aad86f 964 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 965 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 966 return false;
12682a97 967
c74696b9
PR		 968 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
969 mode,
970 adjusted_mode);
e2f0ba97 971 }
32aad86f
CW		 972
973 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 974 * SDVO device will factor out the multiplier during mode_set.
32aad86f 975 */
6c9547ff
CW		 976 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
977 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 978
e2f0ba97
JB		 979 return true;
980}
981
982static void intel_sdvo_mode_set(struct drm_encoder *encoder,
983 struct drm_display_mode *mode,
984 struct drm_display_mode *adjusted_mode)
985{
986 struct drm_device *dev = encoder->dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 struct drm_crtc *crtc = encoder->crtc;
989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 990 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 991 u32 sdvox;
e2f0ba97
JB		 992 struct intel_sdvo_in_out_map in_out;
993 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 994 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
995 int rate;
e2f0ba97
JB		 996
997 if (!mode)
998 return;
999
1000 /* First, set the input mapping for the first input to our controlled
1001 * output. This is only correct if we're a single-input device, in
1002 * which case the first input is the output from the appropriate SDVO
1003 * channel on the motherboard. In a two-input device, the first input
1004 * will be SDVOB and the second SDVOC.
1005 */
ea5b213a 1006 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1007 in_out.in1 = 0;
1008
c74696b9
PR		 1009 intel_sdvo_set_value(intel_sdvo,
1010 SDVO_CMD_SET_IN_OUT_MAP,
1011 &in_out, sizeof(in_out));
e2f0ba97 1012
6c9547ff
CW		 1013 /* Set the output timings to the screen */
1014 if (!intel_sdvo_set_target_output(intel_sdvo,
1015 intel_sdvo->attached_output))
1016 return;
e2f0ba97 1017
7026d4ac 1018 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1019 * adjusted_mode.
e2f0ba97 1020 */
6c9547ff
CW		 1021 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1022 input_dtd = intel_sdvo->input_dtd;
1023 } else {
e2f0ba97 1024 /* Set the output timing to the screen */
32aad86f
CW		 1025 if (!intel_sdvo_set_target_output(intel_sdvo,
1026 intel_sdvo->attached_output))
1027 return;
1028
6c9547ff 1029 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1030 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1031 }
79e53945
JB		 1032
1033 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1034 if (!intel_sdvo_set_target_input(intel_sdvo))
1035 return;
79e53945 1036
97aaf910
CW		 1037 if (intel_sdvo->has_hdmi_monitor) {
1038 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1039 intel_sdvo_set_colorimetry(intel_sdvo,
1040 SDVO_COLORIMETRY_RGB256);
1041 intel_sdvo_set_avi_infoframe(intel_sdvo);
1042 } else
1043 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1044
6c9547ff
CW		 1045 if (intel_sdvo->is_tv &&
1046 !intel_sdvo_set_tv_format(intel_sdvo))
1047 return;
e2f0ba97 1048
c74696b9 1049 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1050
6c9547ff
CW		 1051 switch (pixel_multiplier) {
1052 default:
32aad86f
CW		 1053 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1054 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1055 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1056 }
32aad86f
CW		 1057 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1058 return;
79e53945
JB		 1059
1060 /* Set the SDVO control regs. */
a6c45cf0 1061 if (INTEL_INFO(dev)->gen >= 4) {
6714afb1 1062 sdvox = 0;
e953fd7b
CW		 1063 if (intel_sdvo->is_hdmi)
1064 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1065 if (INTEL_INFO(dev)->gen < 5)
1066 sdvox |= SDVO_BORDER_ENABLE;
81a14b46
AJ		 1067 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1068 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1069 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1070 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1071 } else {
6c9547ff 1072 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1073 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1074 case SDVOB:
1075 sdvox &= SDVOB_PRESERVE_MASK;
1076 break;
1077 case SDVOC:
1078 sdvox &= SDVOC_PRESERVE_MASK;
1079 break;
1080 }
1081 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1082 }
79e53945
JB		 1083 if (intel_crtc->pipe == 1)
1084 sdvox |= SDVO_PIPE_B_SELECT;
da79de97 1085 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1086 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1087
a6c45cf0 1088 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1089 /* done in crtc_mode_set as the dpll_md reg must be written early */
1090 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1091 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1092 } else {
6c9547ff 1093 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1094 }
1095
6714afb1
CW		 1096 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1097 INTEL_INFO(dev)->gen < 5)
12682a97 1098 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1099 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1100}
1101
1102static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1103{
1104 struct drm_device *dev = encoder->dev;
1105 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1106 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1107 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1108 u32 temp;
1109
1110 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1111 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1112 if (0)
ea5b213a 1113 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1114
1115 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1116 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1117 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1118 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1119 }
1120 }
1121 } else {
1122 bool input1, input2;
1123 int i;
1124 u8 status;
1125
ea5b213a 1126 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1127 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1128 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1129 for (i = 0; i < 2; i++)
9d0498a2 1130 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1131
32aad86f 1132 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1133 /* Warn if the device reported failure to sync.
1134 * A lot of SDVO devices fail to notify of sync, but it's
1135 * a given it the status is a success, we succeeded.
1136 */
1137 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1138 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1139 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1140 }
1141
1142 if (0)
ea5b213a
CW		 1143 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1144 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1145 }
1146 return;
1147}
1148
79e53945
JB		 1149static int intel_sdvo_mode_valid(struct drm_connector *connector,
1150 struct drm_display_mode *mode)
1151{
df0e9248 1152 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1153
1154 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1155 return MODE_NO_DBLESCAN;
1156
ea5b213a 1157 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1158 return MODE_CLOCK_LOW;
1159
ea5b213a 1160 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1161 return MODE_CLOCK_HIGH;
1162
8545423a 1163 if (intel_sdvo->is_lvds) {
ea5b213a 1164 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1165 return MODE_PANEL;
1166
ea5b213a 1167 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1168 return MODE_PANEL;
1169 }
1170
79e53945
JB		 1171 return MODE_OK;
1172}
1173
ea5b213a 1174static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1175{
1a3665c8 1176 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1177 if (!intel_sdvo_get_value(intel_sdvo,
1178 SDVO_CMD_GET_DEVICE_CAPS,
1179 caps, sizeof(*caps)))
1180 return false;
1181
1182 DRM_DEBUG_KMS("SDVO capabilities:\n"
1183 " vendor_id: %d\n"
1184 " device_id: %d\n"
1185 " device_rev_id: %d\n"
1186 " sdvo_version_major: %d\n"
1187 " sdvo_version_minor: %d\n"
1188 " sdvo_inputs_mask: %d\n"
1189 " smooth_scaling: %d\n"
1190 " sharp_scaling: %d\n"
1191 " up_scaling: %d\n"
1192 " down_scaling: %d\n"
1193 " stall_support: %d\n"
1194 " output_flags: %d\n",
1195 caps->vendor_id,
1196 caps->device_id,
1197 caps->device_rev_id,
1198 caps->sdvo_version_major,
1199 caps->sdvo_version_minor,
1200 caps->sdvo_inputs_mask,
1201 caps->smooth_scaling,
1202 caps->sharp_scaling,
1203 caps->up_scaling,
1204 caps->down_scaling,
1205 caps->stall_support,
1206 caps->output_flags);
1207
1208 return true;
79e53945
JB		 1209}
1210
d2a82a6f
ZW		 1211/* No use! */
1212#if 0
79e53945
JB		 1213struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1214{
1215 struct drm_connector *connector = NULL;
ea5b213a
CW		 1216 struct intel_sdvo *iout = NULL;
1217 struct intel_sdvo *sdvo;
79e53945
JB		 1218
1219 /* find the sdvo connector */
1220 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1221 iout = to_intel_sdvo(connector);
79e53945
JB		 1222
1223 if (iout->type != INTEL_OUTPUT_SDVO)
1224 continue;
1225
1226 sdvo = iout->dev_priv;
1227
c751ce4f 1228 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1229 return connector;
1230
c751ce4f 1231 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1232 return connector;
1233
1234 }
1235
1236 return NULL;
1237}
1238
1239int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1240{
1241 u8 response[2];
1242 u8 status;
ea5b213a 1243 struct intel_sdvo *intel_sdvo;
8a4c47f3 1244 DRM_DEBUG_KMS("\n");
79e53945
JB		 1245
1246 if (!connector)
1247 return 0;
1248
ea5b213a 1249 intel_sdvo = to_intel_sdvo(connector);
79e53945 1250
32aad86f
CW		 1251 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1252 &response, 2) && response[0];
79e53945
JB		 1253}
1254
1255void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1256{
1257 u8 response[2];
1258 u8 status;
ea5b213a 1259 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1260
ea5b213a
CW		 1261 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1262 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1263
1264 if (on) {
ea5b213a
CW		 1265 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1266 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1267
ea5b213a 1268 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1269 } else {
1270 response[0] = 0;
1271 response[1] = 0;
ea5b213a 1272 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1273 }
1274
ea5b213a
CW		 1275 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1276 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1277}
d2a82a6f 1278#endif
79e53945 1279
fb7a46f3 1280static bool
ea5b213a 1281intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1282{
bc65212c
CW		 1283 /* Is there more than one type of output? */
1284 int caps = intel_sdvo->caps.output_flags & 0xf;
1285 return caps & -caps;
fb7a46f3 1286}
1287
f899fc64 1288static struct edid *
e957d772 1289intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1290{
e957d772
CW		 1291 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1292 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1293}
1294
ff482d83
CW		 1295/* Mac mini hack -- use the same DDC as the analog connector */
1296static struct edid *
1297intel_sdvo_get_analog_edid(struct drm_connector *connector)
1298{
f899fc64 1299 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1300
0c1dab89
CW		 1301 return drm_get_edid(connector,
1302 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
ff482d83
CW		 1303}
1304
2b8d33f7 1305enum drm_connector_status
149c36a3 1306intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1307{
df0e9248 1308 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1309 enum drm_connector_status status;
1310 struct edid *edid;
9dff6af8 1311
e957d772 1312 edid = intel_sdvo_get_edid(connector);
57cdaf90 1313
ea5b213a 1314 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1315 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1316
7c3f0a27
ZY		 1317 /*
1318 * Don't use the 1 as the argument of DDC bus switch to get
1319 * the EDID. It is used for SDVO SPD ROM.
1320 */
9d1a903d 1321 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1322 intel_sdvo->ddc_bus = ddc;
1323 edid = intel_sdvo_get_edid(connector);
1324 if (edid)
7c3f0a27 1325 break;
7c3f0a27 1326 }
e957d772
CW		 1327 /*
1328 * If we found the EDID on the other bus,
1329 * assume that is the correct DDC bus.
1330 */
1331 if (edid == NULL)
1332 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1333 }
9d1a903d
CW		 1334
1335 /*
1336 * When there is no edid and no monitor is connected with VGA
1337 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1338 */
ff482d83
CW		 1339 if (edid == NULL)
1340 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1341
2f551c84 1342 status = connector_status_unknown;
9dff6af8 1343 if (edid != NULL) {
149c36a3 1344 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1345 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1346 status = connector_status_connected;
da79de97
CW		 1347 if (intel_sdvo->is_hdmi) {
1348 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1349 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1350 }
13946743
CW		 1351 } else
1352 status = connector_status_disconnected;
149c36a3 1353 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1354 kfree(edid);
1355 }
7f36e7ed
CW		 1356
1357 if (status == connector_status_connected) {
1358 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1359 if (intel_sdvo_connector->force_audio)
da79de97 1360 intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0;
7f36e7ed
CW		 1361 }
1362
2b8d33f7 1363 return status;
9dff6af8
ML		 1364}
1365
7b334fcb 1366static enum drm_connector_status
930a9e28 1367intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1368{
fb7a46f3 1369 uint16_t response;
df0e9248 1370 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1371 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1372 enum drm_connector_status ret;
79e53945 1373
32aad86f 1374 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1375 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1376 return connector_status_unknown;
ba84cd1f
CW		 1377
1378 /* add 30ms delay when the output type might be TV */
1379 if (intel_sdvo->caps.output_flags &
1380 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
d09c23de 1381 mdelay(30);
ba84cd1f 1382
32aad86f
CW		 1383 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1384 return connector_status_unknown;
79e53945 1385
e957d772
CW		 1386 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1387 response & 0xff, response >> 8,
1388 intel_sdvo_connector->output_flag);
e2f0ba97 1389
fb7a46f3 1390 if (response == 0)
79e53945 1391 return connector_status_disconnected;
fb7a46f3 1392
ea5b213a 1393 intel_sdvo->attached_output = response;
14571b4c 1394
97aaf910
CW		 1395 intel_sdvo->has_hdmi_monitor = false;
1396 intel_sdvo->has_hdmi_audio = false;
1397
615fb93f 1398 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1399 ret = connector_status_disconnected;
13946743 1400 else if (IS_TMDS(intel_sdvo_connector))
149c36a3 1401 ret = intel_sdvo_hdmi_sink_detect(connector);
13946743
CW		 1402 else {
1403 struct edid *edid;
1404
1405 /* if we have an edid check it matches the connection */
1406 edid = intel_sdvo_get_edid(connector);
1407 if (edid == NULL)
1408 edid = intel_sdvo_get_analog_edid(connector);
1409 if (edid != NULL) {
1410 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1411 ret = connector_status_disconnected;
1412 else
1413 ret = connector_status_connected;
1414 connector->display_info.raw_edid = NULL;
1415 kfree(edid);
1416 } else
1417 ret = connector_status_connected;
1418 }
14571b4c
ZW		 1419
1420 /* May update encoder flag for like clock for SDVO TV, etc.*/
1421 if (ret == connector_status_connected) {
ea5b213a
CW		 1422 intel_sdvo->is_tv = false;
1423 intel_sdvo->is_lvds = false;
1424 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1425
1426 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1427 intel_sdvo->is_tv = true;
1428 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1429 }
1430 if (response & SDVO_LVDS_MASK)
8545423a 1431 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1432 }
14571b4c
ZW		 1433
1434 return ret;
79e53945
JB		 1435}
1436
e2f0ba97 1437static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1438{
ff482d83 1439 struct edid *edid;
79e53945
JB		 1440
1441 /* set the bus switch and get the modes */
e957d772 1442 edid = intel_sdvo_get_edid(connector);
79e53945 1443
57cdaf90
KP		 1444 /*
1445 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1446 * link between analog and digital outputs. So, if the regular SDVO
1447 * DDC fails, check to see if the analog output is disconnected, in
1448 * which case we'll look there for the digital DDC data.
e2f0ba97 1449 */
f899fc64
CW		 1450 if (edid == NULL)
1451 edid = intel_sdvo_get_analog_edid(connector);
1452
ff482d83 1453 if (edid != NULL) {
13946743
CW		 1454 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1455 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1456 bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector);
1457
1458 if (connector_is_digital == monitor_is_digital) {
0c1dab89
CW		 1459 drm_mode_connector_update_edid_property(connector, edid);
1460 drm_add_edid_modes(connector, edid);
1461 }
13946743 1462
ff482d83
CW		 1463 connector->display_info.raw_edid = NULL;
1464 kfree(edid);
e2f0ba97 1465 }
e2f0ba97
JB		 1466}
1467
1468/*
1469 * Set of SDVO TV modes.
1470 * Note! This is in reply order (see loop in get_tv_modes).
1471 * XXX: all 60Hz refresh?
1472 */
b1f559ec 1473static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1474 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1475 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1477 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1478 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1480 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1481 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1483 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1484 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1486 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1487 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1489 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1490 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1492 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1493 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1495 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1496 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1498 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1499 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1501 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1502 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1504 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1505 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1507 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1508 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1510 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1511 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1513 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1514 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1516 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1517 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1518 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1519 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1520 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1522 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1523 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1525 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1526 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1528 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1529 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1531};
1532
1533static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1534{
df0e9248 1535 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1536 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1537 uint32_t reply = 0, format_map = 0;
1538 int i;
e2f0ba97
JB		 1539
1540 /* Read the list of supported input resolutions for the selected TV
1541 * format.
1542 */
40039750 1543 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1544 memcpy(&tv_res, &format_map,
32aad86f 1545 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1546
32aad86f
CW		 1547 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1548 return;
ce6feabd 1549
32aad86f 1550 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1551 if (!intel_sdvo_write_cmd(intel_sdvo,
1552 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1553 &tv_res, sizeof(tv_res)))
1554 return;
1555 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1556 return;
1557
1558 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1559 if (reply & (1 << i)) {
1560 struct drm_display_mode *nmode;
1561 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1562 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1563 if (nmode)
1564 drm_mode_probed_add(connector, nmode);
1565 }
e2f0ba97
JB		 1566}
1567
7086c87f
ML		 1568static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1569{
df0e9248 1570 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1571 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1572 struct drm_display_mode *newmode;
7086c87f
ML		 1573
1574 /*
1575 * Attempt to get the mode list from DDC.
1576 * Assume that the preferred modes are
1577 * arranged in priority order.
1578 */
f899fc64 1579 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1580 if (list_empty(&connector->probed_modes) == false)
12682a97 1581 goto end;
7086c87f
ML		 1582
1583 /* Fetch modes from VBT */
1584 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1585 newmode = drm_mode_duplicate(connector->dev,
1586 dev_priv->sdvo_lvds_vbt_mode);
1587 if (newmode != NULL) {
1588 /* Guarantee the mode is preferred */
1589 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1590 DRM_MODE_TYPE_DRIVER);
1591 drm_mode_probed_add(connector, newmode);
1592 }
1593 }
12682a97 1594
1595end:
1596 list_for_each_entry(newmode, &connector->probed_modes, head) {
1597 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1598 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1599 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1600
1601 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1602 0);
1603
8545423a 1604 intel_sdvo->is_lvds = true;
12682a97 1605 break;
1606 }
1607 }
1608
7086c87f
ML		 1609}
1610
e2f0ba97
JB		 1611static int intel_sdvo_get_modes(struct drm_connector *connector)
1612{
615fb93f 1613 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1614
615fb93f 1615 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1616 intel_sdvo_get_tv_modes(connector);
615fb93f 1617 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1618 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1619 else
1620 intel_sdvo_get_ddc_modes(connector);
1621
32aad86f 1622 return !list_empty(&connector->probed_modes);
79e53945
JB		 1623}
1624
fcc8d672
CW		 1625static void
1626intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1627{
615fb93f 1628 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1629 struct drm_device *dev = connector->dev;
1630
c5521706
CW		 1631 if (intel_sdvo_connector->left)
1632 drm_property_destroy(dev, intel_sdvo_connector->left);
1633 if (intel_sdvo_connector->right)
1634 drm_property_destroy(dev, intel_sdvo_connector->right);
1635 if (intel_sdvo_connector->top)
1636 drm_property_destroy(dev, intel_sdvo_connector->top);
1637 if (intel_sdvo_connector->bottom)
1638 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1639 if (intel_sdvo_connector->hpos)
1640 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1641 if (intel_sdvo_connector->vpos)
1642 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1643 if (intel_sdvo_connector->saturation)
1644 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1645 if (intel_sdvo_connector->contrast)
1646 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1647 if (intel_sdvo_connector->hue)
1648 drm_property_destroy(dev, intel_sdvo_connector->hue);
1649 if (intel_sdvo_connector->sharpness)
1650 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1651 if (intel_sdvo_connector->flicker_filter)
1652 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1653 if (intel_sdvo_connector->flicker_filter_2d)
1654 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1655 if (intel_sdvo_connector->flicker_filter_adaptive)
1656 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1657 if (intel_sdvo_connector->tv_luma_filter)
1658 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1659 if (intel_sdvo_connector->tv_chroma_filter)
1660 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1661 if (intel_sdvo_connector->dot_crawl)
1662 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1663 if (intel_sdvo_connector->brightness)
1664 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1665}
1666
79e53945
JB		 1667static void intel_sdvo_destroy(struct drm_connector *connector)
1668{
615fb93f 1669 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1670
c5521706 1671 if (intel_sdvo_connector->tv_format)
ce6feabd 1672 drm_property_destroy(connector->dev,
c5521706 1673 intel_sdvo_connector->tv_format);
b9219c5e 1674
d2a82a6f 1675 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1676 drm_sysfs_connector_remove(connector);
1677 drm_connector_cleanup(connector);
d2a82a6f 1678 kfree(connector);
79e53945
JB		 1679}
1680
1aad7ac0
CW		 1681static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1682{
1683 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1684 struct edid *edid;
1685 bool has_audio = false;
1686
1687 if (!intel_sdvo->is_hdmi)
1688 return false;
1689
1690 edid = intel_sdvo_get_edid(connector);
1691 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1692 has_audio = drm_detect_monitor_audio(edid);
1693
1694 return has_audio;
1695}
1696
ce6feabd
ZY		 1697static int
1698intel_sdvo_set_property(struct drm_connector *connector,
1699 struct drm_property *property,
1700 uint64_t val)
1701{
df0e9248 1702 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1703 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1704 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1705 uint16_t temp_value;
32aad86f
CW		 1706 uint8_t cmd;
1707 int ret;
ce6feabd
ZY		 1708
1709 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1710 if (ret)
1711 return ret;
ce6feabd 1712
3f43c48d 1713 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1714 int i = val;
1715 bool has_audio;
1716
1717 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1718 return 0;
1719
1aad7ac0 1720 intel_sdvo_connector->force_audio = i;
7f36e7ed 1721
1aad7ac0
CW		 1722 if (i == 0)
1723 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1724 else
1725 has_audio = i > 0;
7f36e7ed 1726
1aad7ac0 1727 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1728 return 0;
7f36e7ed 1729
1aad7ac0 1730 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1731 goto done;
1732 }
1733
e953fd7b
CW		 1734 if (property == dev_priv->broadcast_rgb_property) {
1735 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1736 return 0;
1737
e953fd7b 1738 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1739 goto done;
1740 }
1741
c5521706
CW		 1742#define CHECK_PROPERTY(name, NAME) \
1743 if (intel_sdvo_connector->name == property) { \
1744 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1745 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1746 cmd = SDVO_CMD_SET_##NAME; \
1747 intel_sdvo_connector->cur_##name = temp_value; \
1748 goto set_value; \
1749 }
1750
1751 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1752 if (val >= TV_FORMAT_NUM)
1753 return -EINVAL;
1754
40039750 1755 if (intel_sdvo->tv_format_index ==
615fb93f 1756 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1757 return 0;
ce6feabd 1758
40039750 1759 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1760 goto done;
32aad86f 1761 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1762 temp_value = val;
c5521706 1763 if (intel_sdvo_connector->left == property) {
b9219c5e 1764 drm_connector_property_set_value(connector,
c5521706 1765 intel_sdvo_connector->right, val);
615fb93f 1766 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1767 return 0;
b9219c5e 1768
615fb93f
CW		 1769 intel_sdvo_connector->left_margin = temp_value;
1770 intel_sdvo_connector->right_margin = temp_value;
1771 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1772 intel_sdvo_connector->left_margin;
b9219c5e 1773 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1774 goto set_value;
1775 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1776 drm_connector_property_set_value(connector,
c5521706 1777 intel_sdvo_connector->left, val);
615fb93f 1778 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1779 return 0;
b9219c5e 1780
615fb93f
CW		 1781 intel_sdvo_connector->left_margin = temp_value;
1782 intel_sdvo_connector->right_margin = temp_value;
1783 temp_value = intel_sdvo_connector->max_hscan -
1784 intel_sdvo_connector->left_margin;
b9219c5e 1785 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1786 goto set_value;
1787 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1788 drm_connector_property_set_value(connector,
c5521706 1789 intel_sdvo_connector->bottom, val);
615fb93f 1790 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1791 return 0;
b9219c5e 1792
615fb93f
CW		 1793 intel_sdvo_connector->top_margin = temp_value;
1794 intel_sdvo_connector->bottom_margin = temp_value;
1795 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1796 intel_sdvo_connector->top_margin;
b9219c5e 1797 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1798 goto set_value;
1799 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1800 drm_connector_property_set_value(connector,
c5521706 1801 intel_sdvo_connector->top, val);
615fb93f 1802 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1803 return 0;
1804
615fb93f
CW		 1805 intel_sdvo_connector->top_margin = temp_value;
1806 intel_sdvo_connector->bottom_margin = temp_value;
1807 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1808 intel_sdvo_connector->top_margin;
b9219c5e 1809 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1810 goto set_value;
1811 }
1812 CHECK_PROPERTY(hpos, HPOS)
1813 CHECK_PROPERTY(vpos, VPOS)
1814 CHECK_PROPERTY(saturation, SATURATION)
1815 CHECK_PROPERTY(contrast, CONTRAST)
1816 CHECK_PROPERTY(hue, HUE)
1817 CHECK_PROPERTY(brightness, BRIGHTNESS)
1818 CHECK_PROPERTY(sharpness, SHARPNESS)
1819 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1820 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1821 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1822 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1823 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1824 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1825 }
b9219c5e 1826
c5521706 1827 return -EINVAL; /* unknown property */
b9219c5e 1828
c5521706
CW		 1829set_value:
1830 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1831 return -EIO;
b9219c5e 1832
b9219c5e 1833
c5521706 1834done:
df0e9248
CW		 1835 if (intel_sdvo->base.base.crtc) {
1836 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1837 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1838 crtc->y, crtc->fb);
1839 }
1840
32aad86f 1841 return 0;
c5521706 1842#undef CHECK_PROPERTY
ce6feabd
ZY		 1843}
1844
79e53945
JB		 1845static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1846 .dpms = intel_sdvo_dpms,
1847 .mode_fixup = intel_sdvo_mode_fixup,
1848 .prepare = intel_encoder_prepare,
1849 .mode_set = intel_sdvo_mode_set,
1850 .commit = intel_encoder_commit,
1851};
1852
1853static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1854 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1855 .detect = intel_sdvo_detect,
1856 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1857 .set_property = intel_sdvo_set_property,
79e53945
JB		 1858 .destroy = intel_sdvo_destroy,
1859};
1860
1861static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1862 .get_modes = intel_sdvo_get_modes,
1863 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1864 .best_encoder = intel_best_encoder,
79e53945
JB		 1865};
1866
b358d0a6 1867static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1868{
890f3359 1869 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1870
ea5b213a 1871 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1872 drm_mode_destroy(encoder->dev,
ea5b213a 1873 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1874
e957d772 1875 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1876 intel_encoder_destroy(encoder);
79e53945
JB		 1877}
1878
1879static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1880 .destroy = intel_sdvo_enc_destroy,
1881};
1882
b66d8424
CW		 1883static void
1884intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1885{
1886 uint16_t mask = 0;
1887 unsigned int num_bits;
1888
1889 /* Make a mask of outputs less than or equal to our own priority in the
1890 * list.
1891 */
1892 switch (sdvo->controlled_output) {
1893 case SDVO_OUTPUT_LVDS1:
1894 mask |= SDVO_OUTPUT_LVDS1;
1895 case SDVO_OUTPUT_LVDS0:
1896 mask |= SDVO_OUTPUT_LVDS0;
1897 case SDVO_OUTPUT_TMDS1:
1898 mask |= SDVO_OUTPUT_TMDS1;
1899 case SDVO_OUTPUT_TMDS0:
1900 mask |= SDVO_OUTPUT_TMDS0;
1901 case SDVO_OUTPUT_RGB1:
1902 mask |= SDVO_OUTPUT_RGB1;
1903 case SDVO_OUTPUT_RGB0:
1904 mask |= SDVO_OUTPUT_RGB0;
1905 break;
1906 }
1907
1908 /* Count bits to find what number we are in the priority list. */
1909 mask &= sdvo->caps.output_flags;
1910 num_bits = hweight16(mask);
1911 /* If more than 3 outputs, default to DDC bus 3 for now. */
1912 if (num_bits > 3)
1913 num_bits = 3;
1914
1915 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1916 sdvo->ddc_bus = 1 << num_bits;
1917}
79e53945 1918
e2f0ba97
JB		 1919/**
1920 * Choose the appropriate DDC bus for control bus switch command for this
1921 * SDVO output based on the controlled output.
1922 *
1923 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1924 * outputs, then LVDS outputs.
1925 */
1926static void
b1083333 1927intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1928 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1929{
b1083333 1930 struct sdvo_device_mapping *mapping;
e2f0ba97 1931
b1083333
AJ		 1932 if (IS_SDVOB(reg))
1933 mapping = &(dev_priv->sdvo_mappings[0]);
1934 else
1935 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1936
b66d8424
CW		 1937 if (mapping->initialized)
1938 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1939 else
1940 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1941}
1942
e957d772
CW		 1943static void
1944intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1945 struct intel_sdvo *sdvo, u32 reg)
1946{
1947 struct sdvo_device_mapping *mapping;
1948 u8 pin, speed;
1949
1950 if (IS_SDVOB(reg))
1951 mapping = &dev_priv->sdvo_mappings[0];
1952 else
1953 mapping = &dev_priv->sdvo_mappings[1];
1954
1955 pin = GMBUS_PORT_DPB;
1956 speed = GMBUS_RATE_1MHZ >> 8;
1957 if (mapping->initialized) {
1958 pin = mapping->i2c_pin;
1959 speed = mapping->i2c_speed;
1960 }
1961
63abf3ed
CW		 1962 if (pin < GMBUS_NUM_PORTS) {
1963 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
1964 intel_gmbus_set_speed(sdvo->i2c, speed);
1965 intel_gmbus_force_bit(sdvo->i2c, true);
1966 } else
1967 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
e957d772
CW		 1968}
1969
e2f0ba97 1970static bool
e27d8538 1971intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1972{
97aaf910 1973 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1974}
1975
714605e4 1976static u8
c751ce4f 1977intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 1978{
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 struct sdvo_device_mapping *my_mapping, *other_mapping;
1981
461ed3ca 1982 if (IS_SDVOB(sdvo_reg)) {
714605e4 1983 my_mapping = &dev_priv->sdvo_mappings[0];
1984 other_mapping = &dev_priv->sdvo_mappings[1];
1985 } else {
1986 my_mapping = &dev_priv->sdvo_mappings[1];
1987 other_mapping = &dev_priv->sdvo_mappings[0];
1988 }
1989
1990 /* If the BIOS described our SDVO device, take advantage of it. */
1991 if (my_mapping->slave_addr)
1992 return my_mapping->slave_addr;
1993
1994 /* If the BIOS only described a different SDVO device, use the
1995 * address that it isn't using.
1996 */
1997 if (other_mapping->slave_addr) {
1998 if (other_mapping->slave_addr == 0x70)
1999 return 0x72;
2000 else
2001 return 0x70;
2002 }
2003
2004 /* No SDVO device info is found for another DVO port,
2005 * so use mapping assumption we had before BIOS parsing.
2006 */
461ed3ca 2007 if (IS_SDVOB(sdvo_reg))
714605e4 2008 return 0x70;
2009 else
2010 return 0x72;
2011}
2012
14571b4c 2013static void
df0e9248
CW		 2014intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2015 struct intel_sdvo *encoder)
14571b4c 2016{
df0e9248
CW		 2017 drm_connector_init(encoder->base.base.dev,
2018 &connector->base.base,
2019 &intel_sdvo_connector_funcs,
2020 connector->base.base.connector_type);
6070a4a9 2021
df0e9248
CW		 2022 drm_connector_helper_add(&connector->base.base,
2023 &intel_sdvo_connector_helper_funcs);
14571b4c 2024
df0e9248
CW		 2025 connector->base.base.interlace_allowed = 0;
2026 connector->base.base.doublescan_allowed = 0;
2027 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2028
df0e9248
CW		 2029 intel_connector_attach_encoder(&connector->base, &encoder->base);
2030 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2031}
6070a4a9 2032
7f36e7ed
CW		 2033static void
2034intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2035{
2036 struct drm_device *dev = connector->base.base.dev;
2037
3f43c48d 2038 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2039 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2040 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2041}
2042
fb7a46f3 2043static bool
ea5b213a 2044intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2045{
4ef69c7a 2046 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c
ZW		 2047 struct drm_connector *connector;
2048 struct intel_connector *intel_connector;
615fb93f 2049 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2050
615fb93f
CW		 2051 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2052 if (!intel_sdvo_connector)
14571b4c
ZW		 2053 return false;
2054
14571b4c 2055 if (device == 0) {
ea5b213a 2056 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2057 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2058 } else if (device == 1) {
ea5b213a 2059 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2060 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2061 }
2062
615fb93f 2063 intel_connector = &intel_sdvo_connector->base;
14571b4c 2064 connector = &intel_connector->base;
eb1f8e4f 2065 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2066 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2067 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2068
e27d8538 2069 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2070 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2071 intel_sdvo->is_hdmi = true;
14571b4c 2072 }
ea5b213a
CW		 2073 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2074 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2075
df0e9248 2076 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2077 if (intel_sdvo->is_hdmi)
2078 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2079
2080 return true;
2081}
2082
2083static bool
ea5b213a 2084intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2085{
4ef69c7a
CW		 2086 struct drm_encoder *encoder = &intel_sdvo->base.base;
2087 struct drm_connector *connector;
2088 struct intel_connector *intel_connector;
2089 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2090
615fb93f
CW		 2091 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2092 if (!intel_sdvo_connector)
2093 return false;
14571b4c 2094
615fb93f 2095 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2096 connector = &intel_connector->base;
2097 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2098 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2099
4ef69c7a
CW		 2100 intel_sdvo->controlled_output |= type;
2101 intel_sdvo_connector->output_flag = type;
14571b4c 2102
4ef69c7a
CW		 2103 intel_sdvo->is_tv = true;
2104 intel_sdvo->base.needs_tv_clock = true;
2105 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2106
df0e9248 2107 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2108
4ef69c7a 2109 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2110 goto err;
14571b4c 2111
4ef69c7a 2112 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2113 goto err;
14571b4c 2114
4ef69c7a 2115 return true;
32aad86f
CW		 2116
2117err:
123d5c01 2118 intel_sdvo_destroy(connector);
32aad86f 2119 return false;
14571b4c
ZW		 2120}
2121
2122static bool
ea5b213a 2123intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2124{
4ef69c7a
CW		 2125 struct drm_encoder *encoder = &intel_sdvo->base.base;
2126 struct drm_connector *connector;
2127 struct intel_connector *intel_connector;
2128 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2129
615fb93f
CW		 2130 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2131 if (!intel_sdvo_connector)
2132 return false;
14571b4c 2133
615fb93f 2134 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2135 connector = &intel_connector->base;
eb1f8e4f 2136 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2137 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2138 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2139
2140 if (device == 0) {
2141 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2142 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2143 } else if (device == 1) {
2144 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2145 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2146 }
2147
2148 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2149 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2150
df0e9248
CW		 2151 intel_sdvo_connector_init(intel_sdvo_connector,
2152 intel_sdvo);
4ef69c7a 2153 return true;
14571b4c
ZW		 2154}
2155
2156static bool
ea5b213a 2157intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2158{
4ef69c7a
CW		 2159 struct drm_encoder *encoder = &intel_sdvo->base.base;
2160 struct drm_connector *connector;
2161 struct intel_connector *intel_connector;
2162 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2163
615fb93f
CW		 2164 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2165 if (!intel_sdvo_connector)
2166 return false;
14571b4c 2167
615fb93f
CW		 2168 intel_connector = &intel_sdvo_connector->base;
2169 connector = &intel_connector->base;
4ef69c7a
CW		 2170 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2171 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2172
2173 if (device == 0) {
2174 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2175 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2176 } else if (device == 1) {
2177 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2178 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2179 }
2180
2181 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2182 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2183
df0e9248 2184 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2185 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2186 goto err;
2187
2188 return true;
2189
2190err:
123d5c01 2191 intel_sdvo_destroy(connector);
32aad86f 2192 return false;
14571b4c
ZW		 2193}
2194
2195static bool
ea5b213a 2196intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2197{
ea5b213a
CW		 2198 intel_sdvo->is_tv = false;
2199 intel_sdvo->base.needs_tv_clock = false;
2200 intel_sdvo->is_lvds = false;
fb7a46f3 2201
14571b4c 2202 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2203
14571b4c 2204 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2205 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2206 return false;
2207
2208 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2209 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2210 return false;
2211
2212 /* TV has no XXX1 function block */
a1f4b7ff 2213 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2214 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2215 return false;
2216
2217 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2218 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2219 return false;
fb7a46f3 2220
14571b4c 2221 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2222 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2223 return false;
2224
2225 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2226 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2227 return false;
2228
2229 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2230 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2231 return false;
2232
2233 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2234 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2235 return false;
fb7a46f3 2236
14571b4c 2237 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2238 unsigned char bytes[2];
2239
ea5b213a
CW		 2240 intel_sdvo->controlled_output = 0;
2241 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2242 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2243 SDVO_NAME(intel_sdvo),
51c8b407 2244 bytes[0], bytes[1]);
14571b4c 2245 return false;
fb7a46f3 2246 }
ea5b213a 2247 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2248
14571b4c 2249 return true;
fb7a46f3 2250}
2251
32aad86f
CW		 2252static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2253 struct intel_sdvo_connector *intel_sdvo_connector,
2254 int type)
ce6feabd 2255{
4ef69c7a 2256 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2257 struct intel_sdvo_tv_format format;
2258 uint32_t format_map, i;
ce6feabd 2259
32aad86f
CW		 2260 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2261 return false;
ce6feabd 2262
1a3665c8 2263 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2264 if (!intel_sdvo_get_value(intel_sdvo,
2265 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2266 &format, sizeof(format)))
2267 return false;
ce6feabd 2268
32aad86f 2269 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2270
2271 if (format_map == 0)
32aad86f 2272 return false;
ce6feabd 2273
615fb93f 2274 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2275 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2276 if (format_map & (1 << i))
2277 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2278
2279
c5521706 2280 intel_sdvo_connector->tv_format =
32aad86f
CW		 2281 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2282 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2283 if (!intel_sdvo_connector->tv_format)
fcc8d672 2284 return false;
ce6feabd 2285
615fb93f 2286 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2287 drm_property_add_enum(
c5521706 2288 intel_sdvo_connector->tv_format, i,
40039750 2289 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2290
40039750 2291 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2292 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2293 intel_sdvo_connector->tv_format, 0);
32aad86f 2294 return true;
ce6feabd
ZY		 2295
2296}
2297
c5521706
CW		 2298#define ENHANCEMENT(name, NAME) do { \
2299 if (enhancements.name) { \
2300 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2301 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2302 return false; \
2303 intel_sdvo_connector->max_##name = data_value[0]; \
2304 intel_sdvo_connector->cur_##name = response; \
2305 intel_sdvo_connector->name = \
2306 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2307 if (!intel_sdvo_connector->name) return false; \
2308 intel_sdvo_connector->name->values[0] = 0; \
2309 intel_sdvo_connector->name->values[1] = data_value[0]; \
2310 drm_connector_attach_property(connector, \
2311 intel_sdvo_connector->name, \
2312 intel_sdvo_connector->cur_##name); \
2313 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2314 data_value[0], data_value[1], response); \
2315 } \
0206e353 2316} while (0)
c5521706
CW		 2317
2318static bool
2319intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2320 struct intel_sdvo_connector *intel_sdvo_connector,
2321 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2322{
4ef69c7a 2323 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2324 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2325 uint16_t response, data_value[2];
2326
c5521706
CW		 2327 /* when horizontal overscan is supported, Add the left/right property */
2328 if (enhancements.overscan_h) {
2329 if (!intel_sdvo_get_value(intel_sdvo,
2330 SDVO_CMD_GET_MAX_OVERSCAN_H,
2331 &data_value, 4))
2332 return false;
32aad86f 2333
c5521706
CW		 2334 if (!intel_sdvo_get_value(intel_sdvo,
2335 SDVO_CMD_GET_OVERSCAN_H,
2336 &response, 2))
2337 return false;
fcc8d672 2338
c5521706
CW		 2339 intel_sdvo_connector->max_hscan = data_value[0];
2340 intel_sdvo_connector->left_margin = data_value[0] - response;
2341 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2342 intel_sdvo_connector->left =
2343 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2344 "left_margin", 2);
2345 if (!intel_sdvo_connector->left)
2346 return false;
fcc8d672 2347
c5521706
CW		 2348 intel_sdvo_connector->left->values[0] = 0;
2349 intel_sdvo_connector->left->values[1] = data_value[0];
2350 drm_connector_attach_property(connector,
2351 intel_sdvo_connector->left,
2352 intel_sdvo_connector->left_margin);
fcc8d672 2353
c5521706
CW		 2354 intel_sdvo_connector->right =
2355 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2356 "right_margin", 2);
2357 if (!intel_sdvo_connector->right)
2358 return false;
32aad86f 2359
c5521706
CW		 2360 intel_sdvo_connector->right->values[0] = 0;
2361 intel_sdvo_connector->right->values[1] = data_value[0];
2362 drm_connector_attach_property(connector,
2363 intel_sdvo_connector->right,
2364 intel_sdvo_connector->right_margin);
2365 DRM_DEBUG_KMS("h_overscan: max %d, "
2366 "default %d, current %d\n",
2367 data_value[0], data_value[1], response);
2368 }
32aad86f 2369
c5521706
CW		 2370 if (enhancements.overscan_v) {
2371 if (!intel_sdvo_get_value(intel_sdvo,
2372 SDVO_CMD_GET_MAX_OVERSCAN_V,
2373 &data_value, 4))
2374 return false;
fcc8d672 2375
c5521706
CW		 2376 if (!intel_sdvo_get_value(intel_sdvo,
2377 SDVO_CMD_GET_OVERSCAN_V,
2378 &response, 2))
2379 return false;
32aad86f 2380
c5521706
CW		 2381 intel_sdvo_connector->max_vscan = data_value[0];
2382 intel_sdvo_connector->top_margin = data_value[0] - response;
2383 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2384 intel_sdvo_connector->top =
2385 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2386 "top_margin", 2);
2387 if (!intel_sdvo_connector->top)
2388 return false;
32aad86f 2389
c5521706
CW		 2390 intel_sdvo_connector->top->values[0] = 0;
2391 intel_sdvo_connector->top->values[1] = data_value[0];
2392 drm_connector_attach_property(connector,
2393 intel_sdvo_connector->top,
2394 intel_sdvo_connector->top_margin);
fcc8d672 2395
c5521706
CW		 2396 intel_sdvo_connector->bottom =
2397 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2398 "bottom_margin", 2);
2399 if (!intel_sdvo_connector->bottom)
2400 return false;
32aad86f 2401
c5521706
CW		 2402 intel_sdvo_connector->bottom->values[0] = 0;
2403 intel_sdvo_connector->bottom->values[1] = data_value[0];
2404 drm_connector_attach_property(connector,
2405 intel_sdvo_connector->bottom,
2406 intel_sdvo_connector->bottom_margin);
2407 DRM_DEBUG_KMS("v_overscan: max %d, "
2408 "default %d, current %d\n",
2409 data_value[0], data_value[1], response);
2410 }
32aad86f 2411
c5521706
CW		 2412 ENHANCEMENT(hpos, HPOS);
2413 ENHANCEMENT(vpos, VPOS);
2414 ENHANCEMENT(saturation, SATURATION);
2415 ENHANCEMENT(contrast, CONTRAST);
2416 ENHANCEMENT(hue, HUE);
2417 ENHANCEMENT(sharpness, SHARPNESS);
2418 ENHANCEMENT(brightness, BRIGHTNESS);
2419 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2420 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2421 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2422 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2423 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2424
e044218a
CW		 2425 if (enhancements.dot_crawl) {
2426 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2427 return false;
2428
2429 intel_sdvo_connector->max_dot_crawl = 1;
2430 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2431 intel_sdvo_connector->dot_crawl =
2432 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2433 if (!intel_sdvo_connector->dot_crawl)
2434 return false;
2435
2436 intel_sdvo_connector->dot_crawl->values[0] = 0;
2437 intel_sdvo_connector->dot_crawl->values[1] = 1;
2438 drm_connector_attach_property(connector,
2439 intel_sdvo_connector->dot_crawl,
2440 intel_sdvo_connector->cur_dot_crawl);
2441 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2442 }
2443
c5521706
CW		 2444 return true;
2445}
32aad86f 2446
c5521706
CW		 2447static bool
2448intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2449 struct intel_sdvo_connector *intel_sdvo_connector,
2450 struct intel_sdvo_enhancements_reply enhancements)
2451{
4ef69c7a 2452 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2453 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2454 uint16_t response, data_value[2];
32aad86f 2455
c5521706 2456 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2457
c5521706
CW		 2458 return true;
2459}
2460#undef ENHANCEMENT
32aad86f 2461
c5521706
CW		 2462static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2463 struct intel_sdvo_connector *intel_sdvo_connector)
2464{
2465 union {
2466 struct intel_sdvo_enhancements_reply reply;
2467 uint16_t response;
2468 } enhancements;
32aad86f 2469
1a3665c8
CW		 2470 BUILD_BUG_ON(sizeof(enhancements) != 2);
2471
cf9a2f3a
CW		 2472 enhancements.response = 0;
2473 intel_sdvo_get_value(intel_sdvo,
2474 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2475 &enhancements, sizeof(enhancements));
c5521706
CW		 2476 if (enhancements.response == 0) {
2477 DRM_DEBUG_KMS("No enhancement is supported\n");
2478 return true;
b9219c5e 2479 }
32aad86f 2480
c5521706
CW		 2481 if (IS_TV(intel_sdvo_connector))
2482 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2483 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2484 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2485 else
2486 return true;
e957d772
CW		 2487}
2488
2489static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2490 struct i2c_msg *msgs,
2491 int num)
2492{
2493 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2494
e957d772
CW		 2495 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2496 return -EIO;
2497
2498 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2499}
2500
2501static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2502{
2503 struct intel_sdvo *sdvo = adapter->algo_data;
2504 return sdvo->i2c->algo->functionality(sdvo->i2c);
2505}
2506
2507static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2508 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2509 .functionality = intel_sdvo_ddc_proxy_func
2510};
2511
2512static bool
2513intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2514 struct drm_device *dev)
2515{
2516 sdvo->ddc.owner = THIS_MODULE;
2517 sdvo->ddc.class = I2C_CLASS_DDC;
2518 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2519 sdvo->ddc.dev.parent = &dev->pdev->dev;
2520 sdvo->ddc.algo_data = sdvo;
2521 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2522
2523 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2524}
2525
c751ce4f 2526bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2527{
b01f2c3a 2528 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2529 struct intel_encoder *intel_encoder;
ea5b213a 2530 struct intel_sdvo *intel_sdvo;
79e53945 2531 int i;
79e53945 2532
ea5b213a
CW		 2533 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2534 if (!intel_sdvo)
7d57382e 2535 return false;
79e53945 2536
56184e3d
CW		 2537 intel_sdvo->sdvo_reg = sdvo_reg;
2538 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2539 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2540 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2541 kfree(intel_sdvo);
2542 return false;
2543 }
2544
56184e3d 2545 /* encoder type will be decided later */
ea5b213a 2546 intel_encoder = &intel_sdvo->base;
21d40d37 2547 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2548 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2549
79e53945
JB		 2550 /* Read the regs to test if we can talk to the device */
2551 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2552 u8 byte;
2553
2554 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
8a4c47f3 2555 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2556 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2557 goto err;
79e53945
JB		 2558 }
2559 }
2560
f899fc64 2561 if (IS_SDVOB(sdvo_reg))
b01f2c3a 2562 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2563 else
b01f2c3a 2564 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2565
4ef69c7a 2566 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2567
af901ca1 2568 /* In default case sdvo lvds is false */
32aad86f 2569 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2570 goto err;
79e53945 2571
ea5b213a
CW		 2572 if (intel_sdvo_output_setup(intel_sdvo,
2573 intel_sdvo->caps.output_flags) != true) {
51c8b407 2574 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2575 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2576 goto err;
79e53945
JB		 2577 }
2578
ea5b213a 2579 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2580
79e53945 2581 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2582 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2583 goto err;
79e53945 2584
32aad86f
CW		 2585 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2586 &intel_sdvo->pixel_clock_min,
2587 &intel_sdvo->pixel_clock_max))
f899fc64 2588 goto err;
79e53945 2589
8a4c47f3 2590 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2591 "clock range %dMHz - %dMHz, "
2592 "input 1: %c, input 2: %c, "
2593 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2594 SDVO_NAME(intel_sdvo),
2595 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2596 intel_sdvo->caps.device_rev_id,
2597 intel_sdvo->pixel_clock_min / 1000,
2598 intel_sdvo->pixel_clock_max / 1000,
2599 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2600 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2601 /* check currently supported outputs */
ea5b213a 2602 intel_sdvo->caps.output_flags &
79e53945 2603 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2604 intel_sdvo->caps.output_flags &
79e53945 2605 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2606 return true;
79e53945 2607
f899fc64 2608err:
373a3cf7 2609 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2610 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2611 kfree(intel_sdvo);
79e53945 2612
7d57382e 2613 return false;
79e53945 2614}
Linux kernel - Deliverables
This page took 0.909345 seconds and 5 git commands to generate.