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drm/i915: make SDVO TV-out work for multifunction devices
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
83 * i830_sdvo_get_capabilities()
84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
890f3359 205static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 206{
4ef69c7a 207 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
212 return container_of(intel_attached_encoder(connector),
213 struct intel_sdvo, base);
214}
215
615fb93f
CW		 216static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
217{
218 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
219}
220
fb7a46f3 221static bool
ea5b213a 222intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 223static bool
224intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
225 struct intel_sdvo_connector *intel_sdvo_connector,
226 int type);
227static bool
228intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
229 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 230
79e53945
JB		 231/**
232 * Writes the SDVOB or SDVOC with the given value, but always writes both
233 * SDVOB and SDVOC to work around apparent hardware issues (according to
234 * comments in the BIOS).
235 */
ea5b213a 236static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 237{
4ef69c7a 238 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 239 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 240 u32 bval = val, cval = val;
241 int i;
242
ea5b213a
CW		 243 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
244 I915_WRITE(intel_sdvo->sdvo_reg, val);
245 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 246 return;
247 }
248
e2debe91
PZ		 249 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
250 cval = I915_READ(GEN3_SDVOC);
251 else
252 bval = I915_READ(GEN3_SDVOB);
253
79e53945
JB		 254 /*
255 * Write the registers twice for luck. Sometimes,
256 * writing them only once doesn't appear to 'stick'.
257 * The BIOS does this too. Yay, magic
258 */
259 for (i = 0; i < 2; i++)
260 {
e2debe91
PZ		 261 I915_WRITE(GEN3_SDVOB, bval);
262 I915_READ(GEN3_SDVOB);
263 I915_WRITE(GEN3_SDVOC, cval);
264 I915_READ(GEN3_SDVOC);
79e53945
JB		 265 }
266}
267
32aad86f 268static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 269{
79e53945
JB		 270 struct i2c_msg msgs[] = {
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = 0,
274 .len = 1,
e957d772 275 .buf = &addr,
79e53945
JB		 276 },
277 {
e957d772 278 .addr = intel_sdvo->slave_addr,
79e53945
JB		 279 .flags = I2C_M_RD,
280 .len = 1,
e957d772 281 .buf = ch,
79e53945
JB		 282 }
283 };
32aad86f 284 int ret;
79e53945 285
f899fc64 286 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 287 return true;
79e53945 288
8a4c47f3 289 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 290 return false;
291}
292
79e53945
JB		 293#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
294/** Mapping of command numbers to names, for debug output */
005568be 295static const struct _sdvo_cmd_name {
e2f0ba97 296 u8 cmd;
2e88e40b 297 const char *name;
79e53945 298} sdvo_cmd_names[] = {
0206e353
AJ		 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
342
343 /* Add the op code for SDVO enhancements */
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
388
389 /* HDMI op code */
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 410};
411
eef4eacb 412#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 413
ea5b213a 414static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 415 const void *args, int args_len)
79e53945 416{
79e53945
JB		 417 int i;
418
8a4c47f3 419 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 420 SDVO_NAME(intel_sdvo), cmd);
79e53945 421 for (i = 0; i < args_len; i++)
342dc382 422 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 423 for (; i < 8; i++)
342dc382 424 DRM_LOG_KMS(" ");
04ad327f 425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 426 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 427 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 428 break;
429 }
430 }
04ad327f 431 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 432 DRM_LOG_KMS("(%02X)", cmd);
433 DRM_LOG_KMS("\n");
79e53945 434}
79e53945 435
e957d772
CW		 436static const char *cmd_status_names[] = {
437 "Power on",
438 "Success",
439 "Not supported",
440 "Invalid arg",
441 "Pending",
442 "Target not specified",
443 "Scaling not supported"
444};
445
32aad86f
CW		 446static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
447 const void *args, int args_len)
79e53945 448{
3bf3f452
BW		 449 u8 *buf, status;
450 struct i2c_msg *msgs;
451 int i, ret = true;
452
0274df3e 453 /* Would be simpler to allocate both in one go ? */
5c67eeb6 454 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 455 if (!buf)
456 return false;
457
458 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 459 if (!msgs) {
460 kfree(buf);
3bf3f452 461 return false;
0274df3e 462 }
79e53945 463
ea5b213a 464 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 465
466 for (i = 0; i < args_len; i++) {
e957d772
CW		 467 msgs[i].addr = intel_sdvo->slave_addr;
468 msgs[i].flags = 0;
469 msgs[i].len = 2;
470 msgs[i].buf = buf + 2 *i;
471 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
472 buf[2*i + 1] = ((u8*)args)[i];
473 }
474 msgs[i].addr = intel_sdvo->slave_addr;
475 msgs[i].flags = 0;
476 msgs[i].len = 2;
477 msgs[i].buf = buf + 2*i;
478 buf[2*i + 0] = SDVO_I2C_OPCODE;
479 buf[2*i + 1] = cmd;
480
481 /* the following two are to read the response */
482 status = SDVO_I2C_CMD_STATUS;
483 msgs[i+1].addr = intel_sdvo->slave_addr;
484 msgs[i+1].flags = 0;
485 msgs[i+1].len = 1;
486 msgs[i+1].buf = &status;
487
488 msgs[i+2].addr = intel_sdvo->slave_addr;
489 msgs[i+2].flags = I2C_M_RD;
490 msgs[i+2].len = 1;
491 msgs[i+2].buf = &status;
492
493 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
494 if (ret < 0) {
495 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 496 ret = false;
497 goto out;
e957d772
CW		 498 }
499 if (ret != i+3) {
500 /* failure in I2C transfer */
501 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 502 ret = false;
e957d772
CW		 503 }
504
3bf3f452
BW		 505out:
506 kfree(msgs);
507 kfree(buf);
508 return ret;
79e53945
JB		 509}
510
b5c616a7
CW		 511static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
512 void *response, int response_len)
79e53945 513{
fc37381c 514 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 515 u8 status;
33b52961 516 int i;
79e53945 517
d121a5d2
CW		 518 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
519
b5c616a7
CW		 520 /*
521 * The documentation states that all commands will be
522 * processed within 15µs, and that we need only poll
523 * the status byte a maximum of 3 times in order for the
524 * command to be complete.
525 *
526 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 527 *
528 * Also beware that the first response by many devices is to
529 * reply PENDING and stall for time. TVs are notorious for
530 * requiring longer than specified to complete their replies.
531 * Originally (in the DDX long ago), the delay was only ever 15ms
532 * with an additional delay of 30ms applied for TVs added later after
533 * many experiments. To accommodate both sets of delays, we do a
534 * sequence of slow checks if the device is falling behind and fails
535 * to reply within 5*15µs.
b5c616a7 536 */
d121a5d2
CW		 537 if (!intel_sdvo_read_byte(intel_sdvo,
538 SDVO_I2C_CMD_STATUS,
539 &status))
540 goto log_fail;
541
fc37381c
CW		 542 while (status == SDVO_CMD_STATUS_PENDING && --retry) {
543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
b5c616a7
CW		 548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
d121a5d2
CW		 551 goto log_fail;
552 }
b5c616a7 553
79e53945 554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 556 else
342dc382 557 DRM_LOG_KMS("(??? %d)", status);
79e53945 558
b5c616a7
CW		 559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
79e53945 561
b5c616a7
CW		 562 /* Read the command response */
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
e957d772 568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 569 }
b5c616a7 570 DRM_LOG_KMS("\n");
b5c616a7 571 return true;
79e53945 572
b5c616a7 573log_fail:
d121a5d2 574 DRM_LOG_KMS("... failed\n");
b5c616a7 575 return false;
79e53945
JB		 576}
577
b358d0a6 578static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 579{
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586}
587
e957d772
CW		 588static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
79e53945 590{
d121a5d2 591 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
79e53945
JB		 595}
596
32aad86f 597static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 598{
d121a5d2
CW		 599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 603}
79e53945 604
32aad86f
CW		 605static bool
606intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607{
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
79e53945 610
32aad86f
CW		 611 return intel_sdvo_read_response(intel_sdvo, value, len);
612}
79e53945 613
32aad86f
CW		 614static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615{
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
79e53945
JB		 620}
621
622/**
623 * Return whether each input is trained.
624 *
625 * This function is making an assumption about the layout of the response,
626 * which should be checked against the docs.
627 */
ea5b213a 628static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 629{
630 struct intel_sdvo_get_trained_inputs_response response;
79e53945 631
1a3665c8 632 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
79e53945
JB		 635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640}
641
ea5b213a 642static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 643 u16 outputs)
644{
32aad86f
CW		 645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
79e53945
JB		 648}
649
4ac41f47
DV		 650static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652{
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656}
657
ea5b213a 658static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 659 int mode)
660{
32aad86f 661 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
32aad86f
CW		 678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 680}
681
ea5b213a 682static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int *clock_min,
684 int *clock_max)
685{
686 struct intel_sdvo_pixel_clock_range clocks;
79e53945 687
1a3665c8 688 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
79e53945
JB		 692 return false;
693
694 /* Convert the values from units of 10 kHz to kHz. */
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
79e53945
JB		 697 return true;
698}
699
ea5b213a 700static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 701 u16 outputs)
702{
32aad86f
CW		 703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
79e53945
JB		 706}
707
ea5b213a 708static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 709 struct intel_sdvo_dtd *dtd)
710{
32aad86f
CW		 711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 713}
714
ea5b213a 715static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 716 struct intel_sdvo_dtd *dtd)
717{
ea5b213a 718 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 719 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
720}
721
ea5b213a 722static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 723 struct intel_sdvo_dtd *dtd)
724{
ea5b213a 725 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 726 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
727}
728
e2f0ba97 729static bool
ea5b213a 730intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 731 uint16_t clock,
732 uint16_t width,
733 uint16_t height)
734{
735 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 736
e642c6f1 737 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 738 args.clock = clock;
739 args.width = width;
740 args.height = height;
e642c6f1 741 args.interlace = 0;
12682a97 742
ea5b213a
CW		 743 if (intel_sdvo->is_lvds &&
744 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
745 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 746 args.scaled = 1;
747
32aad86f
CW		 748 return intel_sdvo_set_value(intel_sdvo,
749 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
750 &args, sizeof(args));
e2f0ba97
JB		 751}
752
ea5b213a 753static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 754 struct intel_sdvo_dtd *dtd)
755{
1a3665c8
CW		 756 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
757 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 758 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
759 &dtd->part1, sizeof(dtd->part1)) &&
760 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
761 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 762}
79e53945 763
ea5b213a 764static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 765{
32aad86f 766 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 767}
768
e2f0ba97 769static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 770 const struct drm_display_mode *mode)
79e53945 771{
e2f0ba97
JB		 772 uint16_t width, height;
773 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
774 uint16_t h_sync_offset, v_sync_offset;
6651819b 775 int mode_clock;
79e53945 776
c6ebd4c0
DV		 777 width = mode->hdisplay;
778 height = mode->vdisplay;
79e53945
JB		 779
780 /* do some mode translations */
c6ebd4c0
DV		 781 h_blank_len = mode->htotal - mode->hdisplay;
782 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 783
c6ebd4c0
DV		 784 v_blank_len = mode->vtotal - mode->vdisplay;
785 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 786
c6ebd4c0
DV		 787 h_sync_offset = mode->hsync_start - mode->hdisplay;
788 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 789
6651819b 790 mode_clock = mode->clock;
6651819b
DV		 791 mode_clock /= 10;
792 dtd->part1.clock = mode_clock;
793
e2f0ba97
JB		 794 dtd->part1.h_active = width & 0xff;
795 dtd->part1.h_blank = h_blank_len & 0xff;
796 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 797 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 798 dtd->part1.v_active = height & 0xff;
799 dtd->part1.v_blank = v_blank_len & 0xff;
800 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 801 ((v_blank_len >> 8) & 0xf);
802
171a9e96 803 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 804 dtd->part2.h_sync_width = h_sync_len & 0xff;
805 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 806 (v_sync_len & 0xf);
e2f0ba97 807 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 808 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
809 ((v_sync_len & 0x30) >> 4);
810
e2f0ba97 811 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 812 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
813 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 814 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 815 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 816 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 817 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 818
819 dtd->part2.sdvo_flags = 0;
820 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
821 dtd->part2.reserved = 0;
822}
823
824static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 825 const struct intel_sdvo_dtd *dtd)
e2f0ba97 826{
e2f0ba97
JB		 827 mode->hdisplay = dtd->part1.h_active;
828 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
829 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 830 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 831 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
832 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
833 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
834 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
835
836 mode->vdisplay = dtd->part1.v_active;
837 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
838 mode->vsync_start = mode->vdisplay;
839 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 840 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 841 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
842 mode->vsync_end = mode->vsync_start +
843 (dtd->part2.v_sync_off_width & 0xf);
844 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
845 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
846 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
847
848 mode->clock = dtd->part1.clock * 10;
849
171a9e96 850 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 851 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
852 mode->flags |= DRM_MODE_FLAG_INTERLACE;
853 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 854 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 855 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 856 mode->flags |= DRM_MODE_FLAG_PVSYNC;
857}
858
e27d8538 859static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 860{
e27d8538 861 struct intel_sdvo_encode encode;
e2f0ba97 862
1a3665c8 863 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 864 return intel_sdvo_get_value(intel_sdvo,
865 SDVO_CMD_GET_SUPP_ENCODE,
866 &encode, sizeof(encode));
e2f0ba97
JB		 867}
868
ea5b213a 869static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 870 uint8_t mode)
e2f0ba97 871{
32aad86f 872 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 873}
874
ea5b213a 875static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 876 uint8_t mode)
877{
32aad86f 878 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 879}
880
881#if 0
ea5b213a 882static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 883{
884 int i, j;
885 uint8_t set_buf_index[2];
886 uint8_t av_split;
887 uint8_t buf_size;
888 uint8_t buf[48];
889 uint8_t *pos;
890
32aad86f 891 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 892
893 for (i = 0; i <= av_split; i++) {
894 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 895 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 896 set_buf_index, 2);
c751ce4f
EA		 897 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
898 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 899
900 pos = buf;
901 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 902 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 903 NULL, 0);
c751ce4f 904 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 905 pos += 8;
906 }
907 }
908}
909#endif
910
b6e0e543
DV		 911static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
912 unsigned if_index, uint8_t tx_rate,
913 uint8_t *data, unsigned length)
914{
915 uint8_t set_buf_index[2] = { if_index, 0 };
916 uint8_t hbuf_size, tmp[8];
917 int i;
918
919 if (!intel_sdvo_set_value(intel_sdvo,
920 SDVO_CMD_SET_HBUF_INDEX,
921 set_buf_index, 2))
922 return false;
923
924 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
925 &hbuf_size, 1))
926 return false;
927
928 /* Buffer size is 0 based, hooray! */
929 hbuf_size++;
930
931 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
932 if_index, length, hbuf_size);
933
934 for (i = 0; i < hbuf_size; i += 8) {
935 memset(tmp, 0, 8);
936 if (i < length)
937 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
938
939 if (!intel_sdvo_set_value(intel_sdvo,
940 SDVO_CMD_SET_HBUF_DATA,
941 tmp, 8))
942 return false;
943 }
944
945 return intel_sdvo_set_value(intel_sdvo,
946 SDVO_CMD_SET_HBUF_TXRATE,
947 &tx_rate, 1);
948}
949
abedc077
VS		 950static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
951 const struct drm_display_mode *adjusted_mode)
e2f0ba97
JB		 952{
953 struct dip_infoframe avi_if = {
954 .type = DIP_TYPE_AVI,
3c17fe4b 955 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 956 .len = DIP_LEN_AVI,
957 };
81014b9d 958 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
50f3b016 959 struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
3c17fe4b 960
abedc077 961 if (intel_sdvo->rgb_quant_range_selectable) {
50f3b016 962 if (intel_crtc->config.limited_color_range)
abedc077
VS		 963 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
964 else
965 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
966 }
967
96b219fa
VS		 968 avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
969
3c17fe4b
DH		 970 intel_dip_infoframe_csum(&avi_if);
971
81014b9d
DV		 972 /* sdvo spec says that the ecc is handled by the hw, and it looks like
973 * we must not send the ecc field, either. */
974 memcpy(sdvo_data, &avi_if, 3);
975 sdvo_data[3] = avi_if.checksum;
976 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
977
b6e0e543
DV		 978 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
979 SDVO_HBUF_TX_VSYNC,
980 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 981}
982
32aad86f 983static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 984{
ce6feabd 985 struct intel_sdvo_tv_format format;
40039750 986 uint32_t format_map;
ce6feabd 987
40039750 988 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 989 memset(&format, 0, sizeof(format));
32aad86f 990 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 991
32aad86f
CW		 992 BUILD_BUG_ON(sizeof(format) != 6);
993 return intel_sdvo_set_value(intel_sdvo,
994 SDVO_CMD_SET_TV_FORMAT,
995 &format, sizeof(format));
7026d4ac
ZW		 996}
997
32aad86f
CW		 998static bool
999intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1000 const struct drm_display_mode *mode)
e2f0ba97 1001{
32aad86f 1002 struct intel_sdvo_dtd output_dtd;
79e53945 1003
32aad86f
CW		 1004 if (!intel_sdvo_set_target_output(intel_sdvo,
1005 intel_sdvo->attached_output))
1006 return false;
e2f0ba97 1007
32aad86f
CW		 1008 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1009 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1010 return false;
e2f0ba97 1011
32aad86f
CW		 1012 return true;
1013}
1014
c9a29698
DV		 1015/* Asks the sdvo controller for the preferred input mode given the output mode.
1016 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1017static bool
c9a29698 1018intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1019 const struct drm_display_mode *mode,
c9a29698 1020 struct drm_display_mode *adjusted_mode)
32aad86f 1021{
c9a29698
DV		 1022 struct intel_sdvo_dtd input_dtd;
1023
32aad86f
CW		 1024 /* Reset the input timing to the screen. Assume always input 0. */
1025 if (!intel_sdvo_set_target_input(intel_sdvo))
1026 return false;
e2f0ba97 1027
32aad86f
CW		 1028 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1029 mode->clock / 10,
1030 mode->hdisplay,
1031 mode->vdisplay))
1032 return false;
e2f0ba97 1033
32aad86f 1034 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1035 &input_dtd))
32aad86f 1036 return false;
e2f0ba97 1037
c9a29698 1038 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1039 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1040
32aad86f
CW		 1041 return true;
1042}
12682a97 1043
70484559
DV		 1044static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1045{
1046 unsigned dotclock = pipe_config->adjusted_mode.clock;
1047 struct dpll *clock = &pipe_config->dpll;
1048
1049 /* SDVO TV has fixed PLL values depend on its clock range,
1050 this mirrors vbios setting. */
1051 if (dotclock >= 100000 && dotclock < 140500) {
1052 clock->p1 = 2;
1053 clock->p2 = 10;
1054 clock->n = 3;
1055 clock->m1 = 16;
1056 clock->m2 = 8;
1057 } else if (dotclock >= 140500 && dotclock <= 200000) {
1058 clock->p1 = 1;
1059 clock->p2 = 10;
1060 clock->n = 6;
1061 clock->m1 = 12;
1062 clock->m2 = 8;
1063 } else {
1064 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1065 }
1066
1067 pipe_config->clock_set = true;
1068}
1069
6cc5f341
DV		 1070static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1071 struct intel_crtc_config *pipe_config)
32aad86f 1072{
6cc5f341
DV		 1073 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1074 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1075 struct drm_display_mode *mode = &pipe_config->requested_mode;
12682a97 1076
5d2d38dd
DV		 1077 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1078 pipe_config->pipe_bpp = 8*3;
1079
5bfe2ac0
DV		 1080 if (HAS_PCH_SPLIT(encoder->base.dev))
1081 pipe_config->has_pch_encoder = true;
1082
32aad86f
CW		 1083 /* We need to construct preferred input timings based on our
1084 * output timings. To do that, we have to set the output
1085 * timings, even though this isn't really the right place in
1086 * the sequence to do it. Oh well.
1087 */
1088 if (intel_sdvo->is_tv) {
1089 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1090 return false;
12682a97 1091
c9a29698
DV		 1092 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1093 mode,
1094 adjusted_mode);
09ede541 1095 pipe_config->sdvo_tv_clock = true;
ea5b213a 1096 } else if (intel_sdvo->is_lvds) {
32aad86f 1097 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1098 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1099 return false;
12682a97 1100
c9a29698
DV		 1101 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1102 mode,
1103 adjusted_mode);
e2f0ba97 1104 }
32aad86f
CW		 1105
1106 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1107 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1108 */
6cc5f341
DV		 1109 pipe_config->pixel_multiplier =
1110 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1111 adjusted_mode->clock *= pipe_config->pixel_multiplier;
32aad86f 1112
55bc60db
VS		 1113 if (intel_sdvo->color_range_auto) {
1114 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1115 /* FIXME: This bit is only valid when using TMDS encoding and 8
1116 * bit per color mode. */
55bc60db 1117 if (intel_sdvo->has_hdmi_monitor &&
18316c8c 1118 drm_match_cea_mode(adjusted_mode) > 1)
4f3a8bc7 1119 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1120 else
1121 intel_sdvo->color_range = 0;
1122 }
1123
3685a8f3 1124 if (intel_sdvo->color_range)
50f3b016 1125 pipe_config->limited_color_range = true;
3685a8f3 1126
70484559
DV		 1127 /* Clock computation needs to happen after pixel multiplier. */
1128 if (intel_sdvo->is_tv)
1129 i9xx_adjust_sdvo_tv_clock(pipe_config);
1130
e2f0ba97
JB		 1131 return true;
1132}
1133
6cc5f341 1134static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
e2f0ba97 1135{
6cc5f341 1136 struct drm_device *dev = intel_encoder->base.dev;
e2f0ba97 1137 struct drm_i915_private *dev_priv = dev->dev_private;
6cc5f341 1138 struct drm_crtc *crtc = intel_encoder->base.crtc;
e2f0ba97 1139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 1140 struct drm_display_mode *adjusted_mode =
1141 &intel_crtc->config.adjusted_mode;
1142 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
1143 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
6c9547ff 1144 u32 sdvox;
e2f0ba97 1145 struct intel_sdvo_in_out_map in_out;
6651819b 1146 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1147 int rate;
e2f0ba97
JB		 1148
1149 if (!mode)
1150 return;
1151
1152 /* First, set the input mapping for the first input to our controlled
1153 * output. This is only correct if we're a single-input device, in
1154 * which case the first input is the output from the appropriate SDVO
1155 * channel on the motherboard. In a two-input device, the first input
1156 * will be SDVOB and the second SDVOC.
1157 */
ea5b213a 1158 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1159 in_out.in1 = 0;
1160
c74696b9
PR		 1161 intel_sdvo_set_value(intel_sdvo,
1162 SDVO_CMD_SET_IN_OUT_MAP,
1163 &in_out, sizeof(in_out));
e2f0ba97 1164
6c9547ff
CW		 1165 /* Set the output timings to the screen */
1166 if (!intel_sdvo_set_target_output(intel_sdvo,
1167 intel_sdvo->attached_output))
1168 return;
e2f0ba97 1169
6651819b
DV		 1170 /* lvds has a special fixed output timing. */
1171 if (intel_sdvo->is_lvds)
1172 intel_sdvo_get_dtd_from_mode(&output_dtd,
1173 intel_sdvo->sdvo_lvds_fixed_mode);
1174 else
1175 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1176 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1177 DRM_INFO("Setting output timings on %s failed\n",
1178 SDVO_NAME(intel_sdvo));
79e53945
JB		 1179
1180 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1181 if (!intel_sdvo_set_target_input(intel_sdvo))
1182 return;
79e53945 1183
97aaf910
CW		 1184 if (intel_sdvo->has_hdmi_monitor) {
1185 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1186 intel_sdvo_set_colorimetry(intel_sdvo,
1187 SDVO_COLORIMETRY_RGB256);
abedc077 1188 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1189 } else
1190 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1191
6c9547ff
CW		 1192 if (intel_sdvo->is_tv &&
1193 !intel_sdvo_set_tv_format(intel_sdvo))
1194 return;
e2f0ba97 1195
6651819b
DV		 1196 /* We have tried to get input timing in mode_fixup, and filled into
1197 * adjusted_mode.
1198 */
1199 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
e751823d
EE		 1200 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1201 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1202 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1203 DRM_INFO("Setting input timings on %s failed\n",
1204 SDVO_NAME(intel_sdvo));
79e53945 1205
6cc5f341 1206 switch (intel_crtc->config.pixel_multiplier) {
6c9547ff 1207 default:
32aad86f
CW		 1208 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1209 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1210 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1211 }
32aad86f
CW		 1212 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1213 return;
79e53945
JB		 1214
1215 /* Set the SDVO control regs. */
a6c45cf0 1216 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1217 /* The real mode polarity is set by the SDVO commands, using
1218 * struct intel_sdvo_dtd. */
1219 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1220 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1221 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1222 if (INTEL_INFO(dev)->gen < 5)
1223 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1224 } else {
6c9547ff 1225 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1226 switch (intel_sdvo->sdvo_reg) {
e2debe91 1227 case GEN3_SDVOB:
e2f0ba97
JB		 1228 sdvox &= SDVOB_PRESERVE_MASK;
1229 break;
e2debe91 1230 case GEN3_SDVOC:
e2f0ba97
JB		 1231 sdvox &= SDVOC_PRESERVE_MASK;
1232 break;
1233 }
1234 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1235 }
3573c410
PZ		 1236
1237 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
dc0fa718 1238 sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
3573c410 1239 else
dc0fa718 1240 sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
3573c410 1241
da79de97 1242 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1243 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1244
a6c45cf0 1245 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1246 /* done in crtc_mode_set as the dpll_md reg must be written early */
1247 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1248 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1249 } else {
6cc5f341
DV		 1250 sdvox |= (intel_crtc->config.pixel_multiplier - 1)
1251 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1252 }
1253
6714afb1
CW		 1254 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1255 INTEL_INFO(dev)->gen < 5)
12682a97 1256 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1257 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1258}
1259
4ac41f47 1260static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1261{
4ac41f47
DV		 1262 struct intel_sdvo_connector *intel_sdvo_connector =
1263 to_intel_sdvo_connector(&connector->base);
1264 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1265 u16 active_outputs;
1266
1267 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1268
1269 if (active_outputs & intel_sdvo_connector->output_flag)
1270 return true;
1271 else
1272 return false;
1273}
1274
1275static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1276 enum pipe *pipe)
1277{
1278 struct drm_device *dev = encoder->base.dev;
79e53945 1279 struct drm_i915_private *dev_priv = dev->dev_private;
4ac41f47 1280 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
7a7d1fb7 1281 u16 active_outputs;
4ac41f47
DV		 1282 u32 tmp;
1283
1284 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1285 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1286
7a7d1fb7 1287 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1288 return false;
1289
1290 if (HAS_PCH_CPT(dev))
1291 *pipe = PORT_TO_PIPE_CPT(tmp);
1292 else
1293 *pipe = PORT_TO_PIPE(tmp);
1294
1295 return true;
1296}
1297
ce22c320
DV		 1298static void intel_disable_sdvo(struct intel_encoder *encoder)
1299{
1300 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1301 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1302 u32 temp;
1303
1304 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1305 if (0)
1306 intel_sdvo_set_encoder_power_state(intel_sdvo,
1307 DRM_MODE_DPMS_OFF);
1308
1309 temp = I915_READ(intel_sdvo->sdvo_reg);
1310 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1311 /* HW workaround for IBX, we need to move the port to
1312 * transcoder A before disabling it. */
1313 if (HAS_PCH_IBX(encoder->base.dev)) {
1314 struct drm_crtc *crtc = encoder->base.crtc;
1315 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1316
1317 if (temp & SDVO_PIPE_B_SELECT) {
1318 temp &= ~SDVO_PIPE_B_SELECT;
1319 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1320 POSTING_READ(intel_sdvo->sdvo_reg);
1321
1322 /* Again we need to write this twice. */
1323 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1324 POSTING_READ(intel_sdvo->sdvo_reg);
1325
1326 /* Transcoder selection bits only update
1327 * effectively on vblank. */
1328 if (crtc)
1329 intel_wait_for_vblank(encoder->base.dev, pipe);
1330 else
1331 msleep(50);
1332 }
1333 }
1334
ce22c320
DV		 1335 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1336 }
1337}
1338
1339static void intel_enable_sdvo(struct intel_encoder *encoder)
1340{
1341 struct drm_device *dev = encoder->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1344 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1345 u32 temp;
ce22c320
DV		 1346 bool input1, input2;
1347 int i;
1348 u8 status;
1349
1350 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1351 if ((temp & SDVO_ENABLE) == 0) {
1352 /* HW workaround for IBX, we need to move the port
dc0fa718
PZ		 1353 * to transcoder A before disabling it, so restore it here. */
1354 if (HAS_PCH_IBX(dev))
1355 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
776ca7cf 1356
ce22c320 1357 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1358 }
ce22c320
DV		 1359 for (i = 0; i < 2; i++)
1360 intel_wait_for_vblank(dev, intel_crtc->pipe);
1361
1362 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1363 /* Warn if the device reported failure to sync.
1364 * A lot of SDVO devices fail to notify of sync, but it's
1365 * a given it the status is a success, we succeeded.
1366 */
1367 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1368 DRM_DEBUG_KMS("First %s output reported failure to "
1369 "sync\n", SDVO_NAME(intel_sdvo));
1370 }
1371
1372 if (0)
1373 intel_sdvo_set_encoder_power_state(intel_sdvo,
1374 DRM_MODE_DPMS_ON);
1375 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1376}
1377
b2cabb0e 1378static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1379{
b2cabb0e
DV		 1380 struct drm_crtc *crtc;
1381 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1382
1383 /* dvo supports only 2 dpms states. */
1384 if (mode != DRM_MODE_DPMS_ON)
1385 mode = DRM_MODE_DPMS_OFF;
1386
1387 if (mode == connector->dpms)
1388 return;
1389
1390 connector->dpms = mode;
1391
1392 /* Only need to change hw state when actually enabled */
1393 crtc = intel_sdvo->base.base.crtc;
1394 if (!crtc) {
1395 intel_sdvo->base.connectors_active = false;
1396 return;
1397 }
79e53945
JB		 1398
1399 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1400 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1401 if (0)
ea5b213a 1402 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1403
b2cabb0e
DV		 1404 intel_sdvo->base.connectors_active = false;
1405
1406 intel_crtc_update_dpms(crtc);
79e53945 1407 } else {
b2cabb0e
DV		 1408 intel_sdvo->base.connectors_active = true;
1409
1410 intel_crtc_update_dpms(crtc);
79e53945
JB		 1411
1412 if (0)
ea5b213a
CW		 1413 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1414 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1415 }
0a91ca29 1416
b980514c 1417 intel_modeset_check_state(connector->dev);
79e53945
JB		 1418}
1419
79e53945
JB		 1420static int intel_sdvo_mode_valid(struct drm_connector *connector,
1421 struct drm_display_mode *mode)
1422{
df0e9248 1423 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1424
1425 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1426 return MODE_NO_DBLESCAN;
1427
ea5b213a 1428 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1429 return MODE_CLOCK_LOW;
1430
ea5b213a 1431 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1432 return MODE_CLOCK_HIGH;
1433
8545423a 1434 if (intel_sdvo->is_lvds) {
ea5b213a 1435 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1436 return MODE_PANEL;
1437
ea5b213a 1438 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1439 return MODE_PANEL;
1440 }
1441
79e53945
JB		 1442 return MODE_OK;
1443}
1444
ea5b213a 1445static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1446{
1a3665c8 1447 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1448 if (!intel_sdvo_get_value(intel_sdvo,
1449 SDVO_CMD_GET_DEVICE_CAPS,
1450 caps, sizeof(*caps)))
1451 return false;
1452
1453 DRM_DEBUG_KMS("SDVO capabilities:\n"
1454 " vendor_id: %d\n"
1455 " device_id: %d\n"
1456 " device_rev_id: %d\n"
1457 " sdvo_version_major: %d\n"
1458 " sdvo_version_minor: %d\n"
1459 " sdvo_inputs_mask: %d\n"
1460 " smooth_scaling: %d\n"
1461 " sharp_scaling: %d\n"
1462 " up_scaling: %d\n"
1463 " down_scaling: %d\n"
1464 " stall_support: %d\n"
1465 " output_flags: %d\n",
1466 caps->vendor_id,
1467 caps->device_id,
1468 caps->device_rev_id,
1469 caps->sdvo_version_major,
1470 caps->sdvo_version_minor,
1471 caps->sdvo_inputs_mask,
1472 caps->smooth_scaling,
1473 caps->sharp_scaling,
1474 caps->up_scaling,
1475 caps->down_scaling,
1476 caps->stall_support,
1477 caps->output_flags);
1478
1479 return true;
79e53945
JB		 1480}
1481
5fa7ac9c 1482static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1483{
768b107e 1484 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1485 uint16_t hotplug;
79e53945 1486
768b107e
DV		 1487 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1488 * on the line. */
1489 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1490 return 0;
768b107e 1491
5fa7ac9c
JN		 1492 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1493 &hotplug, sizeof(hotplug)))
1494 return 0;
768b107e 1495
5fa7ac9c 1496 return hotplug;
79e53945
JB		 1497}
1498
cc68c81a 1499static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1500{
cc68c81a 1501 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1502
5fa7ac9c
JN		 1503 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1504 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1505}
1506
fb7a46f3 1507static bool
ea5b213a 1508intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1509{
bc65212c 1510 /* Is there more than one type of output? */
2294488d 1511 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1512}
1513
f899fc64 1514static struct edid *
e957d772 1515intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1516{
e957d772
CW		 1517 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1518 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1519}
1520
ff482d83
CW		 1521/* Mac mini hack -- use the same DDC as the analog connector */
1522static struct edid *
1523intel_sdvo_get_analog_edid(struct drm_connector *connector)
1524{
f899fc64 1525 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1526
0c1dab89 1527 return drm_get_edid(connector,
3bd7d909
DK		 1528 intel_gmbus_get_adapter(dev_priv,
1529 dev_priv->crt_ddc_pin));
ff482d83
CW		 1530}
1531
c43b5634 1532static enum drm_connector_status
8bf38485 1533intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1534{
df0e9248 1535 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1536 enum drm_connector_status status;
1537 struct edid *edid;
9dff6af8 1538
e957d772 1539 edid = intel_sdvo_get_edid(connector);
57cdaf90 1540
ea5b213a 1541 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1542 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1543
7c3f0a27
ZY		 1544 /*
1545 * Don't use the 1 as the argument of DDC bus switch to get
1546 * the EDID. It is used for SDVO SPD ROM.
1547 */
9d1a903d 1548 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1549 intel_sdvo->ddc_bus = ddc;
1550 edid = intel_sdvo_get_edid(connector);
1551 if (edid)
7c3f0a27 1552 break;
7c3f0a27 1553 }
e957d772
CW		 1554 /*
1555 * If we found the EDID on the other bus,
1556 * assume that is the correct DDC bus.
1557 */
1558 if (edid == NULL)
1559 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1560 }
9d1a903d
CW		 1561
1562 /*
1563 * When there is no edid and no monitor is connected with VGA
1564 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1565 */
ff482d83
CW		 1566 if (edid == NULL)
1567 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1568
2f551c84 1569 status = connector_status_unknown;
9dff6af8 1570 if (edid != NULL) {
149c36a3 1571 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1572 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1573 status = connector_status_connected;
da79de97
CW		 1574 if (intel_sdvo->is_hdmi) {
1575 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1576 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1577 intel_sdvo->rgb_quant_range_selectable =
1578 drm_rgb_quant_range_selectable(edid);
da79de97 1579 }
13946743
CW		 1580 } else
1581 status = connector_status_disconnected;
9d1a903d
CW		 1582 kfree(edid);
1583 }
7f36e7ed
CW		 1584
1585 if (status == connector_status_connected) {
1586 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1587 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1588 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1589 }
1590
2b8d33f7 1591 return status;
9dff6af8
ML		 1592}
1593
52220085
CW		 1594static bool
1595intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1596 struct edid *edid)
1597{
1598 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1599 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1600
1601 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1602 connector_is_digital, monitor_is_digital);
1603 return connector_is_digital == monitor_is_digital;
1604}
1605
7b334fcb 1606static enum drm_connector_status
930a9e28 1607intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1608{
fb7a46f3 1609 uint16_t response;
df0e9248 1610 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1611 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1612 enum drm_connector_status ret;
79e53945 1613
fc37381c
CW		 1614 if (!intel_sdvo_get_value(intel_sdvo,
1615 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1616 &response, 2))
32aad86f 1617 return connector_status_unknown;
79e53945 1618
e957d772
CW		 1619 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1620 response & 0xff, response >> 8,
1621 intel_sdvo_connector->output_flag);
e2f0ba97 1622
fb7a46f3 1623 if (response == 0)
79e53945 1624 return connector_status_disconnected;
fb7a46f3 1625
ea5b213a 1626 intel_sdvo->attached_output = response;
14571b4c 1627
97aaf910
CW		 1628 intel_sdvo->has_hdmi_monitor = false;
1629 intel_sdvo->has_hdmi_audio = false;
abedc077 1630 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1631
615fb93f 1632 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1633 ret = connector_status_disconnected;
13946743 1634 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1635 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1636 else {
1637 struct edid *edid;
1638
1639 /* if we have an edid check it matches the connection */
1640 edid = intel_sdvo_get_edid(connector);
1641 if (edid == NULL)
1642 edid = intel_sdvo_get_analog_edid(connector);
1643 if (edid != NULL) {
52220085
CW		 1644 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1645 edid))
13946743 1646 ret = connector_status_connected;
52220085
CW		 1647 else
1648 ret = connector_status_disconnected;
1649
13946743
CW		 1650 kfree(edid);
1651 } else
1652 ret = connector_status_connected;
1653 }
14571b4c
ZW		 1654
1655 /* May update encoder flag for like clock for SDVO TV, etc.*/
1656 if (ret == connector_status_connected) {
ea5b213a
CW		 1657 intel_sdvo->is_tv = false;
1658 intel_sdvo->is_lvds = false;
14571b4c 1659
09ede541 1660 if (response & SDVO_TV_MASK)
ea5b213a 1661 intel_sdvo->is_tv = true;
14571b4c 1662 if (response & SDVO_LVDS_MASK)
8545423a 1663 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1664 }
14571b4c
ZW		 1665
1666 return ret;
79e53945
JB		 1667}
1668
e2f0ba97 1669static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1670{
ff482d83 1671 struct edid *edid;
79e53945
JB		 1672
1673 /* set the bus switch and get the modes */
e957d772 1674 edid = intel_sdvo_get_edid(connector);
79e53945 1675
57cdaf90
KP		 1676 /*
1677 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1678 * link between analog and digital outputs. So, if the regular SDVO
1679 * DDC fails, check to see if the analog output is disconnected, in
1680 * which case we'll look there for the digital DDC data.
e2f0ba97 1681 */
f899fc64
CW		 1682 if (edid == NULL)
1683 edid = intel_sdvo_get_analog_edid(connector);
1684
ff482d83 1685 if (edid != NULL) {
52220085
CW		 1686 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1687 edid)) {
0c1dab89
CW		 1688 drm_mode_connector_update_edid_property(connector, edid);
1689 drm_add_edid_modes(connector, edid);
1690 }
13946743 1691
ff482d83 1692 kfree(edid);
e2f0ba97 1693 }
e2f0ba97
JB		 1694}
1695
1696/*
1697 * Set of SDVO TV modes.
1698 * Note! This is in reply order (see loop in get_tv_modes).
1699 * XXX: all 60Hz refresh?
1700 */
b1f559ec 1701static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1702 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1703 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1705 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1706 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1708 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1709 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1710 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1711 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1712 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1713 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1714 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1715 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1716 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1717 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1718 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1720 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1721 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1722 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1723 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1724 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1725 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1726 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1727 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1728 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1729 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1730 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1731 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1732 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1733 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1734 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1735 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1736 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1738 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1739 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1740 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1741 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1742 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1744 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1745 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1746 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1747 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1748 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1750 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1751 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1752 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1753 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1754 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1756 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1757 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1759};
1760
1761static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1762{
df0e9248 1763 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1764 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1765 uint32_t reply = 0, format_map = 0;
1766 int i;
e2f0ba97
JB		 1767
1768 /* Read the list of supported input resolutions for the selected TV
1769 * format.
1770 */
40039750 1771 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1772 memcpy(&tv_res, &format_map,
32aad86f 1773 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1774
32aad86f
CW		 1775 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1776 return;
ce6feabd 1777
32aad86f 1778 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1779 if (!intel_sdvo_write_cmd(intel_sdvo,
1780 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1781 &tv_res, sizeof(tv_res)))
1782 return;
1783 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1784 return;
1785
1786 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1787 if (reply & (1 << i)) {
1788 struct drm_display_mode *nmode;
1789 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1790 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1791 if (nmode)
1792 drm_mode_probed_add(connector, nmode);
1793 }
e2f0ba97
JB		 1794}
1795
7086c87f
ML		 1796static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1797{
df0e9248 1798 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1799 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1800 struct drm_display_mode *newmode;
7086c87f
ML		 1801
1802 /*
1803 * Attempt to get the mode list from DDC.
1804 * Assume that the preferred modes are
1805 * arranged in priority order.
1806 */
f899fc64 1807 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1808 if (list_empty(&connector->probed_modes) == false)
12682a97 1809 goto end;
7086c87f
ML		 1810
1811 /* Fetch modes from VBT */
1812 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1813 newmode = drm_mode_duplicate(connector->dev,
1814 dev_priv->sdvo_lvds_vbt_mode);
1815 if (newmode != NULL) {
1816 /* Guarantee the mode is preferred */
1817 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1818 DRM_MODE_TYPE_DRIVER);
1819 drm_mode_probed_add(connector, newmode);
1820 }
1821 }
12682a97 1822
1823end:
1824 list_for_each_entry(newmode, &connector->probed_modes, head) {
1825 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1826 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1827 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1828
8545423a 1829 intel_sdvo->is_lvds = true;
12682a97 1830 break;
1831 }
1832 }
1833
7086c87f
ML		 1834}
1835
e2f0ba97
JB		 1836static int intel_sdvo_get_modes(struct drm_connector *connector)
1837{
615fb93f 1838 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1839
615fb93f 1840 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1841 intel_sdvo_get_tv_modes(connector);
615fb93f 1842 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1843 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1844 else
1845 intel_sdvo_get_ddc_modes(connector);
1846
32aad86f 1847 return !list_empty(&connector->probed_modes);
79e53945
JB		 1848}
1849
fcc8d672
CW		 1850static void
1851intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1852{
615fb93f 1853 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1854 struct drm_device *dev = connector->dev;
1855
c5521706
CW		 1856 if (intel_sdvo_connector->left)
1857 drm_property_destroy(dev, intel_sdvo_connector->left);
1858 if (intel_sdvo_connector->right)
1859 drm_property_destroy(dev, intel_sdvo_connector->right);
1860 if (intel_sdvo_connector->top)
1861 drm_property_destroy(dev, intel_sdvo_connector->top);
1862 if (intel_sdvo_connector->bottom)
1863 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1864 if (intel_sdvo_connector->hpos)
1865 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1866 if (intel_sdvo_connector->vpos)
1867 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1868 if (intel_sdvo_connector->saturation)
1869 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1870 if (intel_sdvo_connector->contrast)
1871 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1872 if (intel_sdvo_connector->hue)
1873 drm_property_destroy(dev, intel_sdvo_connector->hue);
1874 if (intel_sdvo_connector->sharpness)
1875 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1876 if (intel_sdvo_connector->flicker_filter)
1877 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1878 if (intel_sdvo_connector->flicker_filter_2d)
1879 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1880 if (intel_sdvo_connector->flicker_filter_adaptive)
1881 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1882 if (intel_sdvo_connector->tv_luma_filter)
1883 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1884 if (intel_sdvo_connector->tv_chroma_filter)
1885 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1886 if (intel_sdvo_connector->dot_crawl)
1887 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1888 if (intel_sdvo_connector->brightness)
1889 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1890}
1891
79e53945
JB		 1892static void intel_sdvo_destroy(struct drm_connector *connector)
1893{
615fb93f 1894 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1895
c5521706 1896 if (intel_sdvo_connector->tv_format)
ce6feabd 1897 drm_property_destroy(connector->dev,
c5521706 1898 intel_sdvo_connector->tv_format);
b9219c5e 1899
d2a82a6f 1900 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1901 drm_sysfs_connector_remove(connector);
1902 drm_connector_cleanup(connector);
4b745b1e 1903 kfree(intel_sdvo_connector);
79e53945
JB		 1904}
1905
1aad7ac0
CW		 1906static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1907{
1908 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1909 struct edid *edid;
1910 bool has_audio = false;
1911
1912 if (!intel_sdvo->is_hdmi)
1913 return false;
1914
1915 edid = intel_sdvo_get_edid(connector);
1916 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1917 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 1918 kfree(edid);
1aad7ac0
CW		 1919
1920 return has_audio;
1921}
1922
ce6feabd
ZY		 1923static int
1924intel_sdvo_set_property(struct drm_connector *connector,
1925 struct drm_property *property,
1926 uint64_t val)
1927{
df0e9248 1928 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1929 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1930 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1931 uint16_t temp_value;
32aad86f
CW		 1932 uint8_t cmd;
1933 int ret;
ce6feabd 1934
662595df 1935 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 1936 if (ret)
1937 return ret;
ce6feabd 1938
3f43c48d 1939 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1940 int i = val;
1941 bool has_audio;
1942
1943 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1944 return 0;
1945
1aad7ac0 1946 intel_sdvo_connector->force_audio = i;
7f36e7ed 1947
c3e5f67b 1948 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1949 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1950 else
c3e5f67b 1951 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1952
1aad7ac0 1953 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1954 return 0;
7f36e7ed 1955
1aad7ac0 1956 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1957 goto done;
1958 }
1959
e953fd7b 1960 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 1961 switch (val) {
1962 case INTEL_BROADCAST_RGB_AUTO:
1963 intel_sdvo->color_range_auto = true;
1964 break;
1965 case INTEL_BROADCAST_RGB_FULL:
1966 intel_sdvo->color_range_auto = false;
1967 intel_sdvo->color_range = 0;
1968 break;
1969 case INTEL_BROADCAST_RGB_LIMITED:
1970 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 1971 /* FIXME: this bit is only valid when using TMDS
1972 * encoding and 8 bit per color mode. */
1973 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1974 break;
1975 default:
1976 return -EINVAL;
1977 }
7f36e7ed
CW		 1978 goto done;
1979 }
1980
c5521706
CW		 1981#define CHECK_PROPERTY(name, NAME) \
1982 if (intel_sdvo_connector->name == property) { \
1983 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1984 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1985 cmd = SDVO_CMD_SET_##NAME; \
1986 intel_sdvo_connector->cur_##name = temp_value; \
1987 goto set_value; \
1988 }
1989
1990 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1991 if (val >= TV_FORMAT_NUM)
1992 return -EINVAL;
1993
40039750 1994 if (intel_sdvo->tv_format_index ==
615fb93f 1995 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1996 return 0;
ce6feabd 1997
40039750 1998 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1999 goto done;
32aad86f 2000 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2001 temp_value = val;
c5521706 2002 if (intel_sdvo_connector->left == property) {
662595df 2003 drm_object_property_set_value(&connector->base,
c5521706 2004 intel_sdvo_connector->right, val);
615fb93f 2005 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2006 return 0;
b9219c5e 2007
615fb93f
CW		 2008 intel_sdvo_connector->left_margin = temp_value;
2009 intel_sdvo_connector->right_margin = temp_value;
2010 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2011 intel_sdvo_connector->left_margin;
b9219c5e 2012 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2013 goto set_value;
2014 } else if (intel_sdvo_connector->right == property) {
662595df 2015 drm_object_property_set_value(&connector->base,
c5521706 2016 intel_sdvo_connector->left, val);
615fb93f 2017 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2018 return 0;
b9219c5e 2019
615fb93f
CW		 2020 intel_sdvo_connector->left_margin = temp_value;
2021 intel_sdvo_connector->right_margin = temp_value;
2022 temp_value = intel_sdvo_connector->max_hscan -
2023 intel_sdvo_connector->left_margin;
b9219c5e 2024 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2025 goto set_value;
2026 } else if (intel_sdvo_connector->top == property) {
662595df 2027 drm_object_property_set_value(&connector->base,
c5521706 2028 intel_sdvo_connector->bottom, val);
615fb93f 2029 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2030 return 0;
b9219c5e 2031
615fb93f
CW		 2032 intel_sdvo_connector->top_margin = temp_value;
2033 intel_sdvo_connector->bottom_margin = temp_value;
2034 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2035 intel_sdvo_connector->top_margin;
b9219c5e 2036 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2037 goto set_value;
2038 } else if (intel_sdvo_connector->bottom == property) {
662595df 2039 drm_object_property_set_value(&connector->base,
c5521706 2040 intel_sdvo_connector->top, val);
615fb93f 2041 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2042 return 0;
2043
615fb93f
CW		 2044 intel_sdvo_connector->top_margin = temp_value;
2045 intel_sdvo_connector->bottom_margin = temp_value;
2046 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2047 intel_sdvo_connector->top_margin;
b9219c5e 2048 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2049 goto set_value;
2050 }
2051 CHECK_PROPERTY(hpos, HPOS)
2052 CHECK_PROPERTY(vpos, VPOS)
2053 CHECK_PROPERTY(saturation, SATURATION)
2054 CHECK_PROPERTY(contrast, CONTRAST)
2055 CHECK_PROPERTY(hue, HUE)
2056 CHECK_PROPERTY(brightness, BRIGHTNESS)
2057 CHECK_PROPERTY(sharpness, SHARPNESS)
2058 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2059 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2060 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2061 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2062 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2063 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2064 }
b9219c5e 2065
c5521706 2066 return -EINVAL; /* unknown property */
b9219c5e 2067
c5521706
CW		 2068set_value:
2069 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2070 return -EIO;
b9219c5e 2071
b9219c5e 2072
c5521706 2073done:
c0c36b94
CW		 2074 if (intel_sdvo->base.base.crtc)
2075 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2076
32aad86f 2077 return 0;
c5521706 2078#undef CHECK_PROPERTY
ce6feabd
ZY		 2079}
2080
79e53945 2081static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2082 .dpms = intel_sdvo_dpms,
79e53945
JB		 2083 .detect = intel_sdvo_detect,
2084 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2085 .set_property = intel_sdvo_set_property,
79e53945
JB		 2086 .destroy = intel_sdvo_destroy,
2087};
2088
2089static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2090 .get_modes = intel_sdvo_get_modes,
2091 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2092 .best_encoder = intel_best_encoder,
79e53945
JB		 2093};
2094
b358d0a6 2095static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2096{
890f3359 2097 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 2098
ea5b213a 2099 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2100 drm_mode_destroy(encoder->dev,
ea5b213a 2101 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2102
e957d772 2103 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2104 intel_encoder_destroy(encoder);
79e53945
JB		 2105}
2106
2107static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2108 .destroy = intel_sdvo_enc_destroy,
2109};
2110
b66d8424
CW		 2111static void
2112intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2113{
2114 uint16_t mask = 0;
2115 unsigned int num_bits;
2116
2117 /* Make a mask of outputs less than or equal to our own priority in the
2118 * list.
2119 */
2120 switch (sdvo->controlled_output) {
2121 case SDVO_OUTPUT_LVDS1:
2122 mask |= SDVO_OUTPUT_LVDS1;
2123 case SDVO_OUTPUT_LVDS0:
2124 mask |= SDVO_OUTPUT_LVDS0;
2125 case SDVO_OUTPUT_TMDS1:
2126 mask |= SDVO_OUTPUT_TMDS1;
2127 case SDVO_OUTPUT_TMDS0:
2128 mask |= SDVO_OUTPUT_TMDS0;
2129 case SDVO_OUTPUT_RGB1:
2130 mask |= SDVO_OUTPUT_RGB1;
2131 case SDVO_OUTPUT_RGB0:
2132 mask |= SDVO_OUTPUT_RGB0;
2133 break;
2134 }
2135
2136 /* Count bits to find what number we are in the priority list. */
2137 mask &= sdvo->caps.output_flags;
2138 num_bits = hweight16(mask);
2139 /* If more than 3 outputs, default to DDC bus 3 for now. */
2140 if (num_bits > 3)
2141 num_bits = 3;
2142
2143 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2144 sdvo->ddc_bus = 1 << num_bits;
2145}
79e53945 2146
e2f0ba97
JB		 2147/**
2148 * Choose the appropriate DDC bus for control bus switch command for this
2149 * SDVO output based on the controlled output.
2150 *
2151 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2152 * outputs, then LVDS outputs.
2153 */
2154static void
b1083333 2155intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2156 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2157{
b1083333 2158 struct sdvo_device_mapping *mapping;
e2f0ba97 2159
eef4eacb 2160 if (sdvo->is_sdvob)
b1083333
AJ		 2161 mapping = &(dev_priv->sdvo_mappings[0]);
2162 else
2163 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2164
b66d8424
CW		 2165 if (mapping->initialized)
2166 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2167 else
2168 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2169}
2170
e957d772
CW		 2171static void
2172intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2173 struct intel_sdvo *sdvo, u32 reg)
2174{
2175 struct sdvo_device_mapping *mapping;
46eb3036 2176 u8 pin;
e957d772 2177
eef4eacb 2178 if (sdvo->is_sdvob)
e957d772
CW		 2179 mapping = &dev_priv->sdvo_mappings[0];
2180 else
2181 mapping = &dev_priv->sdvo_mappings[1];
2182
6cb1612a 2183 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2184 pin = mapping->i2c_pin;
6cb1612a
JN		 2185 else
2186 pin = GMBUS_PORT_DPB;
e957d772 2187
6cb1612a
JN		 2188 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2189
2190 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2191 * our code totally fails once we start using gmbus. Hence fall back to
2192 * bit banging for now. */
2193 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2194}
2195
fbfcc4f3
JN		 2196/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2197static void
2198intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2199{
2200 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2201}
2202
e2f0ba97 2203static bool
e27d8538 2204intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2205{
97aaf910 2206 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2207}
2208
714605e4 2209static u8
eef4eacb 2210intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2211{
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 struct sdvo_device_mapping *my_mapping, *other_mapping;
2214
eef4eacb 2215 if (sdvo->is_sdvob) {
714605e4 2216 my_mapping = &dev_priv->sdvo_mappings[0];
2217 other_mapping = &dev_priv->sdvo_mappings[1];
2218 } else {
2219 my_mapping = &dev_priv->sdvo_mappings[1];
2220 other_mapping = &dev_priv->sdvo_mappings[0];
2221 }
2222
2223 /* If the BIOS described our SDVO device, take advantage of it. */
2224 if (my_mapping->slave_addr)
2225 return my_mapping->slave_addr;
2226
2227 /* If the BIOS only described a different SDVO device, use the
2228 * address that it isn't using.
2229 */
2230 if (other_mapping->slave_addr) {
2231 if (other_mapping->slave_addr == 0x70)
2232 return 0x72;
2233 else
2234 return 0x70;
2235 }
2236
2237 /* No SDVO device info is found for another DVO port,
2238 * so use mapping assumption we had before BIOS parsing.
2239 */
eef4eacb 2240 if (sdvo->is_sdvob)
714605e4 2241 return 0x70;
2242 else
2243 return 0x72;
2244}
2245
14571b4c 2246static void
df0e9248
CW		 2247intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2248 struct intel_sdvo *encoder)
14571b4c 2249{
df0e9248
CW		 2250 drm_connector_init(encoder->base.base.dev,
2251 &connector->base.base,
2252 &intel_sdvo_connector_funcs,
2253 connector->base.base.connector_type);
6070a4a9 2254
df0e9248
CW		 2255 drm_connector_helper_add(&connector->base.base,
2256 &intel_sdvo_connector_helper_funcs);
14571b4c 2257
8f4839e2 2258 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2259 connector->base.base.doublescan_allowed = 0;
2260 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2261 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2262
df0e9248
CW		 2263 intel_connector_attach_encoder(&connector->base, &encoder->base);
2264 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2265}
6070a4a9 2266
7f36e7ed 2267static void
55bc60db
VS		 2268intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2269 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2270{
2271 struct drm_device *dev = connector->base.base.dev;
2272
3f43c48d 2273 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2274 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2275 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2276 intel_sdvo->color_range_auto = true;
2277 }
7f36e7ed
CW		 2278}
2279
fb7a46f3 2280static bool
ea5b213a 2281intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2282{
4ef69c7a 2283 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2284 struct drm_connector *connector;
cc68c81a 2285 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2286 struct intel_connector *intel_connector;
615fb93f 2287 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2288
615fb93f
CW		 2289 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2290 if (!intel_sdvo_connector)
14571b4c
ZW		 2291 return false;
2292
14571b4c 2293 if (device == 0) {
ea5b213a 2294 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2295 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2296 } else if (device == 1) {
ea5b213a 2297 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2298 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2299 }
2300
615fb93f 2301 intel_connector = &intel_sdvo_connector->base;
14571b4c 2302 connector = &intel_connector->base;
5fa7ac9c
JN		 2303 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2304 intel_sdvo_connector->output_flag) {
5fa7ac9c 2305 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2306 /* Some SDVO devices have one-shot hotplug interrupts.
2307 * Ensure that they get re-enabled when an interrupt happens.
2308 */
2309 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2310 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2311 } else {
821450c6 2312 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2313 }
14571b4c
ZW		 2314 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2315 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2316
e27d8538 2317 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2318 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2319 intel_sdvo->is_hdmi = true;
14571b4c 2320 }
14571b4c 2321
df0e9248 2322 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221 2323 if (intel_sdvo->is_hdmi)
55bc60db 2324 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2325
2326 return true;
2327}
2328
2329static bool
ea5b213a 2330intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2331{
4ef69c7a
CW		 2332 struct drm_encoder *encoder = &intel_sdvo->base.base;
2333 struct drm_connector *connector;
2334 struct intel_connector *intel_connector;
2335 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2336
615fb93f
CW		 2337 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2338 if (!intel_sdvo_connector)
2339 return false;
14571b4c 2340
615fb93f 2341 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2342 connector = &intel_connector->base;
2343 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2344 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2345
4ef69c7a
CW		 2346 intel_sdvo->controlled_output |= type;
2347 intel_sdvo_connector->output_flag = type;
14571b4c 2348
4ef69c7a 2349 intel_sdvo->is_tv = true;
14571b4c 2350
df0e9248 2351 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2352
4ef69c7a 2353 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2354 goto err;
14571b4c 2355
4ef69c7a 2356 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2357 goto err;
14571b4c 2358
4ef69c7a 2359 return true;
32aad86f
CW		 2360
2361err:
123d5c01 2362 intel_sdvo_destroy(connector);
32aad86f 2363 return false;
14571b4c
ZW		 2364}
2365
2366static bool
ea5b213a 2367intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2368{
4ef69c7a
CW		 2369 struct drm_encoder *encoder = &intel_sdvo->base.base;
2370 struct drm_connector *connector;
2371 struct intel_connector *intel_connector;
2372 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2373
615fb93f
CW		 2374 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2375 if (!intel_sdvo_connector)
2376 return false;
14571b4c 2377
615fb93f 2378 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2379 connector = &intel_connector->base;
821450c6 2380 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2381 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2382 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2383
2384 if (device == 0) {
2385 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2386 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2387 } else if (device == 1) {
2388 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2389 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2390 }
2391
df0e9248
CW		 2392 intel_sdvo_connector_init(intel_sdvo_connector,
2393 intel_sdvo);
4ef69c7a 2394 return true;
14571b4c
ZW		 2395}
2396
2397static bool
ea5b213a 2398intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2399{
4ef69c7a
CW		 2400 struct drm_encoder *encoder = &intel_sdvo->base.base;
2401 struct drm_connector *connector;
2402 struct intel_connector *intel_connector;
2403 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2404
615fb93f
CW		 2405 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2406 if (!intel_sdvo_connector)
2407 return false;
14571b4c 2408
615fb93f
CW		 2409 intel_connector = &intel_sdvo_connector->base;
2410 connector = &intel_connector->base;
4ef69c7a
CW		 2411 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2412 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2413
2414 if (device == 0) {
2415 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2416 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2417 } else if (device == 1) {
2418 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2419 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2420 }
2421
df0e9248 2422 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2423 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2424 goto err;
2425
2426 return true;
2427
2428err:
123d5c01 2429 intel_sdvo_destroy(connector);
32aad86f 2430 return false;
14571b4c
ZW		 2431}
2432
2433static bool
ea5b213a 2434intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2435{
ea5b213a 2436 intel_sdvo->is_tv = false;
ea5b213a 2437 intel_sdvo->is_lvds = false;
fb7a46f3 2438
14571b4c 2439 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2440
14571b4c 2441 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2442 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2443 return false;
2444
2445 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2446 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2447 return false;
2448
2449 /* TV has no XXX1 function block */
a1f4b7ff 2450 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2451 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2452 return false;
2453
2454 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2455 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2456 return false;
fb7a46f3 2457
a0b1c7a5
CW		 2458 if (flags & SDVO_OUTPUT_YPRPB0)
2459 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2460 return false;
2461
14571b4c 2462 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2463 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2464 return false;
2465
2466 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2467 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2468 return false;
2469
2470 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2471 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2472 return false;
2473
2474 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2475 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2476 return false;
fb7a46f3 2477
14571b4c 2478 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2479 unsigned char bytes[2];
2480
ea5b213a
CW		 2481 intel_sdvo->controlled_output = 0;
2482 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2483 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2484 SDVO_NAME(intel_sdvo),
51c8b407 2485 bytes[0], bytes[1]);
14571b4c 2486 return false;
fb7a46f3 2487 }
27f8227b 2488 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2489
14571b4c 2490 return true;
fb7a46f3 2491}
2492
d0ddfbd3
JN		 2493static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2494{
2495 struct drm_device *dev = intel_sdvo->base.base.dev;
2496 struct drm_connector *connector, *tmp;
2497
2498 list_for_each_entry_safe(connector, tmp,
2499 &dev->mode_config.connector_list, head) {
2500 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2501 intel_sdvo_destroy(connector);
2502 }
2503}
2504
32aad86f
CW		 2505static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2506 struct intel_sdvo_connector *intel_sdvo_connector,
2507 int type)
ce6feabd 2508{
4ef69c7a 2509 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2510 struct intel_sdvo_tv_format format;
2511 uint32_t format_map, i;
ce6feabd 2512
32aad86f
CW		 2513 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2514 return false;
ce6feabd 2515
1a3665c8 2516 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2517 if (!intel_sdvo_get_value(intel_sdvo,
2518 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2519 &format, sizeof(format)))
2520 return false;
ce6feabd 2521
32aad86f 2522 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2523
2524 if (format_map == 0)
32aad86f 2525 return false;
ce6feabd 2526
615fb93f 2527 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2528 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2529 if (format_map & (1 << i))
2530 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2531
2532
c5521706 2533 intel_sdvo_connector->tv_format =
32aad86f
CW		 2534 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2535 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2536 if (!intel_sdvo_connector->tv_format)
fcc8d672 2537 return false;
ce6feabd 2538
615fb93f 2539 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2540 drm_property_add_enum(
c5521706 2541 intel_sdvo_connector->tv_format, i,
40039750 2542 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2543
40039750 2544 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2545 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2546 intel_sdvo_connector->tv_format, 0);
32aad86f 2547 return true;
ce6feabd
ZY		 2548
2549}
2550
c5521706
CW		 2551#define ENHANCEMENT(name, NAME) do { \
2552 if (enhancements.name) { \
2553 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2554 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2555 return false; \
2556 intel_sdvo_connector->max_##name = data_value[0]; \
2557 intel_sdvo_connector->cur_##name = response; \
2558 intel_sdvo_connector->name = \
d9bc3c02 2559 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2560 if (!intel_sdvo_connector->name) return false; \
662595df 2561 drm_object_attach_property(&connector->base, \
c5521706
CW		 2562 intel_sdvo_connector->name, \
2563 intel_sdvo_connector->cur_##name); \
2564 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2565 data_value[0], data_value[1], response); \
2566 } \
0206e353 2567} while (0)
c5521706
CW		 2568
2569static bool
2570intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2571 struct intel_sdvo_connector *intel_sdvo_connector,
2572 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2573{
4ef69c7a 2574 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2575 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2576 uint16_t response, data_value[2];
2577
c5521706
CW		 2578 /* when horizontal overscan is supported, Add the left/right property */
2579 if (enhancements.overscan_h) {
2580 if (!intel_sdvo_get_value(intel_sdvo,
2581 SDVO_CMD_GET_MAX_OVERSCAN_H,
2582 &data_value, 4))
2583 return false;
32aad86f 2584
c5521706
CW		 2585 if (!intel_sdvo_get_value(intel_sdvo,
2586 SDVO_CMD_GET_OVERSCAN_H,
2587 &response, 2))
2588 return false;
fcc8d672 2589
c5521706
CW		 2590 intel_sdvo_connector->max_hscan = data_value[0];
2591 intel_sdvo_connector->left_margin = data_value[0] - response;
2592 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2593 intel_sdvo_connector->left =
d9bc3c02 2594 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2595 if (!intel_sdvo_connector->left)
2596 return false;
fcc8d672 2597
662595df 2598 drm_object_attach_property(&connector->base,
c5521706
CW		 2599 intel_sdvo_connector->left,
2600 intel_sdvo_connector->left_margin);
fcc8d672 2601
c5521706 2602 intel_sdvo_connector->right =
d9bc3c02 2603 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2604 if (!intel_sdvo_connector->right)
2605 return false;
32aad86f 2606
662595df 2607 drm_object_attach_property(&connector->base,
c5521706
CW		 2608 intel_sdvo_connector->right,
2609 intel_sdvo_connector->right_margin);
2610 DRM_DEBUG_KMS("h_overscan: max %d, "
2611 "default %d, current %d\n",
2612 data_value[0], data_value[1], response);
2613 }
32aad86f 2614
c5521706
CW		 2615 if (enhancements.overscan_v) {
2616 if (!intel_sdvo_get_value(intel_sdvo,
2617 SDVO_CMD_GET_MAX_OVERSCAN_V,
2618 &data_value, 4))
2619 return false;
fcc8d672 2620
c5521706
CW		 2621 if (!intel_sdvo_get_value(intel_sdvo,
2622 SDVO_CMD_GET_OVERSCAN_V,
2623 &response, 2))
2624 return false;
32aad86f 2625
c5521706
CW		 2626 intel_sdvo_connector->max_vscan = data_value[0];
2627 intel_sdvo_connector->top_margin = data_value[0] - response;
2628 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2629 intel_sdvo_connector->top =
d9bc3c02
SH		 2630 drm_property_create_range(dev, 0,
2631 "top_margin", 0, data_value[0]);
c5521706
CW		 2632 if (!intel_sdvo_connector->top)
2633 return false;
32aad86f 2634
662595df 2635 drm_object_attach_property(&connector->base,
c5521706
CW		 2636 intel_sdvo_connector->top,
2637 intel_sdvo_connector->top_margin);
fcc8d672 2638
c5521706 2639 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2640 drm_property_create_range(dev, 0,
2641 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2642 if (!intel_sdvo_connector->bottom)
2643 return false;
32aad86f 2644
662595df 2645 drm_object_attach_property(&connector->base,
c5521706
CW		 2646 intel_sdvo_connector->bottom,
2647 intel_sdvo_connector->bottom_margin);
2648 DRM_DEBUG_KMS("v_overscan: max %d, "
2649 "default %d, current %d\n",
2650 data_value[0], data_value[1], response);
2651 }
32aad86f 2652
c5521706
CW		 2653 ENHANCEMENT(hpos, HPOS);
2654 ENHANCEMENT(vpos, VPOS);
2655 ENHANCEMENT(saturation, SATURATION);
2656 ENHANCEMENT(contrast, CONTRAST);
2657 ENHANCEMENT(hue, HUE);
2658 ENHANCEMENT(sharpness, SHARPNESS);
2659 ENHANCEMENT(brightness, BRIGHTNESS);
2660 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2661 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2662 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2663 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2664 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2665
e044218a
CW		 2666 if (enhancements.dot_crawl) {
2667 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2668 return false;
2669
2670 intel_sdvo_connector->max_dot_crawl = 1;
2671 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2672 intel_sdvo_connector->dot_crawl =
d9bc3c02 2673 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2674 if (!intel_sdvo_connector->dot_crawl)
2675 return false;
2676
662595df 2677 drm_object_attach_property(&connector->base,
e044218a
CW		 2678 intel_sdvo_connector->dot_crawl,
2679 intel_sdvo_connector->cur_dot_crawl);
2680 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2681 }
2682
c5521706
CW		 2683 return true;
2684}
32aad86f 2685
c5521706
CW		 2686static bool
2687intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2688 struct intel_sdvo_connector *intel_sdvo_connector,
2689 struct intel_sdvo_enhancements_reply enhancements)
2690{
4ef69c7a 2691 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2692 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2693 uint16_t response, data_value[2];
32aad86f 2694
c5521706 2695 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2696
c5521706
CW		 2697 return true;
2698}
2699#undef ENHANCEMENT
32aad86f 2700
c5521706
CW		 2701static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2702 struct intel_sdvo_connector *intel_sdvo_connector)
2703{
2704 union {
2705 struct intel_sdvo_enhancements_reply reply;
2706 uint16_t response;
2707 } enhancements;
32aad86f 2708
1a3665c8
CW		 2709 BUILD_BUG_ON(sizeof(enhancements) != 2);
2710
cf9a2f3a
CW		 2711 enhancements.response = 0;
2712 intel_sdvo_get_value(intel_sdvo,
2713 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2714 &enhancements, sizeof(enhancements));
c5521706
CW		 2715 if (enhancements.response == 0) {
2716 DRM_DEBUG_KMS("No enhancement is supported\n");
2717 return true;
b9219c5e 2718 }
32aad86f 2719
c5521706
CW		 2720 if (IS_TV(intel_sdvo_connector))
2721 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2722 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2723 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2724 else
2725 return true;
e957d772
CW		 2726}
2727
2728static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2729 struct i2c_msg *msgs,
2730 int num)
2731{
2732 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2733
e957d772
CW		 2734 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2735 return -EIO;
2736
2737 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2738}
2739
2740static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2741{
2742 struct intel_sdvo *sdvo = adapter->algo_data;
2743 return sdvo->i2c->algo->functionality(sdvo->i2c);
2744}
2745
2746static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2747 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2748 .functionality = intel_sdvo_ddc_proxy_func
2749};
2750
2751static bool
2752intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2753 struct drm_device *dev)
2754{
2755 sdvo->ddc.owner = THIS_MODULE;
2756 sdvo->ddc.class = I2C_CLASS_DDC;
2757 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2758 sdvo->ddc.dev.parent = &dev->pdev->dev;
2759 sdvo->ddc.algo_data = sdvo;
2760 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2761
2762 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2763}
2764
eef4eacb 2765bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2766{
b01f2c3a 2767 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2768 struct intel_encoder *intel_encoder;
ea5b213a 2769 struct intel_sdvo *intel_sdvo;
084b612e 2770 u32 hotplug_mask;
79e53945 2771 int i;
ea5b213a
CW		 2772 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2773 if (!intel_sdvo)
7d57382e 2774 return false;
79e53945 2775
56184e3d 2776 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2777 intel_sdvo->is_sdvob = is_sdvob;
2778 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2779 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2780 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2781 goto err_i2c_bus;
e957d772 2782
56184e3d 2783 /* encoder type will be decided later */
ea5b213a 2784 intel_encoder = &intel_sdvo->base;
21d40d37 2785 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2786 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2787
79e53945
JB		 2788 /* Read the regs to test if we can talk to the device */
2789 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2790 u8 byte;
2791
2792 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2793 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2794 SDVO_NAME(intel_sdvo));
f899fc64 2795 goto err;
79e53945
JB		 2796 }
2797 }
2798
084b612e
CW		 2799 hotplug_mask = 0;
2800 if (IS_G4X(dev)) {
2801 hotplug_mask = intel_sdvo->is_sdvob ?
2802 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2803 } else if (IS_GEN4(dev)) {
2804 hotplug_mask = intel_sdvo->is_sdvob ?
2805 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2806 } else {
2807 hotplug_mask = intel_sdvo->is_sdvob ?
2808 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2809 }
619ac3b7 2810
4f770a5b
EE		 2811 /* Only enable the hotplug irq if we need it, to work around noisy
2812 * hotplug lines.
2813 */
1d843f9d
EE		 2814 if (intel_sdvo->hotplug_active)
2815 intel_encoder->hpd_pin = HPD_SDVO_B ? HPD_SDVO_B : HPD_SDVO_C;
2816
6cc5f341 2817 intel_encoder->compute_config = intel_sdvo_compute_config;
ce22c320 2818 intel_encoder->disable = intel_disable_sdvo;
6cc5f341 2819 intel_encoder->mode_set = intel_sdvo_mode_set;
ce22c320 2820 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2821 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
ce22c320 2822
af901ca1 2823 /* In default case sdvo lvds is false */
32aad86f 2824 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2825 goto err;
79e53945 2826
ea5b213a
CW		 2827 if (intel_sdvo_output_setup(intel_sdvo,
2828 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2829 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2830 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 2831 /* Output_setup can leave behind connectors! */
2832 goto err_output;
79e53945
JB		 2833 }
2834
e506d6fd
DV		 2835 /*
2836 * Cloning SDVO with anything is often impossible, since the SDVO
2837 * encoder can request a special input timing mode. And even if that's
2838 * not the case we have evidence that cloning a plain unscaled mode with
2839 * VGA doesn't really work. Furthermore the cloning flags are way too
2840 * simplistic anyway to express such constraints, so just give up on
2841 * cloning for SDVO encoders.
2842 */
2843 intel_sdvo->base.cloneable = false;
2844
ea5b213a 2845 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2846
79e53945 2847 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2848 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 2849 goto err_output;
79e53945 2850
32aad86f
CW		 2851 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2852 &intel_sdvo->pixel_clock_min,
2853 &intel_sdvo->pixel_clock_max))
d0ddfbd3 2854 goto err_output;
79e53945 2855
8a4c47f3 2856 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2857 "clock range %dMHz - %dMHz, "
2858 "input 1: %c, input 2: %c, "
2859 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2860 SDVO_NAME(intel_sdvo),
2861 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2862 intel_sdvo->caps.device_rev_id,
2863 intel_sdvo->pixel_clock_min / 1000,
2864 intel_sdvo->pixel_clock_max / 1000,
2865 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2866 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2867 /* check currently supported outputs */
ea5b213a 2868 intel_sdvo->caps.output_flags &
79e53945 2869 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2870 intel_sdvo->caps.output_flags &
79e53945 2871 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2872 return true;
79e53945 2873
d0ddfbd3
JN		 2874err_output:
2875 intel_sdvo_output_cleanup(intel_sdvo);
2876
f899fc64 2877err:
373a3cf7 2878 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2879 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2880err_i2c_bus:
2881 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2882 kfree(intel_sdvo);
79e53945 2883
7d57382e 2884 return false;
79e53945 2885}
Linux kernel - Deliverables
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