projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: enable sdvo lvds scaling function.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
29#include <linux/delay.h>
30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
36#include "intel_sdvo_regs.h"
37
38#undef SDVO_DEBUG
342dc382 39#define I915_SDVO "i915_sdvo"
79e53945 40struct intel_sdvo_priv {
f9c10a9b 41 u8 slave_addr;
e2f0ba97
JB		 42
43 /* Register for the SDVO device: SDVOB or SDVOC */
79e53945
JB		 44 int output_device;
45
e2f0ba97
JB		 46 /* Active outputs controlled by this SDVO output */
47 uint16_t controlled_output;
79e53945 48
e2f0ba97
JB		 49 /*
50 * Capabilities of the SDVO device returned by
51 * i830_sdvo_get_capabilities()
52 */
79e53945 53 struct intel_sdvo_caps caps;
e2f0ba97
JB		 54
55 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 56 int pixel_clock_min, pixel_clock_max;
57
e2f0ba97
JB		 58 /**
59 * This is set if we're going to treat the device as TV-out.
60 *
61 * While we have these nice friendly flags for output types that ought
62 * to decide this for us, the S-Video output on our HDMI+S-Video card
63 * shows up as RGB1 (VGA).
64 */
65 bool is_tv;
66
67 /**
68 * This is set if we treat the device as HDMI, instead of DVI.
69 */
70 bool is_hdmi;
12682a97 71
7086c87f
ML		 72 /**
73 * This is set if we detect output of sdvo device as LVDS.
74 */
75 bool is_lvds;
e2f0ba97 76
12682a97 77 /**
78 * This is sdvo flags for input timing.
79 */
80 uint8_t sdvo_flags;
81
82 /**
83 * This is sdvo fixed pannel mode pointer
84 */
85 struct drm_display_mode *sdvo_lvds_fixed_mode;
86
e2f0ba97
JB		 87 /**
88 * Returned SDTV resolutions allowed for the current format, if the
89 * device reported it.
90 */
91 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
92
93 /**
94 * Current selected TV format.
95 *
96 * This is stored in the same structure that's passed to the device, for
97 * convenience.
98 */
99 struct intel_sdvo_tv_format tv_format;
100
101 /*
102 * supported encoding mode, used to determine whether HDMI is
103 * supported
104 */
105 struct intel_sdvo_encode encode;
106
107 /* DDC bus used by this SDVO output */
108 uint8_t ddc_bus;
109
79e53945
JB		 110 int save_sdvo_mult;
111 u16 save_active_outputs;
112 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
113 struct intel_sdvo_dtd save_output_dtd[16];
114 u32 save_SDVOX;
115};
116
117/**
118 * Writes the SDVOB or SDVOC with the given value, but always writes both
119 * SDVOB and SDVOC to work around apparent hardware issues (according to
120 * comments in the BIOS).
121 */
b358d0a6 122static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
79e53945
JB		 123{
124 struct drm_device *dev = intel_output->base.dev;
125 struct drm_i915_private *dev_priv = dev->dev_private;
126 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
127 u32 bval = val, cval = val;
128 int i;
129
130 if (sdvo_priv->output_device == SDVOB) {
131 cval = I915_READ(SDVOC);
132 } else {
133 bval = I915_READ(SDVOB);
134 }
135 /*
136 * Write the registers twice for luck. Sometimes,
137 * writing them only once doesn't appear to 'stick'.
138 * The BIOS does this too. Yay, magic
139 */
140 for (i = 0; i < 2; i++)
141 {
142 I915_WRITE(SDVOB, bval);
143 I915_READ(SDVOB);
144 I915_WRITE(SDVOC, cval);
145 I915_READ(SDVOC);
146 }
147}
148
149static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
150 u8 *ch)
151{
152 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
153 u8 out_buf[2];
154 u8 buf[2];
155 int ret;
156
157 struct i2c_msg msgs[] = {
158 {
f9c10a9b 159 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 160 .flags = 0,
161 .len = 1,
162 .buf = out_buf,
163 },
164 {
f9c10a9b 165 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 166 .flags = I2C_M_RD,
167 .len = 1,
168 .buf = buf,
169 }
170 };
171
172 out_buf[0] = addr;
173 out_buf[1] = 0;
174
308cd3a2 175 if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
79e53945
JB		 176 {
177 *ch = buf[0];
178 return true;
179 }
180
181 DRM_DEBUG("i2c transfer returned %d\n", ret);
182 return false;
183}
184
185static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
186 u8 ch)
187{
f9c10a9b 188 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
79e53945
JB		 189 u8 out_buf[2];
190 struct i2c_msg msgs[] = {
191 {
f9c10a9b 192 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 193 .flags = 0,
194 .len = 2,
195 .buf = out_buf,
196 }
197 };
198
199 out_buf[0] = addr;
200 out_buf[1] = ch;
201
f9c10a9b 202 if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
79e53945
JB		 203 {
204 return true;
205 }
206 return false;
207}
208
209#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
210/** Mapping of command numbers to names, for debug output */
005568be 211static const struct _sdvo_cmd_name {
e2f0ba97
JB		 212 u8 cmd;
213 char *name;
79e53945
JB		 214} sdvo_cmd_names[] = {
215 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
216 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
217 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
218 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
219 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
220 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
221 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
222 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
223 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
224 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
225 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
226 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
227 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
228 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
229 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
230 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
231 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
232 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
233 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
234 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
235 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
236 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
237 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
238 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
239 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
240 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
241 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
242 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
243 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
244 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
245 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
246 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
247 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
248 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
249 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 250 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
251 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
252 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
253 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 254 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 255 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
256 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
257 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
258 /* HDMI op code */
259 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
260 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
261 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
262 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
263 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
264 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
265 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
268 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
269 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
270 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
271 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
272 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
273 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
274 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
275 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
276 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
277 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
278 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 279};
280
281#define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
282#define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
283
284#ifdef SDVO_DEBUG
285static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
286 void *args, int args_len)
287{
288 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
289 int i;
290
342dc382 291 DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ",
292 SDVO_NAME(sdvo_priv), cmd);
79e53945 293 for (i = 0; i < args_len; i++)
342dc382 294 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 295 for (; i < 8; i++)
342dc382 296 DRM_LOG_KMS(" ");
79e53945
JB		 297 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
298 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 299 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 300 break;
301 }
302 }
303 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
342dc382 304 DRM_LOG_KMS("(%02X)", cmd);
305 DRM_LOG_KMS("\n");
79e53945
JB		 306}
307#else
308#define intel_sdvo_debug_write(o, c, a, l)
309#endif
310
311static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
312 void *args, int args_len)
313{
314 int i;
315
316 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
317
318 for (i = 0; i < args_len; i++) {
319 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
320 ((u8*)args)[i]);
321 }
322
323 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
324}
325
326#ifdef SDVO_DEBUG
327static const char *cmd_status_names[] = {
328 "Power on",
329 "Success",
330 "Not supported",
331 "Invalid arg",
332 "Pending",
333 "Target not specified",
334 "Scaling not supported"
335};
336
337static void intel_sdvo_debug_response(struct intel_output *intel_output,
338 void *response, int response_len,
339 u8 status)
340{
341 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
33b52961 342 int i;
79e53945 343
342dc382 344 DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv));
79e53945 345 for (i = 0; i < response_len; i++)
342dc382 346 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 347 for (; i < 8; i++)
342dc382 348 DRM_LOG_KMS(" ");
79e53945 349 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 350 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 351 else
342dc382 352 DRM_LOG_KMS("(??? %d)", status);
353 DRM_LOG_KMS("\n");
79e53945
JB		 354}
355#else
356#define intel_sdvo_debug_response(o, r, l, s)
357#endif
358
359static u8 intel_sdvo_read_response(struct intel_output *intel_output,
360 void *response, int response_len)
361{
362 int i;
363 u8 status;
364 u8 retry = 50;
365
366 while (retry--) {
367 /* Read the command response */
368 for (i = 0; i < response_len; i++) {
369 intel_sdvo_read_byte(intel_output,
370 SDVO_I2C_RETURN_0 + i,
371 &((u8 *)response)[i]);
372 }
373
374 /* read the return status */
375 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
376 &status);
377
378 intel_sdvo_debug_response(intel_output, response, response_len,
379 status);
380 if (status != SDVO_CMD_STATUS_PENDING)
381 return status;
382
383 mdelay(50);
384 }
385
386 return status;
387}
388
b358d0a6 389static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 390{
391 if (mode->clock >= 100000)
392 return 1;
393 else if (mode->clock >= 50000)
394 return 2;
395 else
396 return 4;
397}
398
399/**
400 * Don't check status code from this as it switches the bus back to the
401 * SDVO chips which defeats the purpose of doing a bus switch in the first
402 * place.
403 */
b358d0a6
HE		 404static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
405 u8 target)
79e53945
JB		 406{
407 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
408}
409
410static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
411{
412 struct intel_sdvo_set_target_input_args targets = {0};
413 u8 status;
414
415 if (target_0 && target_1)
416 return SDVO_CMD_STATUS_NOTSUPP;
417
418 if (target_1)
419 targets.target_1 = 1;
420
421 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
422 sizeof(targets));
423
424 status = intel_sdvo_read_response(intel_output, NULL, 0);
425
426 return (status == SDVO_CMD_STATUS_SUCCESS);
427}
428
429/**
430 * Return whether each input is trained.
431 *
432 * This function is making an assumption about the layout of the response,
433 * which should be checked against the docs.
434 */
435static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
436{
437 struct intel_sdvo_get_trained_inputs_response response;
438 u8 status;
439
440 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
441 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
442 if (status != SDVO_CMD_STATUS_SUCCESS)
443 return false;
444
445 *input_1 = response.input0_trained;
446 *input_2 = response.input1_trained;
447 return true;
448}
449
450static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
451 u16 *outputs)
452{
453 u8 status;
454
455 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
456 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
457
458 return (status == SDVO_CMD_STATUS_SUCCESS);
459}
460
461static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
462 u16 outputs)
463{
464 u8 status;
465
466 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
467 sizeof(outputs));
468 status = intel_sdvo_read_response(intel_output, NULL, 0);
469 return (status == SDVO_CMD_STATUS_SUCCESS);
470}
471
472static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
473 int mode)
474{
475 u8 status, state = SDVO_ENCODER_STATE_ON;
476
477 switch (mode) {
478 case DRM_MODE_DPMS_ON:
479 state = SDVO_ENCODER_STATE_ON;
480 break;
481 case DRM_MODE_DPMS_STANDBY:
482 state = SDVO_ENCODER_STATE_STANDBY;
483 break;
484 case DRM_MODE_DPMS_SUSPEND:
485 state = SDVO_ENCODER_STATE_SUSPEND;
486 break;
487 case DRM_MODE_DPMS_OFF:
488 state = SDVO_ENCODER_STATE_OFF;
489 break;
490 }
491
492 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
493 sizeof(state));
494 status = intel_sdvo_read_response(intel_output, NULL, 0);
495
496 return (status == SDVO_CMD_STATUS_SUCCESS);
497}
498
499static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
500 int *clock_min,
501 int *clock_max)
502{
503 struct intel_sdvo_pixel_clock_range clocks;
504 u8 status;
505
506 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
507 NULL, 0);
508
509 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
510
511 if (status != SDVO_CMD_STATUS_SUCCESS)
512 return false;
513
514 /* Convert the values from units of 10 kHz to kHz. */
515 *clock_min = clocks.min * 10;
516 *clock_max = clocks.max * 10;
517
518 return true;
519}
520
521static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
522 u16 outputs)
523{
524 u8 status;
525
526 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
527 sizeof(outputs));
528
529 status = intel_sdvo_read_response(intel_output, NULL, 0);
530 return (status == SDVO_CMD_STATUS_SUCCESS);
531}
532
533static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
534 struct intel_sdvo_dtd *dtd)
535{
536 u8 status;
537
538 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
539 status = intel_sdvo_read_response(intel_output, &dtd->part1,
540 sizeof(dtd->part1));
541 if (status != SDVO_CMD_STATUS_SUCCESS)
542 return false;
543
544 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
545 status = intel_sdvo_read_response(intel_output, &dtd->part2,
546 sizeof(dtd->part2));
547 if (status != SDVO_CMD_STATUS_SUCCESS)
548 return false;
549
550 return true;
551}
552
553static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
554 struct intel_sdvo_dtd *dtd)
555{
556 return intel_sdvo_get_timing(intel_output,
557 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
558}
559
560static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
561 struct intel_sdvo_dtd *dtd)
562{
563 return intel_sdvo_get_timing(intel_output,
564 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
565}
566
567static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
568 struct intel_sdvo_dtd *dtd)
569{
570 u8 status;
571
572 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
573 status = intel_sdvo_read_response(intel_output, NULL, 0);
574 if (status != SDVO_CMD_STATUS_SUCCESS)
575 return false;
576
577 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
578 status = intel_sdvo_read_response(intel_output, NULL, 0);
579 if (status != SDVO_CMD_STATUS_SUCCESS)
580 return false;
581
582 return true;
583}
584
585static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
586 struct intel_sdvo_dtd *dtd)
587{
588 return intel_sdvo_set_timing(intel_output,
589 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
590}
591
592static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
593 struct intel_sdvo_dtd *dtd)
594{
595 return intel_sdvo_set_timing(intel_output,
596 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
597}
598
e2f0ba97
JB		 599static bool
600intel_sdvo_create_preferred_input_timing(struct intel_output *output,
601 uint16_t clock,
602 uint16_t width,
603 uint16_t height)
604{
605 struct intel_sdvo_preferred_input_timing_args args;
12682a97 606 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
e2f0ba97
JB		 607 uint8_t status;
608
e642c6f1 609 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 610 args.clock = clock;
611 args.width = width;
612 args.height = height;
e642c6f1 613 args.interlace = 0;
12682a97 614
615 if (sdvo_priv->is_lvds &&
616 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
617 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
618 args.scaled = 1;
619
e2f0ba97
JB		 620 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
621 &args, sizeof(args));
622 status = intel_sdvo_read_response(output, NULL, 0);
623 if (status != SDVO_CMD_STATUS_SUCCESS)
624 return false;
625
626 return true;
627}
628
629static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
630 struct intel_sdvo_dtd *dtd)
631{
632 bool status;
633
634 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
635 NULL, 0);
636
637 status = intel_sdvo_read_response(output, &dtd->part1,
638 sizeof(dtd->part1));
639 if (status != SDVO_CMD_STATUS_SUCCESS)
640 return false;
641
642 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
643 NULL, 0);
644
645 status = intel_sdvo_read_response(output, &dtd->part2,
646 sizeof(dtd->part2));
647 if (status != SDVO_CMD_STATUS_SUCCESS)
648 return false;
649
650 return false;
651}
79e53945
JB		 652
653static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
654{
655 u8 response, status;
656
657 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
658 status = intel_sdvo_read_response(intel_output, &response, 1);
659
660 if (status != SDVO_CMD_STATUS_SUCCESS) {
661 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
662 return SDVO_CLOCK_RATE_MULT_1X;
663 } else {
664 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
665 }
666
667 return response;
668}
669
670static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
671{
672 u8 status;
673
674 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
675 status = intel_sdvo_read_response(intel_output, NULL, 0);
676 if (status != SDVO_CMD_STATUS_SUCCESS)
677 return false;
678
679 return true;
680}
681
e2f0ba97
JB		 682static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
683 struct drm_display_mode *mode)
79e53945 684{
e2f0ba97
JB		 685 uint16_t width, height;
686 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
687 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 688
689 width = mode->crtc_hdisplay;
690 height = mode->crtc_vdisplay;
691
692 /* do some mode translations */
693 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
694 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
695
696 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
697 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
698
699 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
700 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
701
e2f0ba97
JB		 702 dtd->part1.clock = mode->clock / 10;
703 dtd->part1.h_active = width & 0xff;
704 dtd->part1.h_blank = h_blank_len & 0xff;
705 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 706 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 707 dtd->part1.v_active = height & 0xff;
708 dtd->part1.v_blank = v_blank_len & 0xff;
709 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 710 ((v_blank_len >> 8) & 0xf);
711
171a9e96 712 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 713 dtd->part2.h_sync_width = h_sync_len & 0xff;
714 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 715 (v_sync_len & 0xf);
e2f0ba97 716 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 717 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
718 ((v_sync_len & 0x30) >> 4);
719
e2f0ba97 720 dtd->part2.dtd_flags = 0x18;
79e53945 721 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 722 dtd->part2.dtd_flags |= 0x2;
79e53945 723 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 724 dtd->part2.dtd_flags |= 0x4;
725
726 dtd->part2.sdvo_flags = 0;
727 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
728 dtd->part2.reserved = 0;
729}
730
731static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
732 struct intel_sdvo_dtd *dtd)
733{
e2f0ba97
JB		 734 mode->hdisplay = dtd->part1.h_active;
735 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
736 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 737 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 738 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
739 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
740 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
741 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
742
743 mode->vdisplay = dtd->part1.v_active;
744 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
745 mode->vsync_start = mode->vdisplay;
746 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 747 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 748 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
749 mode->vsync_end = mode->vsync_start +
750 (dtd->part2.v_sync_off_width & 0xf);
751 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
752 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
753 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
754
755 mode->clock = dtd->part1.clock * 10;
756
171a9e96 757 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 758 if (dtd->part2.dtd_flags & 0x2)
759 mode->flags |= DRM_MODE_FLAG_PHSYNC;
760 if (dtd->part2.dtd_flags & 0x4)
761 mode->flags |= DRM_MODE_FLAG_PVSYNC;
762}
763
764static bool intel_sdvo_get_supp_encode(struct intel_output *output,
765 struct intel_sdvo_encode *encode)
766{
767 uint8_t status;
768
769 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
770 status = intel_sdvo_read_response(output, encode, sizeof(*encode));
771 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
772 memset(encode, 0, sizeof(*encode));
773 return false;
774 }
775
776 return true;
777}
778
779static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
780{
781 uint8_t status;
782
783 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
784 status = intel_sdvo_read_response(output, NULL, 0);
785
786 return (status == SDVO_CMD_STATUS_SUCCESS);
787}
788
789static bool intel_sdvo_set_colorimetry(struct intel_output *output,
790 uint8_t mode)
791{
792 uint8_t status;
793
794 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
795 status = intel_sdvo_read_response(output, NULL, 0);
796
797 return (status == SDVO_CMD_STATUS_SUCCESS);
798}
799
800#if 0
801static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
802{
803 int i, j;
804 uint8_t set_buf_index[2];
805 uint8_t av_split;
806 uint8_t buf_size;
807 uint8_t buf[48];
808 uint8_t *pos;
809
810 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
811 intel_sdvo_read_response(output, &av_split, 1);
812
813 for (i = 0; i <= av_split; i++) {
814 set_buf_index[0] = i; set_buf_index[1] = 0;
815 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
816 set_buf_index, 2);
817 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
818 intel_sdvo_read_response(output, &buf_size, 1);
819
820 pos = buf;
821 for (j = 0; j <= buf_size; j += 8) {
822 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
823 NULL, 0);
824 intel_sdvo_read_response(output, pos, 8);
825 pos += 8;
826 }
827 }
828}
829#endif
830
831static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
832 uint8_t *data, int8_t size, uint8_t tx_rate)
833{
834 uint8_t set_buf_index[2];
835
836 set_buf_index[0] = index;
837 set_buf_index[1] = 0;
838
839 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
840
841 for (; size > 0; size -= 8) {
842 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
843 data += 8;
844 }
845
846 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
847}
848
849static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
850{
851 uint8_t csum = 0;
852 int i;
853
854 for (i = 0; i < size; i++)
855 csum += data[i];
856
857 return 0x100 - csum;
858}
859
860#define DIP_TYPE_AVI 0x82
861#define DIP_VERSION_AVI 0x2
862#define DIP_LEN_AVI 13
863
864struct dip_infoframe {
865 uint8_t type;
866 uint8_t version;
867 uint8_t len;
868 uint8_t checksum;
869 union {
870 struct {
871 /* Packet Byte #1 */
872 uint8_t S:2;
873 uint8_t B:2;
874 uint8_t A:1;
875 uint8_t Y:2;
876 uint8_t rsvd1:1;
877 /* Packet Byte #2 */
878 uint8_t R:4;
879 uint8_t M:2;
880 uint8_t C:2;
881 /* Packet Byte #3 */
882 uint8_t SC:2;
883 uint8_t Q:2;
884 uint8_t EC:3;
885 uint8_t ITC:1;
886 /* Packet Byte #4 */
887 uint8_t VIC:7;
888 uint8_t rsvd2:1;
889 /* Packet Byte #5 */
890 uint8_t PR:4;
891 uint8_t rsvd3:4;
892 /* Packet Byte #6~13 */
893 uint16_t top_bar_end;
894 uint16_t bottom_bar_start;
895 uint16_t left_bar_end;
896 uint16_t right_bar_start;
897 } avi;
898 struct {
899 /* Packet Byte #1 */
900 uint8_t channel_count:3;
901 uint8_t rsvd1:1;
902 uint8_t coding_type:4;
903 /* Packet Byte #2 */
904 uint8_t sample_size:2; /* SS0, SS1 */
905 uint8_t sample_frequency:3;
906 uint8_t rsvd2:3;
907 /* Packet Byte #3 */
908 uint8_t coding_type_private:5;
909 uint8_t rsvd3:3;
910 /* Packet Byte #4 */
911 uint8_t channel_allocation;
912 /* Packet Byte #5 */
913 uint8_t rsvd4:3;
914 uint8_t level_shift:4;
915 uint8_t downmix_inhibit:1;
916 } audio;
917 uint8_t payload[28];
918 } __attribute__ ((packed)) u;
919} __attribute__((packed));
920
921static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
922 struct drm_display_mode * mode)
923{
924 struct dip_infoframe avi_if = {
925 .type = DIP_TYPE_AVI,
926 .version = DIP_VERSION_AVI,
927 .len = DIP_LEN_AVI,
928 };
929
930 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
931 4 + avi_if.len);
932 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
933 SDVO_HBUF_TX_VSYNC);
934}
935
7026d4ac
ZW		 936static void intel_sdvo_set_tv_format(struct intel_output *output)
937{
938 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
939 struct intel_sdvo_tv_format *format, unset;
940 u8 status;
941
942 format = &sdvo_priv->tv_format;
943 memset(&unset, 0, sizeof(unset));
944 if (memcmp(format, &unset, sizeof(*format))) {
945 DRM_DEBUG("%s: Choosing default TV format of NTSC-M\n",
946 SDVO_NAME(sdvo_priv));
947 format->ntsc_m = 1;
948 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, format,
949 sizeof(*format));
950 status = intel_sdvo_read_response(output, NULL, 0);
951 if (status != SDVO_CMD_STATUS_SUCCESS)
952 DRM_DEBUG("%s: Failed to set TV format\n",
953 SDVO_NAME(sdvo_priv));
954 }
955}
956
e2f0ba97
JB		 957static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
958 struct drm_display_mode *mode,
959 struct drm_display_mode *adjusted_mode)
960{
961 struct intel_output *output = enc_to_intel_output(encoder);
962 struct intel_sdvo_priv *dev_priv = output->dev_priv;
79e53945 963
12682a97 964 if (dev_priv->is_tv) {
e2f0ba97
JB		 965 struct intel_sdvo_dtd output_dtd;
966 bool success;
967
968 /* We need to construct preferred input timings based on our
969 * output timings. To do that, we have to set the output
970 * timings, even though this isn't really the right place in
971 * the sequence to do it. Oh well.
972 */
973
974
975 /* Set output timings */
976 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
977 intel_sdvo_set_target_output(output,
978 dev_priv->controlled_output);
979 intel_sdvo_set_output_timing(output, &output_dtd);
980
981 /* Set the input timing to the screen. Assume always input 0. */
982 intel_sdvo_set_target_input(output, true, false);
983
984
985 success = intel_sdvo_create_preferred_input_timing(output,
986 mode->clock / 10,
987 mode->hdisplay,
988 mode->vdisplay);
989 if (success) {
990 struct intel_sdvo_dtd input_dtd;
79e53945 991
e2f0ba97
JB		 992 intel_sdvo_get_preferred_input_timing(output,
993 &input_dtd);
994 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
12682a97 995 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
996
997 drm_mode_set_crtcinfo(adjusted_mode, 0);
998
999 mode->clock = adjusted_mode->clock;
1000
1001 adjusted_mode->clock *=
1002 intel_sdvo_get_pixel_multiplier(mode);
1003 } else {
1004 return false;
1005 }
1006 } else if (dev_priv->is_lvds) {
1007 struct intel_sdvo_dtd output_dtd;
1008 bool success;
1009
1010 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1011 /* Set output timings */
1012 intel_sdvo_get_dtd_from_mode(&output_dtd,
1013 dev_priv->sdvo_lvds_fixed_mode);
1014
1015 intel_sdvo_set_target_output(output,
1016 dev_priv->controlled_output);
1017 intel_sdvo_set_output_timing(output, &output_dtd);
1018
1019 /* Set the input timing to the screen. Assume always input 0. */
1020 intel_sdvo_set_target_input(output, true, false);
1021
1022
1023 success = intel_sdvo_create_preferred_input_timing(
1024 output,
1025 mode->clock / 10,
1026 mode->hdisplay,
1027 mode->vdisplay);
1028
1029 if (success) {
1030 struct intel_sdvo_dtd input_dtd;
1031
1032 intel_sdvo_get_preferred_input_timing(output,
1033 &input_dtd);
1034 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1035 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
e2f0ba97 1036
7026d4ac
ZW		 1037 drm_mode_set_crtcinfo(adjusted_mode, 0);
1038
1039 mode->clock = adjusted_mode->clock;
1040
1041 adjusted_mode->clock *=
1042 intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1043 } else {
1044 return false;
1045 }
12682a97 1046
1047 } else {
1048 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1049 * SDVO device will be told of the multiplier during mode_set.
1050 */
1051 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1052 }
1053 return true;
1054}
1055
1056static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1057 struct drm_display_mode *mode,
1058 struct drm_display_mode *adjusted_mode)
1059{
1060 struct drm_device *dev = encoder->dev;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 struct drm_crtc *crtc = encoder->crtc;
1063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1064 struct intel_output *output = enc_to_intel_output(encoder);
1065 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1066 u32 sdvox = 0;
1067 int sdvo_pixel_multiply;
1068 struct intel_sdvo_in_out_map in_out;
1069 struct intel_sdvo_dtd input_dtd;
1070 u8 status;
1071
1072 if (!mode)
1073 return;
1074
1075 /* First, set the input mapping for the first input to our controlled
1076 * output. This is only correct if we're a single-input device, in
1077 * which case the first input is the output from the appropriate SDVO
1078 * channel on the motherboard. In a two-input device, the first input
1079 * will be SDVOB and the second SDVOC.
1080 */
1081 in_out.in0 = sdvo_priv->controlled_output;
1082 in_out.in1 = 0;
1083
1084 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1085 &in_out, sizeof(in_out));
1086 status = intel_sdvo_read_response(output, NULL, 0);
1087
1088 if (sdvo_priv->is_hdmi) {
1089 intel_sdvo_set_avi_infoframe(output, mode);
1090 sdvox |= SDVO_AUDIO_ENABLE;
1091 }
1092
7026d4ac
ZW		 1093 /* We have tried to get input timing in mode_fixup, and filled into
1094 adjusted_mode */
12682a97 1095 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
7026d4ac 1096 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
12682a97 1097 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1098 } else
7026d4ac 1099 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
e2f0ba97
JB		 1100
1101 /* If it's a TV, we already set the output timing in mode_fixup.
1102 * Otherwise, the output timing is equal to the input timing.
1103 */
12682a97 1104 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
e2f0ba97
JB		 1105 /* Set the output timing to the screen */
1106 intel_sdvo_set_target_output(output,
1107 sdvo_priv->controlled_output);
1108 intel_sdvo_set_output_timing(output, &input_dtd);
1109 }
79e53945
JB		 1110
1111 /* Set the input timing to the screen. Assume always input 0. */
e2f0ba97 1112 intel_sdvo_set_target_input(output, true, false);
79e53945 1113
7026d4ac
ZW		 1114 if (sdvo_priv->is_tv)
1115 intel_sdvo_set_tv_format(output);
1116
e2f0ba97 1117 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1118 * provide the device with a timing it can support, if it supports that
1119 * feature. However, presumably we would need to adjust the CRTC to
1120 * output the preferred timing, and we don't support that currently.
1121 */
e2f0ba97
JB		 1122#if 0
1123 success = intel_sdvo_create_preferred_input_timing(output, clock,
1124 width, height);
1125 if (success) {
1126 struct intel_sdvo_dtd *input_dtd;
1127
1128 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1129 intel_sdvo_set_input_timing(output, &input_dtd);
1130 }
1131#else
1132 intel_sdvo_set_input_timing(output, &input_dtd);
1133#endif
79e53945
JB		 1134
1135 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1136 case 1:
e2f0ba97 1137 intel_sdvo_set_clock_rate_mult(output,
79e53945
JB		 1138 SDVO_CLOCK_RATE_MULT_1X);
1139 break;
1140 case 2:
e2f0ba97 1141 intel_sdvo_set_clock_rate_mult(output,
79e53945
JB		 1142 SDVO_CLOCK_RATE_MULT_2X);
1143 break;
1144 case 4:
e2f0ba97 1145 intel_sdvo_set_clock_rate_mult(output,
79e53945
JB		 1146 SDVO_CLOCK_RATE_MULT_4X);
1147 break;
1148 }
1149
1150 /* Set the SDVO control regs. */
e2f0ba97
JB		 1151 if (IS_I965G(dev)) {
1152 sdvox |= SDVO_BORDER_ENABLE |
1153 SDVO_VSYNC_ACTIVE_HIGH |
1154 SDVO_HSYNC_ACTIVE_HIGH;
1155 } else {
1156 sdvox |= I915_READ(sdvo_priv->output_device);
1157 switch (sdvo_priv->output_device) {
1158 case SDVOB:
1159 sdvox &= SDVOB_PRESERVE_MASK;
1160 break;
1161 case SDVOC:
1162 sdvox &= SDVOC_PRESERVE_MASK;
1163 break;
1164 }
1165 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1166 }
79e53945
JB		 1167 if (intel_crtc->pipe == 1)
1168 sdvox |= SDVO_PIPE_B_SELECT;
1169
1170 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1171 if (IS_I965G(dev)) {
e2f0ba97
JB		 1172 /* done in crtc_mode_set as the dpll_md reg must be written early */
1173 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1174 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1175 } else {
1176 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1177 }
1178
12682a97 1179 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1180 sdvox |= SDVO_STALL_SELECT;
e2f0ba97 1181 intel_sdvo_write_sdvox(output, sdvox);
79e53945
JB		 1182}
1183
1184static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1185{
1186 struct drm_device *dev = encoder->dev;
1187 struct drm_i915_private *dev_priv = dev->dev_private;
1188 struct intel_output *intel_output = enc_to_intel_output(encoder);
1189 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1190 u32 temp;
1191
1192 if (mode != DRM_MODE_DPMS_ON) {
1193 intel_sdvo_set_active_outputs(intel_output, 0);
1194 if (0)
1195 intel_sdvo_set_encoder_power_state(intel_output, mode);
1196
1197 if (mode == DRM_MODE_DPMS_OFF) {
1198 temp = I915_READ(sdvo_priv->output_device);
1199 if ((temp & SDVO_ENABLE) != 0) {
1200 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1201 }
1202 }
1203 } else {
1204 bool input1, input2;
1205 int i;
1206 u8 status;
1207
1208 temp = I915_READ(sdvo_priv->output_device);
1209 if ((temp & SDVO_ENABLE) == 0)
1210 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1211 for (i = 0; i < 2; i++)
1212 intel_wait_for_vblank(dev);
1213
1214 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1215 &input2);
1216
1217
1218 /* Warn if the device reported failure to sync.
1219 * A lot of SDVO devices fail to notify of sync, but it's
1220 * a given it the status is a success, we succeeded.
1221 */
1222 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1223 DRM_DEBUG("First %s output reported failure to sync\n",
1224 SDVO_NAME(sdvo_priv));
1225 }
1226
1227 if (0)
1228 intel_sdvo_set_encoder_power_state(intel_output, mode);
e2f0ba97 1229 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
79e53945
JB		 1230 }
1231 return;
1232}
1233
1234static void intel_sdvo_save(struct drm_connector *connector)
1235{
1236 struct drm_device *dev = connector->dev;
1237 struct drm_i915_private *dev_priv = dev->dev_private;
1238 struct intel_output *intel_output = to_intel_output(connector);
1239 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1240 int o;
1241
1242 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1243 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1244
1245 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1246 intel_sdvo_set_target_input(intel_output, true, false);
1247 intel_sdvo_get_input_timing(intel_output,
1248 &sdvo_priv->save_input_dtd_1);
1249 }
1250
1251 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1252 intel_sdvo_set_target_input(intel_output, false, true);
1253 intel_sdvo_get_input_timing(intel_output,
1254 &sdvo_priv->save_input_dtd_2);
1255 }
1256
1257 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1258 {
1259 u16 this_output = (1 << o);
1260 if (sdvo_priv->caps.output_flags & this_output)
1261 {
1262 intel_sdvo_set_target_output(intel_output, this_output);
1263 intel_sdvo_get_output_timing(intel_output,
1264 &sdvo_priv->save_output_dtd[o]);
1265 }
1266 }
e2f0ba97
JB		 1267 if (sdvo_priv->is_tv) {
1268 /* XXX: Save TV format/enhancements. */
1269 }
79e53945
JB		 1270
1271 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1272}
1273
1274static void intel_sdvo_restore(struct drm_connector *connector)
1275{
1276 struct drm_device *dev = connector->dev;
79e53945
JB		 1277 struct intel_output *intel_output = to_intel_output(connector);
1278 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1279 int o;
1280 int i;
1281 bool input1, input2;
1282 u8 status;
1283
1284 intel_sdvo_set_active_outputs(intel_output, 0);
1285
1286 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1287 {
1288 u16 this_output = (1 << o);
1289 if (sdvo_priv->caps.output_flags & this_output) {
1290 intel_sdvo_set_target_output(intel_output, this_output);
1291 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1292 }
1293 }
1294
1295 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1296 intel_sdvo_set_target_input(intel_output, true, false);
1297 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1298 }
1299
1300 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1301 intel_sdvo_set_target_input(intel_output, false, true);
1302 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1303 }
1304
1305 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1306
e2f0ba97
JB		 1307 if (sdvo_priv->is_tv) {
1308 /* XXX: Restore TV format/enhancements. */
1309 }
1310
1311 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
79e53945
JB		 1312
1313 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1314 {
1315 for (i = 0; i < 2; i++)
1316 intel_wait_for_vblank(dev);
1317 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1318 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1319 DRM_DEBUG("First %s output reported failure to sync\n",
1320 SDVO_NAME(sdvo_priv));
1321 }
1322
1323 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1324}
1325
1326static int intel_sdvo_mode_valid(struct drm_connector *connector,
1327 struct drm_display_mode *mode)
1328{
1329 struct intel_output *intel_output = to_intel_output(connector);
1330 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1331
1332 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1333 return MODE_NO_DBLESCAN;
1334
1335 if (sdvo_priv->pixel_clock_min > mode->clock)
1336 return MODE_CLOCK_LOW;
1337
1338 if (sdvo_priv->pixel_clock_max < mode->clock)
1339 return MODE_CLOCK_HIGH;
1340
12682a97 1341 if (sdvo_priv->is_lvds == true) {
1342 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1343 return MODE_PANEL;
1344
1345 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1346 return MODE_PANEL;
1347
1348 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1349 return MODE_PANEL;
1350 }
1351
79e53945
JB		 1352 return MODE_OK;
1353}
1354
1355static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1356{
1357 u8 status;
1358
1359 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1360 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1361 if (status != SDVO_CMD_STATUS_SUCCESS)
1362 return false;
1363
1364 return true;
1365}
1366
1367struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1368{
1369 struct drm_connector *connector = NULL;
1370 struct intel_output *iout = NULL;
1371 struct intel_sdvo_priv *sdvo;
1372
1373 /* find the sdvo connector */
1374 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1375 iout = to_intel_output(connector);
1376
1377 if (iout->type != INTEL_OUTPUT_SDVO)
1378 continue;
1379
1380 sdvo = iout->dev_priv;
1381
1382 if (sdvo->output_device == SDVOB && sdvoB)
1383 return connector;
1384
1385 if (sdvo->output_device == SDVOC && !sdvoB)
1386 return connector;
1387
1388 }
1389
1390 return NULL;
1391}
1392
1393int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1394{
1395 u8 response[2];
1396 u8 status;
1397 struct intel_output *intel_output;
1398 DRM_DEBUG("\n");
1399
1400 if (!connector)
1401 return 0;
1402
1403 intel_output = to_intel_output(connector);
1404
1405 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1406 status = intel_sdvo_read_response(intel_output, &response, 2);
1407
1408 if (response[0] !=0)
1409 return 1;
1410
1411 return 0;
1412}
1413
1414void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1415{
1416 u8 response[2];
1417 u8 status;
1418 struct intel_output *intel_output = to_intel_output(connector);
1419
1420 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1421 intel_sdvo_read_response(intel_output, &response, 2);
1422
1423 if (on) {
1424 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1425 status = intel_sdvo_read_response(intel_output, &response, 2);
1426
1427 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1428 } else {
1429 response[0] = 0;
1430 response[1] = 0;
1431 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1432 }
1433
1434 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1435 intel_sdvo_read_response(intel_output, &response, 2);
1436}
1437
9dff6af8
ML		 1438static void
1439intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1440{
1441 struct intel_output *intel_output = to_intel_output(connector);
1442 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1443 struct edid *edid = NULL;
1444
9dff6af8 1445 edid = drm_get_edid(&intel_output->base,
f9c10a9b 1446 intel_output->ddc_bus);
9dff6af8
ML		 1447 if (edid != NULL) {
1448 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
1449 kfree(edid);
1450 intel_output->base.display_info.raw_edid = NULL;
1451 }
1452}
1453
79e53945
JB		 1454static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1455{
1456 u8 response[2];
1457 u8 status;
1458 struct intel_output *intel_output = to_intel_output(connector);
1459
1460 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1461 status = intel_sdvo_read_response(intel_output, &response, 2);
1462
1463 DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
e2f0ba97
JB		 1464
1465 if (status != SDVO_CMD_STATUS_SUCCESS)
1466 return connector_status_unknown;
1467
9dff6af8
ML		 1468 if ((response[0] != 0) || (response[1] != 0)) {
1469 intel_sdvo_hdmi_sink_detect(connector);
79e53945 1470 return connector_status_connected;
9dff6af8 1471 } else
79e53945
JB		 1472 return connector_status_disconnected;
1473}
1474
e2f0ba97 1475static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945
JB		 1476{
1477 struct intel_output *intel_output = to_intel_output(connector);
1478
1479 /* set the bus switch and get the modes */
79e53945
JB		 1480 intel_ddc_get_modes(intel_output);
1481
e2f0ba97
JB		 1482#if 0
1483 struct drm_device *dev = encoder->dev;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 /* Mac mini hack. On this device, I get DDC through the analog, which
1486 * load-detects as disconnected. I fail to DDC through the SDVO DDC,
1487 * but it does load-detect as connected. So, just steal the DDC bits
1488 * from analog when we fail at finding it the right way.
1489 */
1490 crt = xf86_config->output[0];
1491 intel_output = crt->driver_private;
1492 if (intel_output->type == I830_OUTPUT_ANALOG &&
1493 crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
1494 I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
1495 edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
1496 xf86DestroyI2CBusRec(intel_output->pDDCBus, true, true);
1497 }
1498 if (edid_mon) {
1499 xf86OutputSetEDID(output, edid_mon);
1500 modes = xf86OutputGetEDIDModes(output);
1501 }
1502#endif
1503}
1504
1505/**
1506 * This function checks the current TV format, and chooses a default if
1507 * it hasn't been set.
1508 */
1509static void
1510intel_sdvo_check_tv_format(struct intel_output *output)
1511{
1512 struct intel_sdvo_priv *dev_priv = output->dev_priv;
7026d4ac 1513 struct intel_sdvo_tv_format format;
e2f0ba97
JB		 1514 uint8_t status;
1515
1516 intel_sdvo_write_cmd(output, SDVO_CMD_GET_TV_FORMAT, NULL, 0);
1517 status = intel_sdvo_read_response(output, &format, sizeof(format));
1518 if (status != SDVO_CMD_STATUS_SUCCESS)
1519 return;
1520
7026d4ac 1521 memcpy(&dev_priv->tv_format, &format, sizeof(format));
e2f0ba97
JB		 1522}
1523
1524/*
1525 * Set of SDVO TV modes.
1526 * Note! This is in reply order (see loop in get_tv_modes).
1527 * XXX: all 60Hz refresh?
1528 */
1529struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1530 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1531 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1533 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1534 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1536 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1537 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1538 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1539 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1540 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1542 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1543 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1545 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1546 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1548 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1549 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1551 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1552 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1554 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1555 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1557 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1558 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1560 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1561 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1563 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1564 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1566 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1567 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1569 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1570 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1572 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1573 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1575 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1576 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1578 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1579 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1581 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1582 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1584 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1585 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1587};
1588
1589static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1590{
1591 struct intel_output *output = to_intel_output(connector);
7026d4ac
ZW		 1592 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1593 struct intel_sdvo_sdtv_resolution_request tv_res;
e2f0ba97
JB		 1594 uint32_t reply = 0;
1595 uint8_t status;
1596 int i = 0;
1597
1598 intel_sdvo_check_tv_format(output);
1599
1600 /* Read the list of supported input resolutions for the selected TV
1601 * format.
1602 */
7026d4ac
ZW		 1603 memset(&tv_res, 0, sizeof(tv_res));
1604 memcpy(&tv_res, &sdvo_priv->tv_format, sizeof(tv_res));
e2f0ba97 1605 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
7026d4ac 1606 &tv_res, sizeof(tv_res));
e2f0ba97
JB		 1607 status = intel_sdvo_read_response(output, &reply, 3);
1608 if (status != SDVO_CMD_STATUS_SUCCESS)
1609 return;
1610
1611 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1612 if (reply & (1 << i)) {
1613 struct drm_display_mode *nmode;
1614 nmode = drm_mode_duplicate(connector->dev,
1615 &sdvo_tv_modes[i]);
1616 if (nmode)
1617 drm_mode_probed_add(connector, nmode);
1618 }
e2f0ba97
JB		 1619}
1620
7086c87f
ML		 1621static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1622{
1623 struct intel_output *intel_output = to_intel_output(connector);
7086c87f 1624 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1625 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1626 struct drm_display_mode *newmode;
7086c87f
ML		 1627
1628 /*
1629 * Attempt to get the mode list from DDC.
1630 * Assume that the preferred modes are
1631 * arranged in priority order.
1632 */
7086c87f
ML		 1633 intel_ddc_get_modes(intel_output);
1634 if (list_empty(&connector->probed_modes) == false)
12682a97 1635 goto end;
7086c87f
ML		 1636
1637 /* Fetch modes from VBT */
1638 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1639 newmode = drm_mode_duplicate(connector->dev,
1640 dev_priv->sdvo_lvds_vbt_mode);
1641 if (newmode != NULL) {
1642 /* Guarantee the mode is preferred */
1643 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1644 DRM_MODE_TYPE_DRIVER);
1645 drm_mode_probed_add(connector, newmode);
1646 }
1647 }
12682a97 1648
1649end:
1650 list_for_each_entry(newmode, &connector->probed_modes, head) {
1651 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1652 sdvo_priv->sdvo_lvds_fixed_mode =
1653 drm_mode_duplicate(connector->dev, newmode);
1654 break;
1655 }
1656 }
1657
7086c87f
ML		 1658}
1659
e2f0ba97
JB		 1660static int intel_sdvo_get_modes(struct drm_connector *connector)
1661{
1662 struct intel_output *output = to_intel_output(connector);
1663 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1664
1665 if (sdvo_priv->is_tv)
1666 intel_sdvo_get_tv_modes(connector);
7086c87f
ML		 1667 else if (sdvo_priv->is_lvds == true)
1668 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1669 else
1670 intel_sdvo_get_ddc_modes(connector);
1671
79e53945
JB		 1672 if (list_empty(&connector->probed_modes))
1673 return 0;
1674 return 1;
1675}
1676
1677static void intel_sdvo_destroy(struct drm_connector *connector)
1678{
1679 struct intel_output *intel_output = to_intel_output(connector);
12682a97 1680 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
79e53945
JB		 1681
1682 if (intel_output->i2c_bus)
1683 intel_i2c_destroy(intel_output->i2c_bus);
619ac3b7
ML		 1684 if (intel_output->ddc_bus)
1685 intel_i2c_destroy(intel_output->ddc_bus);
1686
12682a97 1687 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1688 drm_mode_destroy(connector->dev,
1689 sdvo_priv->sdvo_lvds_fixed_mode);
1690
79e53945
JB		 1691 drm_sysfs_connector_remove(connector);
1692 drm_connector_cleanup(connector);
12682a97 1693
79e53945
JB		 1694 kfree(intel_output);
1695}
1696
1697static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1698 .dpms = intel_sdvo_dpms,
1699 .mode_fixup = intel_sdvo_mode_fixup,
1700 .prepare = intel_encoder_prepare,
1701 .mode_set = intel_sdvo_mode_set,
1702 .commit = intel_encoder_commit,
1703};
1704
1705static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1706 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1707 .save = intel_sdvo_save,
1708 .restore = intel_sdvo_restore,
1709 .detect = intel_sdvo_detect,
1710 .fill_modes = drm_helper_probe_single_connector_modes,
1711 .destroy = intel_sdvo_destroy,
1712};
1713
1714static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1715 .get_modes = intel_sdvo_get_modes,
1716 .mode_valid = intel_sdvo_mode_valid,
1717 .best_encoder = intel_best_encoder,
1718};
1719
b358d0a6 1720static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945
JB		 1721{
1722 drm_encoder_cleanup(encoder);
1723}
1724
1725static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1726 .destroy = intel_sdvo_enc_destroy,
1727};
1728
1729
e2f0ba97
JB		 1730/**
1731 * Choose the appropriate DDC bus for control bus switch command for this
1732 * SDVO output based on the controlled output.
1733 *
1734 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1735 * outputs, then LVDS outputs.
1736 */
1737static void
1738intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1739{
1740 uint16_t mask = 0;
1741 unsigned int num_bits;
1742
1743 /* Make a mask of outputs less than or equal to our own priority in the
1744 * list.
1745 */
1746 switch (dev_priv->controlled_output) {
1747 case SDVO_OUTPUT_LVDS1:
1748 mask |= SDVO_OUTPUT_LVDS1;
1749 case SDVO_OUTPUT_LVDS0:
1750 mask |= SDVO_OUTPUT_LVDS0;
1751 case SDVO_OUTPUT_TMDS1:
1752 mask |= SDVO_OUTPUT_TMDS1;
1753 case SDVO_OUTPUT_TMDS0:
1754 mask |= SDVO_OUTPUT_TMDS0;
1755 case SDVO_OUTPUT_RGB1:
1756 mask |= SDVO_OUTPUT_RGB1;
1757 case SDVO_OUTPUT_RGB0:
1758 mask |= SDVO_OUTPUT_RGB0;
1759 break;
1760 }
1761
1762 /* Count bits to find what number we are in the priority list. */
1763 mask &= dev_priv->caps.output_flags;
1764 num_bits = hweight16(mask);
1765 if (num_bits > 3) {
1766 /* if more than 3 outputs, default to DDC bus 3 for now */
1767 num_bits = 3;
1768 }
1769
1770 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1771 dev_priv->ddc_bus = 1 << num_bits;
1772}
1773
1774static bool
1775intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
1776{
1777 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1778 uint8_t status;
1779
1780 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1781
1782 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
1783 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
1784 if (status != SDVO_CMD_STATUS_SUCCESS)
1785 return false;
1786 return true;
1787}
1788
619ac3b7
ML		 1789static struct intel_output *
1790intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
1791{
1792 struct drm_device *dev = chan->drm_dev;
1793 struct drm_connector *connector;
1794 struct intel_output *intel_output = NULL;
1795
1796 list_for_each_entry(connector,
1797 &dev->mode_config.connector_list, head) {
f9c10a9b 1798 if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
619ac3b7
ML		 1799 intel_output = to_intel_output(connector);
1800 break;
1801 }
1802 }
1803 return intel_output;
1804}
1805
1806static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1807 struct i2c_msg msgs[], int num)
1808{
1809 struct intel_output *intel_output;
1810 struct intel_sdvo_priv *sdvo_priv;
1811 struct i2c_algo_bit_data *algo_data;
f9c10a9b 1812 const struct i2c_algorithm *algo;
619ac3b7
ML		 1813
1814 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
1815 intel_output =
1816 intel_sdvo_chan_to_intel_output(
1817 (struct intel_i2c_chan *)(algo_data->data));
1818 if (intel_output == NULL)
1819 return -EINVAL;
1820
1821 sdvo_priv = intel_output->dev_priv;
f9c10a9b 1822 algo = intel_output->i2c_bus->algo;
619ac3b7
ML		 1823
1824 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
1825 return algo->master_xfer(i2c_adap, msgs, num);
1826}
1827
1828static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1829 .master_xfer = intel_sdvo_master_xfer,
1830};
1831
714605e4 1832static u8
1833intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
1834{
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836 struct sdvo_device_mapping *my_mapping, *other_mapping;
1837
1838 if (output_device == SDVOB) {
1839 my_mapping = &dev_priv->sdvo_mappings[0];
1840 other_mapping = &dev_priv->sdvo_mappings[1];
1841 } else {
1842 my_mapping = &dev_priv->sdvo_mappings[1];
1843 other_mapping = &dev_priv->sdvo_mappings[0];
1844 }
1845
1846 /* If the BIOS described our SDVO device, take advantage of it. */
1847 if (my_mapping->slave_addr)
1848 return my_mapping->slave_addr;
1849
1850 /* If the BIOS only described a different SDVO device, use the
1851 * address that it isn't using.
1852 */
1853 if (other_mapping->slave_addr) {
1854 if (other_mapping->slave_addr == 0x70)
1855 return 0x72;
1856 else
1857 return 0x70;
1858 }
1859
1860 /* No SDVO device info is found for another DVO port,
1861 * so use mapping assumption we had before BIOS parsing.
1862 */
1863 if (output_device == SDVOB)
1864 return 0x70;
1865 else
1866 return 0x72;
1867}
1868
7d57382e 1869bool intel_sdvo_init(struct drm_device *dev, int output_device)
79e53945
JB		 1870{
1871 struct drm_connector *connector;
1872 struct intel_output *intel_output;
1873 struct intel_sdvo_priv *sdvo_priv;
f9c10a9b 1874
79e53945
JB		 1875 int connector_type;
1876 u8 ch[0x40];
1877 int i;
f9c10a9b 1878 int encoder_type;
79e53945
JB		 1879
1880 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1881 if (!intel_output) {
7d57382e 1882 return false;
79e53945
JB		 1883 }
1884
79e53945 1885 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
308cd3a2
KP		 1886 sdvo_priv->output_device = output_device;
1887
1888 intel_output->dev_priv = sdvo_priv;
79e53945
JB		 1889 intel_output->type = INTEL_OUTPUT_SDVO;
1890
79e53945 1891 /* setup the DDC bus. */
308cd3a2
KP		 1892 if (output_device == SDVOB)
1893 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1894 else
1895 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1896
1897 if (!intel_output->i2c_bus)
ad5b2a6d 1898 goto err_inteloutput;
79e53945 1899
308cd3a2 1900 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
79e53945 1901
308cd3a2
KP		 1902 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
1903 intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
79e53945 1904
79e53945
JB		 1905 /* Read the regs to test if we can talk to the device */
1906 for (i = 0; i < 0x40; i++) {
1907 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
342dc382 1908 DRM_DEBUG_KMS(I915_SDVO,
1909 "No SDVO device found on SDVO%c\n",
1910 output_device == SDVOB ? 'B' : 'C');
79e53945
JB		 1911 goto err_i2c;
1912 }
1913 }
1914
619ac3b7
ML		 1915 /* setup the DDC bus. */
1916 if (output_device == SDVOB)
308cd3a2 1917 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
619ac3b7 1918 else
308cd3a2 1919 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
619ac3b7 1920
308cd3a2 1921 if (intel_output->ddc_bus == NULL)
619ac3b7
ML		 1922 goto err_i2c;
1923
308cd3a2
KP		 1924 /* Wrap with our custom algo which switches to DDC mode */
1925 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 1926
7086c87f
ML		 1927 /* In defaut case sdvo lvds is false */
1928 sdvo_priv->is_lvds = false;
79e53945
JB		 1929 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1930
e2f0ba97
JB		 1931 if (sdvo_priv->caps.output_flags &
1932 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1933 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1934 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
1935 else
1936 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
1937
e2f0ba97
JB		 1938 encoder_type = DRM_MODE_ENCODER_TMDS;
1939 connector_type = DRM_MODE_CONNECTOR_DVID;
79e53945 1940
e2f0ba97
JB		 1941 if (intel_sdvo_get_supp_encode(intel_output,
1942 &sdvo_priv->encode) &&
1943 intel_sdvo_get_digital_encoding_mode(intel_output) &&
1944 sdvo_priv->is_hdmi) {
1945 /* enable hdmi encoding mode if supported */
1946 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
1947 intel_sdvo_set_colorimetry(intel_output,
1948 SDVO_COLORIMETRY_RGB256);
1949 connector_type = DRM_MODE_CONNECTOR_HDMIA;
1950 }
1951 }
1952 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_SVID0)
79e53945 1953 {
e2f0ba97 1954 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
e2f0ba97
JB		 1955 encoder_type = DRM_MODE_ENCODER_TVDAC;
1956 connector_type = DRM_MODE_CONNECTOR_SVIDEO;
1957 sdvo_priv->is_tv = true;
1958 intel_output->needs_tv_clock = true;
1959 }
1960 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1961 {
1962 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
79e53945
JB		 1963 encoder_type = DRM_MODE_ENCODER_DAC;
1964 connector_type = DRM_MODE_CONNECTOR_VGA;
1965 }
1966 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1967 {
e2f0ba97 1968 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
79e53945
JB		 1969 encoder_type = DRM_MODE_ENCODER_DAC;
1970 connector_type = DRM_MODE_CONNECTOR_VGA;
1971 }
e2f0ba97 1972 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS0)
79e53945 1973 {
e2f0ba97 1974 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
e2f0ba97
JB		 1975 encoder_type = DRM_MODE_ENCODER_LVDS;
1976 connector_type = DRM_MODE_CONNECTOR_LVDS;
7086c87f 1977 sdvo_priv->is_lvds = true;
79e53945 1978 }
e2f0ba97 1979 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_LVDS1)
79e53945 1980 {
e2f0ba97 1981 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
e2f0ba97
JB		 1982 encoder_type = DRM_MODE_ENCODER_LVDS;
1983 connector_type = DRM_MODE_CONNECTOR_LVDS;
7086c87f 1984 sdvo_priv->is_lvds = true;
79e53945
JB		 1985 }
1986 else
1987 {
1988 unsigned char bytes[2];
1989
e2f0ba97 1990 sdvo_priv->controlled_output = 0;
79e53945 1991 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
342dc382 1992 DRM_DEBUG_KMS(I915_SDVO,
1993 "%s: Unknown SDVO output type (0x%02x%02x)\n",
1994 SDVO_NAME(sdvo_priv),
1995 bytes[0], bytes[1]);
e2f0ba97
JB		 1996 encoder_type = DRM_MODE_ENCODER_NONE;
1997 connector_type = DRM_MODE_CONNECTOR_Unknown;
79e53945
JB		 1998 goto err_i2c;
1999 }
2000
ad5b2a6d
JB		 2001 connector = &intel_output->base;
2002 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2003 connector_type);
2004 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2005 connector->interlace_allowed = 0;
2006 connector->doublescan_allowed = 0;
2007 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2008
79e53945
JB		 2009 drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
2010 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
79e53945
JB		 2011
2012 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
2013 drm_sysfs_connector_add(connector);
2014
e2f0ba97
JB		 2015 intel_sdvo_select_ddc_bus(sdvo_priv);
2016
79e53945
JB		 2017 /* Set the input timing to the screen. Assume always input 0. */
2018 intel_sdvo_set_target_input(intel_output, true, false);
2019
2020 intel_sdvo_get_input_pixel_clock_range(intel_output,
2021 &sdvo_priv->pixel_clock_min,
2022 &sdvo_priv->pixel_clock_max);
2023
2024
342dc382 2025 DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, "
2026 "clock range %dMHz - %dMHz, "
2027 "input 1: %c, input 2: %c, "
2028 "output 1: %c, output 2: %c\n",
2029 SDVO_NAME(sdvo_priv),
2030 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2031 sdvo_priv->caps.device_rev_id,
2032 sdvo_priv->pixel_clock_min / 1000,
2033 sdvo_priv->pixel_clock_max / 1000,
2034 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2035 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2036 /* check currently supported outputs */
2037 sdvo_priv->caps.output_flags &
79e53945 2038 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
342dc382 2039 sdvo_priv->caps.output_flags &
79e53945
JB		 2040 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2041
7d57382e 2042 return true;
79e53945
JB		 2043
2044err_i2c:
308cd3a2 2045 if (intel_output->ddc_bus != NULL)
619ac3b7 2046 intel_i2c_destroy(intel_output->ddc_bus);
308cd3a2
KP		 2047 if (intel_output->i2c_bus != NULL)
2048 intel_i2c_destroy(intel_output->i2c_bus);
ad5b2a6d 2049err_inteloutput:
79e53945
JB		 2050 kfree(intel_output);
2051
7d57382e 2052 return false;
79e53945 2053}
Linux kernel - Deliverables
This page took 0.156122 seconds and 5 git commands to generate.