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drm/i915: Fix port_clock and adjusted_mode.clock readout all over
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
19d415a2 83 * intel_sdvo_get_capabilities()
e2f0ba97 84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
8aca63aa 205static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 206{
8aca63aa 207 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
8aca63aa 212 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 213}
214
615fb93f
CW		 215static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
216{
217 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
218}
219
fb7a46f3 220static bool
ea5b213a 221intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 222static bool
223intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
224 struct intel_sdvo_connector *intel_sdvo_connector,
225 int type);
226static bool
227intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
228 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 229
79e53945
JB		 230/**
231 * Writes the SDVOB or SDVOC with the given value, but always writes both
232 * SDVOB and SDVOC to work around apparent hardware issues (according to
233 * comments in the BIOS).
234 */
ea5b213a 235static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 236{
4ef69c7a 237 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 238 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 239 u32 bval = val, cval = val;
240 int i;
241
ea5b213a
CW		 242 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
243 I915_WRITE(intel_sdvo->sdvo_reg, val);
244 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 245 return;
246 }
247
e2debe91
PZ		 248 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
249 cval = I915_READ(GEN3_SDVOC);
250 else
251 bval = I915_READ(GEN3_SDVOB);
252
79e53945
JB		 253 /*
254 * Write the registers twice for luck. Sometimes,
255 * writing them only once doesn't appear to 'stick'.
256 * The BIOS does this too. Yay, magic
257 */
258 for (i = 0; i < 2; i++)
259 {
e2debe91
PZ		 260 I915_WRITE(GEN3_SDVOB, bval);
261 I915_READ(GEN3_SDVOB);
262 I915_WRITE(GEN3_SDVOC, cval);
263 I915_READ(GEN3_SDVOC);
79e53945
JB		 264 }
265}
266
32aad86f 267static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 268{
79e53945
JB		 269 struct i2c_msg msgs[] = {
270 {
e957d772 271 .addr = intel_sdvo->slave_addr,
79e53945
JB		 272 .flags = 0,
273 .len = 1,
e957d772 274 .buf = &addr,
79e53945
JB		 275 },
276 {
e957d772 277 .addr = intel_sdvo->slave_addr,
79e53945
JB		 278 .flags = I2C_M_RD,
279 .len = 1,
e957d772 280 .buf = ch,
79e53945
JB		 281 }
282 };
32aad86f 283 int ret;
79e53945 284
f899fc64 285 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 286 return true;
79e53945 287
8a4c47f3 288 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 289 return false;
290}
291
79e53945
JB		 292#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
293/** Mapping of command numbers to names, for debug output */
005568be 294static const struct _sdvo_cmd_name {
e2f0ba97 295 u8 cmd;
2e88e40b 296 const char *name;
79e53945 297} sdvo_cmd_names[] = {
0206e353
AJ		 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
341
342 /* Add the op code for SDVO enhancements */
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
387
388 /* HDMI op code */
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 409};
410
eef4eacb 411#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 412
ea5b213a 413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 414 const void *args, int args_len)
79e53945 415{
79e53945
JB		 416 int i;
417
8a4c47f3 418 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 419 SDVO_NAME(intel_sdvo), cmd);
79e53945 420 for (i = 0; i < args_len; i++)
342dc382 421 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 422 for (; i < 8; i++)
342dc382 423 DRM_LOG_KMS(" ");
04ad327f 424 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 425 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 426 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 427 break;
428 }
429 }
04ad327f 430 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 431 DRM_LOG_KMS("(%02X)", cmd);
432 DRM_LOG_KMS("\n");
79e53945 433}
79e53945 434
e957d772
CW		 435static const char *cmd_status_names[] = {
436 "Power on",
437 "Success",
438 "Not supported",
439 "Invalid arg",
440 "Pending",
441 "Target not specified",
442 "Scaling not supported"
443};
444
32aad86f
CW		 445static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
446 const void *args, int args_len)
79e53945 447{
3bf3f452
BW		 448 u8 *buf, status;
449 struct i2c_msg *msgs;
450 int i, ret = true;
451
0274df3e 452 /* Would be simpler to allocate both in one go ? */
5c67eeb6 453 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 454 if (!buf)
455 return false;
456
457 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 458 if (!msgs) {
459 kfree(buf);
3bf3f452 460 return false;
0274df3e 461 }
79e53945 462
ea5b213a 463 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 464
465 for (i = 0; i < args_len; i++) {
e957d772
CW		 466 msgs[i].addr = intel_sdvo->slave_addr;
467 msgs[i].flags = 0;
468 msgs[i].len = 2;
469 msgs[i].buf = buf + 2 *i;
470 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
471 buf[2*i + 1] = ((u8*)args)[i];
472 }
473 msgs[i].addr = intel_sdvo->slave_addr;
474 msgs[i].flags = 0;
475 msgs[i].len = 2;
476 msgs[i].buf = buf + 2*i;
477 buf[2*i + 0] = SDVO_I2C_OPCODE;
478 buf[2*i + 1] = cmd;
479
480 /* the following two are to read the response */
481 status = SDVO_I2C_CMD_STATUS;
482 msgs[i+1].addr = intel_sdvo->slave_addr;
483 msgs[i+1].flags = 0;
484 msgs[i+1].len = 1;
485 msgs[i+1].buf = &status;
486
487 msgs[i+2].addr = intel_sdvo->slave_addr;
488 msgs[i+2].flags = I2C_M_RD;
489 msgs[i+2].len = 1;
490 msgs[i+2].buf = &status;
491
492 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
493 if (ret < 0) {
494 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 495 ret = false;
496 goto out;
e957d772
CW		 497 }
498 if (ret != i+3) {
499 /* failure in I2C transfer */
500 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 501 ret = false;
e957d772
CW		 502 }
503
3bf3f452
BW		 504out:
505 kfree(msgs);
506 kfree(buf);
507 return ret;
79e53945
JB		 508}
509
b5c616a7
CW		 510static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
511 void *response, int response_len)
79e53945 512{
fc37381c 513 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 514 u8 status;
33b52961 515 int i;
79e53945 516
d121a5d2
CW		 517 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
518
b5c616a7
CW		 519 /*
520 * The documentation states that all commands will be
521 * processed within 15µs, and that we need only poll
522 * the status byte a maximum of 3 times in order for the
523 * command to be complete.
524 *
525 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 526 *
527 * Also beware that the first response by many devices is to
528 * reply PENDING and stall for time. TVs are notorious for
529 * requiring longer than specified to complete their replies.
530 * Originally (in the DDX long ago), the delay was only ever 15ms
531 * with an additional delay of 30ms applied for TVs added later after
532 * many experiments. To accommodate both sets of delays, we do a
533 * sequence of slow checks if the device is falling behind and fails
534 * to reply within 5*15µs.
b5c616a7 535 */
d121a5d2
CW		 536 if (!intel_sdvo_read_byte(intel_sdvo,
537 SDVO_I2C_CMD_STATUS,
538 &status))
539 goto log_fail;
540
1ad87e72
GC		 541 while ((status == SDVO_CMD_STATUS_PENDING ||
542 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
b5c616a7
CW		 548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
d121a5d2
CW		 551 goto log_fail;
552 }
b5c616a7 553
79e53945 554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 556 else
342dc382 557 DRM_LOG_KMS("(??? %d)", status);
79e53945 558
b5c616a7
CW		 559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
79e53945 561
b5c616a7
CW		 562 /* Read the command response */
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
e957d772 568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 569 }
b5c616a7 570 DRM_LOG_KMS("\n");
b5c616a7 571 return true;
79e53945 572
b5c616a7 573log_fail:
d121a5d2 574 DRM_LOG_KMS("... failed\n");
b5c616a7 575 return false;
79e53945
JB		 576}
577
b358d0a6 578static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 579{
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586}
587
e957d772
CW		 588static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
79e53945 590{
d121a5d2 591 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
79e53945
JB		 595}
596
32aad86f 597static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 598{
d121a5d2
CW		 599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 603}
79e53945 604
32aad86f
CW		 605static bool
606intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607{
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
79e53945 610
32aad86f
CW		 611 return intel_sdvo_read_response(intel_sdvo, value, len);
612}
79e53945 613
32aad86f
CW		 614static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615{
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
79e53945
JB		 620}
621
622/**
623 * Return whether each input is trained.
624 *
625 * This function is making an assumption about the layout of the response,
626 * which should be checked against the docs.
627 */
ea5b213a 628static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 629{
630 struct intel_sdvo_get_trained_inputs_response response;
79e53945 631
1a3665c8 632 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
79e53945
JB		 635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640}
641
ea5b213a 642static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 643 u16 outputs)
644{
32aad86f
CW		 645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
79e53945
JB		 648}
649
4ac41f47
DV		 650static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652{
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656}
657
ea5b213a 658static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 659 int mode)
660{
32aad86f 661 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
32aad86f
CW		 678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 680}
681
ea5b213a 682static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int *clock_min,
684 int *clock_max)
685{
686 struct intel_sdvo_pixel_clock_range clocks;
79e53945 687
1a3665c8 688 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
79e53945
JB		 692 return false;
693
694 /* Convert the values from units of 10 kHz to kHz. */
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
79e53945
JB		 697 return true;
698}
699
ea5b213a 700static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 701 u16 outputs)
702{
32aad86f
CW		 703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
79e53945
JB		 706}
707
ea5b213a 708static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 709 struct intel_sdvo_dtd *dtd)
710{
32aad86f
CW		 711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 713}
714
045ac3b5
JB		 715static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
716 struct intel_sdvo_dtd *dtd)
717{
718 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
720}
721
ea5b213a 722static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 723 struct intel_sdvo_dtd *dtd)
724{
ea5b213a 725 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 726 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
727}
728
ea5b213a 729static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 730 struct intel_sdvo_dtd *dtd)
731{
ea5b213a 732 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 733 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
734}
735
045ac3b5
JB		 736static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
737 struct intel_sdvo_dtd *dtd)
738{
739 return intel_sdvo_get_timing(intel_sdvo,
740 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
741}
742
e2f0ba97 743static bool
ea5b213a 744intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 745 uint16_t clock,
746 uint16_t width,
747 uint16_t height)
748{
749 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 750
e642c6f1 751 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 752 args.clock = clock;
753 args.width = width;
754 args.height = height;
e642c6f1 755 args.interlace = 0;
12682a97 756
ea5b213a
CW		 757 if (intel_sdvo->is_lvds &&
758 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
759 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 760 args.scaled = 1;
761
32aad86f
CW		 762 return intel_sdvo_set_value(intel_sdvo,
763 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
764 &args, sizeof(args));
e2f0ba97
JB		 765}
766
ea5b213a 767static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 768 struct intel_sdvo_dtd *dtd)
769{
1a3665c8
CW		 770 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
771 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 772 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
773 &dtd->part1, sizeof(dtd->part1)) &&
774 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
775 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 776}
79e53945 777
ea5b213a 778static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 779{
32aad86f 780 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 781}
782
e2f0ba97 783static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 784 const struct drm_display_mode *mode)
79e53945 785{
e2f0ba97
JB		 786 uint16_t width, height;
787 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
788 uint16_t h_sync_offset, v_sync_offset;
6651819b 789 int mode_clock;
79e53945 790
c6ebd4c0
DV		 791 width = mode->hdisplay;
792 height = mode->vdisplay;
79e53945
JB		 793
794 /* do some mode translations */
c6ebd4c0
DV		 795 h_blank_len = mode->htotal - mode->hdisplay;
796 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 797
c6ebd4c0
DV		 798 v_blank_len = mode->vtotal - mode->vdisplay;
799 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 800
c6ebd4c0
DV		 801 h_sync_offset = mode->hsync_start - mode->hdisplay;
802 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 803
6651819b 804 mode_clock = mode->clock;
6651819b
DV		 805 mode_clock /= 10;
806 dtd->part1.clock = mode_clock;
807
e2f0ba97
JB		 808 dtd->part1.h_active = width & 0xff;
809 dtd->part1.h_blank = h_blank_len & 0xff;
810 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 811 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 812 dtd->part1.v_active = height & 0xff;
813 dtd->part1.v_blank = v_blank_len & 0xff;
814 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 815 ((v_blank_len >> 8) & 0xf);
816
171a9e96 817 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 818 dtd->part2.h_sync_width = h_sync_len & 0xff;
819 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 820 (v_sync_len & 0xf);
e2f0ba97 821 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 822 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
823 ((v_sync_len & 0x30) >> 4);
824
e2f0ba97 825 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 826 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
827 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 828 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 829 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 830 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 831 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 832
833 dtd->part2.sdvo_flags = 0;
834 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
835 dtd->part2.reserved = 0;
836}
837
838static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 839 const struct intel_sdvo_dtd *dtd)
e2f0ba97 840{
e2f0ba97
JB		 841 mode->hdisplay = dtd->part1.h_active;
842 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
843 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 844 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 845 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
846 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
847 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
848 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
849
850 mode->vdisplay = dtd->part1.v_active;
851 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
852 mode->vsync_start = mode->vdisplay;
853 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 854 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 855 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
856 mode->vsync_end = mode->vsync_start +
857 (dtd->part2.v_sync_off_width & 0xf);
858 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
859 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
860 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
861
862 mode->clock = dtd->part1.clock * 10;
863
171a9e96 864 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 865 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
866 mode->flags |= DRM_MODE_FLAG_INTERLACE;
867 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 868 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 869 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 870 mode->flags |= DRM_MODE_FLAG_PVSYNC;
871}
872
e27d8538 873static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 874{
e27d8538 875 struct intel_sdvo_encode encode;
e2f0ba97 876
1a3665c8 877 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 878 return intel_sdvo_get_value(intel_sdvo,
879 SDVO_CMD_GET_SUPP_ENCODE,
880 &encode, sizeof(encode));
e2f0ba97
JB		 881}
882
ea5b213a 883static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 884 uint8_t mode)
e2f0ba97 885{
32aad86f 886 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 887}
888
ea5b213a 889static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 890 uint8_t mode)
891{
32aad86f 892 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 893}
894
895#if 0
ea5b213a 896static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 897{
898 int i, j;
899 uint8_t set_buf_index[2];
900 uint8_t av_split;
901 uint8_t buf_size;
902 uint8_t buf[48];
903 uint8_t *pos;
904
32aad86f 905 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 906
907 for (i = 0; i <= av_split; i++) {
908 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 909 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 910 set_buf_index, 2);
c751ce4f
EA		 911 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
912 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 913
914 pos = buf;
915 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 916 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 917 NULL, 0);
c751ce4f 918 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 919 pos += 8;
920 }
921 }
922}
923#endif
924
b6e0e543
DV		 925static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
926 unsigned if_index, uint8_t tx_rate,
927 uint8_t *data, unsigned length)
928{
929 uint8_t set_buf_index[2] = { if_index, 0 };
930 uint8_t hbuf_size, tmp[8];
931 int i;
932
933 if (!intel_sdvo_set_value(intel_sdvo,
934 SDVO_CMD_SET_HBUF_INDEX,
935 set_buf_index, 2))
936 return false;
937
938 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
939 &hbuf_size, 1))
940 return false;
941
942 /* Buffer size is 0 based, hooray! */
943 hbuf_size++;
944
945 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
946 if_index, length, hbuf_size);
947
948 for (i = 0; i < hbuf_size; i += 8) {
949 memset(tmp, 0, 8);
950 if (i < length)
951 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
952
953 if (!intel_sdvo_set_value(intel_sdvo,
954 SDVO_CMD_SET_HBUF_DATA,
955 tmp, 8))
956 return false;
957 }
958
959 return intel_sdvo_set_value(intel_sdvo,
960 SDVO_CMD_SET_HBUF_TXRATE,
961 &tx_rate, 1);
962}
963
abedc077
VS		 964static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
965 const struct drm_display_mode *adjusted_mode)
e2f0ba97 966{
15dcd350
DL		 967 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
968 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
970 union hdmi_infoframe frame;
971 int ret;
972 ssize_t len;
973
974 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
975 adjusted_mode);
976 if (ret < 0) {
977 DRM_ERROR("couldn't fill AVI infoframe\n");
978 return false;
979 }
3c17fe4b 980
abedc077 981 if (intel_sdvo->rgb_quant_range_selectable) {
50f3b016 982 if (intel_crtc->config.limited_color_range)
15dcd350
DL		 983 frame.avi.quantization_range =
984 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 985 else
15dcd350
DL		 986 frame.avi.quantization_range =
987 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 988 }
989
15dcd350
DL		 990 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
991 if (len < 0)
992 return false;
81014b9d 993
b6e0e543
DV		 994 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
995 SDVO_HBUF_TX_VSYNC,
996 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 997}
998
32aad86f 999static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 1000{
ce6feabd 1001 struct intel_sdvo_tv_format format;
40039750 1002 uint32_t format_map;
ce6feabd 1003
40039750 1004 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1005 memset(&format, 0, sizeof(format));
32aad86f 1006 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1007
32aad86f
CW		 1008 BUILD_BUG_ON(sizeof(format) != 6);
1009 return intel_sdvo_set_value(intel_sdvo,
1010 SDVO_CMD_SET_TV_FORMAT,
1011 &format, sizeof(format));
7026d4ac
ZW		 1012}
1013
32aad86f
CW		 1014static bool
1015intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1016 const struct drm_display_mode *mode)
e2f0ba97 1017{
32aad86f 1018 struct intel_sdvo_dtd output_dtd;
79e53945 1019
32aad86f
CW		 1020 if (!intel_sdvo_set_target_output(intel_sdvo,
1021 intel_sdvo->attached_output))
1022 return false;
e2f0ba97 1023
32aad86f
CW		 1024 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1025 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1026 return false;
e2f0ba97 1027
32aad86f
CW		 1028 return true;
1029}
1030
c9a29698
DV		 1031/* Asks the sdvo controller for the preferred input mode given the output mode.
1032 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1033static bool
c9a29698 1034intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1035 const struct drm_display_mode *mode,
c9a29698 1036 struct drm_display_mode *adjusted_mode)
32aad86f 1037{
c9a29698
DV		 1038 struct intel_sdvo_dtd input_dtd;
1039
32aad86f
CW		 1040 /* Reset the input timing to the screen. Assume always input 0. */
1041 if (!intel_sdvo_set_target_input(intel_sdvo))
1042 return false;
e2f0ba97 1043
32aad86f
CW		 1044 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1045 mode->clock / 10,
1046 mode->hdisplay,
1047 mode->vdisplay))
1048 return false;
e2f0ba97 1049
32aad86f 1050 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1051 &input_dtd))
32aad86f 1052 return false;
e2f0ba97 1053
c9a29698 1054 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1055 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1056
32aad86f
CW		 1057 return true;
1058}
12682a97 1059
70484559
DV		 1060static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1061{
3c52f4eb 1062 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1063 struct dpll *clock = &pipe_config->dpll;
1064
1065 /* SDVO TV has fixed PLL values depend on its clock range,
1066 this mirrors vbios setting. */
1067 if (dotclock >= 100000 && dotclock < 140500) {
1068 clock->p1 = 2;
1069 clock->p2 = 10;
1070 clock->n = 3;
1071 clock->m1 = 16;
1072 clock->m2 = 8;
1073 } else if (dotclock >= 140500 && dotclock <= 200000) {
1074 clock->p1 = 1;
1075 clock->p2 = 10;
1076 clock->n = 6;
1077 clock->m1 = 12;
1078 clock->m2 = 8;
1079 } else {
1080 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1081 }
1082
1083 pipe_config->clock_set = true;
1084}
1085
6cc5f341
DV		 1086static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1087 struct intel_crtc_config *pipe_config)
32aad86f 1088{
8aca63aa 1089 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
6cc5f341
DV		 1090 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1091 struct drm_display_mode *mode = &pipe_config->requested_mode;
12682a97 1092
5d2d38dd
DV		 1093 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1094 pipe_config->pipe_bpp = 8*3;
1095
5bfe2ac0
DV		 1096 if (HAS_PCH_SPLIT(encoder->base.dev))
1097 pipe_config->has_pch_encoder = true;
1098
32aad86f
CW		 1099 /* We need to construct preferred input timings based on our
1100 * output timings. To do that, we have to set the output
1101 * timings, even though this isn't really the right place in
1102 * the sequence to do it. Oh well.
1103 */
1104 if (intel_sdvo->is_tv) {
1105 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1106 return false;
12682a97 1107
c9a29698
DV		 1108 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1109 mode,
1110 adjusted_mode);
09ede541 1111 pipe_config->sdvo_tv_clock = true;
ea5b213a 1112 } else if (intel_sdvo->is_lvds) {
32aad86f 1113 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1114 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1115 return false;
12682a97 1116
c9a29698
DV		 1117 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1118 mode,
1119 adjusted_mode);
e2f0ba97 1120 }
32aad86f
CW		 1121
1122 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1123 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1124 */
6cc5f341
DV		 1125 pipe_config->pixel_multiplier =
1126 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1127
55bc60db
VS		 1128 if (intel_sdvo->color_range_auto) {
1129 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1130 /* FIXME: This bit is only valid when using TMDS encoding and 8
1131 * bit per color mode. */
55bc60db 1132 if (intel_sdvo->has_hdmi_monitor &&
18316c8c 1133 drm_match_cea_mode(adjusted_mode) > 1)
4f3a8bc7 1134 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1135 else
1136 intel_sdvo->color_range = 0;
1137 }
1138
3685a8f3 1139 if (intel_sdvo->color_range)
50f3b016 1140 pipe_config->limited_color_range = true;
3685a8f3 1141
70484559
DV		 1142 /* Clock computation needs to happen after pixel multiplier. */
1143 if (intel_sdvo->is_tv)
1144 i9xx_adjust_sdvo_tv_clock(pipe_config);
1145
e2f0ba97
JB		 1146 return true;
1147}
1148
6cc5f341 1149static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
e2f0ba97 1150{
6cc5f341 1151 struct drm_device *dev = intel_encoder->base.dev;
e2f0ba97 1152 struct drm_i915_private *dev_priv = dev->dev_private;
eeb47937 1153 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
6cc5f341 1154 struct drm_display_mode *adjusted_mode =
eeb47937
DV		 1155 &crtc->config.adjusted_mode;
1156 struct drm_display_mode *mode = &crtc->config.requested_mode;
8aca63aa 1157 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1158 u32 sdvox;
e2f0ba97 1159 struct intel_sdvo_in_out_map in_out;
6651819b 1160 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1161 int rate;
e2f0ba97
JB		 1162
1163 if (!mode)
1164 return;
1165
1166 /* First, set the input mapping for the first input to our controlled
1167 * output. This is only correct if we're a single-input device, in
1168 * which case the first input is the output from the appropriate SDVO
1169 * channel on the motherboard. In a two-input device, the first input
1170 * will be SDVOB and the second SDVOC.
1171 */
ea5b213a 1172 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1173 in_out.in1 = 0;
1174
c74696b9
PR		 1175 intel_sdvo_set_value(intel_sdvo,
1176 SDVO_CMD_SET_IN_OUT_MAP,
1177 &in_out, sizeof(in_out));
e2f0ba97 1178
6c9547ff
CW		 1179 /* Set the output timings to the screen */
1180 if (!intel_sdvo_set_target_output(intel_sdvo,
1181 intel_sdvo->attached_output))
1182 return;
e2f0ba97 1183
6651819b
DV		 1184 /* lvds has a special fixed output timing. */
1185 if (intel_sdvo->is_lvds)
1186 intel_sdvo_get_dtd_from_mode(&output_dtd,
1187 intel_sdvo->sdvo_lvds_fixed_mode);
1188 else
1189 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1190 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1191 DRM_INFO("Setting output timings on %s failed\n",
1192 SDVO_NAME(intel_sdvo));
79e53945
JB		 1193
1194 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1195 if (!intel_sdvo_set_target_input(intel_sdvo))
1196 return;
79e53945 1197
97aaf910
CW		 1198 if (intel_sdvo->has_hdmi_monitor) {
1199 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1200 intel_sdvo_set_colorimetry(intel_sdvo,
1201 SDVO_COLORIMETRY_RGB256);
abedc077 1202 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1203 } else
1204 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1205
6c9547ff
CW		 1206 if (intel_sdvo->is_tv &&
1207 !intel_sdvo_set_tv_format(intel_sdvo))
1208 return;
e2f0ba97 1209
6651819b 1210 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1211
e751823d
EE		 1212 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1213 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1214 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1215 DRM_INFO("Setting input timings on %s failed\n",
1216 SDVO_NAME(intel_sdvo));
79e53945 1217
eeb47937 1218 switch (crtc->config.pixel_multiplier) {
6c9547ff 1219 default:
ef1b460d 1220 WARN(1, "unknown pixel mutlipler specified\n");
32aad86f
CW		 1221 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1222 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1223 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1224 }
32aad86f
CW		 1225 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1226 return;
79e53945
JB		 1227
1228 /* Set the SDVO control regs. */
a6c45cf0 1229 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1230 /* The real mode polarity is set by the SDVO commands, using
1231 * struct intel_sdvo_dtd. */
1232 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1233 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1234 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1235 if (INTEL_INFO(dev)->gen < 5)
1236 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1237 } else {
6c9547ff 1238 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1239 switch (intel_sdvo->sdvo_reg) {
e2debe91 1240 case GEN3_SDVOB:
e2f0ba97
JB		 1241 sdvox &= SDVOB_PRESERVE_MASK;
1242 break;
e2debe91 1243 case GEN3_SDVOC:
e2f0ba97
JB		 1244 sdvox &= SDVOC_PRESERVE_MASK;
1245 break;
1246 }
1247 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1248 }
3573c410
PZ		 1249
1250 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
eeb47937 1251 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1252 else
eeb47937 1253 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1254
da79de97 1255 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1256 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1257
a6c45cf0 1258 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1259 /* done in crtc_mode_set as the dpll_md reg must be written early */
1260 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1261 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1262 } else {
eeb47937 1263 sdvox |= (crtc->config.pixel_multiplier - 1)
6cc5f341 1264 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1265 }
1266
6714afb1
CW		 1267 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1268 INTEL_INFO(dev)->gen < 5)
12682a97 1269 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1270 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1271}
1272
4ac41f47 1273static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1274{
4ac41f47
DV		 1275 struct intel_sdvo_connector *intel_sdvo_connector =
1276 to_intel_sdvo_connector(&connector->base);
1277 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1278 u16 active_outputs = 0;
4ac41f47
DV		 1279
1280 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1281
1282 if (active_outputs & intel_sdvo_connector->output_flag)
1283 return true;
1284 else
1285 return false;
1286}
1287
1288static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1289 enum pipe *pipe)
1290{
1291 struct drm_device *dev = encoder->base.dev;
79e53945 1292 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1293 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1294 u16 active_outputs = 0;
4ac41f47
DV		 1295 u32 tmp;
1296
1297 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1298 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1299
7a7d1fb7 1300 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1301 return false;
1302
1303 if (HAS_PCH_CPT(dev))
1304 *pipe = PORT_TO_PIPE_CPT(tmp);
1305 else
1306 *pipe = PORT_TO_PIPE(tmp);
1307
1308 return true;
1309}
1310
045ac3b5
JB		 1311static void intel_sdvo_get_config(struct intel_encoder *encoder,
1312 struct intel_crtc_config *pipe_config)
1313{
6c49f241
DV		 1314 struct drm_device *dev = encoder->base.dev;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1316 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1317 struct intel_sdvo_dtd dtd;
6c49f241 1318 int encoder_pixel_multiplier = 0;
18442d08 1319 int dotclock;
6c49f241
DV		 1320 u32 flags = 0, sdvox;
1321 u8 val;
045ac3b5
JB		 1322 bool ret;
1323
1324 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1325 if (!ret) {
bb760063
DV		 1326 /* Some sdvo encoders are not spec compliant and don't
1327 * implement the mandatory get_timings function. */
045ac3b5 1328 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1329 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1330 } else {
1331 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1332 flags |= DRM_MODE_FLAG_PHSYNC;
1333 else
1334 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1335
bb760063
DV		 1336 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1337 flags |= DRM_MODE_FLAG_PVSYNC;
1338 else
1339 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1340 }
1341
045ac3b5 1342 pipe_config->adjusted_mode.flags |= flags;
045ac3b5 1343
fdafa9e2
DV		 1344 /*
1345 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1346 * the sdvo port register, on all other platforms it is part of the dpll
1347 * state. Since the general pipe state readout happens before the
1348 * encoder->get_config we so already have a valid pixel multplier on all
1349 * other platfroms.
1350 */
6c49f241
DV		 1351 if (IS_I915G(dev) || IS_I915GM(dev)) {
1352 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1353 pipe_config->pixel_multiplier =
1354 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1355 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1356 }
045ac3b5 1357
18442d08
VS		 1358 dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier;
1359
1360 if (HAS_PCH_SPLIT(dev))
1361 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1362
1363 pipe_config->adjusted_mode.clock = dotclock;
1364
6c49f241 1365 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1366 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1367 &val, 1)) {
1368 switch (val) {
1369 case SDVO_CLOCK_RATE_MULT_1X:
1370 encoder_pixel_multiplier = 1;
1371 break;
1372 case SDVO_CLOCK_RATE_MULT_2X:
1373 encoder_pixel_multiplier = 2;
1374 break;
1375 case SDVO_CLOCK_RATE_MULT_4X:
1376 encoder_pixel_multiplier = 4;
1377 break;
1378 }
6c49f241 1379 }
fdafa9e2 1380
6c49f241
DV		 1381 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1382 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1383 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1384}
1385
ce22c320
DV		 1386static void intel_disable_sdvo(struct intel_encoder *encoder)
1387{
1388 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
8aca63aa 1389 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320
DV		 1390 u32 temp;
1391
1392 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1393 if (0)
1394 intel_sdvo_set_encoder_power_state(intel_sdvo,
1395 DRM_MODE_DPMS_OFF);
1396
1397 temp = I915_READ(intel_sdvo->sdvo_reg);
1398 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1399 /* HW workaround for IBX, we need to move the port to
1400 * transcoder A before disabling it. */
1401 if (HAS_PCH_IBX(encoder->base.dev)) {
1402 struct drm_crtc *crtc = encoder->base.crtc;
1403 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1404
1405 if (temp & SDVO_PIPE_B_SELECT) {
1406 temp &= ~SDVO_PIPE_B_SELECT;
1407 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1408 POSTING_READ(intel_sdvo->sdvo_reg);
1409
1410 /* Again we need to write this twice. */
1411 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1412 POSTING_READ(intel_sdvo->sdvo_reg);
1413
1414 /* Transcoder selection bits only update
1415 * effectively on vblank. */
1416 if (crtc)
1417 intel_wait_for_vblank(encoder->base.dev, pipe);
1418 else
1419 msleep(50);
1420 }
1421 }
1422
ce22c320
DV		 1423 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1424 }
1425}
1426
1427static void intel_enable_sdvo(struct intel_encoder *encoder)
1428{
1429 struct drm_device *dev = encoder->base.dev;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1431 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1432 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1433 u32 temp;
ce22c320
DV		 1434 bool input1, input2;
1435 int i;
1436 u8 status;
1437
1438 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1439 if ((temp & SDVO_ENABLE) == 0) {
1440 /* HW workaround for IBX, we need to move the port
dc0fa718
PZ		 1441 * to transcoder A before disabling it, so restore it here. */
1442 if (HAS_PCH_IBX(dev))
1443 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
776ca7cf 1444
ce22c320 1445 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1446 }
ce22c320
DV		 1447 for (i = 0; i < 2; i++)
1448 intel_wait_for_vblank(dev, intel_crtc->pipe);
1449
1450 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1451 /* Warn if the device reported failure to sync.
1452 * A lot of SDVO devices fail to notify of sync, but it's
1453 * a given it the status is a success, we succeeded.
1454 */
1455 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1456 DRM_DEBUG_KMS("First %s output reported failure to "
1457 "sync\n", SDVO_NAME(intel_sdvo));
1458 }
1459
1460 if (0)
1461 intel_sdvo_set_encoder_power_state(intel_sdvo,
1462 DRM_MODE_DPMS_ON);
1463 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1464}
1465
6b1c087b 1466/* Special dpms function to support cloning between dvo/sdvo/crt. */
b2cabb0e 1467static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1468{
b2cabb0e
DV		 1469 struct drm_crtc *crtc;
1470 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1471
1472 /* dvo supports only 2 dpms states. */
1473 if (mode != DRM_MODE_DPMS_ON)
1474 mode = DRM_MODE_DPMS_OFF;
1475
1476 if (mode == connector->dpms)
1477 return;
1478
1479 connector->dpms = mode;
1480
1481 /* Only need to change hw state when actually enabled */
1482 crtc = intel_sdvo->base.base.crtc;
1483 if (!crtc) {
1484 intel_sdvo->base.connectors_active = false;
1485 return;
1486 }
79e53945 1487
6b1c087b
JN		 1488 /* We set active outputs manually below in case pipe dpms doesn't change
1489 * due to cloning. */
79e53945 1490 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1491 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1492 if (0)
ea5b213a 1493 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1494
b2cabb0e
DV		 1495 intel_sdvo->base.connectors_active = false;
1496
1497 intel_crtc_update_dpms(crtc);
79e53945 1498 } else {
b2cabb0e
DV		 1499 intel_sdvo->base.connectors_active = true;
1500
1501 intel_crtc_update_dpms(crtc);
79e53945
JB		 1502
1503 if (0)
ea5b213a
CW		 1504 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1505 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1506 }
0a91ca29 1507
b980514c 1508 intel_modeset_check_state(connector->dev);
79e53945
JB		 1509}
1510
79e53945
JB		 1511static int intel_sdvo_mode_valid(struct drm_connector *connector,
1512 struct drm_display_mode *mode)
1513{
df0e9248 1514 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1515
1516 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1517 return MODE_NO_DBLESCAN;
1518
ea5b213a 1519 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1520 return MODE_CLOCK_LOW;
1521
ea5b213a 1522 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1523 return MODE_CLOCK_HIGH;
1524
8545423a 1525 if (intel_sdvo->is_lvds) {
ea5b213a 1526 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1527 return MODE_PANEL;
1528
ea5b213a 1529 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1530 return MODE_PANEL;
1531 }
1532
79e53945
JB		 1533 return MODE_OK;
1534}
1535
ea5b213a 1536static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1537{
1a3665c8 1538 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1539 if (!intel_sdvo_get_value(intel_sdvo,
1540 SDVO_CMD_GET_DEVICE_CAPS,
1541 caps, sizeof(*caps)))
1542 return false;
1543
1544 DRM_DEBUG_KMS("SDVO capabilities:\n"
1545 " vendor_id: %d\n"
1546 " device_id: %d\n"
1547 " device_rev_id: %d\n"
1548 " sdvo_version_major: %d\n"
1549 " sdvo_version_minor: %d\n"
1550 " sdvo_inputs_mask: %d\n"
1551 " smooth_scaling: %d\n"
1552 " sharp_scaling: %d\n"
1553 " up_scaling: %d\n"
1554 " down_scaling: %d\n"
1555 " stall_support: %d\n"
1556 " output_flags: %d\n",
1557 caps->vendor_id,
1558 caps->device_id,
1559 caps->device_rev_id,
1560 caps->sdvo_version_major,
1561 caps->sdvo_version_minor,
1562 caps->sdvo_inputs_mask,
1563 caps->smooth_scaling,
1564 caps->sharp_scaling,
1565 caps->up_scaling,
1566 caps->down_scaling,
1567 caps->stall_support,
1568 caps->output_flags);
1569
1570 return true;
79e53945
JB		 1571}
1572
5fa7ac9c 1573static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1574{
768b107e 1575 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1576 uint16_t hotplug;
79e53945 1577
768b107e
DV		 1578 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1579 * on the line. */
1580 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1581 return 0;
768b107e 1582
5fa7ac9c
JN		 1583 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1584 &hotplug, sizeof(hotplug)))
1585 return 0;
768b107e 1586
5fa7ac9c 1587 return hotplug;
79e53945
JB		 1588}
1589
cc68c81a 1590static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1591{
8aca63aa 1592 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1593
5fa7ac9c
JN		 1594 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1595 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1596}
1597
fb7a46f3 1598static bool
ea5b213a 1599intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1600{
bc65212c 1601 /* Is there more than one type of output? */
2294488d 1602 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1603}
1604
f899fc64 1605static struct edid *
e957d772 1606intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1607{
e957d772
CW		 1608 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1609 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1610}
1611
ff482d83
CW		 1612/* Mac mini hack -- use the same DDC as the analog connector */
1613static struct edid *
1614intel_sdvo_get_analog_edid(struct drm_connector *connector)
1615{
f899fc64 1616 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1617
0c1dab89 1618 return drm_get_edid(connector,
3bd7d909 1619 intel_gmbus_get_adapter(dev_priv,
41aa3448 1620 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1621}
1622
c43b5634 1623static enum drm_connector_status
8bf38485 1624intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1625{
df0e9248 1626 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1627 enum drm_connector_status status;
1628 struct edid *edid;
9dff6af8 1629
e957d772 1630 edid = intel_sdvo_get_edid(connector);
57cdaf90 1631
ea5b213a 1632 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1633 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1634
7c3f0a27
ZY		 1635 /*
1636 * Don't use the 1 as the argument of DDC bus switch to get
1637 * the EDID. It is used for SDVO SPD ROM.
1638 */
9d1a903d 1639 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1640 intel_sdvo->ddc_bus = ddc;
1641 edid = intel_sdvo_get_edid(connector);
1642 if (edid)
7c3f0a27 1643 break;
7c3f0a27 1644 }
e957d772
CW		 1645 /*
1646 * If we found the EDID on the other bus,
1647 * assume that is the correct DDC bus.
1648 */
1649 if (edid == NULL)
1650 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1651 }
9d1a903d
CW		 1652
1653 /*
1654 * When there is no edid and no monitor is connected with VGA
1655 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1656 */
ff482d83
CW		 1657 if (edid == NULL)
1658 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1659
2f551c84 1660 status = connector_status_unknown;
9dff6af8 1661 if (edid != NULL) {
149c36a3 1662 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1663 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1664 status = connector_status_connected;
da79de97
CW		 1665 if (intel_sdvo->is_hdmi) {
1666 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1667 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1668 intel_sdvo->rgb_quant_range_selectable =
1669 drm_rgb_quant_range_selectable(edid);
da79de97 1670 }
13946743
CW		 1671 } else
1672 status = connector_status_disconnected;
9d1a903d
CW		 1673 kfree(edid);
1674 }
7f36e7ed
CW		 1675
1676 if (status == connector_status_connected) {
1677 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1678 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1679 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1680 }
1681
2b8d33f7 1682 return status;
9dff6af8
ML		 1683}
1684
52220085
CW		 1685static bool
1686intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1687 struct edid *edid)
1688{
1689 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1690 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1691
1692 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1693 connector_is_digital, monitor_is_digital);
1694 return connector_is_digital == monitor_is_digital;
1695}
1696
7b334fcb 1697static enum drm_connector_status
930a9e28 1698intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1699{
fb7a46f3 1700 uint16_t response;
df0e9248 1701 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1702 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1703 enum drm_connector_status ret;
79e53945 1704
164c8598
CW		 1705 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1706 connector->base.id, drm_get_connector_name(connector));
1707
fc37381c
CW		 1708 if (!intel_sdvo_get_value(intel_sdvo,
1709 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1710 &response, 2))
32aad86f 1711 return connector_status_unknown;
79e53945 1712
e957d772
CW		 1713 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1714 response & 0xff, response >> 8,
1715 intel_sdvo_connector->output_flag);
e2f0ba97 1716
fb7a46f3 1717 if (response == 0)
79e53945 1718 return connector_status_disconnected;
fb7a46f3 1719
ea5b213a 1720 intel_sdvo->attached_output = response;
14571b4c 1721
97aaf910
CW		 1722 intel_sdvo->has_hdmi_monitor = false;
1723 intel_sdvo->has_hdmi_audio = false;
abedc077 1724 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1725
615fb93f 1726 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1727 ret = connector_status_disconnected;
13946743 1728 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1729 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1730 else {
1731 struct edid *edid;
1732
1733 /* if we have an edid check it matches the connection */
1734 edid = intel_sdvo_get_edid(connector);
1735 if (edid == NULL)
1736 edid = intel_sdvo_get_analog_edid(connector);
1737 if (edid != NULL) {
52220085
CW		 1738 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1739 edid))
13946743 1740 ret = connector_status_connected;
52220085
CW		 1741 else
1742 ret = connector_status_disconnected;
1743
13946743
CW		 1744 kfree(edid);
1745 } else
1746 ret = connector_status_connected;
1747 }
14571b4c
ZW		 1748
1749 /* May update encoder flag for like clock for SDVO TV, etc.*/
1750 if (ret == connector_status_connected) {
ea5b213a
CW		 1751 intel_sdvo->is_tv = false;
1752 intel_sdvo->is_lvds = false;
14571b4c 1753
09ede541 1754 if (response & SDVO_TV_MASK)
ea5b213a 1755 intel_sdvo->is_tv = true;
14571b4c 1756 if (response & SDVO_LVDS_MASK)
8545423a 1757 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1758 }
14571b4c
ZW		 1759
1760 return ret;
79e53945
JB		 1761}
1762
e2f0ba97 1763static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1764{
ff482d83 1765 struct edid *edid;
79e53945
JB		 1766
1767 /* set the bus switch and get the modes */
e957d772 1768 edid = intel_sdvo_get_edid(connector);
79e53945 1769
57cdaf90
KP		 1770 /*
1771 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1772 * link between analog and digital outputs. So, if the regular SDVO
1773 * DDC fails, check to see if the analog output is disconnected, in
1774 * which case we'll look there for the digital DDC data.
e2f0ba97 1775 */
f899fc64
CW		 1776 if (edid == NULL)
1777 edid = intel_sdvo_get_analog_edid(connector);
1778
ff482d83 1779 if (edid != NULL) {
52220085
CW		 1780 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1781 edid)) {
0c1dab89
CW		 1782 drm_mode_connector_update_edid_property(connector, edid);
1783 drm_add_edid_modes(connector, edid);
1784 }
13946743 1785
ff482d83 1786 kfree(edid);
e2f0ba97 1787 }
e2f0ba97
JB		 1788}
1789
1790/*
1791 * Set of SDVO TV modes.
1792 * Note! This is in reply order (see loop in get_tv_modes).
1793 * XXX: all 60Hz refresh?
1794 */
b1f559ec 1795static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1796 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1797 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1798 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1799 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1800 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1801 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1802 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1803 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1805 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1806 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1807 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1808 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1809 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1810 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1811 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1812 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1814 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1815 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1817 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1818 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1820 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1821 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1823 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1824 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1826 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1827 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1829 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1830 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1832 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1833 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1835 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1836 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1838 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1839 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1841 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1842 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1844 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1845 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1847 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1848 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1850 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1851 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1853};
1854
1855static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1856{
df0e9248 1857 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1858 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1859 uint32_t reply = 0, format_map = 0;
1860 int i;
e2f0ba97
JB		 1861
1862 /* Read the list of supported input resolutions for the selected TV
1863 * format.
1864 */
40039750 1865 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1866 memcpy(&tv_res, &format_map,
32aad86f 1867 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1868
32aad86f
CW		 1869 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1870 return;
ce6feabd 1871
32aad86f 1872 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1873 if (!intel_sdvo_write_cmd(intel_sdvo,
1874 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1875 &tv_res, sizeof(tv_res)))
1876 return;
1877 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1878 return;
1879
1880 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1881 if (reply & (1 << i)) {
1882 struct drm_display_mode *nmode;
1883 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1884 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1885 if (nmode)
1886 drm_mode_probed_add(connector, nmode);
1887 }
e2f0ba97
JB		 1888}
1889
7086c87f
ML		 1890static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1891{
df0e9248 1892 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1893 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1894 struct drm_display_mode *newmode;
7086c87f
ML		 1895
1896 /*
c3456fb3 1897 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 1898 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 1899 */
41aa3448 1900 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1901 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1902 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1903 if (newmode != NULL) {
1904 /* Guarantee the mode is preferred */
1905 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1906 DRM_MODE_TYPE_DRIVER);
1907 drm_mode_probed_add(connector, newmode);
1908 }
1909 }
12682a97 1910
4300a0f8
DA		 1911 /*
1912 * Attempt to get the mode list from DDC.
1913 * Assume that the preferred modes are
1914 * arranged in priority order.
1915 */
1916 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1917
12682a97 1918 list_for_each_entry(newmode, &connector->probed_modes, head) {
1919 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1920 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1921 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1922
8545423a 1923 intel_sdvo->is_lvds = true;
12682a97 1924 break;
1925 }
1926 }
1927
7086c87f
ML		 1928}
1929
e2f0ba97
JB		 1930static int intel_sdvo_get_modes(struct drm_connector *connector)
1931{
615fb93f 1932 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1933
615fb93f 1934 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1935 intel_sdvo_get_tv_modes(connector);
615fb93f 1936 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1937 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1938 else
1939 intel_sdvo_get_ddc_modes(connector);
1940
32aad86f 1941 return !list_empty(&connector->probed_modes);
79e53945
JB		 1942}
1943
fcc8d672
CW		 1944static void
1945intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1946{
615fb93f 1947 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1948 struct drm_device *dev = connector->dev;
1949
c5521706
CW		 1950 if (intel_sdvo_connector->left)
1951 drm_property_destroy(dev, intel_sdvo_connector->left);
1952 if (intel_sdvo_connector->right)
1953 drm_property_destroy(dev, intel_sdvo_connector->right);
1954 if (intel_sdvo_connector->top)
1955 drm_property_destroy(dev, intel_sdvo_connector->top);
1956 if (intel_sdvo_connector->bottom)
1957 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1958 if (intel_sdvo_connector->hpos)
1959 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1960 if (intel_sdvo_connector->vpos)
1961 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1962 if (intel_sdvo_connector->saturation)
1963 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1964 if (intel_sdvo_connector->contrast)
1965 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1966 if (intel_sdvo_connector->hue)
1967 drm_property_destroy(dev, intel_sdvo_connector->hue);
1968 if (intel_sdvo_connector->sharpness)
1969 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1970 if (intel_sdvo_connector->flicker_filter)
1971 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1972 if (intel_sdvo_connector->flicker_filter_2d)
1973 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1974 if (intel_sdvo_connector->flicker_filter_adaptive)
1975 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1976 if (intel_sdvo_connector->tv_luma_filter)
1977 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1978 if (intel_sdvo_connector->tv_chroma_filter)
1979 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1980 if (intel_sdvo_connector->dot_crawl)
1981 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1982 if (intel_sdvo_connector->brightness)
1983 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1984}
1985
79e53945
JB		 1986static void intel_sdvo_destroy(struct drm_connector *connector)
1987{
615fb93f 1988 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1989
c5521706 1990 if (intel_sdvo_connector->tv_format)
ce6feabd 1991 drm_property_destroy(connector->dev,
c5521706 1992 intel_sdvo_connector->tv_format);
b9219c5e 1993
d2a82a6f 1994 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1995 drm_sysfs_connector_remove(connector);
1996 drm_connector_cleanup(connector);
4b745b1e 1997 kfree(intel_sdvo_connector);
79e53945
JB		 1998}
1999
1aad7ac0
CW		 2000static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
2001{
2002 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2003 struct edid *edid;
2004 bool has_audio = false;
2005
2006 if (!intel_sdvo->is_hdmi)
2007 return false;
2008
2009 edid = intel_sdvo_get_edid(connector);
2010 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2011 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 2012 kfree(edid);
1aad7ac0
CW		 2013
2014 return has_audio;
2015}
2016
ce6feabd
ZY		 2017static int
2018intel_sdvo_set_property(struct drm_connector *connector,
2019 struct drm_property *property,
2020 uint64_t val)
2021{
df0e9248 2022 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 2023 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 2024 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 2025 uint16_t temp_value;
32aad86f
CW		 2026 uint8_t cmd;
2027 int ret;
ce6feabd 2028
662595df 2029 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 2030 if (ret)
2031 return ret;
ce6feabd 2032
3f43c48d 2033 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2034 int i = val;
2035 bool has_audio;
2036
2037 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 2038 return 0;
2039
1aad7ac0 2040 intel_sdvo_connector->force_audio = i;
7f36e7ed 2041
c3e5f67b 2042 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2043 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2044 else
c3e5f67b 2045 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 2046
1aad7ac0 2047 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 2048 return 0;
7f36e7ed 2049
1aad7ac0 2050 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 2051 goto done;
2052 }
2053
e953fd7b 2054 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2055 bool old_auto = intel_sdvo->color_range_auto;
2056 uint32_t old_range = intel_sdvo->color_range;
2057
55bc60db
VS		 2058 switch (val) {
2059 case INTEL_BROADCAST_RGB_AUTO:
2060 intel_sdvo->color_range_auto = true;
2061 break;
2062 case INTEL_BROADCAST_RGB_FULL:
2063 intel_sdvo->color_range_auto = false;
2064 intel_sdvo->color_range = 0;
2065 break;
2066 case INTEL_BROADCAST_RGB_LIMITED:
2067 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 2068 /* FIXME: this bit is only valid when using TMDS
2069 * encoding and 8 bit per color mode. */
2070 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 2071 break;
2072 default:
2073 return -EINVAL;
2074 }
ae4edb80
DV		 2075
2076 if (old_auto == intel_sdvo->color_range_auto &&
2077 old_range == intel_sdvo->color_range)
2078 return 0;
2079
7f36e7ed
CW		 2080 goto done;
2081 }
2082
c5521706
CW		 2083#define CHECK_PROPERTY(name, NAME) \
2084 if (intel_sdvo_connector->name == property) { \
2085 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2086 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2087 cmd = SDVO_CMD_SET_##NAME; \
2088 intel_sdvo_connector->cur_##name = temp_value; \
2089 goto set_value; \
2090 }
2091
2092 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 2093 if (val >= TV_FORMAT_NUM)
2094 return -EINVAL;
2095
40039750 2096 if (intel_sdvo->tv_format_index ==
615fb93f 2097 intel_sdvo_connector->tv_format_supported[val])
32aad86f 2098 return 0;
ce6feabd 2099
40039750 2100 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 2101 goto done;
32aad86f 2102 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2103 temp_value = val;
c5521706 2104 if (intel_sdvo_connector->left == property) {
662595df 2105 drm_object_property_set_value(&connector->base,
c5521706 2106 intel_sdvo_connector->right, val);
615fb93f 2107 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2108 return 0;
b9219c5e 2109
615fb93f
CW		 2110 intel_sdvo_connector->left_margin = temp_value;
2111 intel_sdvo_connector->right_margin = temp_value;
2112 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2113 intel_sdvo_connector->left_margin;
b9219c5e 2114 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2115 goto set_value;
2116 } else if (intel_sdvo_connector->right == property) {
662595df 2117 drm_object_property_set_value(&connector->base,
c5521706 2118 intel_sdvo_connector->left, val);
615fb93f 2119 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2120 return 0;
b9219c5e 2121
615fb93f
CW		 2122 intel_sdvo_connector->left_margin = temp_value;
2123 intel_sdvo_connector->right_margin = temp_value;
2124 temp_value = intel_sdvo_connector->max_hscan -
2125 intel_sdvo_connector->left_margin;
b9219c5e 2126 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2127 goto set_value;
2128 } else if (intel_sdvo_connector->top == property) {
662595df 2129 drm_object_property_set_value(&connector->base,
c5521706 2130 intel_sdvo_connector->bottom, val);
615fb93f 2131 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2132 return 0;
b9219c5e 2133
615fb93f
CW		 2134 intel_sdvo_connector->top_margin = temp_value;
2135 intel_sdvo_connector->bottom_margin = temp_value;
2136 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2137 intel_sdvo_connector->top_margin;
b9219c5e 2138 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2139 goto set_value;
2140 } else if (intel_sdvo_connector->bottom == property) {
662595df 2141 drm_object_property_set_value(&connector->base,
c5521706 2142 intel_sdvo_connector->top, val);
615fb93f 2143 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2144 return 0;
2145
615fb93f
CW		 2146 intel_sdvo_connector->top_margin = temp_value;
2147 intel_sdvo_connector->bottom_margin = temp_value;
2148 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2149 intel_sdvo_connector->top_margin;
b9219c5e 2150 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2151 goto set_value;
2152 }
2153 CHECK_PROPERTY(hpos, HPOS)
2154 CHECK_PROPERTY(vpos, VPOS)
2155 CHECK_PROPERTY(saturation, SATURATION)
2156 CHECK_PROPERTY(contrast, CONTRAST)
2157 CHECK_PROPERTY(hue, HUE)
2158 CHECK_PROPERTY(brightness, BRIGHTNESS)
2159 CHECK_PROPERTY(sharpness, SHARPNESS)
2160 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2161 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2162 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2163 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2164 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2165 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2166 }
b9219c5e 2167
c5521706 2168 return -EINVAL; /* unknown property */
b9219c5e 2169
c5521706
CW		 2170set_value:
2171 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2172 return -EIO;
b9219c5e 2173
b9219c5e 2174
c5521706 2175done:
c0c36b94
CW		 2176 if (intel_sdvo->base.base.crtc)
2177 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2178
32aad86f 2179 return 0;
c5521706 2180#undef CHECK_PROPERTY
ce6feabd
ZY		 2181}
2182
79e53945 2183static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2184 .dpms = intel_sdvo_dpms,
79e53945
JB		 2185 .detect = intel_sdvo_detect,
2186 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2187 .set_property = intel_sdvo_set_property,
79e53945
JB		 2188 .destroy = intel_sdvo_destroy,
2189};
2190
2191static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2192 .get_modes = intel_sdvo_get_modes,
2193 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2194 .best_encoder = intel_best_encoder,
79e53945
JB		 2195};
2196
b358d0a6 2197static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2198{
8aca63aa 2199 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2200
ea5b213a 2201 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2202 drm_mode_destroy(encoder->dev,
ea5b213a 2203 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2204
e957d772 2205 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2206 intel_encoder_destroy(encoder);
79e53945
JB		 2207}
2208
2209static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2210 .destroy = intel_sdvo_enc_destroy,
2211};
2212
b66d8424
CW		 2213static void
2214intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2215{
2216 uint16_t mask = 0;
2217 unsigned int num_bits;
2218
2219 /* Make a mask of outputs less than or equal to our own priority in the
2220 * list.
2221 */
2222 switch (sdvo->controlled_output) {
2223 case SDVO_OUTPUT_LVDS1:
2224 mask |= SDVO_OUTPUT_LVDS1;
2225 case SDVO_OUTPUT_LVDS0:
2226 mask |= SDVO_OUTPUT_LVDS0;
2227 case SDVO_OUTPUT_TMDS1:
2228 mask |= SDVO_OUTPUT_TMDS1;
2229 case SDVO_OUTPUT_TMDS0:
2230 mask |= SDVO_OUTPUT_TMDS0;
2231 case SDVO_OUTPUT_RGB1:
2232 mask |= SDVO_OUTPUT_RGB1;
2233 case SDVO_OUTPUT_RGB0:
2234 mask |= SDVO_OUTPUT_RGB0;
2235 break;
2236 }
2237
2238 /* Count bits to find what number we are in the priority list. */
2239 mask &= sdvo->caps.output_flags;
2240 num_bits = hweight16(mask);
2241 /* If more than 3 outputs, default to DDC bus 3 for now. */
2242 if (num_bits > 3)
2243 num_bits = 3;
2244
2245 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2246 sdvo->ddc_bus = 1 << num_bits;
2247}
79e53945 2248
e2f0ba97
JB		 2249/**
2250 * Choose the appropriate DDC bus for control bus switch command for this
2251 * SDVO output based on the controlled output.
2252 *
2253 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2254 * outputs, then LVDS outputs.
2255 */
2256static void
b1083333 2257intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2258 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2259{
b1083333 2260 struct sdvo_device_mapping *mapping;
e2f0ba97 2261
eef4eacb 2262 if (sdvo->is_sdvob)
b1083333
AJ		 2263 mapping = &(dev_priv->sdvo_mappings[0]);
2264 else
2265 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2266
b66d8424
CW		 2267 if (mapping->initialized)
2268 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2269 else
2270 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2271}
2272
e957d772
CW		 2273static void
2274intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2275 struct intel_sdvo *sdvo, u32 reg)
2276{
2277 struct sdvo_device_mapping *mapping;
46eb3036 2278 u8 pin;
e957d772 2279
eef4eacb 2280 if (sdvo->is_sdvob)
e957d772
CW		 2281 mapping = &dev_priv->sdvo_mappings[0];
2282 else
2283 mapping = &dev_priv->sdvo_mappings[1];
2284
6cb1612a 2285 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2286 pin = mapping->i2c_pin;
6cb1612a
JN		 2287 else
2288 pin = GMBUS_PORT_DPB;
e957d772 2289
6cb1612a
JN		 2290 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2291
2292 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2293 * our code totally fails once we start using gmbus. Hence fall back to
2294 * bit banging for now. */
2295 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2296}
2297
fbfcc4f3
JN		 2298/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2299static void
2300intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2301{
2302 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2303}
2304
e2f0ba97 2305static bool
e27d8538 2306intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2307{
97aaf910 2308 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2309}
2310
714605e4 2311static u8
eef4eacb 2312intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2313{
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315 struct sdvo_device_mapping *my_mapping, *other_mapping;
2316
eef4eacb 2317 if (sdvo->is_sdvob) {
714605e4 2318 my_mapping = &dev_priv->sdvo_mappings[0];
2319 other_mapping = &dev_priv->sdvo_mappings[1];
2320 } else {
2321 my_mapping = &dev_priv->sdvo_mappings[1];
2322 other_mapping = &dev_priv->sdvo_mappings[0];
2323 }
2324
2325 /* If the BIOS described our SDVO device, take advantage of it. */
2326 if (my_mapping->slave_addr)
2327 return my_mapping->slave_addr;
2328
2329 /* If the BIOS only described a different SDVO device, use the
2330 * address that it isn't using.
2331 */
2332 if (other_mapping->slave_addr) {
2333 if (other_mapping->slave_addr == 0x70)
2334 return 0x72;
2335 else
2336 return 0x70;
2337 }
2338
2339 /* No SDVO device info is found for another DVO port,
2340 * so use mapping assumption we had before BIOS parsing.
2341 */
eef4eacb 2342 if (sdvo->is_sdvob)
714605e4 2343 return 0x70;
2344 else
2345 return 0x72;
2346}
2347
14571b4c 2348static void
df0e9248
CW		 2349intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2350 struct intel_sdvo *encoder)
14571b4c 2351{
df0e9248
CW		 2352 drm_connector_init(encoder->base.base.dev,
2353 &connector->base.base,
2354 &intel_sdvo_connector_funcs,
2355 connector->base.base.connector_type);
6070a4a9 2356
df0e9248
CW		 2357 drm_connector_helper_add(&connector->base.base,
2358 &intel_sdvo_connector_helper_funcs);
14571b4c 2359
8f4839e2 2360 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2361 connector->base.base.doublescan_allowed = 0;
2362 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2363 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2364
df0e9248
CW		 2365 intel_connector_attach_encoder(&connector->base, &encoder->base);
2366 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2367}
6070a4a9 2368
7f36e7ed 2369static void
55bc60db
VS		 2370intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2371 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2372{
2373 struct drm_device *dev = connector->base.base.dev;
2374
3f43c48d 2375 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2376 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2377 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2378 intel_sdvo->color_range_auto = true;
2379 }
7f36e7ed
CW		 2380}
2381
fb7a46f3 2382static bool
ea5b213a 2383intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2384{
4ef69c7a 2385 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2386 struct drm_connector *connector;
cc68c81a 2387 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2388 struct intel_connector *intel_connector;
615fb93f 2389 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2390
615fb93f
CW		 2391 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2392 if (!intel_sdvo_connector)
14571b4c
ZW		 2393 return false;
2394
14571b4c 2395 if (device == 0) {
ea5b213a 2396 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2397 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2398 } else if (device == 1) {
ea5b213a 2399 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2400 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2401 }
2402
615fb93f 2403 intel_connector = &intel_sdvo_connector->base;
14571b4c 2404 connector = &intel_connector->base;
5fa7ac9c
JN		 2405 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2406 intel_sdvo_connector->output_flag) {
5fa7ac9c 2407 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2408 /* Some SDVO devices have one-shot hotplug interrupts.
2409 * Ensure that they get re-enabled when an interrupt happens.
2410 */
2411 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2412 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2413 } else {
821450c6 2414 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2415 }
14571b4c
ZW		 2416 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2417 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2418
e27d8538 2419 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2420 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2421 intel_sdvo->is_hdmi = true;
14571b4c 2422 }
14571b4c 2423
df0e9248 2424 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221 2425 if (intel_sdvo->is_hdmi)
55bc60db 2426 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2427
2428 return true;
2429}
2430
2431static bool
ea5b213a 2432intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2433{
4ef69c7a
CW		 2434 struct drm_encoder *encoder = &intel_sdvo->base.base;
2435 struct drm_connector *connector;
2436 struct intel_connector *intel_connector;
2437 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2438
615fb93f
CW		 2439 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2440 if (!intel_sdvo_connector)
2441 return false;
14571b4c 2442
615fb93f 2443 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2444 connector = &intel_connector->base;
2445 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2446 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2447
4ef69c7a
CW		 2448 intel_sdvo->controlled_output |= type;
2449 intel_sdvo_connector->output_flag = type;
14571b4c 2450
4ef69c7a 2451 intel_sdvo->is_tv = true;
14571b4c 2452
df0e9248 2453 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2454
4ef69c7a 2455 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2456 goto err;
14571b4c 2457
4ef69c7a 2458 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2459 goto err;
14571b4c 2460
4ef69c7a 2461 return true;
32aad86f
CW		 2462
2463err:
123d5c01 2464 intel_sdvo_destroy(connector);
32aad86f 2465 return false;
14571b4c
ZW		 2466}
2467
2468static bool
ea5b213a 2469intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2470{
4ef69c7a
CW		 2471 struct drm_encoder *encoder = &intel_sdvo->base.base;
2472 struct drm_connector *connector;
2473 struct intel_connector *intel_connector;
2474 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2475
615fb93f
CW		 2476 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2477 if (!intel_sdvo_connector)
2478 return false;
14571b4c 2479
615fb93f 2480 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2481 connector = &intel_connector->base;
821450c6 2482 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2483 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2484 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2485
2486 if (device == 0) {
2487 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2488 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2489 } else if (device == 1) {
2490 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2491 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2492 }
2493
df0e9248
CW		 2494 intel_sdvo_connector_init(intel_sdvo_connector,
2495 intel_sdvo);
4ef69c7a 2496 return true;
14571b4c
ZW		 2497}
2498
2499static bool
ea5b213a 2500intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2501{
4ef69c7a
CW		 2502 struct drm_encoder *encoder = &intel_sdvo->base.base;
2503 struct drm_connector *connector;
2504 struct intel_connector *intel_connector;
2505 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2506
615fb93f
CW		 2507 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2508 if (!intel_sdvo_connector)
2509 return false;
14571b4c 2510
615fb93f
CW		 2511 intel_connector = &intel_sdvo_connector->base;
2512 connector = &intel_connector->base;
4ef69c7a
CW		 2513 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2514 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2515
2516 if (device == 0) {
2517 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2518 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2519 } else if (device == 1) {
2520 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2521 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2522 }
2523
df0e9248 2524 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2525 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2526 goto err;
2527
2528 return true;
2529
2530err:
123d5c01 2531 intel_sdvo_destroy(connector);
32aad86f 2532 return false;
14571b4c
ZW		 2533}
2534
2535static bool
ea5b213a 2536intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2537{
ea5b213a 2538 intel_sdvo->is_tv = false;
ea5b213a 2539 intel_sdvo->is_lvds = false;
fb7a46f3 2540
14571b4c 2541 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2542
14571b4c 2543 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2544 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2545 return false;
2546
2547 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2548 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2549 return false;
2550
2551 /* TV has no XXX1 function block */
a1f4b7ff 2552 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2553 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2554 return false;
2555
2556 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2557 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2558 return false;
fb7a46f3 2559
a0b1c7a5
CW		 2560 if (flags & SDVO_OUTPUT_YPRPB0)
2561 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2562 return false;
2563
14571b4c 2564 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2565 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2566 return false;
2567
2568 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2569 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2570 return false;
2571
2572 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2573 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2574 return false;
2575
2576 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2577 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2578 return false;
fb7a46f3 2579
14571b4c 2580 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2581 unsigned char bytes[2];
2582
ea5b213a
CW		 2583 intel_sdvo->controlled_output = 0;
2584 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2585 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2586 SDVO_NAME(intel_sdvo),
51c8b407 2587 bytes[0], bytes[1]);
14571b4c 2588 return false;
fb7a46f3 2589 }
27f8227b 2590 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2591
14571b4c 2592 return true;
fb7a46f3 2593}
2594
d0ddfbd3
JN		 2595static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2596{
2597 struct drm_device *dev = intel_sdvo->base.base.dev;
2598 struct drm_connector *connector, *tmp;
2599
2600 list_for_each_entry_safe(connector, tmp,
2601 &dev->mode_config.connector_list, head) {
2602 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2603 intel_sdvo_destroy(connector);
2604 }
2605}
2606
32aad86f
CW		 2607static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2608 struct intel_sdvo_connector *intel_sdvo_connector,
2609 int type)
ce6feabd 2610{
4ef69c7a 2611 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2612 struct intel_sdvo_tv_format format;
2613 uint32_t format_map, i;
ce6feabd 2614
32aad86f
CW		 2615 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2616 return false;
ce6feabd 2617
1a3665c8 2618 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2619 if (!intel_sdvo_get_value(intel_sdvo,
2620 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2621 &format, sizeof(format)))
2622 return false;
ce6feabd 2623
32aad86f 2624 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2625
2626 if (format_map == 0)
32aad86f 2627 return false;
ce6feabd 2628
615fb93f 2629 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2630 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2631 if (format_map & (1 << i))
2632 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2633
2634
c5521706 2635 intel_sdvo_connector->tv_format =
32aad86f
CW		 2636 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2637 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2638 if (!intel_sdvo_connector->tv_format)
fcc8d672 2639 return false;
ce6feabd 2640
615fb93f 2641 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2642 drm_property_add_enum(
c5521706 2643 intel_sdvo_connector->tv_format, i,
40039750 2644 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2645
40039750 2646 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2647 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2648 intel_sdvo_connector->tv_format, 0);
32aad86f 2649 return true;
ce6feabd
ZY		 2650
2651}
2652
c5521706
CW		 2653#define ENHANCEMENT(name, NAME) do { \
2654 if (enhancements.name) { \
2655 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2656 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2657 return false; \
2658 intel_sdvo_connector->max_##name = data_value[0]; \
2659 intel_sdvo_connector->cur_##name = response; \
2660 intel_sdvo_connector->name = \
d9bc3c02 2661 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2662 if (!intel_sdvo_connector->name) return false; \
662595df 2663 drm_object_attach_property(&connector->base, \
c5521706
CW		 2664 intel_sdvo_connector->name, \
2665 intel_sdvo_connector->cur_##name); \
2666 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2667 data_value[0], data_value[1], response); \
2668 } \
0206e353 2669} while (0)
c5521706
CW		 2670
2671static bool
2672intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2673 struct intel_sdvo_connector *intel_sdvo_connector,
2674 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2675{
4ef69c7a 2676 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2677 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2678 uint16_t response, data_value[2];
2679
c5521706
CW		 2680 /* when horizontal overscan is supported, Add the left/right property */
2681 if (enhancements.overscan_h) {
2682 if (!intel_sdvo_get_value(intel_sdvo,
2683 SDVO_CMD_GET_MAX_OVERSCAN_H,
2684 &data_value, 4))
2685 return false;
32aad86f 2686
c5521706
CW		 2687 if (!intel_sdvo_get_value(intel_sdvo,
2688 SDVO_CMD_GET_OVERSCAN_H,
2689 &response, 2))
2690 return false;
fcc8d672 2691
c5521706
CW		 2692 intel_sdvo_connector->max_hscan = data_value[0];
2693 intel_sdvo_connector->left_margin = data_value[0] - response;
2694 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2695 intel_sdvo_connector->left =
d9bc3c02 2696 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2697 if (!intel_sdvo_connector->left)
2698 return false;
fcc8d672 2699
662595df 2700 drm_object_attach_property(&connector->base,
c5521706
CW		 2701 intel_sdvo_connector->left,
2702 intel_sdvo_connector->left_margin);
fcc8d672 2703
c5521706 2704 intel_sdvo_connector->right =
d9bc3c02 2705 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2706 if (!intel_sdvo_connector->right)
2707 return false;
32aad86f 2708
662595df 2709 drm_object_attach_property(&connector->base,
c5521706
CW		 2710 intel_sdvo_connector->right,
2711 intel_sdvo_connector->right_margin);
2712 DRM_DEBUG_KMS("h_overscan: max %d, "
2713 "default %d, current %d\n",
2714 data_value[0], data_value[1], response);
2715 }
32aad86f 2716
c5521706
CW		 2717 if (enhancements.overscan_v) {
2718 if (!intel_sdvo_get_value(intel_sdvo,
2719 SDVO_CMD_GET_MAX_OVERSCAN_V,
2720 &data_value, 4))
2721 return false;
fcc8d672 2722
c5521706
CW		 2723 if (!intel_sdvo_get_value(intel_sdvo,
2724 SDVO_CMD_GET_OVERSCAN_V,
2725 &response, 2))
2726 return false;
32aad86f 2727
c5521706
CW		 2728 intel_sdvo_connector->max_vscan = data_value[0];
2729 intel_sdvo_connector->top_margin = data_value[0] - response;
2730 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2731 intel_sdvo_connector->top =
d9bc3c02
SH		 2732 drm_property_create_range(dev, 0,
2733 "top_margin", 0, data_value[0]);
c5521706
CW		 2734 if (!intel_sdvo_connector->top)
2735 return false;
32aad86f 2736
662595df 2737 drm_object_attach_property(&connector->base,
c5521706
CW		 2738 intel_sdvo_connector->top,
2739 intel_sdvo_connector->top_margin);
fcc8d672 2740
c5521706 2741 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2742 drm_property_create_range(dev, 0,
2743 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2744 if (!intel_sdvo_connector->bottom)
2745 return false;
32aad86f 2746
662595df 2747 drm_object_attach_property(&connector->base,
c5521706
CW		 2748 intel_sdvo_connector->bottom,
2749 intel_sdvo_connector->bottom_margin);
2750 DRM_DEBUG_KMS("v_overscan: max %d, "
2751 "default %d, current %d\n",
2752 data_value[0], data_value[1], response);
2753 }
32aad86f 2754
c5521706
CW		 2755 ENHANCEMENT(hpos, HPOS);
2756 ENHANCEMENT(vpos, VPOS);
2757 ENHANCEMENT(saturation, SATURATION);
2758 ENHANCEMENT(contrast, CONTRAST);
2759 ENHANCEMENT(hue, HUE);
2760 ENHANCEMENT(sharpness, SHARPNESS);
2761 ENHANCEMENT(brightness, BRIGHTNESS);
2762 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2763 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2764 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2765 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2766 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2767
e044218a
CW		 2768 if (enhancements.dot_crawl) {
2769 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2770 return false;
2771
2772 intel_sdvo_connector->max_dot_crawl = 1;
2773 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2774 intel_sdvo_connector->dot_crawl =
d9bc3c02 2775 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2776 if (!intel_sdvo_connector->dot_crawl)
2777 return false;
2778
662595df 2779 drm_object_attach_property(&connector->base,
e044218a
CW		 2780 intel_sdvo_connector->dot_crawl,
2781 intel_sdvo_connector->cur_dot_crawl);
2782 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2783 }
2784
c5521706
CW		 2785 return true;
2786}
32aad86f 2787
c5521706
CW		 2788static bool
2789intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2790 struct intel_sdvo_connector *intel_sdvo_connector,
2791 struct intel_sdvo_enhancements_reply enhancements)
2792{
4ef69c7a 2793 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2794 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2795 uint16_t response, data_value[2];
32aad86f 2796
c5521706 2797 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2798
c5521706
CW		 2799 return true;
2800}
2801#undef ENHANCEMENT
32aad86f 2802
c5521706
CW		 2803static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2804 struct intel_sdvo_connector *intel_sdvo_connector)
2805{
2806 union {
2807 struct intel_sdvo_enhancements_reply reply;
2808 uint16_t response;
2809 } enhancements;
32aad86f 2810
1a3665c8
CW		 2811 BUILD_BUG_ON(sizeof(enhancements) != 2);
2812
cf9a2f3a
CW		 2813 enhancements.response = 0;
2814 intel_sdvo_get_value(intel_sdvo,
2815 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2816 &enhancements, sizeof(enhancements));
c5521706
CW		 2817 if (enhancements.response == 0) {
2818 DRM_DEBUG_KMS("No enhancement is supported\n");
2819 return true;
b9219c5e 2820 }
32aad86f 2821
c5521706
CW		 2822 if (IS_TV(intel_sdvo_connector))
2823 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2824 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2825 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2826 else
2827 return true;
e957d772
CW		 2828}
2829
2830static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2831 struct i2c_msg *msgs,
2832 int num)
2833{
2834 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2835
e957d772
CW		 2836 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2837 return -EIO;
2838
2839 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2840}
2841
2842static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2843{
2844 struct intel_sdvo *sdvo = adapter->algo_data;
2845 return sdvo->i2c->algo->functionality(sdvo->i2c);
2846}
2847
2848static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2849 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2850 .functionality = intel_sdvo_ddc_proxy_func
2851};
2852
2853static bool
2854intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2855 struct drm_device *dev)
2856{
2857 sdvo->ddc.owner = THIS_MODULE;
2858 sdvo->ddc.class = I2C_CLASS_DDC;
2859 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2860 sdvo->ddc.dev.parent = &dev->pdev->dev;
2861 sdvo->ddc.algo_data = sdvo;
2862 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2863
2864 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2865}
2866
eef4eacb 2867bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2868{
b01f2c3a 2869 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2870 struct intel_encoder *intel_encoder;
ea5b213a 2871 struct intel_sdvo *intel_sdvo;
79e53945 2872 int i;
ea5b213a
CW		 2873 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2874 if (!intel_sdvo)
7d57382e 2875 return false;
79e53945 2876
56184e3d 2877 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2878 intel_sdvo->is_sdvob = is_sdvob;
2879 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2880 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2881 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2882 goto err_i2c_bus;
e957d772 2883
56184e3d 2884 /* encoder type will be decided later */
ea5b213a 2885 intel_encoder = &intel_sdvo->base;
21d40d37 2886 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2887 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2888
79e53945
JB		 2889 /* Read the regs to test if we can talk to the device */
2890 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2891 u8 byte;
2892
2893 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2894 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2895 SDVO_NAME(intel_sdvo));
f899fc64 2896 goto err;
79e53945
JB		 2897 }
2898 }
2899
6cc5f341 2900 intel_encoder->compute_config = intel_sdvo_compute_config;
ce22c320 2901 intel_encoder->disable = intel_disable_sdvo;
6cc5f341 2902 intel_encoder->mode_set = intel_sdvo_mode_set;
ce22c320 2903 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2904 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 2905 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 2906
af901ca1 2907 /* In default case sdvo lvds is false */
32aad86f 2908 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2909 goto err;
79e53945 2910
ea5b213a
CW		 2911 if (intel_sdvo_output_setup(intel_sdvo,
2912 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2913 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2914 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 2915 /* Output_setup can leave behind connectors! */
2916 goto err_output;
79e53945
JB		 2917 }
2918
7ba220ce
CW		 2919 /* Only enable the hotplug irq if we need it, to work around noisy
2920 * hotplug lines.
2921 */
2922 if (intel_sdvo->hotplug_active) {
2923 intel_encoder->hpd_pin =
2924 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
2925 }
2926
e506d6fd
DV		 2927 /*
2928 * Cloning SDVO with anything is often impossible, since the SDVO
2929 * encoder can request a special input timing mode. And even if that's
2930 * not the case we have evidence that cloning a plain unscaled mode with
2931 * VGA doesn't really work. Furthermore the cloning flags are way too
2932 * simplistic anyway to express such constraints, so just give up on
2933 * cloning for SDVO encoders.
2934 */
2935 intel_sdvo->base.cloneable = false;
2936
ea5b213a 2937 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2938
79e53945 2939 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2940 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 2941 goto err_output;
79e53945 2942
32aad86f
CW		 2943 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2944 &intel_sdvo->pixel_clock_min,
2945 &intel_sdvo->pixel_clock_max))
d0ddfbd3 2946 goto err_output;
79e53945 2947
8a4c47f3 2948 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2949 "clock range %dMHz - %dMHz, "
2950 "input 1: %c, input 2: %c, "
2951 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2952 SDVO_NAME(intel_sdvo),
2953 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2954 intel_sdvo->caps.device_rev_id,
2955 intel_sdvo->pixel_clock_min / 1000,
2956 intel_sdvo->pixel_clock_max / 1000,
2957 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2958 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2959 /* check currently supported outputs */
ea5b213a 2960 intel_sdvo->caps.output_flags &
79e53945 2961 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2962 intel_sdvo->caps.output_flags &
79e53945 2963 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2964 return true;
79e53945 2965
d0ddfbd3
JN		 2966err_output:
2967 intel_sdvo_output_cleanup(intel_sdvo);
2968
f899fc64 2969err:
373a3cf7 2970 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2971 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2972err_i2c_bus:
2973 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2974 kfree(intel_sdvo);
79e53945 2975
7d57382e 2976 return false;
79e53945 2977}
Linux kernel - Deliverables
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