projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
agp/intel: Fix resume regression from 2d2430cf
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 51
79e53945 52
2e88e40b 53static const char *tv_format_names[] = {
ce6feabd
ZY		 54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61};
62
63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
ea5b213a
CW		 65struct intel_sdvo {
66 struct intel_encoder base;
67
f9c10a9b 68 u8 slave_addr;
e2f0ba97
JB		 69
70 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 71 int sdvo_reg;
79e53945 72
e2f0ba97
JB		 73 /* Active outputs controlled by this SDVO output */
74 uint16_t controlled_output;
79e53945 75
e2f0ba97
JB		 76 /*
77 * Capabilities of the SDVO device returned by
78 * i830_sdvo_get_capabilities()
79 */
79e53945 80 struct intel_sdvo_caps caps;
e2f0ba97
JB		 81
82 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 83 int pixel_clock_min, pixel_clock_max;
84
fb7a46f3 85 /*
86 * For multiple function SDVO device,
87 * this is for current attached outputs.
88 */
89 uint16_t attached_output;
90
e2f0ba97
JB		 91 /**
92 * This is set if we're going to treat the device as TV-out.
93 *
94 * While we have these nice friendly flags for output types that ought
95 * to decide this for us, the S-Video output on our HDMI+S-Video card
96 * shows up as RGB1 (VGA).
97 */
98 bool is_tv;
99
ce6feabd 100 /* This is for current tv format name */
40039750 101 int tv_format_index;
ce6feabd 102
e2f0ba97
JB		 103 /**
104 * This is set if we treat the device as HDMI, instead of DVI.
105 */
106 bool is_hdmi;
12682a97 107
7086c87f 108 /**
6c9547ff
CW		 109 * This is set if we detect output of sdvo device as LVDS and
110 * have a valid fixed mode to use with the panel.
7086c87f
ML		 111 */
112 bool is_lvds;
e2f0ba97 113
12682a97 114 /**
115 * This is sdvo fixed pannel mode pointer
116 */
117 struct drm_display_mode *sdvo_lvds_fixed_mode;
118
e2f0ba97
JB		 119 /*
120 * supported encoding mode, used to determine whether HDMI is
121 * supported
122 */
123 struct intel_sdvo_encode encode;
124
c751ce4f 125 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 126 uint8_t ddc_bus;
127
57cdaf90
KP		 128 /* Mac mini hack -- use the same DDC as the analog connector */
129 struct i2c_adapter *analog_ddc_bus;
130
6c9547ff
CW		 131 /* Input timings for adjusted_mode */
132 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 133};
134
135struct intel_sdvo_connector {
615fb93f
CW		 136 struct intel_connector base;
137
14571b4c
ZW		 138 /* Mark the type of connector */
139 uint16_t output_flag;
140
141 /* This contains all current supported TV format */
40039750 142 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 143 int format_supported_num;
c5521706 144 struct drm_property *tv_format;
14571b4c 145
b9219c5e 146 /* add the property for the SDVO-TV */
c5521706
CW		 147 struct drm_property *left;
148 struct drm_property *right;
149 struct drm_property *top;
150 struct drm_property *bottom;
151 struct drm_property *hpos;
152 struct drm_property *vpos;
153 struct drm_property *contrast;
154 struct drm_property *saturation;
155 struct drm_property *hue;
156 struct drm_property *sharpness;
157 struct drm_property *flicker_filter;
158 struct drm_property *flicker_filter_adaptive;
159 struct drm_property *flicker_filter_2d;
160 struct drm_property *tv_chroma_filter;
161 struct drm_property *tv_luma_filter;
e044218a 162 struct drm_property *dot_crawl;
b9219c5e
ZY		 163
164 /* add the property for the SDVO-TV/LVDS */
c5521706 165 struct drm_property *brightness;
b9219c5e
ZY		 166
167 /* Add variable to record current setting for the above property */
168 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 169
b9219c5e
ZY		 170 /* this is to get the range of margin.*/
171 u32 max_hscan, max_vscan;
172 u32 max_hpos, cur_hpos;
173 u32 max_vpos, cur_vpos;
174 u32 cur_brightness, max_brightness;
175 u32 cur_contrast, max_contrast;
176 u32 cur_saturation, max_saturation;
177 u32 cur_hue, max_hue;
c5521706
CW		 178 u32 cur_sharpness, max_sharpness;
179 u32 cur_flicker_filter, max_flicker_filter;
180 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
181 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
182 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
183 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 184 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 185};
186
890f3359 187static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 188{
4ef69c7a 189 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 190}
191
df0e9248
CW		 192static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
193{
194 return container_of(intel_attached_encoder(connector),
195 struct intel_sdvo, base);
196}
197
615fb93f
CW		 198static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
199{
200 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
201}
202
fb7a46f3 203static bool
ea5b213a 204intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 205static bool
206intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
207 struct intel_sdvo_connector *intel_sdvo_connector,
208 int type);
209static bool
210intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
211 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 212
79e53945
JB		 213/**
214 * Writes the SDVOB or SDVOC with the given value, but always writes both
215 * SDVOB and SDVOC to work around apparent hardware issues (according to
216 * comments in the BIOS).
217 */
ea5b213a 218static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 219{
4ef69c7a 220 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 221 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 222 u32 bval = val, cval = val;
223 int i;
224
ea5b213a
CW		 225 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
226 I915_WRITE(intel_sdvo->sdvo_reg, val);
227 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 228 return;
229 }
230
ea5b213a 231 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 232 cval = I915_READ(SDVOC);
233 } else {
234 bval = I915_READ(SDVOB);
235 }
236 /*
237 * Write the registers twice for luck. Sometimes,
238 * writing them only once doesn't appear to 'stick'.
239 * The BIOS does this too. Yay, magic
240 */
241 for (i = 0; i < 2; i++)
242 {
243 I915_WRITE(SDVOB, bval);
244 I915_READ(SDVOB);
245 I915_WRITE(SDVOC, cval);
246 I915_READ(SDVOC);
247 }
248}
249
32aad86f 250static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 251{
32aad86f 252 u8 out_buf[2] = { addr, 0 };
79e53945 253 u8 buf[2];
79e53945
JB		 254 struct i2c_msg msgs[] = {
255 {
ea5b213a 256 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 257 .flags = 0,
258 .len = 1,
259 .buf = out_buf,
260 },
261 {
ea5b213a 262 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 263 .flags = I2C_M_RD,
264 .len = 1,
265 .buf = buf,
266 }
267 };
32aad86f 268 int ret;
79e53945 269
ea5b213a 270 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
79e53945
JB		 271 {
272 *ch = buf[0];
273 return true;
274 }
275
8a4c47f3 276 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 277 return false;
278}
279
32aad86f 280static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
79e53945 281{
32aad86f 282 u8 out_buf[2] = { addr, ch };
79e53945
JB		 283 struct i2c_msg msgs[] = {
284 {
ea5b213a 285 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 286 .flags = 0,
287 .len = 2,
288 .buf = out_buf,
289 }
290 };
291
32aad86f 292 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
79e53945
JB		 293}
294
295#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
296/** Mapping of command numbers to names, for debug output */
005568be 297static const struct _sdvo_cmd_name {
e2f0ba97 298 u8 cmd;
2e88e40b 299 const char *name;
79e53945
JB		 300} sdvo_cmd_names[] = {
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
c5521706 344
b9219c5e 345 /* Add the op code for SDVO enhancements */
c5521706
CW		 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
b9219c5e
ZY		 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
c5521706
CW		 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
390
e2f0ba97
JB		 391 /* HDMI op code */
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 412};
413
461ed3ca 414#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 415#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 416
ea5b213a 417static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 418 const void *args, int args_len)
79e53945 419{
79e53945
JB		 420 int i;
421
8a4c47f3 422 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 423 SDVO_NAME(intel_sdvo), cmd);
79e53945 424 for (i = 0; i < args_len; i++)
342dc382 425 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 426 for (; i < 8; i++)
342dc382 427 DRM_LOG_KMS(" ");
04ad327f 428 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 429 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 430 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 431 break;
432 }
433 }
04ad327f 434 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 435 DRM_LOG_KMS("(%02X)", cmd);
436 DRM_LOG_KMS("\n");
79e53945 437}
79e53945 438
32aad86f
CW		 439static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
440 const void *args, int args_len)
79e53945
JB		 441{
442 int i;
443
ea5b213a 444 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 445
446 for (i = 0; i < args_len; i++) {
32aad86f
CW		 447 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
448 ((u8*)args)[i]))
449 return false;
79e53945
JB		 450 }
451
32aad86f 452 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 453}
454
79e53945
JB		 455static const char *cmd_status_names[] = {
456 "Power on",
457 "Success",
458 "Not supported",
459 "Invalid arg",
460 "Pending",
461 "Target not specified",
462 "Scaling not supported"
463};
464
b5c616a7
CW		 465static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
466 void *response, int response_len)
79e53945 467{
b5c616a7
CW		 468 u8 retry = 5;
469 u8 status;
33b52961 470 int i;
79e53945 471
b5c616a7
CW		 472 /*
473 * The documentation states that all commands will be
474 * processed within 15µs, and that we need only poll
475 * the status byte a maximum of 3 times in order for the
476 * command to be complete.
477 *
478 * Check 5 times in case the hardware failed to read the docs.
479 */
480 do {
481 if (!intel_sdvo_read_byte(intel_sdvo,
482 SDVO_I2C_CMD_STATUS,
483 &status))
484 return false;
485 } while (status == SDVO_CMD_STATUS_PENDING && --retry);
486
ea5b213a 487 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 488 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 489 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 490 else
342dc382 491 DRM_LOG_KMS("(??? %d)", status);
79e53945 492
b5c616a7
CW		 493 if (status != SDVO_CMD_STATUS_SUCCESS)
494 goto log_fail;
79e53945 495
b5c616a7
CW		 496 /* Read the command response */
497 for (i = 0; i < response_len; i++) {
498 if (!intel_sdvo_read_byte(intel_sdvo,
499 SDVO_I2C_RETURN_0 + i,
500 &((u8 *)response)[i]))
501 goto log_fail;
502 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
503 }
79e53945 504
b5c616a7
CW		 505 for (; i < 8; i++)
506 DRM_LOG_KMS(" ");
507 DRM_LOG_KMS("\n");
79e53945 508
b5c616a7 509 return true;
79e53945 510
b5c616a7
CW		 511log_fail:
512 DRM_LOG_KMS("\n");
513 return false;
79e53945
JB		 514}
515
b358d0a6 516static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 517{
518 if (mode->clock >= 100000)
519 return 1;
520 else if (mode->clock >= 50000)
521 return 2;
522 else
523 return 4;
524}
525
526/**
6a304caf
ZY		 527 * Try to read the response after issuie the DDC switch command. But it
528 * is noted that we must do the action of reading response and issuing DDC
529 * switch command in one I2C transaction. Otherwise when we try to start
530 * another I2C transaction after issuing the DDC bus switch, it will be
531 * switched to the internal SDVO register.
79e53945 532 */
819f3fb7
CW		 533static int intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
534 u8 target)
79e53945 535{
6a304caf
ZY		 536 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
537 struct i2c_msg msgs[] = {
538 {
ea5b213a 539 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 540 .flags = 0,
541 .len = 2,
542 .buf = out_buf,
543 },
544 /* the following two are to read the response */
545 {
ea5b213a 546 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 547 .flags = 0,
548 .len = 1,
549 .buf = cmd_buf,
550 },
551 {
ea5b213a 552 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 553 .flags = I2C_M_RD,
554 .len = 1,
555 .buf = ret_value,
556 },
557 };
558
ea5b213a 559 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
819f3fb7 560 &target, 1);
6a304caf 561 /* write the DDC switch command argument */
819f3fb7
CW		 562 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target))
563 return -EIO;
6a304caf
ZY		 564
565 out_buf[0] = SDVO_I2C_OPCODE;
566 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
567 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
568 cmd_buf[1] = 0;
569 ret_value[0] = 0;
570 ret_value[1] = 0;
571
ea5b213a 572 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
819f3fb7
CW		 573 if (ret < 0)
574 return ret;
6a304caf
ZY		 575 if (ret != 3) {
576 /* failure in I2C transfer */
577 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
819f3fb7 578 return -EIO;
6a304caf
ZY		 579 }
580 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
581 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
819f3fb7
CW		 582 ret_value[0]);
583 return -EIO;
6a304caf 584 }
819f3fb7
CW		 585
586 return 0;
79e53945
JB		 587}
588
32aad86f 589static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 590{
32aad86f
CW		 591 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
592 return false;
79e53945 593
32aad86f
CW		 594 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
595}
79e53945 596
32aad86f
CW		 597static bool
598intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
599{
600 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
601 return false;
79e53945 602
32aad86f
CW		 603 return intel_sdvo_read_response(intel_sdvo, value, len);
604}
79e53945 605
32aad86f
CW		 606static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
607{
608 struct intel_sdvo_set_target_input_args targets = {0};
609 return intel_sdvo_set_value(intel_sdvo,
610 SDVO_CMD_SET_TARGET_INPUT,
611 &targets, sizeof(targets));
79e53945
JB		 612}
613
614/**
615 * Return whether each input is trained.
616 *
617 * This function is making an assumption about the layout of the response,
618 * which should be checked against the docs.
619 */
ea5b213a 620static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 621{
622 struct intel_sdvo_get_trained_inputs_response response;
79e53945 623
32aad86f
CW		 624 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
625 &response, sizeof(response)))
79e53945
JB		 626 return false;
627
628 *input_1 = response.input0_trained;
629 *input_2 = response.input1_trained;
630 return true;
631}
632
ea5b213a 633static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 634 u16 outputs)
635{
32aad86f
CW		 636 return intel_sdvo_set_value(intel_sdvo,
637 SDVO_CMD_SET_ACTIVE_OUTPUTS,
638 &outputs, sizeof(outputs));
79e53945
JB		 639}
640
ea5b213a 641static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 642 int mode)
643{
32aad86f 644 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 645
646 switch (mode) {
647 case DRM_MODE_DPMS_ON:
648 state = SDVO_ENCODER_STATE_ON;
649 break;
650 case DRM_MODE_DPMS_STANDBY:
651 state = SDVO_ENCODER_STATE_STANDBY;
652 break;
653 case DRM_MODE_DPMS_SUSPEND:
654 state = SDVO_ENCODER_STATE_SUSPEND;
655 break;
656 case DRM_MODE_DPMS_OFF:
657 state = SDVO_ENCODER_STATE_OFF;
658 break;
659 }
660
32aad86f
CW		 661 return intel_sdvo_set_value(intel_sdvo,
662 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 663}
664
ea5b213a 665static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 666 int *clock_min,
667 int *clock_max)
668{
669 struct intel_sdvo_pixel_clock_range clocks;
79e53945 670
32aad86f
CW		 671 if (!intel_sdvo_get_value(intel_sdvo,
672 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
673 &clocks, sizeof(clocks)))
79e53945
JB		 674 return false;
675
676 /* Convert the values from units of 10 kHz to kHz. */
677 *clock_min = clocks.min * 10;
678 *clock_max = clocks.max * 10;
79e53945
JB		 679 return true;
680}
681
ea5b213a 682static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 u16 outputs)
684{
32aad86f
CW		 685 return intel_sdvo_set_value(intel_sdvo,
686 SDVO_CMD_SET_TARGET_OUTPUT,
687 &outputs, sizeof(outputs));
79e53945
JB		 688}
689
ea5b213a 690static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 691 struct intel_sdvo_dtd *dtd)
692{
32aad86f
CW		 693 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
694 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 695}
696
ea5b213a 697static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 698 struct intel_sdvo_dtd *dtd)
699{
ea5b213a 700 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 701 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
702}
703
ea5b213a 704static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 705 struct intel_sdvo_dtd *dtd)
706{
ea5b213a 707 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 708 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
709}
710
e2f0ba97 711static bool
ea5b213a 712intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 713 uint16_t clock,
714 uint16_t width,
715 uint16_t height)
716{
717 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 718
e642c6f1 719 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 720 args.clock = clock;
721 args.width = width;
722 args.height = height;
e642c6f1 723 args.interlace = 0;
12682a97 724
ea5b213a
CW		 725 if (intel_sdvo->is_lvds &&
726 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
727 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 728 args.scaled = 1;
729
32aad86f
CW		 730 return intel_sdvo_set_value(intel_sdvo,
731 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
732 &args, sizeof(args));
e2f0ba97
JB		 733}
734
ea5b213a 735static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 736 struct intel_sdvo_dtd *dtd)
737{
32aad86f
CW		 738 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
739 &dtd->part1, sizeof(dtd->part1)) &&
740 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
741 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 742}
79e53945 743
ea5b213a 744static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 745{
32aad86f 746 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 747}
748
e2f0ba97 749static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 750 const struct drm_display_mode *mode)
79e53945 751{
e2f0ba97
JB		 752 uint16_t width, height;
753 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
754 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 755
756 width = mode->crtc_hdisplay;
757 height = mode->crtc_vdisplay;
758
759 /* do some mode translations */
760 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
761 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
762
763 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
764 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
765
766 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
767 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
768
e2f0ba97
JB		 769 dtd->part1.clock = mode->clock / 10;
770 dtd->part1.h_active = width & 0xff;
771 dtd->part1.h_blank = h_blank_len & 0xff;
772 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 773 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 774 dtd->part1.v_active = height & 0xff;
775 dtd->part1.v_blank = v_blank_len & 0xff;
776 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 777 ((v_blank_len >> 8) & 0xf);
778
171a9e96 779 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 780 dtd->part2.h_sync_width = h_sync_len & 0xff;
781 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 782 (v_sync_len & 0xf);
e2f0ba97 783 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 784 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
785 ((v_sync_len & 0x30) >> 4);
786
e2f0ba97 787 dtd->part2.dtd_flags = 0x18;
79e53945 788 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 789 dtd->part2.dtd_flags |= 0x2;
79e53945 790 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 791 dtd->part2.dtd_flags |= 0x4;
792
793 dtd->part2.sdvo_flags = 0;
794 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
795 dtd->part2.reserved = 0;
796}
797
798static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 799 const struct intel_sdvo_dtd *dtd)
e2f0ba97 800{
e2f0ba97
JB		 801 mode->hdisplay = dtd->part1.h_active;
802 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
803 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 804 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 805 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
806 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
807 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
808 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
809
810 mode->vdisplay = dtd->part1.v_active;
811 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
812 mode->vsync_start = mode->vdisplay;
813 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 814 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 815 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
816 mode->vsync_end = mode->vsync_start +
817 (dtd->part2.v_sync_off_width & 0xf);
818 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
819 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
820 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
821
822 mode->clock = dtd->part1.clock * 10;
823
171a9e96 824 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 825 if (dtd->part2.dtd_flags & 0x2)
826 mode->flags |= DRM_MODE_FLAG_PHSYNC;
827 if (dtd->part2.dtd_flags & 0x4)
828 mode->flags |= DRM_MODE_FLAG_PVSYNC;
829}
830
ea5b213a 831static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 832 struct intel_sdvo_encode *encode)
833{
32aad86f
CW		 834 if (intel_sdvo_get_value(intel_sdvo,
835 SDVO_CMD_GET_SUPP_ENCODE,
836 encode, sizeof(*encode)))
837 return true;
e2f0ba97 838
32aad86f
CW		 839 /* non-support means DVI */
840 memset(encode, 0, sizeof(*encode));
841 return false;
e2f0ba97
JB		 842}
843
ea5b213a 844static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 845 uint8_t mode)
e2f0ba97 846{
32aad86f 847 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 848}
849
ea5b213a 850static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 851 uint8_t mode)
852{
32aad86f 853 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 854}
855
856#if 0
ea5b213a 857static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 858{
859 int i, j;
860 uint8_t set_buf_index[2];
861 uint8_t av_split;
862 uint8_t buf_size;
863 uint8_t buf[48];
864 uint8_t *pos;
865
32aad86f 866 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 867
868 for (i = 0; i <= av_split; i++) {
869 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 870 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 871 set_buf_index, 2);
c751ce4f
EA		 872 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
873 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 874
875 pos = buf;
876 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 877 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 878 NULL, 0);
c751ce4f 879 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 880 pos += 8;
881 }
882 }
883}
884#endif
885
32aad86f 886static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
c751ce4f
EA		 887 int index,
888 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 889{
890 uint8_t set_buf_index[2];
891
892 set_buf_index[0] = index;
893 set_buf_index[1] = 0;
894
32aad86f
CW		 895 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
896 set_buf_index, 2))
897 return false;
e2f0ba97
JB		 898
899 for (; size > 0; size -= 8) {
32aad86f
CW		 900 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
901 return false;
902
e2f0ba97
JB		 903 data += 8;
904 }
905
32aad86f 906 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 907}
908
909static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
910{
911 uint8_t csum = 0;
912 int i;
913
914 for (i = 0; i < size; i++)
915 csum += data[i];
916
917 return 0x100 - csum;
918}
919
920#define DIP_TYPE_AVI 0x82
921#define DIP_VERSION_AVI 0x2
922#define DIP_LEN_AVI 13
923
924struct dip_infoframe {
925 uint8_t type;
926 uint8_t version;
927 uint8_t len;
928 uint8_t checksum;
929 union {
930 struct {
931 /* Packet Byte #1 */
932 uint8_t S:2;
933 uint8_t B:2;
934 uint8_t A:1;
935 uint8_t Y:2;
936 uint8_t rsvd1:1;
937 /* Packet Byte #2 */
938 uint8_t R:4;
939 uint8_t M:2;
940 uint8_t C:2;
941 /* Packet Byte #3 */
942 uint8_t SC:2;
943 uint8_t Q:2;
944 uint8_t EC:3;
945 uint8_t ITC:1;
946 /* Packet Byte #4 */
947 uint8_t VIC:7;
948 uint8_t rsvd2:1;
949 /* Packet Byte #5 */
950 uint8_t PR:4;
951 uint8_t rsvd3:4;
952 /* Packet Byte #6~13 */
953 uint16_t top_bar_end;
954 uint16_t bottom_bar_start;
955 uint16_t left_bar_end;
956 uint16_t right_bar_start;
957 } avi;
958 struct {
959 /* Packet Byte #1 */
960 uint8_t channel_count:3;
961 uint8_t rsvd1:1;
962 uint8_t coding_type:4;
963 /* Packet Byte #2 */
964 uint8_t sample_size:2; /* SS0, SS1 */
965 uint8_t sample_frequency:3;
966 uint8_t rsvd2:3;
967 /* Packet Byte #3 */
968 uint8_t coding_type_private:5;
969 uint8_t rsvd3:3;
970 /* Packet Byte #4 */
971 uint8_t channel_allocation;
972 /* Packet Byte #5 */
973 uint8_t rsvd4:3;
974 uint8_t level_shift:4;
975 uint8_t downmix_inhibit:1;
976 } audio;
977 uint8_t payload[28];
978 } __attribute__ ((packed)) u;
979} __attribute__((packed));
980
32aad86f 981static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 982 struct drm_display_mode * mode)
983{
984 struct dip_infoframe avi_if = {
985 .type = DIP_TYPE_AVI,
986 .version = DIP_VERSION_AVI,
987 .len = DIP_LEN_AVI,
988 };
989
990 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
991 4 + avi_if.len);
32aad86f
CW		 992 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
993 4 + avi_if.len,
994 SDVO_HBUF_TX_VSYNC);
e2f0ba97
JB		 995}
996
32aad86f 997static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 998{
ce6feabd 999 struct intel_sdvo_tv_format format;
40039750 1000 uint32_t format_map;
ce6feabd 1001
40039750 1002 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1003 memset(&format, 0, sizeof(format));
32aad86f 1004 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1005
32aad86f
CW		 1006 BUILD_BUG_ON(sizeof(format) != 6);
1007 return intel_sdvo_set_value(intel_sdvo,
1008 SDVO_CMD_SET_TV_FORMAT,
1009 &format, sizeof(format));
7026d4ac
ZW		 1010}
1011
32aad86f
CW		 1012static bool
1013intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1014 struct drm_display_mode *mode)
e2f0ba97 1015{
32aad86f 1016 struct intel_sdvo_dtd output_dtd;
79e53945 1017
32aad86f
CW		 1018 if (!intel_sdvo_set_target_output(intel_sdvo,
1019 intel_sdvo->attached_output))
1020 return false;
e2f0ba97 1021
32aad86f
CW		 1022 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1023 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1024 return false;
e2f0ba97 1025
32aad86f
CW		 1026 return true;
1027}
1028
1029static bool
1030intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1031 struct drm_display_mode *mode,
1032 struct drm_display_mode *adjusted_mode)
1033{
32aad86f
CW		 1034 /* Reset the input timing to the screen. Assume always input 0. */
1035 if (!intel_sdvo_set_target_input(intel_sdvo))
1036 return false;
e2f0ba97 1037
32aad86f
CW		 1038 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1039 mode->clock / 10,
1040 mode->hdisplay,
1041 mode->vdisplay))
1042 return false;
e2f0ba97 1043
32aad86f 1044 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 1045 &intel_sdvo->input_dtd))
32aad86f 1046 return false;
e2f0ba97 1047
6c9547ff 1048 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 1049
32aad86f 1050 drm_mode_set_crtcinfo(adjusted_mode, 0);
32aad86f
CW		 1051 return true;
1052}
12682a97 1053
32aad86f
CW		 1054static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1055 struct drm_display_mode *mode,
1056 struct drm_display_mode *adjusted_mode)
1057{
890f3359 1058 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1059 int multiplier;
12682a97 1060
32aad86f
CW		 1061 /* We need to construct preferred input timings based on our
1062 * output timings. To do that, we have to set the output
1063 * timings, even though this isn't really the right place in
1064 * the sequence to do it. Oh well.
1065 */
1066 if (intel_sdvo->is_tv) {
1067 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1068 return false;
12682a97 1069
c74696b9
PR		 1070 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1071 mode,
1072 adjusted_mode);
ea5b213a 1073 } else if (intel_sdvo->is_lvds) {
32aad86f 1074 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1075 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1076 return false;
12682a97 1077
c74696b9
PR		 1078 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1079 mode,
1080 adjusted_mode);
e2f0ba97 1081 }
32aad86f
CW		 1082
1083 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1084 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1085 */
6c9547ff
CW		 1086 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1087 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1088
e2f0ba97
JB		 1089 return true;
1090}
1091
1092static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1093 struct drm_display_mode *mode,
1094 struct drm_display_mode *adjusted_mode)
1095{
1096 struct drm_device *dev = encoder->dev;
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 struct drm_crtc *crtc = encoder->crtc;
1099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1100 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1101 u32 sdvox;
e2f0ba97
JB		 1102 struct intel_sdvo_in_out_map in_out;
1103 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 1104 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1105 int rate;
e2f0ba97
JB		 1106
1107 if (!mode)
1108 return;
1109
1110 /* First, set the input mapping for the first input to our controlled
1111 * output. This is only correct if we're a single-input device, in
1112 * which case the first input is the output from the appropriate SDVO
1113 * channel on the motherboard. In a two-input device, the first input
1114 * will be SDVOB and the second SDVOC.
1115 */
ea5b213a 1116 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1117 in_out.in1 = 0;
1118
c74696b9
PR		 1119 intel_sdvo_set_value(intel_sdvo,
1120 SDVO_CMD_SET_IN_OUT_MAP,
1121 &in_out, sizeof(in_out));
e2f0ba97 1122
6c9547ff
CW		 1123 /* Set the output timings to the screen */
1124 if (!intel_sdvo_set_target_output(intel_sdvo,
1125 intel_sdvo->attached_output))
1126 return;
e2f0ba97 1127
7026d4ac 1128 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1129 * adjusted_mode.
e2f0ba97 1130 */
6c9547ff
CW		 1131 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1132 input_dtd = intel_sdvo->input_dtd;
1133 } else {
e2f0ba97 1134 /* Set the output timing to the screen */
32aad86f
CW		 1135 if (!intel_sdvo_set_target_output(intel_sdvo,
1136 intel_sdvo->attached_output))
1137 return;
1138
6c9547ff 1139 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1140 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1141 }
79e53945
JB		 1142
1143 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1144 if (!intel_sdvo_set_target_input(intel_sdvo))
1145 return;
79e53945 1146
6c9547ff
CW		 1147 if (intel_sdvo->is_hdmi &&
1148 !intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1149 return;
7026d4ac 1150
6c9547ff
CW		 1151 if (intel_sdvo->is_tv &&
1152 !intel_sdvo_set_tv_format(intel_sdvo))
1153 return;
e2f0ba97 1154
c74696b9 1155 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1156
6c9547ff
CW		 1157 switch (pixel_multiplier) {
1158 default:
32aad86f
CW		 1159 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1160 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1161 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1162 }
32aad86f
CW		 1163 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1164 return;
79e53945
JB		 1165
1166 /* Set the SDVO control regs. */
e2f0ba97 1167 if (IS_I965G(dev)) {
6c9547ff 1168 sdvox = SDVO_BORDER_ENABLE;
81a14b46
AJ		 1169 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1170 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1171 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1172 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1173 } else {
6c9547ff 1174 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1175 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1176 case SDVOB:
1177 sdvox &= SDVOB_PRESERVE_MASK;
1178 break;
1179 case SDVOC:
1180 sdvox &= SDVOC_PRESERVE_MASK;
1181 break;
1182 }
1183 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1184 }
79e53945
JB		 1185 if (intel_crtc->pipe == 1)
1186 sdvox |= SDVO_PIPE_B_SELECT;
6c9547ff
CW		 1187 if (intel_sdvo->is_hdmi)
1188 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1189
79e53945 1190 if (IS_I965G(dev)) {
e2f0ba97
JB		 1191 /* done in crtc_mode_set as the dpll_md reg must be written early */
1192 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1193 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1194 } else {
6c9547ff 1195 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1196 }
1197
6c9547ff 1198 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1199 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1200 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1201}
1202
1203static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1204{
1205 struct drm_device *dev = encoder->dev;
1206 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1207 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1208 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1209 u32 temp;
1210
1211 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1212 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1213 if (0)
ea5b213a 1214 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1215
1216 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1217 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1218 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1219 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1220 }
1221 }
1222 } else {
1223 bool input1, input2;
1224 int i;
1225 u8 status;
1226
ea5b213a 1227 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1228 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1229 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1230 for (i = 0; i < 2; i++)
9d0498a2 1231 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1232
32aad86f 1233 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1234 /* Warn if the device reported failure to sync.
1235 * A lot of SDVO devices fail to notify of sync, but it's
1236 * a given it the status is a success, we succeeded.
1237 */
1238 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1239 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1240 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1241 }
1242
1243 if (0)
ea5b213a
CW		 1244 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1245 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1246 }
1247 return;
1248}
1249
79e53945
JB		 1250static int intel_sdvo_mode_valid(struct drm_connector *connector,
1251 struct drm_display_mode *mode)
1252{
df0e9248 1253 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1254
1255 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1256 return MODE_NO_DBLESCAN;
1257
ea5b213a 1258 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1259 return MODE_CLOCK_LOW;
1260
ea5b213a 1261 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1262 return MODE_CLOCK_HIGH;
1263
8545423a 1264 if (intel_sdvo->is_lvds) {
ea5b213a 1265 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1266 return MODE_PANEL;
1267
ea5b213a 1268 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1269 return MODE_PANEL;
1270 }
1271
79e53945
JB		 1272 return MODE_OK;
1273}
1274
ea5b213a 1275static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1276{
32aad86f 1277 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
79e53945
JB		 1278}
1279
d2a82a6f
ZW		 1280/* No use! */
1281#if 0
79e53945
JB		 1282struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1283{
1284 struct drm_connector *connector = NULL;
ea5b213a
CW		 1285 struct intel_sdvo *iout = NULL;
1286 struct intel_sdvo *sdvo;
79e53945
JB		 1287
1288 /* find the sdvo connector */
1289 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1290 iout = to_intel_sdvo(connector);
79e53945
JB		 1291
1292 if (iout->type != INTEL_OUTPUT_SDVO)
1293 continue;
1294
1295 sdvo = iout->dev_priv;
1296
c751ce4f 1297 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1298 return connector;
1299
c751ce4f 1300 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1301 return connector;
1302
1303 }
1304
1305 return NULL;
1306}
1307
1308int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1309{
1310 u8 response[2];
1311 u8 status;
ea5b213a 1312 struct intel_sdvo *intel_sdvo;
8a4c47f3 1313 DRM_DEBUG_KMS("\n");
79e53945
JB		 1314
1315 if (!connector)
1316 return 0;
1317
ea5b213a 1318 intel_sdvo = to_intel_sdvo(connector);
79e53945 1319
32aad86f
CW		 1320 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1321 &response, 2) && response[0];
79e53945
JB		 1322}
1323
1324void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1325{
1326 u8 response[2];
1327 u8 status;
ea5b213a 1328 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1329
ea5b213a
CW		 1330 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1331 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1332
1333 if (on) {
ea5b213a
CW		 1334 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1335 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1336
ea5b213a 1337 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1338 } else {
1339 response[0] = 0;
1340 response[1] = 0;
ea5b213a 1341 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1342 }
1343
ea5b213a
CW		 1344 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1345 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1346}
d2a82a6f 1347#endif
79e53945 1348
fb7a46f3 1349static bool
ea5b213a 1350intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1351{
fb7a46f3 1352 int caps = 0;
1353
ea5b213a 1354 if (intel_sdvo->caps.output_flags &
fb7a46f3 1355 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1356 caps++;
ea5b213a 1357 if (intel_sdvo->caps.output_flags &
fb7a46f3 1358 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1359 caps++;
ea5b213a 1360 if (intel_sdvo->caps.output_flags &
19e1f888 1361 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1362 caps++;
ea5b213a 1363 if (intel_sdvo->caps.output_flags &
fb7a46f3 1364 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1365 caps++;
ea5b213a 1366 if (intel_sdvo->caps.output_flags &
fb7a46f3 1367 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1368 caps++;
1369
ea5b213a 1370 if (intel_sdvo->caps.output_flags &
fb7a46f3 1371 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1372 caps++;
1373
ea5b213a 1374 if (intel_sdvo->caps.output_flags &
fb7a46f3 1375 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1376 caps++;
1377
1378 return (caps > 1);
1379}
1380
57cdaf90
KP		 1381static struct drm_connector *
1382intel_find_analog_connector(struct drm_device *dev)
1383{
1384 struct drm_connector *connector;
df0e9248
CW		 1385 struct intel_sdvo *encoder;
1386
1387 list_for_each_entry(encoder,
1388 &dev->mode_config.encoder_list,
1389 base.base.head) {
1390 if (encoder->base.type == INTEL_OUTPUT_ANALOG) {
1391 list_for_each_entry(connector,
1392 &dev->mode_config.connector_list,
1393 head) {
1394 if (&encoder->base ==
1395 intel_attached_encoder(connector))
d2a82a6f
ZW		 1396 return connector;
1397 }
1398 }
57cdaf90 1399 }
df0e9248 1400
57cdaf90
KP		 1401 return NULL;
1402}
1403
1404static int
1405intel_analog_is_connected(struct drm_device *dev)
1406{
1407 struct drm_connector *analog_connector;
57cdaf90 1408
32aad86f 1409 analog_connector = intel_find_analog_connector(dev);
57cdaf90
KP		 1410 if (!analog_connector)
1411 return false;
1412
1413 if (analog_connector->funcs->detect(analog_connector) ==
1414 connector_status_disconnected)
1415 return false;
1416
1417 return true;
1418}
1419
2b8d33f7 1420enum drm_connector_status
149c36a3 1421intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1422{
df0e9248 1423 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1424 enum drm_connector_status status;
1425 struct edid *edid;
9dff6af8 1426
ea5b213a 1427 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
57cdaf90 1428
ea5b213a 1429 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
9d1a903d
CW		 1430 u8 saved_ddc = intel_sdvo->ddc_bus, ddc;
1431
7c3f0a27
ZY		 1432 /*
1433 * Don't use the 1 as the argument of DDC bus switch to get
1434 * the EDID. It is used for SDVO SPD ROM.
1435 */
9d1a903d
CW		 1436 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1437 intel_sdvo->ddc_bus = ddc;
ea5b213a 1438 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
9d1a903d 1439 if (edid)
7c3f0a27 1440 break;
7c3f0a27 1441 }
9d1a903d
CW		 1442
1443 /*
1444 * If we found the EDID on the other bus, maybe that is the
1445 * correct DDC bus.
1446 */
7c3f0a27 1447 if (edid == NULL)
ea5b213a 1448 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1449 }
9d1a903d
CW		 1450
1451 /*
1452 * When there is no edid and no monitor is connected with VGA
1453 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1454 */
9d1a903d
CW		 1455 if (edid == NULL &&
1456 intel_sdvo->analog_ddc_bus &&
d2a82a6f 1457 !intel_analog_is_connected(connector->dev))
ea5b213a 1458 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
149c36a3 1459
9d1a903d 1460 status = connector_status_disconnected;
9dff6af8 1461 if (edid != NULL) {
149c36a3 1462 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1463 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1464 status = connector_status_connected;
ea5b213a 1465 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
9d1a903d 1466 }
149c36a3 1467 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1468 kfree(edid);
1469 }
149c36a3 1470
2b8d33f7 1471 return status;
9dff6af8
ML		 1472}
1473
79e53945
JB		 1474static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1475{
fb7a46f3 1476 uint16_t response;
df0e9248 1477 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1478 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1479 enum drm_connector_status ret;
79e53945 1480
32aad86f
CW		 1481 if (!intel_sdvo_write_cmd(intel_sdvo,
1482 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1483 return connector_status_unknown;
ea5b213a 1484 if (intel_sdvo->is_tv) {
d09c23de
ZY		 1485 /* add 30ms delay when the output type is SDVO-TV */
1486 mdelay(30);
1487 }
32aad86f
CW		 1488 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1489 return connector_status_unknown;
79e53945 1490
51c8b407 1491 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97 1492
fb7a46f3 1493 if (response == 0)
79e53945 1494 return connector_status_disconnected;
fb7a46f3 1495
ea5b213a 1496 intel_sdvo->attached_output = response;
14571b4c 1497
615fb93f 1498 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1499 ret = connector_status_disconnected;
149c36a3
AJ		 1500 else if (response & SDVO_TMDS_MASK)
1501 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1502 else
1503 ret = connector_status_connected;
1504
1505 /* May update encoder flag for like clock for SDVO TV, etc.*/
1506 if (ret == connector_status_connected) {
ea5b213a
CW		 1507 intel_sdvo->is_tv = false;
1508 intel_sdvo->is_lvds = false;
1509 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1510
1511 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1512 intel_sdvo->is_tv = true;
1513 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1514 }
1515 if (response & SDVO_LVDS_MASK)
8545423a 1516 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1517 }
14571b4c
ZW		 1518
1519 return ret;
79e53945
JB		 1520}
1521
e2f0ba97 1522static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1523{
df0e9248 1524 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
57cdaf90 1525 int num_modes;
79e53945
JB		 1526
1527 /* set the bus switch and get the modes */
ea5b213a 1528 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
79e53945 1529
57cdaf90
KP		 1530 /*
1531 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1532 * link between analog and digital outputs. So, if the regular SDVO
1533 * DDC fails, check to see if the analog output is disconnected, in
1534 * which case we'll look there for the digital DDC data.
e2f0ba97 1535 */
57cdaf90 1536 if (num_modes == 0 &&
ea5b213a 1537 intel_sdvo->analog_ddc_bus &&
d2a82a6f 1538 !intel_analog_is_connected(connector->dev)) {
57cdaf90
KP		 1539 /* Switch to the analog ddc bus and try that
1540 */
ea5b213a 1541 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
e2f0ba97 1542 }
e2f0ba97
JB		 1543}
1544
1545/*
1546 * Set of SDVO TV modes.
1547 * Note! This is in reply order (see loop in get_tv_modes).
1548 * XXX: all 60Hz refresh?
1549 */
1550struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1551 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1552 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1554 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1555 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1557 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1558 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1560 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1561 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1563 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1564 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1566 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1567 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1569 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1570 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1572 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1573 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1575 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1576 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1578 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1579 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1581 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1582 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1584 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1585 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1587 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1588 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1590 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1591 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1594 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1596 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1597 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1598 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1599 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1600 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1602 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1603 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1605 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1606 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1608};
1609
1610static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1611{
df0e9248 1612 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1613 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1614 uint32_t reply = 0, format_map = 0;
1615 int i;
e2f0ba97
JB		 1616
1617 /* Read the list of supported input resolutions for the selected TV
1618 * format.
1619 */
40039750 1620 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1621 memcpy(&tv_res, &format_map,
32aad86f 1622 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1623
32aad86f
CW		 1624 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1625 return;
ce6feabd 1626
32aad86f
CW		 1627 BUILD_BUG_ON(sizeof(tv_res) != 3);
1628 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1629 &tv_res, sizeof(tv_res)))
1630 return;
1631 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1632 return;
1633
1634 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1635 if (reply & (1 << i)) {
1636 struct drm_display_mode *nmode;
1637 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1638 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1639 if (nmode)
1640 drm_mode_probed_add(connector, nmode);
1641 }
e2f0ba97
JB		 1642}
1643
7086c87f
ML		 1644static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1645{
df0e9248 1646 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1647 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1648 struct drm_display_mode *newmode;
7086c87f
ML		 1649
1650 /*
1651 * Attempt to get the mode list from DDC.
1652 * Assume that the preferred modes are
1653 * arranged in priority order.
1654 */
ea5b213a 1655 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
7086c87f 1656 if (list_empty(&connector->probed_modes) == false)
12682a97 1657 goto end;
7086c87f
ML		 1658
1659 /* Fetch modes from VBT */
1660 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1661 newmode = drm_mode_duplicate(connector->dev,
1662 dev_priv->sdvo_lvds_vbt_mode);
1663 if (newmode != NULL) {
1664 /* Guarantee the mode is preferred */
1665 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1666 DRM_MODE_TYPE_DRIVER);
1667 drm_mode_probed_add(connector, newmode);
1668 }
1669 }
12682a97 1670
1671end:
1672 list_for_each_entry(newmode, &connector->probed_modes, head) {
1673 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1674 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1675 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1676
1677 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1678 0);
1679
8545423a 1680 intel_sdvo->is_lvds = true;
12682a97 1681 break;
1682 }
1683 }
1684
7086c87f
ML		 1685}
1686
e2f0ba97
JB		 1687static int intel_sdvo_get_modes(struct drm_connector *connector)
1688{
615fb93f 1689 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1690
615fb93f 1691 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1692 intel_sdvo_get_tv_modes(connector);
615fb93f 1693 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1694 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1695 else
1696 intel_sdvo_get_ddc_modes(connector);
1697
32aad86f 1698 return !list_empty(&connector->probed_modes);
79e53945
JB		 1699}
1700
fcc8d672
CW		 1701static void
1702intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1703{
615fb93f 1704 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1705 struct drm_device *dev = connector->dev;
1706
c5521706
CW		 1707 if (intel_sdvo_connector->left)
1708 drm_property_destroy(dev, intel_sdvo_connector->left);
1709 if (intel_sdvo_connector->right)
1710 drm_property_destroy(dev, intel_sdvo_connector->right);
1711 if (intel_sdvo_connector->top)
1712 drm_property_destroy(dev, intel_sdvo_connector->top);
1713 if (intel_sdvo_connector->bottom)
1714 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1715 if (intel_sdvo_connector->hpos)
1716 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1717 if (intel_sdvo_connector->vpos)
1718 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1719 if (intel_sdvo_connector->saturation)
1720 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1721 if (intel_sdvo_connector->contrast)
1722 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1723 if (intel_sdvo_connector->hue)
1724 drm_property_destroy(dev, intel_sdvo_connector->hue);
1725 if (intel_sdvo_connector->sharpness)
1726 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1727 if (intel_sdvo_connector->flicker_filter)
1728 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1729 if (intel_sdvo_connector->flicker_filter_2d)
1730 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1731 if (intel_sdvo_connector->flicker_filter_adaptive)
1732 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1733 if (intel_sdvo_connector->tv_luma_filter)
1734 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1735 if (intel_sdvo_connector->tv_chroma_filter)
1736 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1737 if (intel_sdvo_connector->dot_crawl)
1738 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1739 if (intel_sdvo_connector->brightness)
1740 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1741}
1742
79e53945
JB		 1743static void intel_sdvo_destroy(struct drm_connector *connector)
1744{
615fb93f 1745 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1746
c5521706 1747 if (intel_sdvo_connector->tv_format)
ce6feabd 1748 drm_property_destroy(connector->dev,
c5521706 1749 intel_sdvo_connector->tv_format);
b9219c5e 1750
d2a82a6f 1751 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1752 drm_sysfs_connector_remove(connector);
1753 drm_connector_cleanup(connector);
d2a82a6f 1754 kfree(connector);
79e53945
JB		 1755}
1756
ce6feabd
ZY		 1757static int
1758intel_sdvo_set_property(struct drm_connector *connector,
1759 struct drm_property *property,
1760 uint64_t val)
1761{
df0e9248 1762 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1763 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e 1764 uint16_t temp_value;
32aad86f
CW		 1765 uint8_t cmd;
1766 int ret;
ce6feabd
ZY		 1767
1768 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1769 if (ret)
1770 return ret;
ce6feabd 1771
c5521706
CW		 1772#define CHECK_PROPERTY(name, NAME) \
1773 if (intel_sdvo_connector->name == property) { \
1774 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1775 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1776 cmd = SDVO_CMD_SET_##NAME; \
1777 intel_sdvo_connector->cur_##name = temp_value; \
1778 goto set_value; \
1779 }
1780
1781 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1782 if (val >= TV_FORMAT_NUM)
1783 return -EINVAL;
1784
40039750 1785 if (intel_sdvo->tv_format_index ==
615fb93f 1786 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1787 return 0;
ce6feabd 1788
40039750 1789 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1790 goto done;
32aad86f 1791 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1792 temp_value = val;
c5521706 1793 if (intel_sdvo_connector->left == property) {
b9219c5e 1794 drm_connector_property_set_value(connector,
c5521706 1795 intel_sdvo_connector->right, val);
615fb93f 1796 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1797 return 0;
b9219c5e 1798
615fb93f
CW		 1799 intel_sdvo_connector->left_margin = temp_value;
1800 intel_sdvo_connector->right_margin = temp_value;
1801 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1802 intel_sdvo_connector->left_margin;
b9219c5e 1803 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1804 goto set_value;
1805 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1806 drm_connector_property_set_value(connector,
c5521706 1807 intel_sdvo_connector->left, val);
615fb93f 1808 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1809 return 0;
b9219c5e 1810
615fb93f
CW		 1811 intel_sdvo_connector->left_margin = temp_value;
1812 intel_sdvo_connector->right_margin = temp_value;
1813 temp_value = intel_sdvo_connector->max_hscan -
1814 intel_sdvo_connector->left_margin;
b9219c5e 1815 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1816 goto set_value;
1817 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1818 drm_connector_property_set_value(connector,
c5521706 1819 intel_sdvo_connector->bottom, val);
615fb93f 1820 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1821 return 0;
b9219c5e 1822
615fb93f
CW		 1823 intel_sdvo_connector->top_margin = temp_value;
1824 intel_sdvo_connector->bottom_margin = temp_value;
1825 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1826 intel_sdvo_connector->top_margin;
b9219c5e 1827 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1828 goto set_value;
1829 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1830 drm_connector_property_set_value(connector,
c5521706 1831 intel_sdvo_connector->top, val);
615fb93f 1832 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1833 return 0;
1834
615fb93f
CW		 1835 intel_sdvo_connector->top_margin = temp_value;
1836 intel_sdvo_connector->bottom_margin = temp_value;
1837 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1838 intel_sdvo_connector->top_margin;
b9219c5e 1839 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1840 goto set_value;
1841 }
1842 CHECK_PROPERTY(hpos, HPOS)
1843 CHECK_PROPERTY(vpos, VPOS)
1844 CHECK_PROPERTY(saturation, SATURATION)
1845 CHECK_PROPERTY(contrast, CONTRAST)
1846 CHECK_PROPERTY(hue, HUE)
1847 CHECK_PROPERTY(brightness, BRIGHTNESS)
1848 CHECK_PROPERTY(sharpness, SHARPNESS)
1849 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1850 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1851 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1852 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1853 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1854 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1855 }
b9219c5e 1856
c5521706 1857 return -EINVAL; /* unknown property */
b9219c5e 1858
c5521706
CW		 1859set_value:
1860 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1861 return -EIO;
b9219c5e 1862
b9219c5e 1863
c5521706 1864done:
df0e9248
CW		 1865 if (intel_sdvo->base.base.crtc) {
1866 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1867 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1868 crtc->y, crtc->fb);
1869 }
1870
32aad86f 1871 return 0;
c5521706 1872#undef CHECK_PROPERTY
ce6feabd
ZY		 1873}
1874
79e53945
JB		 1875static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1876 .dpms = intel_sdvo_dpms,
1877 .mode_fixup = intel_sdvo_mode_fixup,
1878 .prepare = intel_encoder_prepare,
1879 .mode_set = intel_sdvo_mode_set,
1880 .commit = intel_encoder_commit,
1881};
1882
1883static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1884 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1885 .detect = intel_sdvo_detect,
1886 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1887 .set_property = intel_sdvo_set_property,
79e53945
JB		 1888 .destroy = intel_sdvo_destroy,
1889};
1890
1891static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1892 .get_modes = intel_sdvo_get_modes,
1893 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1894 .best_encoder = intel_best_encoder,
79e53945
JB		 1895};
1896
b358d0a6 1897static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1898{
890f3359 1899 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1900
ea5b213a
CW		 1901 if (intel_sdvo->analog_ddc_bus)
1902 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
d2a82a6f 1903
ea5b213a 1904 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1905 drm_mode_destroy(encoder->dev,
ea5b213a 1906 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1907
ea5b213a 1908 intel_encoder_destroy(encoder);
79e53945
JB		 1909}
1910
1911static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1912 .destroy = intel_sdvo_enc_destroy,
1913};
1914
b66d8424
CW		 1915static void
1916intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1917{
1918 uint16_t mask = 0;
1919 unsigned int num_bits;
1920
1921 /* Make a mask of outputs less than or equal to our own priority in the
1922 * list.
1923 */
1924 switch (sdvo->controlled_output) {
1925 case SDVO_OUTPUT_LVDS1:
1926 mask |= SDVO_OUTPUT_LVDS1;
1927 case SDVO_OUTPUT_LVDS0:
1928 mask |= SDVO_OUTPUT_LVDS0;
1929 case SDVO_OUTPUT_TMDS1:
1930 mask |= SDVO_OUTPUT_TMDS1;
1931 case SDVO_OUTPUT_TMDS0:
1932 mask |= SDVO_OUTPUT_TMDS0;
1933 case SDVO_OUTPUT_RGB1:
1934 mask |= SDVO_OUTPUT_RGB1;
1935 case SDVO_OUTPUT_RGB0:
1936 mask |= SDVO_OUTPUT_RGB0;
1937 break;
1938 }
1939
1940 /* Count bits to find what number we are in the priority list. */
1941 mask &= sdvo->caps.output_flags;
1942 num_bits = hweight16(mask);
1943 /* If more than 3 outputs, default to DDC bus 3 for now. */
1944 if (num_bits > 3)
1945 num_bits = 3;
1946
1947 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1948 sdvo->ddc_bus = 1 << num_bits;
1949}
79e53945 1950
e2f0ba97
JB		 1951/**
1952 * Choose the appropriate DDC bus for control bus switch command for this
1953 * SDVO output based on the controlled output.
1954 *
1955 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1956 * outputs, then LVDS outputs.
1957 */
1958static void
b1083333 1959intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1960 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1961{
b1083333 1962 struct sdvo_device_mapping *mapping;
e2f0ba97 1963
b1083333
AJ		 1964 if (IS_SDVOB(reg))
1965 mapping = &(dev_priv->sdvo_mappings[0]);
1966 else
1967 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1968
b66d8424
CW		 1969 if (mapping->initialized)
1970 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1971 else
1972 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1973}
1974
1975static bool
ea5b213a 1976intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1977{
32aad86f
CW		 1978 return intel_sdvo_set_target_output(intel_sdvo,
1979 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
1980 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1981 &intel_sdvo->is_hdmi, 1);
e2f0ba97
JB		 1982}
1983
619ac3b7
ML		 1984static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
1985 struct i2c_msg msgs[], int num)
1986{
ea5b213a 1987 struct intel_sdvo *intel_sdvo;
f9c10a9b 1988 const struct i2c_algorithm *algo;
819f3fb7 1989 int ret;
619ac3b7 1990
890f3359
CW		 1991 intel_sdvo = container_of(i2c_adap->algo_data,
1992 struct intel_sdvo,
1993 base);
ea5b213a 1994 algo = intel_sdvo->base.i2c_bus->algo;
619ac3b7 1995
819f3fb7
CW		 1996 ret = intel_sdvo_set_control_bus_switch(intel_sdvo,
1997 intel_sdvo->ddc_bus);
1998 if (ret)
1999 return ret;
2000
619ac3b7
ML		 2001 return algo->master_xfer(i2c_adap, msgs, num);
2002}
2003
2004static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2005 .master_xfer = intel_sdvo_master_xfer,
2006};
2007
714605e4 2008static u8
c751ce4f 2009intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2010{
2011 struct drm_i915_private *dev_priv = dev->dev_private;
2012 struct sdvo_device_mapping *my_mapping, *other_mapping;
2013
461ed3ca 2014 if (IS_SDVOB(sdvo_reg)) {
714605e4 2015 my_mapping = &dev_priv->sdvo_mappings[0];
2016 other_mapping = &dev_priv->sdvo_mappings[1];
2017 } else {
2018 my_mapping = &dev_priv->sdvo_mappings[1];
2019 other_mapping = &dev_priv->sdvo_mappings[0];
2020 }
2021
2022 /* If the BIOS described our SDVO device, take advantage of it. */
2023 if (my_mapping->slave_addr)
2024 return my_mapping->slave_addr;
2025
2026 /* If the BIOS only described a different SDVO device, use the
2027 * address that it isn't using.
2028 */
2029 if (other_mapping->slave_addr) {
2030 if (other_mapping->slave_addr == 0x70)
2031 return 0x72;
2032 else
2033 return 0x70;
2034 }
2035
2036 /* No SDVO device info is found for another DVO port,
2037 * so use mapping assumption we had before BIOS parsing.
2038 */
461ed3ca 2039 if (IS_SDVOB(sdvo_reg))
714605e4 2040 return 0x70;
2041 else
2042 return 0x72;
2043}
2044
14571b4c 2045static void
df0e9248
CW		 2046intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2047 struct intel_sdvo *encoder)
14571b4c 2048{
df0e9248
CW		 2049 drm_connector_init(encoder->base.base.dev,
2050 &connector->base.base,
2051 &intel_sdvo_connector_funcs,
2052 connector->base.base.connector_type);
6070a4a9 2053
df0e9248
CW		 2054 drm_connector_helper_add(&connector->base.base,
2055 &intel_sdvo_connector_helper_funcs);
14571b4c 2056
df0e9248
CW		 2057 connector->base.base.interlace_allowed = 0;
2058 connector->base.base.doublescan_allowed = 0;
2059 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2060
df0e9248
CW		 2061 intel_connector_attach_encoder(&connector->base, &encoder->base);
2062 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2063}
6070a4a9 2064
fb7a46f3 2065static bool
ea5b213a 2066intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2067{
4ef69c7a 2068 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c
ZW		 2069 struct drm_connector *connector;
2070 struct intel_connector *intel_connector;
615fb93f 2071 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2072
615fb93f
CW		 2073 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2074 if (!intel_sdvo_connector)
14571b4c
ZW		 2075 return false;
2076
14571b4c 2077 if (device == 0) {
ea5b213a 2078 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2079 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2080 } else if (device == 1) {
ea5b213a 2081 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2082 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2083 }
2084
615fb93f 2085 intel_connector = &intel_sdvo_connector->base;
14571b4c 2086 connector = &intel_connector->base;
eb1f8e4f 2087 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2088 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2089 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2090
ea5b213a
CW		 2091 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2092 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2093 && intel_sdvo->is_hdmi) {
14571b4c 2094 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2095 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2096 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2097 SDVO_COLORIMETRY_RGB256);
2098 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2099 }
ea5b213a
CW		 2100 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2101 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2102
df0e9248 2103 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c
ZW		 2104
2105 return true;
2106}
2107
2108static bool
ea5b213a 2109intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2110{
4ef69c7a
CW		 2111 struct drm_encoder *encoder = &intel_sdvo->base.base;
2112 struct drm_connector *connector;
2113 struct intel_connector *intel_connector;
2114 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2115
615fb93f
CW		 2116 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2117 if (!intel_sdvo_connector)
2118 return false;
14571b4c 2119
615fb93f 2120 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2121 connector = &intel_connector->base;
2122 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2123 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2124
4ef69c7a
CW		 2125 intel_sdvo->controlled_output |= type;
2126 intel_sdvo_connector->output_flag = type;
14571b4c 2127
4ef69c7a
CW		 2128 intel_sdvo->is_tv = true;
2129 intel_sdvo->base.needs_tv_clock = true;
2130 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2131
df0e9248 2132 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2133
4ef69c7a 2134 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2135 goto err;
14571b4c 2136
4ef69c7a 2137 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2138 goto err;
14571b4c 2139
4ef69c7a 2140 return true;
32aad86f
CW		 2141
2142err:
fcc8d672 2143 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2144 kfree(intel_sdvo_connector);
2145 return false;
14571b4c
ZW		 2146}
2147
2148static bool
ea5b213a 2149intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2150{
4ef69c7a
CW		 2151 struct drm_encoder *encoder = &intel_sdvo->base.base;
2152 struct drm_connector *connector;
2153 struct intel_connector *intel_connector;
2154 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2155
615fb93f
CW		 2156 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2157 if (!intel_sdvo_connector)
2158 return false;
14571b4c 2159
615fb93f 2160 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2161 connector = &intel_connector->base;
eb1f8e4f 2162 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2163 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2164 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2165
2166 if (device == 0) {
2167 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2168 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2169 } else if (device == 1) {
2170 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2171 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2172 }
2173
2174 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2175 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2176
df0e9248
CW		 2177 intel_sdvo_connector_init(intel_sdvo_connector,
2178 intel_sdvo);
4ef69c7a 2179 return true;
14571b4c
ZW		 2180}
2181
2182static bool
ea5b213a 2183intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2184{
4ef69c7a
CW		 2185 struct drm_encoder *encoder = &intel_sdvo->base.base;
2186 struct drm_connector *connector;
2187 struct intel_connector *intel_connector;
2188 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2189
615fb93f
CW		 2190 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2191 if (!intel_sdvo_connector)
2192 return false;
14571b4c 2193
615fb93f
CW		 2194 intel_connector = &intel_sdvo_connector->base;
2195 connector = &intel_connector->base;
4ef69c7a
CW		 2196 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2197 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2198
2199 if (device == 0) {
2200 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2201 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2202 } else if (device == 1) {
2203 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2204 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2205 }
2206
2207 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2208 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2209
df0e9248 2210 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2211 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2212 goto err;
2213
2214 return true;
2215
2216err:
fcc8d672 2217 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2218 kfree(intel_sdvo_connector);
2219 return false;
14571b4c
ZW		 2220}
2221
2222static bool
ea5b213a 2223intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2224{
ea5b213a
CW		 2225 intel_sdvo->is_tv = false;
2226 intel_sdvo->base.needs_tv_clock = false;
2227 intel_sdvo->is_lvds = false;
fb7a46f3 2228
14571b4c 2229 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2230
14571b4c 2231 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2232 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2233 return false;
2234
2235 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2236 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2237 return false;
2238
2239 /* TV has no XXX1 function block */
a1f4b7ff 2240 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2241 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2242 return false;
2243
2244 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2245 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2246 return false;
fb7a46f3 2247
14571b4c 2248 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2249 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2250 return false;
2251
2252 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2253 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2254 return false;
2255
2256 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2257 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2258 return false;
2259
2260 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2261 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2262 return false;
fb7a46f3 2263
14571b4c 2264 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2265 unsigned char bytes[2];
2266
ea5b213a
CW		 2267 intel_sdvo->controlled_output = 0;
2268 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2269 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2270 SDVO_NAME(intel_sdvo),
51c8b407 2271 bytes[0], bytes[1]);
14571b4c 2272 return false;
fb7a46f3 2273 }
ea5b213a 2274 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2275
14571b4c 2276 return true;
fb7a46f3 2277}
2278
32aad86f
CW		 2279static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2280 struct intel_sdvo_connector *intel_sdvo_connector,
2281 int type)
ce6feabd 2282{
4ef69c7a 2283 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2284 struct intel_sdvo_tv_format format;
2285 uint32_t format_map, i;
ce6feabd 2286
32aad86f
CW		 2287 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2288 return false;
ce6feabd 2289
32aad86f
CW		 2290 if (!intel_sdvo_get_value(intel_sdvo,
2291 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2292 &format, sizeof(format)))
2293 return false;
ce6feabd 2294
32aad86f 2295 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2296
2297 if (format_map == 0)
32aad86f 2298 return false;
ce6feabd 2299
615fb93f 2300 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2301 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2302 if (format_map & (1 << i))
2303 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2304
2305
c5521706 2306 intel_sdvo_connector->tv_format =
32aad86f
CW		 2307 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2308 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2309 if (!intel_sdvo_connector->tv_format)
fcc8d672 2310 return false;
ce6feabd 2311
615fb93f 2312 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2313 drm_property_add_enum(
c5521706 2314 intel_sdvo_connector->tv_format, i,
40039750 2315 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2316
40039750 2317 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2318 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2319 intel_sdvo_connector->tv_format, 0);
32aad86f 2320 return true;
ce6feabd
ZY		 2321
2322}
2323
c5521706
CW		 2324#define ENHANCEMENT(name, NAME) do { \
2325 if (enhancements.name) { \
2326 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2327 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2328 return false; \
2329 intel_sdvo_connector->max_##name = data_value[0]; \
2330 intel_sdvo_connector->cur_##name = response; \
2331 intel_sdvo_connector->name = \
2332 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2333 if (!intel_sdvo_connector->name) return false; \
2334 intel_sdvo_connector->name->values[0] = 0; \
2335 intel_sdvo_connector->name->values[1] = data_value[0]; \
2336 drm_connector_attach_property(connector, \
2337 intel_sdvo_connector->name, \
2338 intel_sdvo_connector->cur_##name); \
2339 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2340 data_value[0], data_value[1], response); \
2341 } \
2342} while(0)
2343
2344static bool
2345intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2346 struct intel_sdvo_connector *intel_sdvo_connector,
2347 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2348{
4ef69c7a 2349 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2350 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2351 uint16_t response, data_value[2];
2352
c5521706
CW		 2353 /* when horizontal overscan is supported, Add the left/right property */
2354 if (enhancements.overscan_h) {
2355 if (!intel_sdvo_get_value(intel_sdvo,
2356 SDVO_CMD_GET_MAX_OVERSCAN_H,
2357 &data_value, 4))
2358 return false;
32aad86f 2359
c5521706
CW		 2360 if (!intel_sdvo_get_value(intel_sdvo,
2361 SDVO_CMD_GET_OVERSCAN_H,
2362 &response, 2))
2363 return false;
fcc8d672 2364
c5521706
CW		 2365 intel_sdvo_connector->max_hscan = data_value[0];
2366 intel_sdvo_connector->left_margin = data_value[0] - response;
2367 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2368 intel_sdvo_connector->left =
2369 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2370 "left_margin", 2);
2371 if (!intel_sdvo_connector->left)
2372 return false;
fcc8d672 2373
c5521706
CW		 2374 intel_sdvo_connector->left->values[0] = 0;
2375 intel_sdvo_connector->left->values[1] = data_value[0];
2376 drm_connector_attach_property(connector,
2377 intel_sdvo_connector->left,
2378 intel_sdvo_connector->left_margin);
fcc8d672 2379
c5521706
CW		 2380 intel_sdvo_connector->right =
2381 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2382 "right_margin", 2);
2383 if (!intel_sdvo_connector->right)
2384 return false;
32aad86f 2385
c5521706
CW		 2386 intel_sdvo_connector->right->values[0] = 0;
2387 intel_sdvo_connector->right->values[1] = data_value[0];
2388 drm_connector_attach_property(connector,
2389 intel_sdvo_connector->right,
2390 intel_sdvo_connector->right_margin);
2391 DRM_DEBUG_KMS("h_overscan: max %d, "
2392 "default %d, current %d\n",
2393 data_value[0], data_value[1], response);
2394 }
32aad86f 2395
c5521706
CW		 2396 if (enhancements.overscan_v) {
2397 if (!intel_sdvo_get_value(intel_sdvo,
2398 SDVO_CMD_GET_MAX_OVERSCAN_V,
2399 &data_value, 4))
2400 return false;
fcc8d672 2401
c5521706
CW		 2402 if (!intel_sdvo_get_value(intel_sdvo,
2403 SDVO_CMD_GET_OVERSCAN_V,
2404 &response, 2))
2405 return false;
32aad86f 2406
c5521706
CW		 2407 intel_sdvo_connector->max_vscan = data_value[0];
2408 intel_sdvo_connector->top_margin = data_value[0] - response;
2409 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2410 intel_sdvo_connector->top =
2411 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2412 "top_margin", 2);
2413 if (!intel_sdvo_connector->top)
2414 return false;
32aad86f 2415
c5521706
CW		 2416 intel_sdvo_connector->top->values[0] = 0;
2417 intel_sdvo_connector->top->values[1] = data_value[0];
2418 drm_connector_attach_property(connector,
2419 intel_sdvo_connector->top,
2420 intel_sdvo_connector->top_margin);
fcc8d672 2421
c5521706
CW		 2422 intel_sdvo_connector->bottom =
2423 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2424 "bottom_margin", 2);
2425 if (!intel_sdvo_connector->bottom)
2426 return false;
32aad86f 2427
c5521706
CW		 2428 intel_sdvo_connector->bottom->values[0] = 0;
2429 intel_sdvo_connector->bottom->values[1] = data_value[0];
2430 drm_connector_attach_property(connector,
2431 intel_sdvo_connector->bottom,
2432 intel_sdvo_connector->bottom_margin);
2433 DRM_DEBUG_KMS("v_overscan: max %d, "
2434 "default %d, current %d\n",
2435 data_value[0], data_value[1], response);
2436 }
32aad86f 2437
c5521706
CW		 2438 ENHANCEMENT(hpos, HPOS);
2439 ENHANCEMENT(vpos, VPOS);
2440 ENHANCEMENT(saturation, SATURATION);
2441 ENHANCEMENT(contrast, CONTRAST);
2442 ENHANCEMENT(hue, HUE);
2443 ENHANCEMENT(sharpness, SHARPNESS);
2444 ENHANCEMENT(brightness, BRIGHTNESS);
2445 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2446 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2447 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2448 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2449 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2450
e044218a
CW		 2451 if (enhancements.dot_crawl) {
2452 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2453 return false;
2454
2455 intel_sdvo_connector->max_dot_crawl = 1;
2456 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2457 intel_sdvo_connector->dot_crawl =
2458 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2459 if (!intel_sdvo_connector->dot_crawl)
2460 return false;
2461
2462 intel_sdvo_connector->dot_crawl->values[0] = 0;
2463 intel_sdvo_connector->dot_crawl->values[1] = 1;
2464 drm_connector_attach_property(connector,
2465 intel_sdvo_connector->dot_crawl,
2466 intel_sdvo_connector->cur_dot_crawl);
2467 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2468 }
2469
c5521706
CW		 2470 return true;
2471}
32aad86f 2472
c5521706
CW		 2473static bool
2474intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2475 struct intel_sdvo_connector *intel_sdvo_connector,
2476 struct intel_sdvo_enhancements_reply enhancements)
2477{
4ef69c7a 2478 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2479 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2480 uint16_t response, data_value[2];
32aad86f 2481
c5521706 2482 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2483
c5521706
CW		 2484 return true;
2485}
2486#undef ENHANCEMENT
32aad86f 2487
c5521706
CW		 2488static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2489 struct intel_sdvo_connector *intel_sdvo_connector)
2490{
2491 union {
2492 struct intel_sdvo_enhancements_reply reply;
2493 uint16_t response;
2494 } enhancements;
32aad86f 2495
c5521706
CW		 2496 if (!intel_sdvo_get_value(intel_sdvo,
2497 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2498 &enhancements, sizeof(enhancements)))
2499 return false;
fcc8d672 2500
c5521706
CW		 2501 if (enhancements.response == 0) {
2502 DRM_DEBUG_KMS("No enhancement is supported\n");
2503 return true;
b9219c5e 2504 }
32aad86f 2505
c5521706
CW		 2506 if (IS_TV(intel_sdvo_connector))
2507 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2508 else if(IS_LVDS(intel_sdvo_connector))
2509 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2510 else
2511 return true;
fcc8d672 2512
b9219c5e
ZY		 2513}
2514
c751ce4f 2515bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2516{
b01f2c3a 2517 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2518 struct intel_encoder *intel_encoder;
ea5b213a 2519 struct intel_sdvo *intel_sdvo;
79e53945
JB		 2520 u8 ch[0x40];
2521 int i;
461ed3ca 2522 u32 i2c_reg, ddc_reg, analog_ddc_reg;
79e53945 2523
ea5b213a
CW		 2524 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2525 if (!intel_sdvo)
7d57382e 2526 return false;
79e53945 2527
ea5b213a 2528 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2529
ea5b213a 2530 intel_encoder = &intel_sdvo->base;
21d40d37 2531 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2532
461ed3ca
ZY		 2533 if (HAS_PCH_SPLIT(dev)) {
2534 i2c_reg = PCH_GPIOE;
2535 ddc_reg = PCH_GPIOE;
2536 analog_ddc_reg = PCH_GPIOA;
2537 } else {
2538 i2c_reg = GPIOE;
2539 ddc_reg = GPIOE;
2540 analog_ddc_reg = GPIOA;
2541 }
2542
79e53945 2543 /* setup the DDC bus. */
461ed3ca 2544 if (IS_SDVOB(sdvo_reg))
890f3359
CW		 2545 intel_encoder->i2c_bus =
2546 intel_i2c_create(intel_encoder,
2547 i2c_reg, "SDVOCTRL_E for SDVOB");
308cd3a2 2548 else
890f3359
CW		 2549 intel_encoder->i2c_bus =
2550 intel_i2c_create(intel_encoder,
2551 i2c_reg, "SDVOCTRL_E for SDVOC");
308cd3a2 2552
21d40d37 2553 if (!intel_encoder->i2c_bus)
ad5b2a6d 2554 goto err_inteloutput;
79e53945 2555
ea5b213a 2556 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2557
308cd3a2 2558 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2559 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2560
79e53945
JB		 2561 /* Read the regs to test if we can talk to the device */
2562 for (i = 0; i < 0x40; i++) {
ea5b213a 2563 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
8a4c47f3 2564 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2565 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2566 goto err_i2c;
2567 }
2568 }
2569
619ac3b7 2570 /* setup the DDC bus. */
461ed3ca 2571 if (IS_SDVOB(sdvo_reg)) {
890f3359
CW		 2572 intel_encoder->ddc_bus =
2573 intel_i2c_create(intel_encoder,
2574 ddc_reg, "SDVOB DDC BUS");
2575 intel_sdvo->analog_ddc_bus =
2576 intel_i2c_create(intel_encoder,
2577 analog_ddc_reg, "SDVOB/VGA DDC BUS");
b01f2c3a 2578 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2579 } else {
890f3359
CW		 2580 intel_encoder->ddc_bus =
2581 intel_i2c_create(intel_encoder,
2582 ddc_reg, "SDVOC DDC BUS");
2583 intel_sdvo->analog_ddc_bus =
2584 intel_i2c_create(intel_encoder,
2585 analog_ddc_reg, "SDVOC/VGA DDC BUS");
b01f2c3a 2586 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2587 }
32aad86f 2588 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
619ac3b7
ML		 2589 goto err_i2c;
2590
308cd3a2 2591 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2592 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2593
14571b4c 2594 /* encoder type will be decided later */
4ef69c7a
CW		 2595 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2596 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2597
af901ca1 2598 /* In default case sdvo lvds is false */
32aad86f
CW		 2599 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2600 goto err_enc;
79e53945 2601
ea5b213a
CW		 2602 if (intel_sdvo_output_setup(intel_sdvo,
2603 intel_sdvo->caps.output_flags) != true) {
51c8b407 2604 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2605 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
32aad86f 2606 goto err_enc;
79e53945
JB		 2607 }
2608
ea5b213a 2609 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2610
79e53945 2611 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 2612 if (!intel_sdvo_set_target_input(intel_sdvo))
2613 goto err_enc;
79e53945 2614
32aad86f
CW		 2615 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2616 &intel_sdvo->pixel_clock_min,
2617 &intel_sdvo->pixel_clock_max))
2618 goto err_enc;
79e53945 2619
8a4c47f3 2620 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2621 "clock range %dMHz - %dMHz, "
2622 "input 1: %c, input 2: %c, "
2623 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2624 SDVO_NAME(intel_sdvo),
2625 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2626 intel_sdvo->caps.device_rev_id,
2627 intel_sdvo->pixel_clock_min / 1000,
2628 intel_sdvo->pixel_clock_max / 1000,
2629 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2630 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2631 /* check currently supported outputs */
ea5b213a 2632 intel_sdvo->caps.output_flags &
79e53945 2633 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2634 intel_sdvo->caps.output_flags &
79e53945 2635 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2636 return true;
79e53945 2637
32aad86f 2638err_enc:
4ef69c7a 2639 drm_encoder_cleanup(&intel_encoder->base);
79e53945 2640err_i2c:
ea5b213a
CW		 2641 if (intel_sdvo->analog_ddc_bus != NULL)
2642 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
21d40d37
EA		 2643 if (intel_encoder->ddc_bus != NULL)
2644 intel_i2c_destroy(intel_encoder->ddc_bus);
2645 if (intel_encoder->i2c_bus != NULL)
2646 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2647err_inteloutput:
ea5b213a 2648 kfree(intel_sdvo);
79e53945 2649
7d57382e 2650 return false;
79e53945 2651}
Linux kernel - Deliverables
This page took 0.331661 seconds and 5 git commands to generate.