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drm/i915/intel_i2c: use i2c pre/post_xfer functions to setup gpio xfers
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
2e88e40b 56static const char *tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 77 uint32_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
100 uint8_t hotplug_active[2];
101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
12682a97 129
7086c87f 130 /**
6c9547ff
CW		 131 * This is set if we detect output of sdvo device as LVDS and
132 * have a valid fixed mode to use with the panel.
7086c87f
ML		 133 */
134 bool is_lvds;
e2f0ba97 135
12682a97 136 /**
137 * This is sdvo fixed pannel mode pointer
138 */
139 struct drm_display_mode *sdvo_lvds_fixed_mode;
140
c751ce4f 141 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 142 uint8_t ddc_bus;
143
6c9547ff
CW		 144 /* Input timings for adjusted_mode */
145 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 146};
147
148struct intel_sdvo_connector {
615fb93f
CW		 149 struct intel_connector base;
150
14571b4c
ZW		 151 /* Mark the type of connector */
152 uint16_t output_flag;
153
c3e5f67b 154 enum hdmi_force_audio force_audio;
7f36e7ed 155
14571b4c 156 /* This contains all current supported TV format */
40039750 157 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 158 int format_supported_num;
c5521706 159 struct drm_property *tv_format;
14571b4c 160
b9219c5e 161 /* add the property for the SDVO-TV */
c5521706
CW		 162 struct drm_property *left;
163 struct drm_property *right;
164 struct drm_property *top;
165 struct drm_property *bottom;
166 struct drm_property *hpos;
167 struct drm_property *vpos;
168 struct drm_property *contrast;
169 struct drm_property *saturation;
170 struct drm_property *hue;
171 struct drm_property *sharpness;
172 struct drm_property *flicker_filter;
173 struct drm_property *flicker_filter_adaptive;
174 struct drm_property *flicker_filter_2d;
175 struct drm_property *tv_chroma_filter;
176 struct drm_property *tv_luma_filter;
e044218a 177 struct drm_property *dot_crawl;
b9219c5e
ZY		 178
179 /* add the property for the SDVO-TV/LVDS */
c5521706 180 struct drm_property *brightness;
b9219c5e
ZY		 181
182 /* Add variable to record current setting for the above property */
183 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 184
b9219c5e
ZY		 185 /* this is to get the range of margin.*/
186 u32 max_hscan, max_vscan;
187 u32 max_hpos, cur_hpos;
188 u32 max_vpos, cur_vpos;
189 u32 cur_brightness, max_brightness;
190 u32 cur_contrast, max_contrast;
191 u32 cur_saturation, max_saturation;
192 u32 cur_hue, max_hue;
c5521706
CW		 193 u32 cur_sharpness, max_sharpness;
194 u32 cur_flicker_filter, max_flicker_filter;
195 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
196 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
197 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
198 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 199 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 200};
201
890f3359 202static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 203{
4ef69c7a 204 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 205}
206
df0e9248
CW		 207static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
208{
209 return container_of(intel_attached_encoder(connector),
210 struct intel_sdvo, base);
211}
212
615fb93f
CW		 213static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
214{
215 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
216}
217
fb7a46f3 218static bool
ea5b213a 219intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 220static bool
221intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
222 struct intel_sdvo_connector *intel_sdvo_connector,
223 int type);
224static bool
225intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
226 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 227
79e53945
JB		 228/**
229 * Writes the SDVOB or SDVOC with the given value, but always writes both
230 * SDVOB and SDVOC to work around apparent hardware issues (according to
231 * comments in the BIOS).
232 */
ea5b213a 233static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 234{
4ef69c7a 235 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 236 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 237 u32 bval = val, cval = val;
238 int i;
239
ea5b213a
CW		 240 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
241 I915_WRITE(intel_sdvo->sdvo_reg, val);
242 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 243 return;
244 }
245
ea5b213a 246 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 247 cval = I915_READ(SDVOC);
248 } else {
249 bval = I915_READ(SDVOB);
250 }
251 /*
252 * Write the registers twice for luck. Sometimes,
253 * writing them only once doesn't appear to 'stick'.
254 * The BIOS does this too. Yay, magic
255 */
256 for (i = 0; i < 2; i++)
257 {
258 I915_WRITE(SDVOB, bval);
259 I915_READ(SDVOB);
260 I915_WRITE(SDVOC, cval);
261 I915_READ(SDVOC);
262 }
263}
264
32aad86f 265static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 266{
79e53945
JB		 267 struct i2c_msg msgs[] = {
268 {
e957d772 269 .addr = intel_sdvo->slave_addr,
79e53945
JB		 270 .flags = 0,
271 .len = 1,
e957d772 272 .buf = &addr,
79e53945
JB		 273 },
274 {
e957d772 275 .addr = intel_sdvo->slave_addr,
79e53945
JB		 276 .flags = I2C_M_RD,
277 .len = 1,
e957d772 278 .buf = ch,
79e53945
JB		 279 }
280 };
32aad86f 281 int ret;
79e53945 282
f899fc64 283 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 284 return true;
79e53945 285
8a4c47f3 286 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 287 return false;
288}
289
79e53945
JB		 290#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
291/** Mapping of command numbers to names, for debug output */
005568be 292static const struct _sdvo_cmd_name {
e2f0ba97 293 u8 cmd;
2e88e40b 294 const char *name;
79e53945 295} sdvo_cmd_names[] = {
0206e353
AJ		 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
339
340 /* Add the op code for SDVO enhancements */
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
385
386 /* HDMI op code */
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 407};
408
eef4eacb 409#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 410
ea5b213a 411static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 412 const void *args, int args_len)
79e53945 413{
79e53945
JB		 414 int i;
415
8a4c47f3 416 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 417 SDVO_NAME(intel_sdvo), cmd);
79e53945 418 for (i = 0; i < args_len; i++)
342dc382 419 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 420 for (; i < 8; i++)
342dc382 421 DRM_LOG_KMS(" ");
04ad327f 422 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 423 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 424 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 425 break;
426 }
427 }
04ad327f 428 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 429 DRM_LOG_KMS("(%02X)", cmd);
430 DRM_LOG_KMS("\n");
79e53945 431}
79e53945 432
e957d772
CW		 433static const char *cmd_status_names[] = {
434 "Power on",
435 "Success",
436 "Not supported",
437 "Invalid arg",
438 "Pending",
439 "Target not specified",
440 "Scaling not supported"
441};
442
32aad86f
CW		 443static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
444 const void *args, int args_len)
79e53945 445{
e957d772
CW		 446 u8 buf[args_len*2 + 2], status;
447 struct i2c_msg msgs[args_len + 3];
448 int i, ret;
79e53945 449
ea5b213a 450 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 451
452 for (i = 0; i < args_len; i++) {
e957d772
CW		 453 msgs[i].addr = intel_sdvo->slave_addr;
454 msgs[i].flags = 0;
455 msgs[i].len = 2;
456 msgs[i].buf = buf + 2 *i;
457 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
458 buf[2*i + 1] = ((u8*)args)[i];
459 }
460 msgs[i].addr = intel_sdvo->slave_addr;
461 msgs[i].flags = 0;
462 msgs[i].len = 2;
463 msgs[i].buf = buf + 2*i;
464 buf[2*i + 0] = SDVO_I2C_OPCODE;
465 buf[2*i + 1] = cmd;
466
467 /* the following two are to read the response */
468 status = SDVO_I2C_CMD_STATUS;
469 msgs[i+1].addr = intel_sdvo->slave_addr;
470 msgs[i+1].flags = 0;
471 msgs[i+1].len = 1;
472 msgs[i+1].buf = &status;
473
474 msgs[i+2].addr = intel_sdvo->slave_addr;
475 msgs[i+2].flags = I2C_M_RD;
476 msgs[i+2].len = 1;
477 msgs[i+2].buf = &status;
478
479 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
480 if (ret < 0) {
481 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
482 return false;
483 }
484 if (ret != i+3) {
485 /* failure in I2C transfer */
486 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
487 return false;
488 }
489
e957d772 490 return true;
79e53945
JB		 491}
492
b5c616a7
CW		 493static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
494 void *response, int response_len)
79e53945 495{
b5c616a7
CW		 496 u8 retry = 5;
497 u8 status;
33b52961 498 int i;
79e53945 499
d121a5d2
CW		 500 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
501
b5c616a7
CW		 502 /*
503 * The documentation states that all commands will be
504 * processed within 15µs, and that we need only poll
505 * the status byte a maximum of 3 times in order for the
506 * command to be complete.
507 *
508 * Check 5 times in case the hardware failed to read the docs.
509 */
d121a5d2
CW		 510 if (!intel_sdvo_read_byte(intel_sdvo,
511 SDVO_I2C_CMD_STATUS,
512 &status))
513 goto log_fail;
514
515 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
516 udelay(15);
b5c616a7
CW		 517 if (!intel_sdvo_read_byte(intel_sdvo,
518 SDVO_I2C_CMD_STATUS,
519 &status))
d121a5d2
CW		 520 goto log_fail;
521 }
b5c616a7 522
79e53945 523 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 524 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 525 else
342dc382 526 DRM_LOG_KMS("(??? %d)", status);
79e53945 527
b5c616a7
CW		 528 if (status != SDVO_CMD_STATUS_SUCCESS)
529 goto log_fail;
79e53945 530
b5c616a7
CW		 531 /* Read the command response */
532 for (i = 0; i < response_len; i++) {
533 if (!intel_sdvo_read_byte(intel_sdvo,
534 SDVO_I2C_RETURN_0 + i,
535 &((u8 *)response)[i]))
536 goto log_fail;
e957d772 537 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 538 }
b5c616a7 539 DRM_LOG_KMS("\n");
b5c616a7 540 return true;
79e53945 541
b5c616a7 542log_fail:
d121a5d2 543 DRM_LOG_KMS("... failed\n");
b5c616a7 544 return false;
79e53945
JB		 545}
546
b358d0a6 547static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 548{
549 if (mode->clock >= 100000)
550 return 1;
551 else if (mode->clock >= 50000)
552 return 2;
553 else
554 return 4;
555}
556
e957d772
CW		 557static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
558 u8 ddc_bus)
79e53945 559{
d121a5d2 560 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 561 return intel_sdvo_write_cmd(intel_sdvo,
562 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
563 &ddc_bus, 1);
79e53945
JB		 564}
565
32aad86f 566static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 567{
d121a5d2
CW		 568 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
569 return false;
570
571 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 572}
79e53945 573
32aad86f
CW		 574static bool
575intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
576{
577 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
578 return false;
79e53945 579
32aad86f
CW		 580 return intel_sdvo_read_response(intel_sdvo, value, len);
581}
79e53945 582
32aad86f
CW		 583static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
584{
585 struct intel_sdvo_set_target_input_args targets = {0};
586 return intel_sdvo_set_value(intel_sdvo,
587 SDVO_CMD_SET_TARGET_INPUT,
588 &targets, sizeof(targets));
79e53945
JB		 589}
590
591/**
592 * Return whether each input is trained.
593 *
594 * This function is making an assumption about the layout of the response,
595 * which should be checked against the docs.
596 */
ea5b213a 597static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 598{
599 struct intel_sdvo_get_trained_inputs_response response;
79e53945 600
1a3665c8 601 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 602 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
603 &response, sizeof(response)))
79e53945
JB		 604 return false;
605
606 *input_1 = response.input0_trained;
607 *input_2 = response.input1_trained;
608 return true;
609}
610
ea5b213a 611static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 612 u16 outputs)
613{
32aad86f
CW		 614 return intel_sdvo_set_value(intel_sdvo,
615 SDVO_CMD_SET_ACTIVE_OUTPUTS,
616 &outputs, sizeof(outputs));
79e53945
JB		 617}
618
ea5b213a 619static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 620 int mode)
621{
32aad86f 622 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 623
624 switch (mode) {
625 case DRM_MODE_DPMS_ON:
626 state = SDVO_ENCODER_STATE_ON;
627 break;
628 case DRM_MODE_DPMS_STANDBY:
629 state = SDVO_ENCODER_STATE_STANDBY;
630 break;
631 case DRM_MODE_DPMS_SUSPEND:
632 state = SDVO_ENCODER_STATE_SUSPEND;
633 break;
634 case DRM_MODE_DPMS_OFF:
635 state = SDVO_ENCODER_STATE_OFF;
636 break;
637 }
638
32aad86f
CW		 639 return intel_sdvo_set_value(intel_sdvo,
640 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 641}
642
ea5b213a 643static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 644 int *clock_min,
645 int *clock_max)
646{
647 struct intel_sdvo_pixel_clock_range clocks;
79e53945 648
1a3665c8 649 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 650 if (!intel_sdvo_get_value(intel_sdvo,
651 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
652 &clocks, sizeof(clocks)))
79e53945
JB		 653 return false;
654
655 /* Convert the values from units of 10 kHz to kHz. */
656 *clock_min = clocks.min * 10;
657 *clock_max = clocks.max * 10;
79e53945
JB		 658 return true;
659}
660
ea5b213a 661static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 662 u16 outputs)
663{
32aad86f
CW		 664 return intel_sdvo_set_value(intel_sdvo,
665 SDVO_CMD_SET_TARGET_OUTPUT,
666 &outputs, sizeof(outputs));
79e53945
JB		 667}
668
ea5b213a 669static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 670 struct intel_sdvo_dtd *dtd)
671{
32aad86f
CW		 672 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
673 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 674}
675
ea5b213a 676static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 677 struct intel_sdvo_dtd *dtd)
678{
ea5b213a 679 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 680 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
681}
682
ea5b213a 683static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 684 struct intel_sdvo_dtd *dtd)
685{
ea5b213a 686 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 687 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
688}
689
e2f0ba97 690static bool
ea5b213a 691intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 692 uint16_t clock,
693 uint16_t width,
694 uint16_t height)
695{
696 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 697
e642c6f1 698 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 699 args.clock = clock;
700 args.width = width;
701 args.height = height;
e642c6f1 702 args.interlace = 0;
12682a97 703
ea5b213a
CW		 704 if (intel_sdvo->is_lvds &&
705 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
706 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 707 args.scaled = 1;
708
32aad86f
CW		 709 return intel_sdvo_set_value(intel_sdvo,
710 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
711 &args, sizeof(args));
e2f0ba97
JB		 712}
713
ea5b213a 714static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 715 struct intel_sdvo_dtd *dtd)
716{
1a3665c8
CW		 717 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
718 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 719 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
720 &dtd->part1, sizeof(dtd->part1)) &&
721 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
722 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 723}
79e53945 724
ea5b213a 725static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 726{
32aad86f 727 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 728}
729
e2f0ba97 730static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 731 const struct drm_display_mode *mode)
79e53945 732{
e2f0ba97
JB		 733 uint16_t width, height;
734 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
735 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 736
737 width = mode->crtc_hdisplay;
738 height = mode->crtc_vdisplay;
739
740 /* do some mode translations */
741 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
742 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
743
744 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
745 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
746
747 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
748 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
749
e2f0ba97
JB		 750 dtd->part1.clock = mode->clock / 10;
751 dtd->part1.h_active = width & 0xff;
752 dtd->part1.h_blank = h_blank_len & 0xff;
753 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 754 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 755 dtd->part1.v_active = height & 0xff;
756 dtd->part1.v_blank = v_blank_len & 0xff;
757 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 758 ((v_blank_len >> 8) & 0xf);
759
171a9e96 760 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 761 dtd->part2.h_sync_width = h_sync_len & 0xff;
762 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 763 (v_sync_len & 0xf);
e2f0ba97 764 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 765 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
766 ((v_sync_len & 0x30) >> 4);
767
e2f0ba97 768 dtd->part2.dtd_flags = 0x18;
79e53945 769 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 770 dtd->part2.dtd_flags |= 0x2;
79e53945 771 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 772 dtd->part2.dtd_flags |= 0x4;
773
774 dtd->part2.sdvo_flags = 0;
775 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
776 dtd->part2.reserved = 0;
777}
778
779static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 780 const struct intel_sdvo_dtd *dtd)
e2f0ba97 781{
e2f0ba97
JB		 782 mode->hdisplay = dtd->part1.h_active;
783 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
784 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 785 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 786 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
787 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
788 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
789 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
790
791 mode->vdisplay = dtd->part1.v_active;
792 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
793 mode->vsync_start = mode->vdisplay;
794 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 795 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 796 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
797 mode->vsync_end = mode->vsync_start +
798 (dtd->part2.v_sync_off_width & 0xf);
799 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
800 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
801 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
802
803 mode->clock = dtd->part1.clock * 10;
804
171a9e96 805 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 806 if (dtd->part2.dtd_flags & 0x2)
807 mode->flags |= DRM_MODE_FLAG_PHSYNC;
808 if (dtd->part2.dtd_flags & 0x4)
809 mode->flags |= DRM_MODE_FLAG_PVSYNC;
810}
811
e27d8538 812static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 813{
e27d8538 814 struct intel_sdvo_encode encode;
e2f0ba97 815
1a3665c8 816 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 817 return intel_sdvo_get_value(intel_sdvo,
818 SDVO_CMD_GET_SUPP_ENCODE,
819 &encode, sizeof(encode));
e2f0ba97
JB		 820}
821
ea5b213a 822static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 823 uint8_t mode)
e2f0ba97 824{
32aad86f 825 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 826}
827
ea5b213a 828static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 829 uint8_t mode)
830{
32aad86f 831 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 832}
833
834#if 0
ea5b213a 835static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 836{
837 int i, j;
838 uint8_t set_buf_index[2];
839 uint8_t av_split;
840 uint8_t buf_size;
841 uint8_t buf[48];
842 uint8_t *pos;
843
32aad86f 844 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 845
846 for (i = 0; i <= av_split; i++) {
847 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 848 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 849 set_buf_index, 2);
c751ce4f
EA		 850 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
851 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 852
853 pos = buf;
854 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 855 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 856 NULL, 0);
c751ce4f 857 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 858 pos += 8;
859 }
860 }
861}
862#endif
863
3c17fe4b 864static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 865{
866 struct dip_infoframe avi_if = {
867 .type = DIP_TYPE_AVI,
3c17fe4b 868 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 869 .len = DIP_LEN_AVI,
870 };
3c17fe4b
DH		 871 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
872 uint8_t set_buf_index[2] = { 1, 0 };
873 uint64_t *data = (uint64_t *)&avi_if;
874 unsigned i;
875
876 intel_dip_infoframe_csum(&avi_if);
877
d121a5d2
CW		 878 if (!intel_sdvo_set_value(intel_sdvo,
879 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 880 set_buf_index, 2))
881 return false;
882
883 for (i = 0; i < sizeof(avi_if); i += 8) {
d121a5d2
CW		 884 if (!intel_sdvo_set_value(intel_sdvo,
885 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 886 data, 8))
887 return false;
888 data++;
889 }
e2f0ba97 890
d121a5d2
CW		 891 return intel_sdvo_set_value(intel_sdvo,
892 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 893 &tx_rate, 1);
e2f0ba97
JB		 894}
895
32aad86f 896static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 897{
ce6feabd 898 struct intel_sdvo_tv_format format;
40039750 899 uint32_t format_map;
ce6feabd 900
40039750 901 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 902 memset(&format, 0, sizeof(format));
32aad86f 903 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 904
32aad86f
CW		 905 BUILD_BUG_ON(sizeof(format) != 6);
906 return intel_sdvo_set_value(intel_sdvo,
907 SDVO_CMD_SET_TV_FORMAT,
908 &format, sizeof(format));
7026d4ac
ZW		 909}
910
32aad86f
CW		 911static bool
912intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
913 struct drm_display_mode *mode)
e2f0ba97 914{
32aad86f 915 struct intel_sdvo_dtd output_dtd;
79e53945 916
32aad86f
CW		 917 if (!intel_sdvo_set_target_output(intel_sdvo,
918 intel_sdvo->attached_output))
919 return false;
e2f0ba97 920
32aad86f
CW		 921 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
922 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
923 return false;
e2f0ba97 924
32aad86f
CW		 925 return true;
926}
927
928static bool
929intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
930 struct drm_display_mode *mode,
931 struct drm_display_mode *adjusted_mode)
932{
32aad86f
CW		 933 /* Reset the input timing to the screen. Assume always input 0. */
934 if (!intel_sdvo_set_target_input(intel_sdvo))
935 return false;
e2f0ba97 936
32aad86f
CW		 937 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
938 mode->clock / 10,
939 mode->hdisplay,
940 mode->vdisplay))
941 return false;
e2f0ba97 942
32aad86f 943 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 944 &intel_sdvo->input_dtd))
32aad86f 945 return false;
e2f0ba97 946
6c9547ff 947 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 948
32aad86f
CW		 949 return true;
950}
12682a97 951
32aad86f
CW		 952static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
953 struct drm_display_mode *mode,
954 struct drm_display_mode *adjusted_mode)
955{
890f3359 956 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 957 int multiplier;
12682a97 958
32aad86f
CW		 959 /* We need to construct preferred input timings based on our
960 * output timings. To do that, we have to set the output
961 * timings, even though this isn't really the right place in
962 * the sequence to do it. Oh well.
963 */
964 if (intel_sdvo->is_tv) {
965 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
966 return false;
12682a97 967
c74696b9
PR		 968 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
969 mode,
970 adjusted_mode);
ea5b213a 971 } else if (intel_sdvo->is_lvds) {
32aad86f 972 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 973 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 974 return false;
12682a97 975
c74696b9
PR		 976 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
977 mode,
978 adjusted_mode);
e2f0ba97 979 }
32aad86f
CW		 980
981 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 982 * SDVO device will factor out the multiplier during mode_set.
32aad86f 983 */
6c9547ff
CW		 984 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
985 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 986
e2f0ba97
JB		 987 return true;
988}
989
990static void intel_sdvo_mode_set(struct drm_encoder *encoder,
991 struct drm_display_mode *mode,
992 struct drm_display_mode *adjusted_mode)
993{
994 struct drm_device *dev = encoder->dev;
995 struct drm_i915_private *dev_priv = dev->dev_private;
996 struct drm_crtc *crtc = encoder->crtc;
997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 998 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 999 u32 sdvox;
e2f0ba97
JB		 1000 struct intel_sdvo_in_out_map in_out;
1001 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 1002 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1003 int rate;
e2f0ba97
JB		 1004
1005 if (!mode)
1006 return;
1007
1008 /* First, set the input mapping for the first input to our controlled
1009 * output. This is only correct if we're a single-input device, in
1010 * which case the first input is the output from the appropriate SDVO
1011 * channel on the motherboard. In a two-input device, the first input
1012 * will be SDVOB and the second SDVOC.
1013 */
ea5b213a 1014 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1015 in_out.in1 = 0;
1016
c74696b9
PR		 1017 intel_sdvo_set_value(intel_sdvo,
1018 SDVO_CMD_SET_IN_OUT_MAP,
1019 &in_out, sizeof(in_out));
e2f0ba97 1020
6c9547ff
CW		 1021 /* Set the output timings to the screen */
1022 if (!intel_sdvo_set_target_output(intel_sdvo,
1023 intel_sdvo->attached_output))
1024 return;
e2f0ba97 1025
7026d4ac 1026 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1027 * adjusted_mode.
e2f0ba97 1028 */
6c9547ff
CW		 1029 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1030 input_dtd = intel_sdvo->input_dtd;
1031 } else {
e2f0ba97 1032 /* Set the output timing to the screen */
32aad86f
CW		 1033 if (!intel_sdvo_set_target_output(intel_sdvo,
1034 intel_sdvo->attached_output))
1035 return;
1036
6c9547ff 1037 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1038 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1039 }
79e53945
JB		 1040
1041 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1042 if (!intel_sdvo_set_target_input(intel_sdvo))
1043 return;
79e53945 1044
97aaf910
CW		 1045 if (intel_sdvo->has_hdmi_monitor) {
1046 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1047 intel_sdvo_set_colorimetry(intel_sdvo,
1048 SDVO_COLORIMETRY_RGB256);
1049 intel_sdvo_set_avi_infoframe(intel_sdvo);
1050 } else
1051 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1052
6c9547ff
CW		 1053 if (intel_sdvo->is_tv &&
1054 !intel_sdvo_set_tv_format(intel_sdvo))
1055 return;
e2f0ba97 1056
c74696b9 1057 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1058
6c9547ff
CW		 1059 switch (pixel_multiplier) {
1060 default:
32aad86f
CW		 1061 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1062 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1063 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1064 }
32aad86f
CW		 1065 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1066 return;
79e53945
JB		 1067
1068 /* Set the SDVO control regs. */
a6c45cf0 1069 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1070 /* The real mode polarity is set by the SDVO commands, using
1071 * struct intel_sdvo_dtd. */
1072 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1073 if (intel_sdvo->is_hdmi)
1074 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1075 if (INTEL_INFO(dev)->gen < 5)
1076 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1077 } else {
6c9547ff 1078 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1079 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1080 case SDVOB:
1081 sdvox &= SDVOB_PRESERVE_MASK;
1082 break;
1083 case SDVOC:
1084 sdvox &= SDVOC_PRESERVE_MASK;
1085 break;
1086 }
1087 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1088 }
3573c410
PZ		 1089
1090 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1091 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1092 else
1093 sdvox |= TRANSCODER(intel_crtc->pipe);
1094
da79de97 1095 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1096 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1097
a6c45cf0 1098 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1099 /* done in crtc_mode_set as the dpll_md reg must be written early */
1100 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1101 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1102 } else {
6c9547ff 1103 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1104 }
1105
6714afb1
CW		 1106 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1107 INTEL_INFO(dev)->gen < 5)
12682a97 1108 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1109 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1110}
1111
1112static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1113{
1114 struct drm_device *dev = encoder->dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1116 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1117 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1118 u32 temp;
1119
1120 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1121 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1122 if (0)
ea5b213a 1123 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1124
1125 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1126 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1127 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1128 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1129 }
1130 }
1131 } else {
1132 bool input1, input2;
1133 int i;
1134 u8 status;
1135
ea5b213a 1136 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1137 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1138 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1139 for (i = 0; i < 2; i++)
9d0498a2 1140 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1141
32aad86f 1142 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1143 /* Warn if the device reported failure to sync.
1144 * A lot of SDVO devices fail to notify of sync, but it's
1145 * a given it the status is a success, we succeeded.
1146 */
1147 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1148 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1149 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1150 }
1151
1152 if (0)
ea5b213a
CW		 1153 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1154 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1155 }
1156 return;
1157}
1158
79e53945
JB		 1159static int intel_sdvo_mode_valid(struct drm_connector *connector,
1160 struct drm_display_mode *mode)
1161{
df0e9248 1162 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1163
1164 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1165 return MODE_NO_DBLESCAN;
1166
ea5b213a 1167 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1168 return MODE_CLOCK_LOW;
1169
ea5b213a 1170 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1171 return MODE_CLOCK_HIGH;
1172
8545423a 1173 if (intel_sdvo->is_lvds) {
ea5b213a 1174 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1175 return MODE_PANEL;
1176
ea5b213a 1177 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1178 return MODE_PANEL;
1179 }
1180
79e53945
JB		 1181 return MODE_OK;
1182}
1183
ea5b213a 1184static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1185{
1a3665c8 1186 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1187 if (!intel_sdvo_get_value(intel_sdvo,
1188 SDVO_CMD_GET_DEVICE_CAPS,
1189 caps, sizeof(*caps)))
1190 return false;
1191
1192 DRM_DEBUG_KMS("SDVO capabilities:\n"
1193 " vendor_id: %d\n"
1194 " device_id: %d\n"
1195 " device_rev_id: %d\n"
1196 " sdvo_version_major: %d\n"
1197 " sdvo_version_minor: %d\n"
1198 " sdvo_inputs_mask: %d\n"
1199 " smooth_scaling: %d\n"
1200 " sharp_scaling: %d\n"
1201 " up_scaling: %d\n"
1202 " down_scaling: %d\n"
1203 " stall_support: %d\n"
1204 " output_flags: %d\n",
1205 caps->vendor_id,
1206 caps->device_id,
1207 caps->device_rev_id,
1208 caps->sdvo_version_major,
1209 caps->sdvo_version_minor,
1210 caps->sdvo_inputs_mask,
1211 caps->smooth_scaling,
1212 caps->sharp_scaling,
1213 caps->up_scaling,
1214 caps->down_scaling,
1215 caps->stall_support,
1216 caps->output_flags);
1217
1218 return true;
79e53945
JB		 1219}
1220
cc68c81a 1221static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945
JB		 1222{
1223 u8 response[2];
79e53945 1224
32aad86f
CW		 1225 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1226 &response, 2) && response[0];
79e53945
JB		 1227}
1228
cc68c81a 1229static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1230{
cc68c81a 1231 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1232
cc68c81a 1233 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1234}
1235
fb7a46f3 1236static bool
ea5b213a 1237intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1238{
bc65212c 1239 /* Is there more than one type of output? */
2294488d 1240 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1241}
1242
f899fc64 1243static struct edid *
e957d772 1244intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1245{
e957d772
CW		 1246 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1247 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1248}
1249
ff482d83
CW		 1250/* Mac mini hack -- use the same DDC as the analog connector */
1251static struct edid *
1252intel_sdvo_get_analog_edid(struct drm_connector *connector)
1253{
f899fc64 1254 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1255
0c1dab89
CW		 1256 return drm_get_edid(connector,
1257 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
ff482d83
CW		 1258}
1259
2b8d33f7 1260enum drm_connector_status
8bf38485 1261intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1262{
df0e9248 1263 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1264 enum drm_connector_status status;
1265 struct edid *edid;
9dff6af8 1266
e957d772 1267 edid = intel_sdvo_get_edid(connector);
57cdaf90 1268
ea5b213a 1269 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1270 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1271
7c3f0a27
ZY		 1272 /*
1273 * Don't use the 1 as the argument of DDC bus switch to get
1274 * the EDID. It is used for SDVO SPD ROM.
1275 */
9d1a903d 1276 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1277 intel_sdvo->ddc_bus = ddc;
1278 edid = intel_sdvo_get_edid(connector);
1279 if (edid)
7c3f0a27 1280 break;
7c3f0a27 1281 }
e957d772
CW		 1282 /*
1283 * If we found the EDID on the other bus,
1284 * assume that is the correct DDC bus.
1285 */
1286 if (edid == NULL)
1287 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1288 }
9d1a903d
CW		 1289
1290 /*
1291 * When there is no edid and no monitor is connected with VGA
1292 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1293 */
ff482d83
CW		 1294 if (edid == NULL)
1295 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1296
2f551c84 1297 status = connector_status_unknown;
9dff6af8 1298 if (edid != NULL) {
149c36a3 1299 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1300 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1301 status = connector_status_connected;
da79de97
CW		 1302 if (intel_sdvo->is_hdmi) {
1303 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1304 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1305 }
13946743
CW		 1306 } else
1307 status = connector_status_disconnected;
149c36a3 1308 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1309 kfree(edid);
1310 }
7f36e7ed
CW		 1311
1312 if (status == connector_status_connected) {
1313 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1314 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1315 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1316 }
1317
2b8d33f7 1318 return status;
9dff6af8
ML		 1319}
1320
52220085
CW		 1321static bool
1322intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1323 struct edid *edid)
1324{
1325 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1326 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1327
1328 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1329 connector_is_digital, monitor_is_digital);
1330 return connector_is_digital == monitor_is_digital;
1331}
1332
7b334fcb 1333static enum drm_connector_status
930a9e28 1334intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1335{
fb7a46f3 1336 uint16_t response;
df0e9248 1337 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1338 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1339 enum drm_connector_status ret;
79e53945 1340
32aad86f 1341 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1342 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1343 return connector_status_unknown;
ba84cd1f
CW		 1344
1345 /* add 30ms delay when the output type might be TV */
1346 if (intel_sdvo->caps.output_flags &
1347 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
d09c23de 1348 mdelay(30);
ba84cd1f 1349
32aad86f
CW		 1350 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1351 return connector_status_unknown;
79e53945 1352
e957d772
CW		 1353 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1354 response & 0xff, response >> 8,
1355 intel_sdvo_connector->output_flag);
e2f0ba97 1356
fb7a46f3 1357 if (response == 0)
79e53945 1358 return connector_status_disconnected;
fb7a46f3 1359
ea5b213a 1360 intel_sdvo->attached_output = response;
14571b4c 1361
97aaf910
CW		 1362 intel_sdvo->has_hdmi_monitor = false;
1363 intel_sdvo->has_hdmi_audio = false;
1364
615fb93f 1365 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1366 ret = connector_status_disconnected;
13946743 1367 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1368 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1369 else {
1370 struct edid *edid;
1371
1372 /* if we have an edid check it matches the connection */
1373 edid = intel_sdvo_get_edid(connector);
1374 if (edid == NULL)
1375 edid = intel_sdvo_get_analog_edid(connector);
1376 if (edid != NULL) {
52220085
CW		 1377 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1378 edid))
13946743 1379 ret = connector_status_connected;
52220085
CW		 1380 else
1381 ret = connector_status_disconnected;
1382
13946743
CW		 1383 connector->display_info.raw_edid = NULL;
1384 kfree(edid);
1385 } else
1386 ret = connector_status_connected;
1387 }
14571b4c
ZW		 1388
1389 /* May update encoder flag for like clock for SDVO TV, etc.*/
1390 if (ret == connector_status_connected) {
ea5b213a
CW		 1391 intel_sdvo->is_tv = false;
1392 intel_sdvo->is_lvds = false;
1393 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1394
1395 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1396 intel_sdvo->is_tv = true;
1397 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1398 }
1399 if (response & SDVO_LVDS_MASK)
8545423a 1400 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1401 }
14571b4c
ZW		 1402
1403 return ret;
79e53945
JB		 1404}
1405
e2f0ba97 1406static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1407{
ff482d83 1408 struct edid *edid;
79e53945
JB		 1409
1410 /* set the bus switch and get the modes */
e957d772 1411 edid = intel_sdvo_get_edid(connector);
79e53945 1412
57cdaf90
KP		 1413 /*
1414 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1415 * link between analog and digital outputs. So, if the regular SDVO
1416 * DDC fails, check to see if the analog output is disconnected, in
1417 * which case we'll look there for the digital DDC data.
e2f0ba97 1418 */
f899fc64
CW		 1419 if (edid == NULL)
1420 edid = intel_sdvo_get_analog_edid(connector);
1421
ff482d83 1422 if (edid != NULL) {
52220085
CW		 1423 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1424 edid)) {
0c1dab89
CW		 1425 drm_mode_connector_update_edid_property(connector, edid);
1426 drm_add_edid_modes(connector, edid);
1427 }
13946743 1428
ff482d83
CW		 1429 connector->display_info.raw_edid = NULL;
1430 kfree(edid);
e2f0ba97 1431 }
e2f0ba97
JB		 1432}
1433
1434/*
1435 * Set of SDVO TV modes.
1436 * Note! This is in reply order (see loop in get_tv_modes).
1437 * XXX: all 60Hz refresh?
1438 */
b1f559ec 1439static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1440 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1441 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1443 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1444 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1446 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1447 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1449 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1450 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1452 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1453 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1455 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1456 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1458 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1459 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1461 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1462 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1464 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1465 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1467 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1468 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1470 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1471 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1473 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1474 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1476 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1477 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1479 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1480 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1482 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1483 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1485 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1486 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1488 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1489 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1491 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1492 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1494 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1495 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1497};
1498
1499static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1500{
df0e9248 1501 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1502 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1503 uint32_t reply = 0, format_map = 0;
1504 int i;
e2f0ba97
JB		 1505
1506 /* Read the list of supported input resolutions for the selected TV
1507 * format.
1508 */
40039750 1509 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1510 memcpy(&tv_res, &format_map,
32aad86f 1511 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1512
32aad86f
CW		 1513 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1514 return;
ce6feabd 1515
32aad86f 1516 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1517 if (!intel_sdvo_write_cmd(intel_sdvo,
1518 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1519 &tv_res, sizeof(tv_res)))
1520 return;
1521 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1522 return;
1523
1524 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1525 if (reply & (1 << i)) {
1526 struct drm_display_mode *nmode;
1527 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1528 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1529 if (nmode)
1530 drm_mode_probed_add(connector, nmode);
1531 }
e2f0ba97
JB		 1532}
1533
7086c87f
ML		 1534static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1535{
df0e9248 1536 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1537 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1538 struct drm_display_mode *newmode;
7086c87f
ML		 1539
1540 /*
1541 * Attempt to get the mode list from DDC.
1542 * Assume that the preferred modes are
1543 * arranged in priority order.
1544 */
f899fc64 1545 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1546 if (list_empty(&connector->probed_modes) == false)
12682a97 1547 goto end;
7086c87f
ML		 1548
1549 /* Fetch modes from VBT */
1550 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1551 newmode = drm_mode_duplicate(connector->dev,
1552 dev_priv->sdvo_lvds_vbt_mode);
1553 if (newmode != NULL) {
1554 /* Guarantee the mode is preferred */
1555 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1556 DRM_MODE_TYPE_DRIVER);
1557 drm_mode_probed_add(connector, newmode);
1558 }
1559 }
12682a97 1560
1561end:
1562 list_for_each_entry(newmode, &connector->probed_modes, head) {
1563 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1564 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1565 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1566
1567 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1568 0);
1569
8545423a 1570 intel_sdvo->is_lvds = true;
12682a97 1571 break;
1572 }
1573 }
1574
7086c87f
ML		 1575}
1576
e2f0ba97
JB		 1577static int intel_sdvo_get_modes(struct drm_connector *connector)
1578{
615fb93f 1579 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1580
615fb93f 1581 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1582 intel_sdvo_get_tv_modes(connector);
615fb93f 1583 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1584 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1585 else
1586 intel_sdvo_get_ddc_modes(connector);
1587
32aad86f 1588 return !list_empty(&connector->probed_modes);
79e53945
JB		 1589}
1590
fcc8d672
CW		 1591static void
1592intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1593{
615fb93f 1594 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1595 struct drm_device *dev = connector->dev;
1596
c5521706
CW		 1597 if (intel_sdvo_connector->left)
1598 drm_property_destroy(dev, intel_sdvo_connector->left);
1599 if (intel_sdvo_connector->right)
1600 drm_property_destroy(dev, intel_sdvo_connector->right);
1601 if (intel_sdvo_connector->top)
1602 drm_property_destroy(dev, intel_sdvo_connector->top);
1603 if (intel_sdvo_connector->bottom)
1604 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1605 if (intel_sdvo_connector->hpos)
1606 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1607 if (intel_sdvo_connector->vpos)
1608 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1609 if (intel_sdvo_connector->saturation)
1610 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1611 if (intel_sdvo_connector->contrast)
1612 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1613 if (intel_sdvo_connector->hue)
1614 drm_property_destroy(dev, intel_sdvo_connector->hue);
1615 if (intel_sdvo_connector->sharpness)
1616 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1617 if (intel_sdvo_connector->flicker_filter)
1618 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1619 if (intel_sdvo_connector->flicker_filter_2d)
1620 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1621 if (intel_sdvo_connector->flicker_filter_adaptive)
1622 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1623 if (intel_sdvo_connector->tv_luma_filter)
1624 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1625 if (intel_sdvo_connector->tv_chroma_filter)
1626 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1627 if (intel_sdvo_connector->dot_crawl)
1628 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1629 if (intel_sdvo_connector->brightness)
1630 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1631}
1632
79e53945
JB		 1633static void intel_sdvo_destroy(struct drm_connector *connector)
1634{
615fb93f 1635 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1636
c5521706 1637 if (intel_sdvo_connector->tv_format)
ce6feabd 1638 drm_property_destroy(connector->dev,
c5521706 1639 intel_sdvo_connector->tv_format);
b9219c5e 1640
d2a82a6f 1641 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1642 drm_sysfs_connector_remove(connector);
1643 drm_connector_cleanup(connector);
d2a82a6f 1644 kfree(connector);
79e53945
JB		 1645}
1646
1aad7ac0
CW		 1647static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1648{
1649 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1650 struct edid *edid;
1651 bool has_audio = false;
1652
1653 if (!intel_sdvo->is_hdmi)
1654 return false;
1655
1656 edid = intel_sdvo_get_edid(connector);
1657 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1658 has_audio = drm_detect_monitor_audio(edid);
1659
1660 return has_audio;
1661}
1662
ce6feabd
ZY		 1663static int
1664intel_sdvo_set_property(struct drm_connector *connector,
1665 struct drm_property *property,
1666 uint64_t val)
1667{
df0e9248 1668 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1669 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1670 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1671 uint16_t temp_value;
32aad86f
CW		 1672 uint8_t cmd;
1673 int ret;
ce6feabd
ZY		 1674
1675 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1676 if (ret)
1677 return ret;
ce6feabd 1678
3f43c48d 1679 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1680 int i = val;
1681 bool has_audio;
1682
1683 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1684 return 0;
1685
1aad7ac0 1686 intel_sdvo_connector->force_audio = i;
7f36e7ed 1687
c3e5f67b 1688 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1689 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1690 else
c3e5f67b 1691 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1692
1aad7ac0 1693 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1694 return 0;
7f36e7ed 1695
1aad7ac0 1696 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1697 goto done;
1698 }
1699
e953fd7b
CW		 1700 if (property == dev_priv->broadcast_rgb_property) {
1701 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1702 return 0;
1703
e953fd7b 1704 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1705 goto done;
1706 }
1707
c5521706
CW		 1708#define CHECK_PROPERTY(name, NAME) \
1709 if (intel_sdvo_connector->name == property) { \
1710 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1711 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1712 cmd = SDVO_CMD_SET_##NAME; \
1713 intel_sdvo_connector->cur_##name = temp_value; \
1714 goto set_value; \
1715 }
1716
1717 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1718 if (val >= TV_FORMAT_NUM)
1719 return -EINVAL;
1720
40039750 1721 if (intel_sdvo->tv_format_index ==
615fb93f 1722 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1723 return 0;
ce6feabd 1724
40039750 1725 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1726 goto done;
32aad86f 1727 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1728 temp_value = val;
c5521706 1729 if (intel_sdvo_connector->left == property) {
b9219c5e 1730 drm_connector_property_set_value(connector,
c5521706 1731 intel_sdvo_connector->right, val);
615fb93f 1732 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1733 return 0;
b9219c5e 1734
615fb93f
CW		 1735 intel_sdvo_connector->left_margin = temp_value;
1736 intel_sdvo_connector->right_margin = temp_value;
1737 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1738 intel_sdvo_connector->left_margin;
b9219c5e 1739 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1740 goto set_value;
1741 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1742 drm_connector_property_set_value(connector,
c5521706 1743 intel_sdvo_connector->left, val);
615fb93f 1744 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1745 return 0;
b9219c5e 1746
615fb93f
CW		 1747 intel_sdvo_connector->left_margin = temp_value;
1748 intel_sdvo_connector->right_margin = temp_value;
1749 temp_value = intel_sdvo_connector->max_hscan -
1750 intel_sdvo_connector->left_margin;
b9219c5e 1751 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1752 goto set_value;
1753 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1754 drm_connector_property_set_value(connector,
c5521706 1755 intel_sdvo_connector->bottom, val);
615fb93f 1756 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1757 return 0;
b9219c5e 1758
615fb93f
CW		 1759 intel_sdvo_connector->top_margin = temp_value;
1760 intel_sdvo_connector->bottom_margin = temp_value;
1761 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1762 intel_sdvo_connector->top_margin;
b9219c5e 1763 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1764 goto set_value;
1765 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1766 drm_connector_property_set_value(connector,
c5521706 1767 intel_sdvo_connector->top, val);
615fb93f 1768 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1769 return 0;
1770
615fb93f
CW		 1771 intel_sdvo_connector->top_margin = temp_value;
1772 intel_sdvo_connector->bottom_margin = temp_value;
1773 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1774 intel_sdvo_connector->top_margin;
b9219c5e 1775 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1776 goto set_value;
1777 }
1778 CHECK_PROPERTY(hpos, HPOS)
1779 CHECK_PROPERTY(vpos, VPOS)
1780 CHECK_PROPERTY(saturation, SATURATION)
1781 CHECK_PROPERTY(contrast, CONTRAST)
1782 CHECK_PROPERTY(hue, HUE)
1783 CHECK_PROPERTY(brightness, BRIGHTNESS)
1784 CHECK_PROPERTY(sharpness, SHARPNESS)
1785 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1786 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1787 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1788 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1789 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1790 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1791 }
b9219c5e 1792
c5521706 1793 return -EINVAL; /* unknown property */
b9219c5e 1794
c5521706
CW		 1795set_value:
1796 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1797 return -EIO;
b9219c5e 1798
b9219c5e 1799
c5521706 1800done:
df0e9248
CW		 1801 if (intel_sdvo->base.base.crtc) {
1802 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1803 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1804 crtc->y, crtc->fb);
1805 }
1806
32aad86f 1807 return 0;
c5521706 1808#undef CHECK_PROPERTY
ce6feabd
ZY		 1809}
1810
79e53945
JB		 1811static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1812 .dpms = intel_sdvo_dpms,
1813 .mode_fixup = intel_sdvo_mode_fixup,
1814 .prepare = intel_encoder_prepare,
1815 .mode_set = intel_sdvo_mode_set,
1816 .commit = intel_encoder_commit,
1817};
1818
1819static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1820 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1821 .detect = intel_sdvo_detect,
1822 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1823 .set_property = intel_sdvo_set_property,
79e53945
JB		 1824 .destroy = intel_sdvo_destroy,
1825};
1826
1827static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1828 .get_modes = intel_sdvo_get_modes,
1829 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1830 .best_encoder = intel_best_encoder,
79e53945
JB		 1831};
1832
b358d0a6 1833static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1834{
890f3359 1835 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1836
ea5b213a 1837 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1838 drm_mode_destroy(encoder->dev,
ea5b213a 1839 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1840
e957d772 1841 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1842 intel_encoder_destroy(encoder);
79e53945
JB		 1843}
1844
1845static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1846 .destroy = intel_sdvo_enc_destroy,
1847};
1848
b66d8424
CW		 1849static void
1850intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1851{
1852 uint16_t mask = 0;
1853 unsigned int num_bits;
1854
1855 /* Make a mask of outputs less than or equal to our own priority in the
1856 * list.
1857 */
1858 switch (sdvo->controlled_output) {
1859 case SDVO_OUTPUT_LVDS1:
1860 mask |= SDVO_OUTPUT_LVDS1;
1861 case SDVO_OUTPUT_LVDS0:
1862 mask |= SDVO_OUTPUT_LVDS0;
1863 case SDVO_OUTPUT_TMDS1:
1864 mask |= SDVO_OUTPUT_TMDS1;
1865 case SDVO_OUTPUT_TMDS0:
1866 mask |= SDVO_OUTPUT_TMDS0;
1867 case SDVO_OUTPUT_RGB1:
1868 mask |= SDVO_OUTPUT_RGB1;
1869 case SDVO_OUTPUT_RGB0:
1870 mask |= SDVO_OUTPUT_RGB0;
1871 break;
1872 }
1873
1874 /* Count bits to find what number we are in the priority list. */
1875 mask &= sdvo->caps.output_flags;
1876 num_bits = hweight16(mask);
1877 /* If more than 3 outputs, default to DDC bus 3 for now. */
1878 if (num_bits > 3)
1879 num_bits = 3;
1880
1881 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1882 sdvo->ddc_bus = 1 << num_bits;
1883}
79e53945 1884
e2f0ba97
JB		 1885/**
1886 * Choose the appropriate DDC bus for control bus switch command for this
1887 * SDVO output based on the controlled output.
1888 *
1889 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1890 * outputs, then LVDS outputs.
1891 */
1892static void
b1083333 1893intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1894 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1895{
b1083333 1896 struct sdvo_device_mapping *mapping;
e2f0ba97 1897
eef4eacb 1898 if (sdvo->is_sdvob)
b1083333
AJ		 1899 mapping = &(dev_priv->sdvo_mappings[0]);
1900 else
1901 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1902
b66d8424
CW		 1903 if (mapping->initialized)
1904 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1905 else
1906 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1907}
1908
e957d772
CW		 1909static void
1910intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1911 struct intel_sdvo *sdvo, u32 reg)
1912{
1913 struct sdvo_device_mapping *mapping;
46eb3036 1914 u8 pin;
e957d772 1915
eef4eacb 1916 if (sdvo->is_sdvob)
e957d772
CW		 1917 mapping = &dev_priv->sdvo_mappings[0];
1918 else
1919 mapping = &dev_priv->sdvo_mappings[1];
1920
1921 pin = GMBUS_PORT_DPB;
46eb3036 1922 if (mapping->initialized)
e957d772 1923 pin = mapping->i2c_pin;
e957d772 1924
63abf3ed
CW		 1925 if (pin < GMBUS_NUM_PORTS) {
1926 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
d5090b96 1927 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1928 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1929 } else {
63abf3ed 1930 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
46eb3036 1931 }
e957d772
CW		 1932}
1933
e2f0ba97 1934static bool
e27d8538 1935intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1936{
97aaf910 1937 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1938}
1939
714605e4 1940static u8
eef4eacb 1941intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 1942{
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 struct sdvo_device_mapping *my_mapping, *other_mapping;
1945
eef4eacb 1946 if (sdvo->is_sdvob) {
714605e4 1947 my_mapping = &dev_priv->sdvo_mappings[0];
1948 other_mapping = &dev_priv->sdvo_mappings[1];
1949 } else {
1950 my_mapping = &dev_priv->sdvo_mappings[1];
1951 other_mapping = &dev_priv->sdvo_mappings[0];
1952 }
1953
1954 /* If the BIOS described our SDVO device, take advantage of it. */
1955 if (my_mapping->slave_addr)
1956 return my_mapping->slave_addr;
1957
1958 /* If the BIOS only described a different SDVO device, use the
1959 * address that it isn't using.
1960 */
1961 if (other_mapping->slave_addr) {
1962 if (other_mapping->slave_addr == 0x70)
1963 return 0x72;
1964 else
1965 return 0x70;
1966 }
1967
1968 /* No SDVO device info is found for another DVO port,
1969 * so use mapping assumption we had before BIOS parsing.
1970 */
eef4eacb 1971 if (sdvo->is_sdvob)
714605e4 1972 return 0x70;
1973 else
1974 return 0x72;
1975}
1976
14571b4c 1977static void
df0e9248
CW		 1978intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
1979 struct intel_sdvo *encoder)
14571b4c 1980{
df0e9248
CW		 1981 drm_connector_init(encoder->base.base.dev,
1982 &connector->base.base,
1983 &intel_sdvo_connector_funcs,
1984 connector->base.base.connector_type);
6070a4a9 1985
df0e9248
CW		 1986 drm_connector_helper_add(&connector->base.base,
1987 &intel_sdvo_connector_helper_funcs);
14571b4c 1988
8f4839e2 1989 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 1990 connector->base.base.doublescan_allowed = 0;
1991 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 1992
df0e9248
CW		 1993 intel_connector_attach_encoder(&connector->base, &encoder->base);
1994 drm_sysfs_connector_add(&connector->base.base);
14571b4c 1995}
6070a4a9 1996
7f36e7ed
CW		 1997static void
1998intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
1999{
2000 struct drm_device *dev = connector->base.base.dev;
2001
3f43c48d 2002 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2003 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2004 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2005}
2006
fb7a46f3 2007static bool
ea5b213a 2008intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2009{
4ef69c7a 2010 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2011 struct drm_connector *connector;
cc68c81a 2012 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2013 struct intel_connector *intel_connector;
615fb93f 2014 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2015
615fb93f
CW		 2016 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2017 if (!intel_sdvo_connector)
14571b4c
ZW		 2018 return false;
2019
14571b4c 2020 if (device == 0) {
ea5b213a 2021 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2022 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2023 } else if (device == 1) {
ea5b213a 2024 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2025 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2026 }
2027
615fb93f 2028 intel_connector = &intel_sdvo_connector->base;
14571b4c 2029 connector = &intel_connector->base;
cc68c81a
SF		 2030 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2031 connector->polled = DRM_CONNECTOR_POLL_HPD;
2032 intel_sdvo->hotplug_active[0] |= 1 << device;
2033 /* Some SDVO devices have one-shot hotplug interrupts.
2034 * Ensure that they get re-enabled when an interrupt happens.
2035 */
2036 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2037 intel_sdvo_enable_hotplug(intel_encoder);
2038 }
2039 else
2040 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2041 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2042 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2043
e27d8538 2044 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2045 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2046 intel_sdvo->is_hdmi = true;
14571b4c 2047 }
ea5b213a
CW		 2048 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2049 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2050
df0e9248 2051 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2052 if (intel_sdvo->is_hdmi)
2053 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2054
2055 return true;
2056}
2057
2058static bool
ea5b213a 2059intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2060{
4ef69c7a
CW		 2061 struct drm_encoder *encoder = &intel_sdvo->base.base;
2062 struct drm_connector *connector;
2063 struct intel_connector *intel_connector;
2064 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2065
615fb93f
CW		 2066 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2067 if (!intel_sdvo_connector)
2068 return false;
14571b4c 2069
615fb93f 2070 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2071 connector = &intel_connector->base;
2072 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2073 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2074
4ef69c7a
CW		 2075 intel_sdvo->controlled_output |= type;
2076 intel_sdvo_connector->output_flag = type;
14571b4c 2077
4ef69c7a
CW		 2078 intel_sdvo->is_tv = true;
2079 intel_sdvo->base.needs_tv_clock = true;
2080 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2081
df0e9248 2082 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2083
4ef69c7a 2084 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2085 goto err;
14571b4c 2086
4ef69c7a 2087 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2088 goto err;
14571b4c 2089
4ef69c7a 2090 return true;
32aad86f
CW		 2091
2092err:
123d5c01 2093 intel_sdvo_destroy(connector);
32aad86f 2094 return false;
14571b4c
ZW		 2095}
2096
2097static bool
ea5b213a 2098intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2099{
4ef69c7a
CW		 2100 struct drm_encoder *encoder = &intel_sdvo->base.base;
2101 struct drm_connector *connector;
2102 struct intel_connector *intel_connector;
2103 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2104
615fb93f
CW		 2105 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2106 if (!intel_sdvo_connector)
2107 return false;
14571b4c 2108
615fb93f 2109 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2110 connector = &intel_connector->base;
eb1f8e4f 2111 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2112 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2113 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2114
2115 if (device == 0) {
2116 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2117 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2118 } else if (device == 1) {
2119 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2120 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2121 }
2122
2123 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2124 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2125
df0e9248
CW		 2126 intel_sdvo_connector_init(intel_sdvo_connector,
2127 intel_sdvo);
4ef69c7a 2128 return true;
14571b4c
ZW		 2129}
2130
2131static bool
ea5b213a 2132intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2133{
4ef69c7a
CW		 2134 struct drm_encoder *encoder = &intel_sdvo->base.base;
2135 struct drm_connector *connector;
2136 struct intel_connector *intel_connector;
2137 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2138
615fb93f
CW		 2139 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2140 if (!intel_sdvo_connector)
2141 return false;
14571b4c 2142
615fb93f
CW		 2143 intel_connector = &intel_sdvo_connector->base;
2144 connector = &intel_connector->base;
4ef69c7a
CW		 2145 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2146 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2147
2148 if (device == 0) {
2149 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2150 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2151 } else if (device == 1) {
2152 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2153 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2154 }
2155
2156 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2157 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2158
df0e9248 2159 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2160 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2161 goto err;
2162
2163 return true;
2164
2165err:
123d5c01 2166 intel_sdvo_destroy(connector);
32aad86f 2167 return false;
14571b4c
ZW		 2168}
2169
2170static bool
ea5b213a 2171intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2172{
ea5b213a
CW		 2173 intel_sdvo->is_tv = false;
2174 intel_sdvo->base.needs_tv_clock = false;
2175 intel_sdvo->is_lvds = false;
fb7a46f3 2176
14571b4c 2177 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2178
14571b4c 2179 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2180 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2181 return false;
2182
2183 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2184 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2185 return false;
2186
2187 /* TV has no XXX1 function block */
a1f4b7ff 2188 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2189 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2190 return false;
2191
2192 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2193 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2194 return false;
fb7a46f3 2195
14571b4c 2196 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2197 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2198 return false;
2199
2200 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2201 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2202 return false;
2203
2204 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2205 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2206 return false;
2207
2208 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2209 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2210 return false;
fb7a46f3 2211
14571b4c 2212 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2213 unsigned char bytes[2];
2214
ea5b213a
CW		 2215 intel_sdvo->controlled_output = 0;
2216 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2217 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2218 SDVO_NAME(intel_sdvo),
51c8b407 2219 bytes[0], bytes[1]);
14571b4c 2220 return false;
fb7a46f3 2221 }
27f8227b 2222 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2223
14571b4c 2224 return true;
fb7a46f3 2225}
2226
32aad86f
CW		 2227static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2228 struct intel_sdvo_connector *intel_sdvo_connector,
2229 int type)
ce6feabd 2230{
4ef69c7a 2231 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2232 struct intel_sdvo_tv_format format;
2233 uint32_t format_map, i;
ce6feabd 2234
32aad86f
CW		 2235 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2236 return false;
ce6feabd 2237
1a3665c8 2238 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2239 if (!intel_sdvo_get_value(intel_sdvo,
2240 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2241 &format, sizeof(format)))
2242 return false;
ce6feabd 2243
32aad86f 2244 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2245
2246 if (format_map == 0)
32aad86f 2247 return false;
ce6feabd 2248
615fb93f 2249 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2250 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2251 if (format_map & (1 << i))
2252 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2253
2254
c5521706 2255 intel_sdvo_connector->tv_format =
32aad86f
CW		 2256 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2257 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2258 if (!intel_sdvo_connector->tv_format)
fcc8d672 2259 return false;
ce6feabd 2260
615fb93f 2261 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2262 drm_property_add_enum(
c5521706 2263 intel_sdvo_connector->tv_format, i,
40039750 2264 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2265
40039750 2266 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2267 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2268 intel_sdvo_connector->tv_format, 0);
32aad86f 2269 return true;
ce6feabd
ZY		 2270
2271}
2272
c5521706
CW		 2273#define ENHANCEMENT(name, NAME) do { \
2274 if (enhancements.name) { \
2275 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2276 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2277 return false; \
2278 intel_sdvo_connector->max_##name = data_value[0]; \
2279 intel_sdvo_connector->cur_##name = response; \
2280 intel_sdvo_connector->name = \
d9bc3c02 2281 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2282 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2283 drm_connector_attach_property(connector, \
2284 intel_sdvo_connector->name, \
2285 intel_sdvo_connector->cur_##name); \
2286 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2287 data_value[0], data_value[1], response); \
2288 } \
0206e353 2289} while (0)
c5521706
CW		 2290
2291static bool
2292intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2293 struct intel_sdvo_connector *intel_sdvo_connector,
2294 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2295{
4ef69c7a 2296 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2297 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2298 uint16_t response, data_value[2];
2299
c5521706
CW		 2300 /* when horizontal overscan is supported, Add the left/right property */
2301 if (enhancements.overscan_h) {
2302 if (!intel_sdvo_get_value(intel_sdvo,
2303 SDVO_CMD_GET_MAX_OVERSCAN_H,
2304 &data_value, 4))
2305 return false;
32aad86f 2306
c5521706
CW		 2307 if (!intel_sdvo_get_value(intel_sdvo,
2308 SDVO_CMD_GET_OVERSCAN_H,
2309 &response, 2))
2310 return false;
fcc8d672 2311
c5521706
CW		 2312 intel_sdvo_connector->max_hscan = data_value[0];
2313 intel_sdvo_connector->left_margin = data_value[0] - response;
2314 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2315 intel_sdvo_connector->left =
d9bc3c02 2316 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2317 if (!intel_sdvo_connector->left)
2318 return false;
fcc8d672 2319
c5521706
CW		 2320 drm_connector_attach_property(connector,
2321 intel_sdvo_connector->left,
2322 intel_sdvo_connector->left_margin);
fcc8d672 2323
c5521706 2324 intel_sdvo_connector->right =
d9bc3c02 2325 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2326 if (!intel_sdvo_connector->right)
2327 return false;
32aad86f 2328
c5521706
CW		 2329 drm_connector_attach_property(connector,
2330 intel_sdvo_connector->right,
2331 intel_sdvo_connector->right_margin);
2332 DRM_DEBUG_KMS("h_overscan: max %d, "
2333 "default %d, current %d\n",
2334 data_value[0], data_value[1], response);
2335 }
32aad86f 2336
c5521706
CW		 2337 if (enhancements.overscan_v) {
2338 if (!intel_sdvo_get_value(intel_sdvo,
2339 SDVO_CMD_GET_MAX_OVERSCAN_V,
2340 &data_value, 4))
2341 return false;
fcc8d672 2342
c5521706
CW		 2343 if (!intel_sdvo_get_value(intel_sdvo,
2344 SDVO_CMD_GET_OVERSCAN_V,
2345 &response, 2))
2346 return false;
32aad86f 2347
c5521706
CW		 2348 intel_sdvo_connector->max_vscan = data_value[0];
2349 intel_sdvo_connector->top_margin = data_value[0] - response;
2350 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2351 intel_sdvo_connector->top =
d9bc3c02
SH		 2352 drm_property_create_range(dev, 0,
2353 "top_margin", 0, data_value[0]);
c5521706
CW		 2354 if (!intel_sdvo_connector->top)
2355 return false;
32aad86f 2356
c5521706
CW		 2357 drm_connector_attach_property(connector,
2358 intel_sdvo_connector->top,
2359 intel_sdvo_connector->top_margin);
fcc8d672 2360
c5521706 2361 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2362 drm_property_create_range(dev, 0,
2363 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2364 if (!intel_sdvo_connector->bottom)
2365 return false;
32aad86f 2366
c5521706
CW		 2367 drm_connector_attach_property(connector,
2368 intel_sdvo_connector->bottom,
2369 intel_sdvo_connector->bottom_margin);
2370 DRM_DEBUG_KMS("v_overscan: max %d, "
2371 "default %d, current %d\n",
2372 data_value[0], data_value[1], response);
2373 }
32aad86f 2374
c5521706
CW		 2375 ENHANCEMENT(hpos, HPOS);
2376 ENHANCEMENT(vpos, VPOS);
2377 ENHANCEMENT(saturation, SATURATION);
2378 ENHANCEMENT(contrast, CONTRAST);
2379 ENHANCEMENT(hue, HUE);
2380 ENHANCEMENT(sharpness, SHARPNESS);
2381 ENHANCEMENT(brightness, BRIGHTNESS);
2382 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2383 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2384 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2385 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2386 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2387
e044218a
CW		 2388 if (enhancements.dot_crawl) {
2389 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2390 return false;
2391
2392 intel_sdvo_connector->max_dot_crawl = 1;
2393 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2394 intel_sdvo_connector->dot_crawl =
d9bc3c02 2395 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2396 if (!intel_sdvo_connector->dot_crawl)
2397 return false;
2398
e044218a
CW		 2399 drm_connector_attach_property(connector,
2400 intel_sdvo_connector->dot_crawl,
2401 intel_sdvo_connector->cur_dot_crawl);
2402 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2403 }
2404
c5521706
CW		 2405 return true;
2406}
32aad86f 2407
c5521706
CW		 2408static bool
2409intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2410 struct intel_sdvo_connector *intel_sdvo_connector,
2411 struct intel_sdvo_enhancements_reply enhancements)
2412{
4ef69c7a 2413 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2414 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2415 uint16_t response, data_value[2];
32aad86f 2416
c5521706 2417 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2418
c5521706
CW		 2419 return true;
2420}
2421#undef ENHANCEMENT
32aad86f 2422
c5521706
CW		 2423static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2424 struct intel_sdvo_connector *intel_sdvo_connector)
2425{
2426 union {
2427 struct intel_sdvo_enhancements_reply reply;
2428 uint16_t response;
2429 } enhancements;
32aad86f 2430
1a3665c8
CW		 2431 BUILD_BUG_ON(sizeof(enhancements) != 2);
2432
cf9a2f3a
CW		 2433 enhancements.response = 0;
2434 intel_sdvo_get_value(intel_sdvo,
2435 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2436 &enhancements, sizeof(enhancements));
c5521706
CW		 2437 if (enhancements.response == 0) {
2438 DRM_DEBUG_KMS("No enhancement is supported\n");
2439 return true;
b9219c5e 2440 }
32aad86f 2441
c5521706
CW		 2442 if (IS_TV(intel_sdvo_connector))
2443 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2444 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2445 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2446 else
2447 return true;
e957d772
CW		 2448}
2449
2450static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2451 struct i2c_msg *msgs,
2452 int num)
2453{
2454 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2455
e957d772
CW		 2456 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2457 return -EIO;
2458
2459 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2460}
2461
2462static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2463{
2464 struct intel_sdvo *sdvo = adapter->algo_data;
2465 return sdvo->i2c->algo->functionality(sdvo->i2c);
2466}
2467
2468static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2469 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2470 .functionality = intel_sdvo_ddc_proxy_func
2471};
2472
2473static bool
2474intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2475 struct drm_device *dev)
2476{
2477 sdvo->ddc.owner = THIS_MODULE;
2478 sdvo->ddc.class = I2C_CLASS_DDC;
2479 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2480 sdvo->ddc.dev.parent = &dev->pdev->dev;
2481 sdvo->ddc.algo_data = sdvo;
2482 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2483
2484 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2485}
2486
eef4eacb 2487bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2488{
b01f2c3a 2489 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2490 struct intel_encoder *intel_encoder;
ea5b213a 2491 struct intel_sdvo *intel_sdvo;
79e53945 2492 int i;
79e53945 2493
ea5b213a
CW		 2494 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2495 if (!intel_sdvo)
7d57382e 2496 return false;
79e53945 2497
56184e3d 2498 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2499 intel_sdvo->is_sdvob = is_sdvob;
2500 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2501 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2502 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2503 kfree(intel_sdvo);
2504 return false;
2505 }
2506
56184e3d 2507 /* encoder type will be decided later */
ea5b213a 2508 intel_encoder = &intel_sdvo->base;
21d40d37 2509 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2510 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2511
79e53945
JB		 2512 /* Read the regs to test if we can talk to the device */
2513 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2514 u8 byte;
2515
2516 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2517 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2518 SDVO_NAME(intel_sdvo));
f899fc64 2519 goto err;
79e53945
JB		 2520 }
2521 }
2522
eef4eacb 2523 if (intel_sdvo->is_sdvob)
b01f2c3a 2524 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2525 else
b01f2c3a 2526 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2527
4ef69c7a 2528 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2529
af901ca1 2530 /* In default case sdvo lvds is false */
32aad86f 2531 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2532 goto err;
79e53945 2533
cc68c81a
SF		 2534 /* Set up hotplug command - note paranoia about contents of reply.
2535 * We assume that the hardware is in a sane state, and only touch
2536 * the bits we think we understand.
2537 */
2538 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2539 &intel_sdvo->hotplug_active, 2);
2540 intel_sdvo->hotplug_active[0] &= ~0x3;
2541
ea5b213a
CW		 2542 if (intel_sdvo_output_setup(intel_sdvo,
2543 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2544 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2545 SDVO_NAME(intel_sdvo));
f899fc64 2546 goto err;
79e53945
JB		 2547 }
2548
ea5b213a 2549 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2550
79e53945 2551 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2552 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2553 goto err;
79e53945 2554
32aad86f
CW		 2555 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2556 &intel_sdvo->pixel_clock_min,
2557 &intel_sdvo->pixel_clock_max))
f899fc64 2558 goto err;
79e53945 2559
8a4c47f3 2560 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2561 "clock range %dMHz - %dMHz, "
2562 "input 1: %c, input 2: %c, "
2563 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2564 SDVO_NAME(intel_sdvo),
2565 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2566 intel_sdvo->caps.device_rev_id,
2567 intel_sdvo->pixel_clock_min / 1000,
2568 intel_sdvo->pixel_clock_max / 1000,
2569 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2570 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2571 /* check currently supported outputs */
ea5b213a 2572 intel_sdvo->caps.output_flags &
79e53945 2573 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2574 intel_sdvo->caps.output_flags &
79e53945 2575 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2576 return true;
79e53945 2577
f899fc64 2578err:
373a3cf7 2579 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2580 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2581 kfree(intel_sdvo);
79e53945 2582
7d57382e 2583 return false;
79e53945 2584}
Linux kernel - Deliverables
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