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drm/i915: convert DVO driver to new encoder/connector structure
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
29#include <linux/delay.h>
30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "intel_drv.h"
2b8d33f7 34#include "drm_edid.h"
79e53945
JB		 35#include "i915_drm.h"
36#include "i915_drv.h"
37#include "intel_sdvo_regs.h"
6070a4a9 38#include <linux/dmi.h>
79e53945 39
ce6feabd
ZY		 40static char *tv_format_names[] = {
41 "NTSC_M" , "NTSC_J" , "NTSC_443",
42 "PAL_B" , "PAL_D" , "PAL_G" ,
43 "PAL_H" , "PAL_I" , "PAL_M" ,
44 "PAL_N" , "PAL_NC" , "PAL_60" ,
45 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
46 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
47 "SECAM_60"
48};
49
50#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
51
79e53945 52struct intel_sdvo_priv {
f9c10a9b 53 u8 slave_addr;
e2f0ba97
JB		 54
55 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 56 int sdvo_reg;
79e53945 57
e2f0ba97
JB		 58 /* Active outputs controlled by this SDVO output */
59 uint16_t controlled_output;
79e53945 60
e2f0ba97
JB		 61 /*
62 * Capabilities of the SDVO device returned by
63 * i830_sdvo_get_capabilities()
64 */
79e53945 65 struct intel_sdvo_caps caps;
e2f0ba97
JB		 66
67 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 68 int pixel_clock_min, pixel_clock_max;
69
fb7a46f3 70 /*
71 * For multiple function SDVO device,
72 * this is for current attached outputs.
73 */
74 uint16_t attached_output;
75
e2f0ba97
JB		 76 /**
77 * This is set if we're going to treat the device as TV-out.
78 *
79 * While we have these nice friendly flags for output types that ought
80 * to decide this for us, the S-Video output on our HDMI+S-Video card
81 * shows up as RGB1 (VGA).
82 */
83 bool is_tv;
84
ce6feabd
ZY		 85 /* This is for current tv format name */
86 char *tv_format_name;
87
88 /* This contains all current supported TV format */
89 char *tv_format_supported[TV_FORMAT_NUM];
90 int format_supported_num;
91 struct drm_property *tv_format_property;
92 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
93
e2f0ba97
JB		 94 /**
95 * This is set if we treat the device as HDMI, instead of DVI.
96 */
97 bool is_hdmi;
12682a97 98
7086c87f
ML		 99 /**
100 * This is set if we detect output of sdvo device as LVDS.
101 */
102 bool is_lvds;
e2f0ba97 103
12682a97 104 /**
105 * This is sdvo flags for input timing.
106 */
107 uint8_t sdvo_flags;
108
109 /**
110 * This is sdvo fixed pannel mode pointer
111 */
112 struct drm_display_mode *sdvo_lvds_fixed_mode;
113
e2f0ba97
JB		 114 /**
115 * Returned SDTV resolutions allowed for the current format, if the
116 * device reported it.
117 */
118 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
119
e2f0ba97
JB		 120 /*
121 * supported encoding mode, used to determine whether HDMI is
122 * supported
123 */
124 struct intel_sdvo_encode encode;
125
c751ce4f 126 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 127 uint8_t ddc_bus;
128
57cdaf90
KP		 129 /* Mac mini hack -- use the same DDC as the analog connector */
130 struct i2c_adapter *analog_ddc_bus;
131
b9219c5e
ZY		 132 /* add the property for the SDVO-TV */
133 struct drm_property *left_property;
134 struct drm_property *right_property;
135 struct drm_property *top_property;
136 struct drm_property *bottom_property;
137 struct drm_property *hpos_property;
138 struct drm_property *vpos_property;
139
140 /* add the property for the SDVO-TV/LVDS */
141 struct drm_property *brightness_property;
142 struct drm_property *contrast_property;
143 struct drm_property *saturation_property;
144 struct drm_property *hue_property;
145
146 /* Add variable to record current setting for the above property */
147 u32 left_margin, right_margin, top_margin, bottom_margin;
148 /* this is to get the range of margin.*/
149 u32 max_hscan, max_vscan;
150 u32 max_hpos, cur_hpos;
151 u32 max_vpos, cur_vpos;
152 u32 cur_brightness, max_brightness;
153 u32 cur_contrast, max_contrast;
154 u32 cur_saturation, max_saturation;
155 u32 cur_hue, max_hue;
79e53945
JB		 156};
157
fb7a46f3 158static bool
21d40d37 159intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags);
fb7a46f3 160
79e53945
JB		 161/**
162 * Writes the SDVOB or SDVOC with the given value, but always writes both
163 * SDVOB and SDVOC to work around apparent hardware issues (according to
164 * comments in the BIOS).
165 */
21d40d37 166static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val)
79e53945 167{
21d40d37 168 struct drm_device *dev = intel_encoder->base.dev;
79e53945 169 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 170 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 171 u32 bval = val, cval = val;
172 int i;
173
c751ce4f 174 if (sdvo_priv->sdvo_reg == SDVOB) {
79e53945
JB		 175 cval = I915_READ(SDVOC);
176 } else {
177 bval = I915_READ(SDVOB);
178 }
179 /*
180 * Write the registers twice for luck. Sometimes,
181 * writing them only once doesn't appear to 'stick'.
182 * The BIOS does this too. Yay, magic
183 */
184 for (i = 0; i < 2; i++)
185 {
186 I915_WRITE(SDVOB, bval);
187 I915_READ(SDVOB);
188 I915_WRITE(SDVOC, cval);
189 I915_READ(SDVOC);
190 }
191}
192
21d40d37 193static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr,
79e53945
JB		 194 u8 *ch)
195{
21d40d37 196 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 197 u8 out_buf[2];
198 u8 buf[2];
199 int ret;
200
201 struct i2c_msg msgs[] = {
202 {
f9c10a9b 203 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 204 .flags = 0,
205 .len = 1,
206 .buf = out_buf,
207 },
208 {
f9c10a9b 209 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 210 .flags = I2C_M_RD,
211 .len = 1,
212 .buf = buf,
213 }
214 };
215
216 out_buf[0] = addr;
217 out_buf[1] = 0;
218
21d40d37 219 if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2)
79e53945
JB		 220 {
221 *ch = buf[0];
222 return true;
223 }
224
8a4c47f3 225 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 226 return false;
227}
228
21d40d37 229static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr,
79e53945
JB		 230 u8 ch)
231{
21d40d37 232 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 233 u8 out_buf[2];
234 struct i2c_msg msgs[] = {
235 {
f9c10a9b 236 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 237 .flags = 0,
238 .len = 2,
239 .buf = out_buf,
240 }
241 };
242
243 out_buf[0] = addr;
244 out_buf[1] = ch;
245
21d40d37 246 if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1)
79e53945
JB		 247 {
248 return true;
249 }
250 return false;
251}
252
253#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
254/** Mapping of command numbers to names, for debug output */
005568be 255static const struct _sdvo_cmd_name {
e2f0ba97
JB		 256 u8 cmd;
257 char *name;
79e53945
JB		 258} sdvo_cmd_names[] = {
259 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
260 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
261 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
262 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
263 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
264 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
265 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
268 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
269 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
270 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
271 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
272 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
273 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
274 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
275 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
276 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
277 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
278 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
b9219c5e
ZY		 302 /* Add the op code for SDVO enhancements */
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
e2f0ba97
JB		 327 /* HDMI op code */
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 348};
349
c751ce4f
EA		 350#define SDVO_NAME(dev_priv) ((dev_priv)->sdvo_reg == SDVOB ? "SDVOB" : "SDVOC")
351#define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv)
79e53945 352
21d40d37 353static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 354 void *args, int args_len)
355{
21d40d37 356 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 357 int i;
358
8a4c47f3 359 DRM_DEBUG_KMS("%s: W: %02X ",
342dc382 360 SDVO_NAME(sdvo_priv), cmd);
79e53945 361 for (i = 0; i < args_len; i++)
342dc382 362 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 363 for (; i < 8; i++)
342dc382 364 DRM_LOG_KMS(" ");
79e53945
JB		 365 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
366 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 367 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 368 break;
369 }
370 }
371 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
342dc382 372 DRM_LOG_KMS("(%02X)", cmd);
373 DRM_LOG_KMS("\n");
79e53945 374}
79e53945 375
21d40d37 376static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 377 void *args, int args_len)
378{
379 int i;
380
21d40d37 381 intel_sdvo_debug_write(intel_encoder, cmd, args, args_len);
79e53945
JB		 382
383 for (i = 0; i < args_len; i++) {
21d40d37 384 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i,
79e53945
JB		 385 ((u8*)args)[i]);
386 }
387
21d40d37 388 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 389}
390
79e53945
JB		 391static const char *cmd_status_names[] = {
392 "Power on",
393 "Success",
394 "Not supported",
395 "Invalid arg",
396 "Pending",
397 "Target not specified",
398 "Scaling not supported"
399};
400
21d40d37 401static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder,
79e53945
JB		 402 void *response, int response_len,
403 u8 status)
404{
21d40d37 405 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
33b52961 406 int i;
79e53945 407
8a4c47f3 408 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
79e53945 409 for (i = 0; i < response_len; i++)
342dc382 410 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 411 for (; i < 8; i++)
342dc382 412 DRM_LOG_KMS(" ");
79e53945 413 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 414 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 415 else
342dc382 416 DRM_LOG_KMS("(??? %d)", status);
417 DRM_LOG_KMS("\n");
79e53945 418}
79e53945 419
21d40d37 420static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder,
79e53945
JB		 421 void *response, int response_len)
422{
423 int i;
424 u8 status;
425 u8 retry = 50;
426
427 while (retry--) {
428 /* Read the command response */
429 for (i = 0; i < response_len; i++) {
21d40d37 430 intel_sdvo_read_byte(intel_encoder,
79e53945
JB		 431 SDVO_I2C_RETURN_0 + i,
432 &((u8 *)response)[i]);
433 }
434
435 /* read the return status */
21d40d37 436 intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS,
79e53945
JB		 437 &status);
438
21d40d37 439 intel_sdvo_debug_response(intel_encoder, response, response_len,
79e53945
JB		 440 status);
441 if (status != SDVO_CMD_STATUS_PENDING)
442 return status;
443
444 mdelay(50);
445 }
446
447 return status;
448}
449
b358d0a6 450static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 451{
452 if (mode->clock >= 100000)
453 return 1;
454 else if (mode->clock >= 50000)
455 return 2;
456 else
457 return 4;
458}
459
460/**
6a304caf
ZY		 461 * Try to read the response after issuie the DDC switch command. But it
462 * is noted that we must do the action of reading response and issuing DDC
463 * switch command in one I2C transaction. Otherwise when we try to start
464 * another I2C transaction after issuing the DDC bus switch, it will be
465 * switched to the internal SDVO register.
79e53945 466 */
21d40d37 467static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder,
b358d0a6 468 u8 target)
79e53945 469{
21d40d37 470 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
6a304caf
ZY		 471 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
472 struct i2c_msg msgs[] = {
473 {
474 .addr = sdvo_priv->slave_addr >> 1,
475 .flags = 0,
476 .len = 2,
477 .buf = out_buf,
478 },
479 /* the following two are to read the response */
480 {
481 .addr = sdvo_priv->slave_addr >> 1,
482 .flags = 0,
483 .len = 1,
484 .buf = cmd_buf,
485 },
486 {
487 .addr = sdvo_priv->slave_addr >> 1,
488 .flags = I2C_M_RD,
489 .len = 1,
490 .buf = ret_value,
491 },
492 };
493
21d40d37 494 intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
6a304caf
ZY		 495 &target, 1);
496 /* write the DDC switch command argument */
21d40d37 497 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target);
6a304caf
ZY		 498
499 out_buf[0] = SDVO_I2C_OPCODE;
500 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
501 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
502 cmd_buf[1] = 0;
503 ret_value[0] = 0;
504 ret_value[1] = 0;
505
21d40d37 506 ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3);
6a304caf
ZY		 507 if (ret != 3) {
508 /* failure in I2C transfer */
509 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
510 return;
511 }
512 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
513 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
514 ret_value[0]);
515 return;
516 }
517 return;
79e53945
JB		 518}
519
21d40d37 520static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1)
79e53945
JB		 521{
522 struct intel_sdvo_set_target_input_args targets = {0};
523 u8 status;
524
525 if (target_0 && target_1)
526 return SDVO_CMD_STATUS_NOTSUPP;
527
528 if (target_1)
529 targets.target_1 = 1;
530
21d40d37 531 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets,
79e53945
JB		 532 sizeof(targets));
533
21d40d37 534 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 535
536 return (status == SDVO_CMD_STATUS_SUCCESS);
537}
538
539/**
540 * Return whether each input is trained.
541 *
542 * This function is making an assumption about the layout of the response,
543 * which should be checked against the docs.
544 */
21d40d37 545static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2)
79e53945
JB		 546{
547 struct intel_sdvo_get_trained_inputs_response response;
548 u8 status;
549
21d40d37
EA		 550 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
551 status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response));
79e53945
JB		 552 if (status != SDVO_CMD_STATUS_SUCCESS)
553 return false;
554
555 *input_1 = response.input0_trained;
556 *input_2 = response.input1_trained;
557 return true;
558}
559
21d40d37 560static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder,
79e53945
JB		 561 u16 outputs)
562{
563 u8 status;
564
21d40d37 565 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
79e53945 566 sizeof(outputs));
21d40d37 567 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 568 return (status == SDVO_CMD_STATUS_SUCCESS);
569}
570
21d40d37 571static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder,
79e53945
JB		 572 int mode)
573{
574 u8 status, state = SDVO_ENCODER_STATE_ON;
575
576 switch (mode) {
577 case DRM_MODE_DPMS_ON:
578 state = SDVO_ENCODER_STATE_ON;
579 break;
580 case DRM_MODE_DPMS_STANDBY:
581 state = SDVO_ENCODER_STATE_STANDBY;
582 break;
583 case DRM_MODE_DPMS_SUSPEND:
584 state = SDVO_ENCODER_STATE_SUSPEND;
585 break;
586 case DRM_MODE_DPMS_OFF:
587 state = SDVO_ENCODER_STATE_OFF;
588 break;
589 }
590
21d40d37 591 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
79e53945 592 sizeof(state));
21d40d37 593 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 594
595 return (status == SDVO_CMD_STATUS_SUCCESS);
596}
597
21d40d37 598static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder,
79e53945
JB		 599 int *clock_min,
600 int *clock_max)
601{
602 struct intel_sdvo_pixel_clock_range clocks;
603 u8 status;
604
21d40d37 605 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
79e53945
JB		 606 NULL, 0);
607
21d40d37 608 status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks));
79e53945
JB		 609
610 if (status != SDVO_CMD_STATUS_SUCCESS)
611 return false;
612
613 /* Convert the values from units of 10 kHz to kHz. */
614 *clock_min = clocks.min * 10;
615 *clock_max = clocks.max * 10;
616
617 return true;
618}
619
21d40d37 620static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder,
79e53945
JB		 621 u16 outputs)
622{
623 u8 status;
624
21d40d37 625 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
79e53945
JB		 626 sizeof(outputs));
627
21d40d37 628 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 629 return (status == SDVO_CMD_STATUS_SUCCESS);
630}
631
21d40d37 632static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 633 struct intel_sdvo_dtd *dtd)
634{
635 u8 status;
636
21d40d37
EA		 637 intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1));
638 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 639 if (status != SDVO_CMD_STATUS_SUCCESS)
640 return false;
641
21d40d37
EA		 642 intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2));
643 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 644 if (status != SDVO_CMD_STATUS_SUCCESS)
645 return false;
646
647 return true;
648}
649
21d40d37 650static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder,
79e53945
JB		 651 struct intel_sdvo_dtd *dtd)
652{
21d40d37 653 return intel_sdvo_set_timing(intel_encoder,
79e53945
JB		 654 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
655}
656
21d40d37 657static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder,
79e53945
JB		 658 struct intel_sdvo_dtd *dtd)
659{
21d40d37 660 return intel_sdvo_set_timing(intel_encoder,
79e53945
JB		 661 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
662}
663
e2f0ba97 664static bool
c751ce4f 665intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 666 uint16_t clock,
667 uint16_t width,
668 uint16_t height)
669{
670 struct intel_sdvo_preferred_input_timing_args args;
c751ce4f 671 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
e2f0ba97
JB		 672 uint8_t status;
673
e642c6f1 674 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 675 args.clock = clock;
676 args.width = width;
677 args.height = height;
e642c6f1 678 args.interlace = 0;
12682a97 679
680 if (sdvo_priv->is_lvds &&
681 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
682 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
683 args.scaled = 1;
684
c751ce4f
EA		 685 intel_sdvo_write_cmd(intel_encoder,
686 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
e2f0ba97 687 &args, sizeof(args));
c751ce4f 688 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 689 if (status != SDVO_CMD_STATUS_SUCCESS)
690 return false;
691
692 return true;
693}
694
c751ce4f 695static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 696 struct intel_sdvo_dtd *dtd)
697{
698 bool status;
699
c751ce4f 700 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
e2f0ba97
JB		 701 NULL, 0);
702
c751ce4f 703 status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
e2f0ba97
JB		 704 sizeof(dtd->part1));
705 if (status != SDVO_CMD_STATUS_SUCCESS)
706 return false;
707
c751ce4f 708 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
e2f0ba97
JB		 709 NULL, 0);
710
c751ce4f 711 status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
e2f0ba97
JB		 712 sizeof(dtd->part2));
713 if (status != SDVO_CMD_STATUS_SUCCESS)
714 return false;
715
716 return false;
717}
79e53945 718
21d40d37 719static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val)
79e53945
JB		 720{
721 u8 status;
722
21d40d37
EA		 723 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
724 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 725 if (status != SDVO_CMD_STATUS_SUCCESS)
726 return false;
727
728 return true;
729}
730
e2f0ba97
JB		 731static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
732 struct drm_display_mode *mode)
79e53945 733{
e2f0ba97
JB		 734 uint16_t width, height;
735 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
736 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 737
738 width = mode->crtc_hdisplay;
739 height = mode->crtc_vdisplay;
740
741 /* do some mode translations */
742 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
743 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
744
745 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
746 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
747
748 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
749 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
750
e2f0ba97
JB		 751 dtd->part1.clock = mode->clock / 10;
752 dtd->part1.h_active = width & 0xff;
753 dtd->part1.h_blank = h_blank_len & 0xff;
754 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 755 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 756 dtd->part1.v_active = height & 0xff;
757 dtd->part1.v_blank = v_blank_len & 0xff;
758 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 759 ((v_blank_len >> 8) & 0xf);
760
171a9e96 761 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 762 dtd->part2.h_sync_width = h_sync_len & 0xff;
763 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 764 (v_sync_len & 0xf);
e2f0ba97 765 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 766 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
767 ((v_sync_len & 0x30) >> 4);
768
e2f0ba97 769 dtd->part2.dtd_flags = 0x18;
79e53945 770 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 771 dtd->part2.dtd_flags |= 0x2;
79e53945 772 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 773 dtd->part2.dtd_flags |= 0x4;
774
775 dtd->part2.sdvo_flags = 0;
776 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
777 dtd->part2.reserved = 0;
778}
779
780static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
781 struct intel_sdvo_dtd *dtd)
782{
e2f0ba97
JB		 783 mode->hdisplay = dtd->part1.h_active;
784 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
785 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 786 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 787 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
788 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
789 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
790 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
791
792 mode->vdisplay = dtd->part1.v_active;
793 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
794 mode->vsync_start = mode->vdisplay;
795 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 796 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 797 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
798 mode->vsync_end = mode->vsync_start +
799 (dtd->part2.v_sync_off_width & 0xf);
800 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
801 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
802 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
803
804 mode->clock = dtd->part1.clock * 10;
805
171a9e96 806 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 807 if (dtd->part2.dtd_flags & 0x2)
808 mode->flags |= DRM_MODE_FLAG_PHSYNC;
809 if (dtd->part2.dtd_flags & 0x4)
810 mode->flags |= DRM_MODE_FLAG_PVSYNC;
811}
812
c751ce4f 813static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 814 struct intel_sdvo_encode *encode)
815{
816 uint8_t status;
817
c751ce4f
EA		 818 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
819 status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode));
e2f0ba97
JB		 820 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
821 memset(encode, 0, sizeof(*encode));
822 return false;
823 }
824
825 return true;
826}
827
c751ce4f
EA		 828static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder,
829 uint8_t mode)
e2f0ba97
JB		 830{
831 uint8_t status;
832
c751ce4f
EA		 833 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);
834 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 835
836 return (status == SDVO_CMD_STATUS_SUCCESS);
837}
838
c751ce4f 839static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 840 uint8_t mode)
841{
842 uint8_t status;
843
c751ce4f
EA		 844 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
845 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 846
847 return (status == SDVO_CMD_STATUS_SUCCESS);
848}
849
850#if 0
c751ce4f 851static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
e2f0ba97
JB		 852{
853 int i, j;
854 uint8_t set_buf_index[2];
855 uint8_t av_split;
856 uint8_t buf_size;
857 uint8_t buf[48];
858 uint8_t *pos;
859
c751ce4f
EA		 860 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
861 intel_sdvo_read_response(encoder, &av_split, 1);
e2f0ba97
JB		 862
863 for (i = 0; i <= av_split; i++) {
864 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 865 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 866 set_buf_index, 2);
c751ce4f
EA		 867 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
868 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 869
870 pos = buf;
871 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 872 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 873 NULL, 0);
c751ce4f 874 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 875 pos += 8;
876 }
877 }
878}
879#endif
880
c751ce4f
EA		 881static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,
882 int index,
883 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 884{
885 uint8_t set_buf_index[2];
886
887 set_buf_index[0] = index;
888 set_buf_index[1] = 0;
889
c751ce4f
EA		 890 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX,
891 set_buf_index, 2);
e2f0ba97
JB		 892
893 for (; size > 0; size -= 8) {
c751ce4f 894 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8);
e2f0ba97
JB		 895 data += 8;
896 }
897
c751ce4f 898 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 899}
900
901static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
902{
903 uint8_t csum = 0;
904 int i;
905
906 for (i = 0; i < size; i++)
907 csum += data[i];
908
909 return 0x100 - csum;
910}
911
912#define DIP_TYPE_AVI 0x82
913#define DIP_VERSION_AVI 0x2
914#define DIP_LEN_AVI 13
915
916struct dip_infoframe {
917 uint8_t type;
918 uint8_t version;
919 uint8_t len;
920 uint8_t checksum;
921 union {
922 struct {
923 /* Packet Byte #1 */
924 uint8_t S:2;
925 uint8_t B:2;
926 uint8_t A:1;
927 uint8_t Y:2;
928 uint8_t rsvd1:1;
929 /* Packet Byte #2 */
930 uint8_t R:4;
931 uint8_t M:2;
932 uint8_t C:2;
933 /* Packet Byte #3 */
934 uint8_t SC:2;
935 uint8_t Q:2;
936 uint8_t EC:3;
937 uint8_t ITC:1;
938 /* Packet Byte #4 */
939 uint8_t VIC:7;
940 uint8_t rsvd2:1;
941 /* Packet Byte #5 */
942 uint8_t PR:4;
943 uint8_t rsvd3:4;
944 /* Packet Byte #6~13 */
945 uint16_t top_bar_end;
946 uint16_t bottom_bar_start;
947 uint16_t left_bar_end;
948 uint16_t right_bar_start;
949 } avi;
950 struct {
951 /* Packet Byte #1 */
952 uint8_t channel_count:3;
953 uint8_t rsvd1:1;
954 uint8_t coding_type:4;
955 /* Packet Byte #2 */
956 uint8_t sample_size:2; /* SS0, SS1 */
957 uint8_t sample_frequency:3;
958 uint8_t rsvd2:3;
959 /* Packet Byte #3 */
960 uint8_t coding_type_private:5;
961 uint8_t rsvd3:3;
962 /* Packet Byte #4 */
963 uint8_t channel_allocation;
964 /* Packet Byte #5 */
965 uint8_t rsvd4:3;
966 uint8_t level_shift:4;
967 uint8_t downmix_inhibit:1;
968 } audio;
969 uint8_t payload[28];
970 } __attribute__ ((packed)) u;
971} __attribute__((packed));
972
c751ce4f 973static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 974 struct drm_display_mode * mode)
975{
976 struct dip_infoframe avi_if = {
977 .type = DIP_TYPE_AVI,
978 .version = DIP_VERSION_AVI,
979 .len = DIP_LEN_AVI,
980 };
981
982 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
983 4 + avi_if.len);
c751ce4f
EA		 984 intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if,
985 4 + avi_if.len,
e2f0ba97
JB		 986 SDVO_HBUF_TX_VSYNC);
987}
988
c751ce4f 989static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder)
7026d4ac 990{
ce6feabd
ZY		 991
992 struct intel_sdvo_tv_format format;
c751ce4f 993 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
ce6feabd
ZY		 994 uint32_t format_map, i;
995 uint8_t status;
7026d4ac 996
ce6feabd
ZY		 997 for (i = 0; i < TV_FORMAT_NUM; i++)
998 if (tv_format_names[i] == sdvo_priv->tv_format_name)
999 break;
1000
1001 format_map = 1 << i;
1002 memset(&format, 0, sizeof(format));
1003 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1004 sizeof(format) : sizeof(format_map));
1005
c751ce4f 1006 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format_map,
ce6feabd
ZY		 1007 sizeof(format));
1008
c751ce4f 1009 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
ce6feabd 1010 if (status != SDVO_CMD_STATUS_SUCCESS)
b9219c5e 1011 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
ce6feabd 1012 SDVO_NAME(sdvo_priv));
7026d4ac
ZW		 1013}
1014
e2f0ba97
JB		 1015static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1016 struct drm_display_mode *mode,
1017 struct drm_display_mode *adjusted_mode)
1018{
c751ce4f
EA		 1019 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1020 struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;
79e53945 1021
12682a97 1022 if (dev_priv->is_tv) {
e2f0ba97
JB		 1023 struct intel_sdvo_dtd output_dtd;
1024 bool success;
1025
1026 /* We need to construct preferred input timings based on our
1027 * output timings. To do that, we have to set the output
1028 * timings, even though this isn't really the right place in
1029 * the sequence to do it. Oh well.
1030 */
1031
1032
1033 /* Set output timings */
1034 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c751ce4f 1035 intel_sdvo_set_target_output(intel_encoder,
e2f0ba97 1036 dev_priv->controlled_output);
c751ce4f 1037 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
e2f0ba97
JB		 1038
1039 /* Set the input timing to the screen. Assume always input 0. */
c751ce4f 1040 intel_sdvo_set_target_input(intel_encoder, true, false);
e2f0ba97
JB		 1041
1042
c751ce4f 1043 success = intel_sdvo_create_preferred_input_timing(intel_encoder,
e2f0ba97
JB		 1044 mode->clock / 10,
1045 mode->hdisplay,
1046 mode->vdisplay);
1047 if (success) {
1048 struct intel_sdvo_dtd input_dtd;
79e53945 1049
c751ce4f 1050 intel_sdvo_get_preferred_input_timing(intel_encoder,
e2f0ba97
JB		 1051 &input_dtd);
1052 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
12682a97 1053 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1054
1055 drm_mode_set_crtcinfo(adjusted_mode, 0);
1056
1057 mode->clock = adjusted_mode->clock;
1058
1059 adjusted_mode->clock *=
1060 intel_sdvo_get_pixel_multiplier(mode);
1061 } else {
1062 return false;
1063 }
1064 } else if (dev_priv->is_lvds) {
1065 struct intel_sdvo_dtd output_dtd;
1066 bool success;
1067
1068 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1069 /* Set output timings */
1070 intel_sdvo_get_dtd_from_mode(&output_dtd,
1071 dev_priv->sdvo_lvds_fixed_mode);
1072
c751ce4f 1073 intel_sdvo_set_target_output(intel_encoder,
12682a97 1074 dev_priv->controlled_output);
c751ce4f 1075 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
12682a97 1076
1077 /* Set the input timing to the screen. Assume always input 0. */
c751ce4f 1078 intel_sdvo_set_target_input(intel_encoder, true, false);
12682a97 1079
1080
1081 success = intel_sdvo_create_preferred_input_timing(
c751ce4f 1082 intel_encoder,
12682a97 1083 mode->clock / 10,
1084 mode->hdisplay,
1085 mode->vdisplay);
1086
1087 if (success) {
1088 struct intel_sdvo_dtd input_dtd;
1089
c751ce4f 1090 intel_sdvo_get_preferred_input_timing(intel_encoder,
12682a97 1091 &input_dtd);
1092 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1093 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
e2f0ba97 1094
7026d4ac
ZW		 1095 drm_mode_set_crtcinfo(adjusted_mode, 0);
1096
1097 mode->clock = adjusted_mode->clock;
1098
1099 adjusted_mode->clock *=
1100 intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1101 } else {
1102 return false;
1103 }
12682a97 1104
1105 } else {
1106 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1107 * SDVO device will be told of the multiplier during mode_set.
1108 */
1109 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1110 }
1111 return true;
1112}
1113
1114static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1115 struct drm_display_mode *mode,
1116 struct drm_display_mode *adjusted_mode)
1117{
1118 struct drm_device *dev = encoder->dev;
1119 struct drm_i915_private *dev_priv = dev->dev_private;
1120 struct drm_crtc *crtc = encoder->crtc;
1121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c751ce4f
EA		 1122 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1123 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
e2f0ba97
JB		 1124 u32 sdvox = 0;
1125 int sdvo_pixel_multiply;
1126 struct intel_sdvo_in_out_map in_out;
1127 struct intel_sdvo_dtd input_dtd;
1128 u8 status;
1129
1130 if (!mode)
1131 return;
1132
1133 /* First, set the input mapping for the first input to our controlled
1134 * output. This is only correct if we're a single-input device, in
1135 * which case the first input is the output from the appropriate SDVO
1136 * channel on the motherboard. In a two-input device, the first input
1137 * will be SDVOB and the second SDVOC.
1138 */
1139 in_out.in0 = sdvo_priv->controlled_output;
1140 in_out.in1 = 0;
1141
c751ce4f 1142 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP,
e2f0ba97 1143 &in_out, sizeof(in_out));
c751ce4f 1144 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 1145
1146 if (sdvo_priv->is_hdmi) {
c751ce4f 1147 intel_sdvo_set_avi_infoframe(intel_encoder, mode);
e2f0ba97
JB		 1148 sdvox |= SDVO_AUDIO_ENABLE;
1149 }
1150
7026d4ac
ZW		 1151 /* We have tried to get input timing in mode_fixup, and filled into
1152 adjusted_mode */
12682a97 1153 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
7026d4ac 1154 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
12682a97 1155 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1156 } else
7026d4ac 1157 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
e2f0ba97
JB		 1158
1159 /* If it's a TV, we already set the output timing in mode_fixup.
1160 * Otherwise, the output timing is equal to the input timing.
1161 */
12682a97 1162 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
e2f0ba97 1163 /* Set the output timing to the screen */
c751ce4f 1164 intel_sdvo_set_target_output(intel_encoder,
e2f0ba97 1165 sdvo_priv->controlled_output);
c751ce4f 1166 intel_sdvo_set_output_timing(intel_encoder, &input_dtd);
e2f0ba97 1167 }
79e53945
JB		 1168
1169 /* Set the input timing to the screen. Assume always input 0. */
c751ce4f 1170 intel_sdvo_set_target_input(intel_encoder, true, false);
79e53945 1171
7026d4ac 1172 if (sdvo_priv->is_tv)
c751ce4f 1173 intel_sdvo_set_tv_format(intel_encoder);
7026d4ac 1174
e2f0ba97 1175 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1176 * provide the device with a timing it can support, if it supports that
1177 * feature. However, presumably we would need to adjust the CRTC to
1178 * output the preferred timing, and we don't support that currently.
1179 */
e2f0ba97 1180#if 0
c751ce4f 1181 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
e2f0ba97
JB		 1182 width, height);
1183 if (success) {
1184 struct intel_sdvo_dtd *input_dtd;
1185
c751ce4f
EA		 1186 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1187 intel_sdvo_set_input_timing(encoder, &input_dtd);
e2f0ba97
JB		 1188 }
1189#else
c751ce4f 1190 intel_sdvo_set_input_timing(intel_encoder, &input_dtd);
e2f0ba97 1191#endif
79e53945
JB		 1192
1193 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1194 case 1:
c751ce4f 1195 intel_sdvo_set_clock_rate_mult(intel_encoder,
79e53945
JB		 1196 SDVO_CLOCK_RATE_MULT_1X);
1197 break;
1198 case 2:
c751ce4f 1199 intel_sdvo_set_clock_rate_mult(intel_encoder,
79e53945
JB		 1200 SDVO_CLOCK_RATE_MULT_2X);
1201 break;
1202 case 4:
c751ce4f 1203 intel_sdvo_set_clock_rate_mult(intel_encoder,
79e53945
JB		 1204 SDVO_CLOCK_RATE_MULT_4X);
1205 break;
1206 }
1207
1208 /* Set the SDVO control regs. */
e2f0ba97
JB		 1209 if (IS_I965G(dev)) {
1210 sdvox |= SDVO_BORDER_ENABLE |
1211 SDVO_VSYNC_ACTIVE_HIGH |
1212 SDVO_HSYNC_ACTIVE_HIGH;
1213 } else {
c751ce4f
EA		 1214 sdvox |= I915_READ(sdvo_priv->sdvo_reg);
1215 switch (sdvo_priv->sdvo_reg) {
e2f0ba97
JB		 1216 case SDVOB:
1217 sdvox &= SDVOB_PRESERVE_MASK;
1218 break;
1219 case SDVOC:
1220 sdvox &= SDVOC_PRESERVE_MASK;
1221 break;
1222 }
1223 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1224 }
79e53945
JB		 1225 if (intel_crtc->pipe == 1)
1226 sdvox |= SDVO_PIPE_B_SELECT;
1227
1228 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1229 if (IS_I965G(dev)) {
e2f0ba97
JB		 1230 /* done in crtc_mode_set as the dpll_md reg must be written early */
1231 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1232 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1233 } else {
1234 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1235 }
1236
12682a97 1237 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1238 sdvox |= SDVO_STALL_SELECT;
c751ce4f 1239 intel_sdvo_write_sdvox(intel_encoder, sdvox);
79e53945
JB		 1240}
1241
1242static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1243{
1244 struct drm_device *dev = encoder->dev;
1245 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37
EA		 1246 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1247 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 1248 u32 temp;
1249
1250 if (mode != DRM_MODE_DPMS_ON) {
21d40d37 1251 intel_sdvo_set_active_outputs(intel_encoder, 0);
79e53945 1252 if (0)
21d40d37 1253 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
79e53945
JB		 1254
1255 if (mode == DRM_MODE_DPMS_OFF) {
c751ce4f 1256 temp = I915_READ(sdvo_priv->sdvo_reg);
79e53945 1257 if ((temp & SDVO_ENABLE) != 0) {
21d40d37 1258 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE);
79e53945
JB		 1259 }
1260 }
1261 } else {
1262 bool input1, input2;
1263 int i;
1264 u8 status;
1265
c751ce4f 1266 temp = I915_READ(sdvo_priv->sdvo_reg);
79e53945 1267 if ((temp & SDVO_ENABLE) == 0)
21d40d37 1268 intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE);
79e53945
JB		 1269 for (i = 0; i < 2; i++)
1270 intel_wait_for_vblank(dev);
1271
21d40d37 1272 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1,
79e53945
JB		 1273 &input2);
1274
1275
1276 /* Warn if the device reported failure to sync.
1277 * A lot of SDVO devices fail to notify of sync, but it's
1278 * a given it the status is a success, we succeeded.
1279 */
1280 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3
ZY		 1281 DRM_DEBUG_KMS("First %s output reported failure to "
1282 "sync\n", SDVO_NAME(sdvo_priv));
79e53945
JB		 1283 }
1284
1285 if (0)
21d40d37
EA		 1286 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1287 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->controlled_output);
79e53945
JB		 1288 }
1289 return;
1290}
1291
79e53945
JB		 1292static int intel_sdvo_mode_valid(struct drm_connector *connector,
1293 struct drm_display_mode *mode)
1294{
21d40d37
EA		 1295 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1296 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 1297
1298 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1299 return MODE_NO_DBLESCAN;
1300
1301 if (sdvo_priv->pixel_clock_min > mode->clock)
1302 return MODE_CLOCK_LOW;
1303
1304 if (sdvo_priv->pixel_clock_max < mode->clock)
1305 return MODE_CLOCK_HIGH;
1306
12682a97 1307 if (sdvo_priv->is_lvds == true) {
1308 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1309 return MODE_PANEL;
1310
1311 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1312 return MODE_PANEL;
1313
1314 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1315 return MODE_PANEL;
1316 }
1317
79e53945
JB		 1318 return MODE_OK;
1319}
1320
21d40d37 1321static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps)
79e53945
JB		 1322{
1323 u8 status;
1324
21d40d37
EA		 1325 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1326 status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps));
79e53945
JB		 1327 if (status != SDVO_CMD_STATUS_SUCCESS)
1328 return false;
1329
1330 return true;
1331}
1332
1333struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1334{
1335 struct drm_connector *connector = NULL;
21d40d37 1336 struct intel_encoder *iout = NULL;
79e53945
JB		 1337 struct intel_sdvo_priv *sdvo;
1338
1339 /* find the sdvo connector */
1340 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
21d40d37 1341 iout = to_intel_encoder(connector);
79e53945
JB		 1342
1343 if (iout->type != INTEL_OUTPUT_SDVO)
1344 continue;
1345
1346 sdvo = iout->dev_priv;
1347
c751ce4f 1348 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1349 return connector;
1350
c751ce4f 1351 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1352 return connector;
1353
1354 }
1355
1356 return NULL;
1357}
1358
1359int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1360{
1361 u8 response[2];
1362 u8 status;
21d40d37 1363 struct intel_encoder *intel_encoder;
8a4c47f3 1364 DRM_DEBUG_KMS("\n");
79e53945
JB		 1365
1366 if (!connector)
1367 return 0;
1368
21d40d37 1369 intel_encoder = to_intel_encoder(connector);
79e53945 1370
21d40d37
EA		 1371 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1372 status = intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945
JB		 1373
1374 if (response[0] !=0)
1375 return 1;
1376
1377 return 0;
1378}
1379
1380void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1381{
1382 u8 response[2];
1383 u8 status;
21d40d37 1384 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
79e53945 1385
21d40d37
EA		 1386 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1387 intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945
JB		 1388
1389 if (on) {
21d40d37
EA		 1390 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1391 status = intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945 1392
21d40d37 1393 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1394 } else {
1395 response[0] = 0;
1396 response[1] = 0;
21d40d37 1397 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1398 }
1399
21d40d37
EA		 1400 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1401 intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945
JB		 1402}
1403
fb7a46f3 1404static bool
21d40d37 1405intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder)
fb7a46f3 1406{
21d40d37 1407 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
fb7a46f3 1408 int caps = 0;
1409
1410 if (sdvo_priv->caps.output_flags &
1411 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1412 caps++;
1413 if (sdvo_priv->caps.output_flags &
1414 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1415 caps++;
1416 if (sdvo_priv->caps.output_flags &
19e1f888 1417 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1418 caps++;
1419 if (sdvo_priv->caps.output_flags &
1420 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1421 caps++;
1422 if (sdvo_priv->caps.output_flags &
1423 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1424 caps++;
1425
1426 if (sdvo_priv->caps.output_flags &
1427 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1428 caps++;
1429
1430 if (sdvo_priv->caps.output_flags &
1431 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1432 caps++;
1433
1434 return (caps > 1);
1435}
1436
57cdaf90
KP		 1437static struct drm_connector *
1438intel_find_analog_connector(struct drm_device *dev)
1439{
1440 struct drm_connector *connector;
21d40d37 1441 struct intel_encoder *intel_encoder;
57cdaf90
KP		 1442
1443 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
21d40d37
EA		 1444 intel_encoder = to_intel_encoder(connector);
1445 if (intel_encoder->type == INTEL_OUTPUT_ANALOG)
57cdaf90
KP		 1446 return connector;
1447 }
1448 return NULL;
1449}
1450
1451static int
1452intel_analog_is_connected(struct drm_device *dev)
1453{
1454 struct drm_connector *analog_connector;
1455 analog_connector = intel_find_analog_connector(dev);
1456
1457 if (!analog_connector)
1458 return false;
1459
1460 if (analog_connector->funcs->detect(analog_connector) ==
1461 connector_status_disconnected)
1462 return false;
1463
1464 return true;
1465}
1466
2b8d33f7 1467enum drm_connector_status
1468intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
9dff6af8 1469{
21d40d37
EA		 1470 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1471 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2b8d33f7 1472 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1473 struct edid *edid = NULL;
1474
21d40d37
EA		 1475 edid = drm_get_edid(&intel_encoder->base,
1476 intel_encoder->ddc_bus);
57cdaf90 1477
7c3f0a27 1478 /* This is only applied to SDVO cards with multiple outputs */
21d40d37 1479 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) {
7c3f0a27
ZY		 1480 uint8_t saved_ddc, temp_ddc;
1481 saved_ddc = sdvo_priv->ddc_bus;
1482 temp_ddc = sdvo_priv->ddc_bus >> 1;
1483 /*
1484 * Don't use the 1 as the argument of DDC bus switch to get
1485 * the EDID. It is used for SDVO SPD ROM.
1486 */
1487 while(temp_ddc > 1) {
1488 sdvo_priv->ddc_bus = temp_ddc;
21d40d37
EA		 1489 edid = drm_get_edid(&intel_encoder->base,
1490 intel_encoder->ddc_bus);
7c3f0a27
ZY		 1491 if (edid) {
1492 /*
1493 * When we can get the EDID, maybe it is the
1494 * correct DDC bus. Update it.
1495 */
1496 sdvo_priv->ddc_bus = temp_ddc;
1497 break;
1498 }
1499 temp_ddc >>= 1;
1500 }
1501 if (edid == NULL)
1502 sdvo_priv->ddc_bus = saved_ddc;
1503 }
57cdaf90
KP		 1504 /* when there is no edid and no monitor is connected with VGA
1505 * port, try to use the CRT ddc to read the EDID for DVI-connector
1506 */
1507 if (edid == NULL &&
1508 sdvo_priv->analog_ddc_bus &&
21d40d37
EA		 1509 !intel_analog_is_connected(intel_encoder->base.dev))
1510 edid = drm_get_edid(&intel_encoder->base,
57cdaf90 1511 sdvo_priv->analog_ddc_bus);
9dff6af8 1512 if (edid != NULL) {
2b8d33f7 1513 /* Don't report the output as connected if it's a DVI-I
1514 * connector with a non-digital EDID coming out.
1515 */
1516 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1517 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1518 sdvo_priv->is_hdmi =
1519 drm_detect_hdmi_monitor(edid);
1520 else
1521 status = connector_status_disconnected;
1522 }
1523
9dff6af8 1524 kfree(edid);
21d40d37 1525 intel_encoder->base.display_info.raw_edid = NULL;
2b8d33f7 1526
1527 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1528 status = connector_status_disconnected;
1529
1530 return status;
9dff6af8
ML		 1531}
1532
79e53945
JB		 1533static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1534{
fb7a46f3 1535 uint16_t response;
79e53945 1536 u8 status;
21d40d37
EA		 1537 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1538 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945 1539
21d40d37 1540 intel_sdvo_write_cmd(intel_encoder,
ce6feabd 1541 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
d09c23de
ZY		 1542 if (sdvo_priv->is_tv) {
1543 /* add 30ms delay when the output type is SDVO-TV */
1544 mdelay(30);
1545 }
21d40d37 1546 status = intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945 1547
51c8b407 1548 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97
JB		 1549
1550 if (status != SDVO_CMD_STATUS_SUCCESS)
1551 return connector_status_unknown;
1552
fb7a46f3 1553 if (response == 0)
79e53945 1554 return connector_status_disconnected;
fb7a46f3 1555
21d40d37 1556 if (intel_sdvo_multifunc_encoder(intel_encoder) &&
fb7a46f3 1557 sdvo_priv->attached_output != response) {
1558 if (sdvo_priv->controlled_output != response &&
21d40d37 1559 intel_sdvo_output_setup(intel_encoder, response) != true)
fb7a46f3 1560 return connector_status_unknown;
1561 sdvo_priv->attached_output = response;
1562 }
2b8d33f7 1563 return intel_sdvo_hdmi_sink_detect(connector, response);
79e53945
JB		 1564}
1565
e2f0ba97 1566static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1567{
21d40d37
EA		 1568 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1569 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
57cdaf90 1570 int num_modes;
79e53945
JB		 1571
1572 /* set the bus switch and get the modes */
335af9a2 1573 num_modes = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
79e53945 1574
57cdaf90
KP		 1575 /*
1576 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1577 * link between analog and digital outputs. So, if the regular SDVO
1578 * DDC fails, check to see if the analog output is disconnected, in
1579 * which case we'll look there for the digital DDC data.
e2f0ba97 1580 */
57cdaf90
KP		 1581 if (num_modes == 0 &&
1582 sdvo_priv->analog_ddc_bus &&
21d40d37 1583 !intel_analog_is_connected(intel_encoder->base.dev)) {
57cdaf90
KP		 1584 /* Switch to the analog ddc bus and try that
1585 */
335af9a2 1586 (void) intel_ddc_get_modes(connector, sdvo_priv->analog_ddc_bus);
e2f0ba97 1587 }
e2f0ba97
JB		 1588}
1589
1590/*
1591 * Set of SDVO TV modes.
1592 * Note! This is in reply order (see loop in get_tv_modes).
1593 * XXX: all 60Hz refresh?
1594 */
1595struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1596 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1597 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1598 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1599 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1600 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1602 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1603 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1605 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1606 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1608 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1609 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1612 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1613 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1614 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1615 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1617 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1618 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1620 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1621 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1623 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1624 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1625 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1626 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1627 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1629 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1630 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1632 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1633 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1635 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1636 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1638 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1639 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1641 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1642 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1643 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1644 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1645 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1647 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1648 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1650 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1651 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1653};
1654
1655static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1656{
21d40d37 1657 struct intel_encoder *output = to_intel_encoder(connector);
7026d4ac
ZW		 1658 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1659 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1660 uint32_t reply = 0, format_map = 0;
1661 int i;
e2f0ba97 1662 uint8_t status;
e2f0ba97 1663
e2f0ba97
JB		 1664
1665 /* Read the list of supported input resolutions for the selected TV
1666 * format.
1667 */
ce6feabd
ZY		 1668 for (i = 0; i < TV_FORMAT_NUM; i++)
1669 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1670 break;
1671
1672 format_map = (1 << i);
1673 memcpy(&tv_res, &format_map,
1674 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1675 sizeof(format_map) ? sizeof(format_map) :
1676 sizeof(struct intel_sdvo_sdtv_resolution_request));
1677
1678 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1679
e2f0ba97 1680 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
7026d4ac 1681 &tv_res, sizeof(tv_res));
e2f0ba97
JB		 1682 status = intel_sdvo_read_response(output, &reply, 3);
1683 if (status != SDVO_CMD_STATUS_SUCCESS)
1684 return;
1685
1686 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1687 if (reply & (1 << i)) {
1688 struct drm_display_mode *nmode;
1689 nmode = drm_mode_duplicate(connector->dev,
1690 &sdvo_tv_modes[i]);
1691 if (nmode)
1692 drm_mode_probed_add(connector, nmode);
1693 }
ce6feabd 1694
e2f0ba97
JB		 1695}
1696
7086c87f
ML		 1697static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1698{
21d40d37 1699 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
7086c87f 1700 struct drm_i915_private *dev_priv = connector->dev->dev_private;
21d40d37 1701 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
12682a97 1702 struct drm_display_mode *newmode;
7086c87f
ML		 1703
1704 /*
1705 * Attempt to get the mode list from DDC.
1706 * Assume that the preferred modes are
1707 * arranged in priority order.
1708 */
335af9a2 1709 intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
7086c87f 1710 if (list_empty(&connector->probed_modes) == false)
12682a97 1711 goto end;
7086c87f
ML		 1712
1713 /* Fetch modes from VBT */
1714 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1715 newmode = drm_mode_duplicate(connector->dev,
1716 dev_priv->sdvo_lvds_vbt_mode);
1717 if (newmode != NULL) {
1718 /* Guarantee the mode is preferred */
1719 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1720 DRM_MODE_TYPE_DRIVER);
1721 drm_mode_probed_add(connector, newmode);
1722 }
1723 }
12682a97 1724
1725end:
1726 list_for_each_entry(newmode, &connector->probed_modes, head) {
1727 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1728 sdvo_priv->sdvo_lvds_fixed_mode =
1729 drm_mode_duplicate(connector->dev, newmode);
1730 break;
1731 }
1732 }
1733
7086c87f
ML		 1734}
1735
e2f0ba97
JB		 1736static int intel_sdvo_get_modes(struct drm_connector *connector)
1737{
21d40d37 1738 struct intel_encoder *output = to_intel_encoder(connector);
e2f0ba97
JB		 1739 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1740
1741 if (sdvo_priv->is_tv)
1742 intel_sdvo_get_tv_modes(connector);
7086c87f
ML		 1743 else if (sdvo_priv->is_lvds == true)
1744 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1745 else
1746 intel_sdvo_get_ddc_modes(connector);
1747
79e53945
JB		 1748 if (list_empty(&connector->probed_modes))
1749 return 0;
1750 return 1;
1751}
1752
b9219c5e
ZY		 1753static
1754void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1755{
21d40d37
EA		 1756 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1757 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
b9219c5e
ZY		 1758 struct drm_device *dev = connector->dev;
1759
1760 if (sdvo_priv->is_tv) {
1761 if (sdvo_priv->left_property)
1762 drm_property_destroy(dev, sdvo_priv->left_property);
1763 if (sdvo_priv->right_property)
1764 drm_property_destroy(dev, sdvo_priv->right_property);
1765 if (sdvo_priv->top_property)
1766 drm_property_destroy(dev, sdvo_priv->top_property);
1767 if (sdvo_priv->bottom_property)
1768 drm_property_destroy(dev, sdvo_priv->bottom_property);
1769 if (sdvo_priv->hpos_property)
1770 drm_property_destroy(dev, sdvo_priv->hpos_property);
1771 if (sdvo_priv->vpos_property)
1772 drm_property_destroy(dev, sdvo_priv->vpos_property);
1773 }
1774 if (sdvo_priv->is_tv) {
1775 if (sdvo_priv->saturation_property)
1776 drm_property_destroy(dev,
1777 sdvo_priv->saturation_property);
1778 if (sdvo_priv->contrast_property)
1779 drm_property_destroy(dev,
1780 sdvo_priv->contrast_property);
1781 if (sdvo_priv->hue_property)
1782 drm_property_destroy(dev, sdvo_priv->hue_property);
1783 }
d0cbde93 1784 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
b9219c5e
ZY		 1785 if (sdvo_priv->brightness_property)
1786 drm_property_destroy(dev,
1787 sdvo_priv->brightness_property);
1788 }
1789 return;
1790}
1791
79e53945
JB		 1792static void intel_sdvo_destroy(struct drm_connector *connector)
1793{
21d40d37
EA		 1794 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1795 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945 1796
21d40d37
EA		 1797 if (intel_encoder->i2c_bus)
1798 intel_i2c_destroy(intel_encoder->i2c_bus);
1799 if (intel_encoder->ddc_bus)
1800 intel_i2c_destroy(intel_encoder->ddc_bus);
57cdaf90
KP		 1801 if (sdvo_priv->analog_ddc_bus)
1802 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
619ac3b7 1803
12682a97 1804 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1805 drm_mode_destroy(connector->dev,
1806 sdvo_priv->sdvo_lvds_fixed_mode);
1807
ce6feabd
ZY		 1808 if (sdvo_priv->tv_format_property)
1809 drm_property_destroy(connector->dev,
1810 sdvo_priv->tv_format_property);
1811
d0cbde93 1812 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
b9219c5e
ZY		 1813 intel_sdvo_destroy_enhance_property(connector);
1814
79e53945
JB		 1815 drm_sysfs_connector_remove(connector);
1816 drm_connector_cleanup(connector);
12682a97 1817
21d40d37 1818 kfree(intel_encoder);
79e53945
JB		 1819}
1820
ce6feabd
ZY		 1821static int
1822intel_sdvo_set_property(struct drm_connector *connector,
1823 struct drm_property *property,
1824 uint64_t val)
1825{
21d40d37
EA		 1826 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1827 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1828 struct drm_encoder *encoder = &intel_encoder->enc;
ce6feabd
ZY		 1829 struct drm_crtc *crtc = encoder->crtc;
1830 int ret = 0;
1831 bool changed = false;
b9219c5e
ZY		 1832 uint8_t cmd, status;
1833 uint16_t temp_value;
ce6feabd
ZY		 1834
1835 ret = drm_connector_property_set_value(connector, property, val);
1836 if (ret < 0)
1837 goto out;
1838
1839 if (property == sdvo_priv->tv_format_property) {
1840 if (val >= TV_FORMAT_NUM) {
1841 ret = -EINVAL;
1842 goto out;
1843 }
1844 if (sdvo_priv->tv_format_name ==
1845 sdvo_priv->tv_format_supported[val])
1846 goto out;
1847
1848 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
1849 changed = true;
ce6feabd
ZY		 1850 }
1851
d0cbde93 1852 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
b9219c5e
ZY		 1853 cmd = 0;
1854 temp_value = val;
1855 if (sdvo_priv->left_property == property) {
1856 drm_connector_property_set_value(connector,
1857 sdvo_priv->right_property, val);
1858 if (sdvo_priv->left_margin == temp_value)
1859 goto out;
1860
1861 sdvo_priv->left_margin = temp_value;
1862 sdvo_priv->right_margin = temp_value;
1863 temp_value = sdvo_priv->max_hscan -
1864 sdvo_priv->left_margin;
1865 cmd = SDVO_CMD_SET_OVERSCAN_H;
1866 } else if (sdvo_priv->right_property == property) {
1867 drm_connector_property_set_value(connector,
1868 sdvo_priv->left_property, val);
1869 if (sdvo_priv->right_margin == temp_value)
1870 goto out;
1871
1872 sdvo_priv->left_margin = temp_value;
1873 sdvo_priv->right_margin = temp_value;
1874 temp_value = sdvo_priv->max_hscan -
1875 sdvo_priv->left_margin;
1876 cmd = SDVO_CMD_SET_OVERSCAN_H;
1877 } else if (sdvo_priv->top_property == property) {
1878 drm_connector_property_set_value(connector,
1879 sdvo_priv->bottom_property, val);
1880 if (sdvo_priv->top_margin == temp_value)
1881 goto out;
1882
1883 sdvo_priv->top_margin = temp_value;
1884 sdvo_priv->bottom_margin = temp_value;
1885 temp_value = sdvo_priv->max_vscan -
1886 sdvo_priv->top_margin;
1887 cmd = SDVO_CMD_SET_OVERSCAN_V;
1888 } else if (sdvo_priv->bottom_property == property) {
1889 drm_connector_property_set_value(connector,
1890 sdvo_priv->top_property, val);
1891 if (sdvo_priv->bottom_margin == temp_value)
1892 goto out;
1893 sdvo_priv->top_margin = temp_value;
1894 sdvo_priv->bottom_margin = temp_value;
1895 temp_value = sdvo_priv->max_vscan -
1896 sdvo_priv->top_margin;
1897 cmd = SDVO_CMD_SET_OVERSCAN_V;
1898 } else if (sdvo_priv->hpos_property == property) {
1899 if (sdvo_priv->cur_hpos == temp_value)
1900 goto out;
1901
1902 cmd = SDVO_CMD_SET_POSITION_H;
1903 sdvo_priv->cur_hpos = temp_value;
1904 } else if (sdvo_priv->vpos_property == property) {
1905 if (sdvo_priv->cur_vpos == temp_value)
1906 goto out;
1907
1908 cmd = SDVO_CMD_SET_POSITION_V;
1909 sdvo_priv->cur_vpos = temp_value;
1910 } else if (sdvo_priv->saturation_property == property) {
1911 if (sdvo_priv->cur_saturation == temp_value)
1912 goto out;
1913
1914 cmd = SDVO_CMD_SET_SATURATION;
1915 sdvo_priv->cur_saturation = temp_value;
1916 } else if (sdvo_priv->contrast_property == property) {
1917 if (sdvo_priv->cur_contrast == temp_value)
1918 goto out;
1919
1920 cmd = SDVO_CMD_SET_CONTRAST;
1921 sdvo_priv->cur_contrast = temp_value;
1922 } else if (sdvo_priv->hue_property == property) {
1923 if (sdvo_priv->cur_hue == temp_value)
1924 goto out;
1925
1926 cmd = SDVO_CMD_SET_HUE;
1927 sdvo_priv->cur_hue = temp_value;
1928 } else if (sdvo_priv->brightness_property == property) {
1929 if (sdvo_priv->cur_brightness == temp_value)
1930 goto out;
1931
1932 cmd = SDVO_CMD_SET_BRIGHTNESS;
1933 sdvo_priv->cur_brightness = temp_value;
1934 }
1935 if (cmd) {
21d40d37
EA		 1936 intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2);
1937 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 1938 NULL, 0);
1939 if (status != SDVO_CMD_STATUS_SUCCESS) {
1940 DRM_DEBUG_KMS("Incorrect SDVO command \n");
1941 return -EINVAL;
1942 }
1943 changed = true;
1944 }
1945 }
ce6feabd
ZY		 1946 if (changed && crtc)
1947 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1948 crtc->y, crtc->fb);
1949out:
1950 return ret;
1951}
1952
79e53945
JB		 1953static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1954 .dpms = intel_sdvo_dpms,
1955 .mode_fixup = intel_sdvo_mode_fixup,
1956 .prepare = intel_encoder_prepare,
1957 .mode_set = intel_sdvo_mode_set,
1958 .commit = intel_encoder_commit,
1959};
1960
1961static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1962 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1963 .detect = intel_sdvo_detect,
1964 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1965 .set_property = intel_sdvo_set_property,
79e53945
JB		 1966 .destroy = intel_sdvo_destroy,
1967};
1968
1969static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1970 .get_modes = intel_sdvo_get_modes,
1971 .mode_valid = intel_sdvo_mode_valid,
1972 .best_encoder = intel_best_encoder,
1973};
1974
b358d0a6 1975static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945
JB		 1976{
1977 drm_encoder_cleanup(encoder);
1978}
1979
1980static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1981 .destroy = intel_sdvo_enc_destroy,
1982};
1983
1984
e2f0ba97
JB		 1985/**
1986 * Choose the appropriate DDC bus for control bus switch command for this
1987 * SDVO output based on the controlled output.
1988 *
1989 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1990 * outputs, then LVDS outputs.
1991 */
1992static void
1993intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
1994{
1995 uint16_t mask = 0;
1996 unsigned int num_bits;
1997
1998 /* Make a mask of outputs less than or equal to our own priority in the
1999 * list.
2000 */
2001 switch (dev_priv->controlled_output) {
2002 case SDVO_OUTPUT_LVDS1:
2003 mask |= SDVO_OUTPUT_LVDS1;
2004 case SDVO_OUTPUT_LVDS0:
2005 mask |= SDVO_OUTPUT_LVDS0;
2006 case SDVO_OUTPUT_TMDS1:
2007 mask |= SDVO_OUTPUT_TMDS1;
2008 case SDVO_OUTPUT_TMDS0:
2009 mask |= SDVO_OUTPUT_TMDS0;
2010 case SDVO_OUTPUT_RGB1:
2011 mask |= SDVO_OUTPUT_RGB1;
2012 case SDVO_OUTPUT_RGB0:
2013 mask |= SDVO_OUTPUT_RGB0;
2014 break;
2015 }
2016
2017 /* Count bits to find what number we are in the priority list. */
2018 mask &= dev_priv->caps.output_flags;
2019 num_bits = hweight16(mask);
2020 if (num_bits > 3) {
2021 /* if more than 3 outputs, default to DDC bus 3 for now */
2022 num_bits = 3;
2023 }
2024
2025 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2026 dev_priv->ddc_bus = 1 << num_bits;
2027}
2028
2029static bool
21d40d37 2030intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output)
e2f0ba97
JB		 2031{
2032 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2033 uint8_t status;
2034
2035 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
2036
2037 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2038 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2039 if (status != SDVO_CMD_STATUS_SUCCESS)
2040 return false;
2041 return true;
2042}
2043
21d40d37
EA		 2044static struct intel_encoder *
2045intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan)
619ac3b7
ML		 2046{
2047 struct drm_device *dev = chan->drm_dev;
2048 struct drm_connector *connector;
21d40d37 2049 struct intel_encoder *intel_encoder = NULL;
619ac3b7
ML		 2050
2051 list_for_each_entry(connector,
2052 &dev->mode_config.connector_list, head) {
21d40d37
EA		 2053 if (to_intel_encoder(connector)->ddc_bus == &chan->adapter) {
2054 intel_encoder = to_intel_encoder(connector);
619ac3b7
ML		 2055 break;
2056 }
2057 }
21d40d37 2058 return intel_encoder;
619ac3b7
ML		 2059}
2060
2061static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2062 struct i2c_msg msgs[], int num)
2063{
21d40d37 2064 struct intel_encoder *intel_encoder;
619ac3b7
ML		 2065 struct intel_sdvo_priv *sdvo_priv;
2066 struct i2c_algo_bit_data *algo_data;
f9c10a9b 2067 const struct i2c_algorithm *algo;
619ac3b7
ML		 2068
2069 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
21d40d37
EA		 2070 intel_encoder =
2071 intel_sdvo_chan_to_intel_encoder(
619ac3b7 2072 (struct intel_i2c_chan *)(algo_data->data));
21d40d37 2073 if (intel_encoder == NULL)
619ac3b7
ML		 2074 return -EINVAL;
2075
21d40d37
EA		 2076 sdvo_priv = intel_encoder->dev_priv;
2077 algo = intel_encoder->i2c_bus->algo;
619ac3b7 2078
21d40d37 2079 intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus);
619ac3b7
ML		 2080 return algo->master_xfer(i2c_adap, msgs, num);
2081}
2082
2083static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2084 .master_xfer = intel_sdvo_master_xfer,
2085};
2086
714605e4 2087static u8
c751ce4f 2088intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2089{
2090 struct drm_i915_private *dev_priv = dev->dev_private;
2091 struct sdvo_device_mapping *my_mapping, *other_mapping;
2092
c751ce4f 2093 if (sdvo_reg == SDVOB) {
714605e4 2094 my_mapping = &dev_priv->sdvo_mappings[0];
2095 other_mapping = &dev_priv->sdvo_mappings[1];
2096 } else {
2097 my_mapping = &dev_priv->sdvo_mappings[1];
2098 other_mapping = &dev_priv->sdvo_mappings[0];
2099 }
2100
2101 /* If the BIOS described our SDVO device, take advantage of it. */
2102 if (my_mapping->slave_addr)
2103 return my_mapping->slave_addr;
2104
2105 /* If the BIOS only described a different SDVO device, use the
2106 * address that it isn't using.
2107 */
2108 if (other_mapping->slave_addr) {
2109 if (other_mapping->slave_addr == 0x70)
2110 return 0x72;
2111 else
2112 return 0x70;
2113 }
2114
2115 /* No SDVO device info is found for another DVO port,
2116 * so use mapping assumption we had before BIOS parsing.
2117 */
c751ce4f 2118 if (sdvo_reg == SDVOB)
714605e4 2119 return 0x70;
2120 else
2121 return 0x72;
2122}
2123
6070a4a9
ZY		 2124static int intel_sdvo_bad_tv_callback(const struct dmi_system_id *id)
2125{
2126 DRM_DEBUG_KMS("Ignoring bad SDVO TV connector for %s\n", id->ident);
2127 return 1;
2128}
2129
2130static struct dmi_system_id intel_sdvo_bad_tv[] = {
2131 {
2132 .callback = intel_sdvo_bad_tv_callback,
2133 .ident = "IntelG45/ICH10R/DME1737",
2134 .matches = {
2135 DMI_MATCH(DMI_SYS_VENDOR, "IBM CORPORATION"),
2136 DMI_MATCH(DMI_PRODUCT_NAME, "4800784"),
2137 },
2138 },
2139
2140 { } /* terminating entry */
2141};
2142
fb7a46f3 2143static bool
21d40d37 2144intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags)
fb7a46f3 2145{
21d40d37
EA		 2146 struct drm_connector *connector = &intel_encoder->base;
2147 struct drm_encoder *encoder = &intel_encoder->enc;
2148 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
fb7a46f3 2149 bool ret = true, registered = false;
2150
2151 sdvo_priv->is_tv = false;
21d40d37 2152 intel_encoder->needs_tv_clock = false;
fb7a46f3 2153 sdvo_priv->is_lvds = false;
2154
2155 if (device_is_registered(&connector->kdev)) {
2156 drm_sysfs_connector_remove(connector);
2157 registered = true;
2158 }
2159
2160 if (flags &
2161 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
2162 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
2163 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
2164 else
2165 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
2166
2167 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2168 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2169
21d40d37 2170 if (intel_sdvo_get_supp_encode(intel_encoder,
fb7a46f3 2171 &sdvo_priv->encode) &&
21d40d37 2172 intel_sdvo_get_digital_encoding_mode(intel_encoder) &&
fb7a46f3 2173 sdvo_priv->is_hdmi) {
2174 /* enable hdmi encoding mode if supported */
21d40d37
EA		 2175 intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI);
2176 intel_sdvo_set_colorimetry(intel_encoder,
fb7a46f3 2177 SDVO_COLORIMETRY_RGB256);
2178 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
21d40d37 2179 intel_encoder->clone_mask =
f8aed700
ML		 2180 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2181 (1 << INTEL_ANALOG_CLONE_BIT);
fb7a46f3 2182 }
6070a4a9
ZY		 2183 } else if ((flags & SDVO_OUTPUT_SVID0) &&
2184 !dmi_check_system(intel_sdvo_bad_tv)) {
fb7a46f3 2185
2186 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
2187 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2188 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2189 sdvo_priv->is_tv = true;
21d40d37
EA		 2190 intel_encoder->needs_tv_clock = true;
2191 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
fb7a46f3 2192 } else if (flags & SDVO_OUTPUT_RGB0) {
2193
2194 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2195 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2196 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
21d40d37 2197 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
f8aed700 2198 (1 << INTEL_ANALOG_CLONE_BIT);
fb7a46f3 2199 } else if (flags & SDVO_OUTPUT_RGB1) {
2200
2201 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2202 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2203 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
21d40d37 2204 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
e270846f 2205 (1 << INTEL_ANALOG_CLONE_BIT);
2dd87383
ZY		 2206 } else if (flags & SDVO_OUTPUT_CVBS0) {
2207
2208 sdvo_priv->controlled_output = SDVO_OUTPUT_CVBS0;
2209 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2210 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2211 sdvo_priv->is_tv = true;
21d40d37
EA		 2212 intel_encoder->needs_tv_clock = true;
2213 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
fb7a46f3 2214 } else if (flags & SDVO_OUTPUT_LVDS0) {
2215
2216 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2217 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2218 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2219 sdvo_priv->is_lvds = true;
21d40d37 2220 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
f8aed700 2221 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
fb7a46f3 2222 } else if (flags & SDVO_OUTPUT_LVDS1) {
2223
2224 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2225 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2226 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2227 sdvo_priv->is_lvds = true;
21d40d37 2228 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
f8aed700 2229 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
fb7a46f3 2230 } else {
2231
2232 unsigned char bytes[2];
2233
2234 sdvo_priv->controlled_output = 0;
2235 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
51c8b407
DA		 2236 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2237 SDVO_NAME(sdvo_priv),
2238 bytes[0], bytes[1]);
fb7a46f3 2239 ret = false;
2240 }
21d40d37 2241 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2242
2243 if (ret && registered)
2244 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2245
2246
2247 return ret;
2248
2249}
2250
ce6feabd
ZY		 2251static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2252{
21d40d37
EA		 2253 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2254 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
ce6feabd
ZY		 2255 struct intel_sdvo_tv_format format;
2256 uint32_t format_map, i;
2257 uint8_t status;
2258
21d40d37 2259 intel_sdvo_set_target_output(intel_encoder,
ce6feabd
ZY		 2260 sdvo_priv->controlled_output);
2261
21d40d37 2262 intel_sdvo_write_cmd(intel_encoder,
ce6feabd 2263 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
21d40d37 2264 status = intel_sdvo_read_response(intel_encoder,
ce6feabd
ZY		 2265 &format, sizeof(format));
2266 if (status != SDVO_CMD_STATUS_SUCCESS)
2267 return;
2268
2269 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2270 sizeof(format_map) : sizeof(format));
2271
2272 if (format_map == 0)
2273 return;
2274
2275 sdvo_priv->format_supported_num = 0;
2276 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2277 if (format_map & (1 << i)) {
2278 sdvo_priv->tv_format_supported
2279 [sdvo_priv->format_supported_num++] =
2280 tv_format_names[i];
2281 }
2282
2283
2284 sdvo_priv->tv_format_property =
2285 drm_property_create(
2286 connector->dev, DRM_MODE_PROP_ENUM,
2287 "mode", sdvo_priv->format_supported_num);
2288
2289 for (i = 0; i < sdvo_priv->format_supported_num; i++)
2290 drm_property_add_enum(
2291 sdvo_priv->tv_format_property, i,
2292 i, sdvo_priv->tv_format_supported[i]);
2293
2294 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
2295 drm_connector_attach_property(
2296 connector, sdvo_priv->tv_format_property, 0);
2297
2298}
2299
b9219c5e
ZY		 2300static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2301{
21d40d37
EA		 2302 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2303 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
b9219c5e
ZY		 2304 struct intel_sdvo_enhancements_reply sdvo_data;
2305 struct drm_device *dev = connector->dev;
2306 uint8_t status;
2307 uint16_t response, data_value[2];
2308
21d40d37 2309 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
b9219c5e 2310 NULL, 0);
21d40d37 2311 status = intel_sdvo_read_response(intel_encoder, &sdvo_data,
b9219c5e
ZY		 2312 sizeof(sdvo_data));
2313 if (status != SDVO_CMD_STATUS_SUCCESS) {
2314 DRM_DEBUG_KMS(" incorrect response is returned\n");
2315 return;
2316 }
2317 response = *((uint16_t *)&sdvo_data);
2318 if (!response) {
2319 DRM_DEBUG_KMS("No enhancement is supported\n");
2320 return;
2321 }
2322 if (sdvo_priv->is_tv) {
2323 /* when horizontal overscan is supported, Add the left/right
2324 * property
2325 */
2326 if (sdvo_data.overscan_h) {
21d40d37 2327 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2328 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
21d40d37 2329 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2330 &data_value, 4);
2331 if (status != SDVO_CMD_STATUS_SUCCESS) {
2332 DRM_DEBUG_KMS("Incorrect SDVO max "
2333 "h_overscan\n");
2334 return;
2335 }
21d40d37 2336 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2337 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
21d40d37 2338 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2339 &response, 2);
2340 if (status != SDVO_CMD_STATUS_SUCCESS) {
2341 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2342 return;
2343 }
2344 sdvo_priv->max_hscan = data_value[0];
2345 sdvo_priv->left_margin = data_value[0] - response;
2346 sdvo_priv->right_margin = sdvo_priv->left_margin;
2347 sdvo_priv->left_property =
2348 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2349 "left_margin", 2);
2350 sdvo_priv->left_property->values[0] = 0;
2351 sdvo_priv->left_property->values[1] = data_value[0];
2352 drm_connector_attach_property(connector,
2353 sdvo_priv->left_property,
2354 sdvo_priv->left_margin);
2355 sdvo_priv->right_property =
2356 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2357 "right_margin", 2);
2358 sdvo_priv->right_property->values[0] = 0;
2359 sdvo_priv->right_property->values[1] = data_value[0];
2360 drm_connector_attach_property(connector,
2361 sdvo_priv->right_property,
2362 sdvo_priv->right_margin);
2363 DRM_DEBUG_KMS("h_overscan: max %d, "
2364 "default %d, current %d\n",
2365 data_value[0], data_value[1], response);
2366 }
2367 if (sdvo_data.overscan_v) {
21d40d37 2368 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2369 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
21d40d37 2370 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2371 &data_value, 4);
2372 if (status != SDVO_CMD_STATUS_SUCCESS) {
2373 DRM_DEBUG_KMS("Incorrect SDVO max "
2374 "v_overscan\n");
2375 return;
2376 }
21d40d37 2377 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2378 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
21d40d37 2379 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2380 &response, 2);
2381 if (status != SDVO_CMD_STATUS_SUCCESS) {
2382 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2383 return;
2384 }
2385 sdvo_priv->max_vscan = data_value[0];
2386 sdvo_priv->top_margin = data_value[0] - response;
2387 sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2388 sdvo_priv->top_property =
2389 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2390 "top_margin", 2);
2391 sdvo_priv->top_property->values[0] = 0;
2392 sdvo_priv->top_property->values[1] = data_value[0];
2393 drm_connector_attach_property(connector,
2394 sdvo_priv->top_property,
2395 sdvo_priv->top_margin);
2396 sdvo_priv->bottom_property =
2397 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2398 "bottom_margin", 2);
2399 sdvo_priv->bottom_property->values[0] = 0;
2400 sdvo_priv->bottom_property->values[1] = data_value[0];
2401 drm_connector_attach_property(connector,
2402 sdvo_priv->bottom_property,
2403 sdvo_priv->bottom_margin);
2404 DRM_DEBUG_KMS("v_overscan: max %d, "
2405 "default %d, current %d\n",
2406 data_value[0], data_value[1], response);
2407 }
2408 if (sdvo_data.position_h) {
21d40d37 2409 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2410 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
21d40d37 2411 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2412 &data_value, 4);
2413 if (status != SDVO_CMD_STATUS_SUCCESS) {
2414 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2415 return;
2416 }
21d40d37 2417 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2418 SDVO_CMD_GET_POSITION_H, NULL, 0);
21d40d37 2419 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2420 &response, 2);
2421 if (status != SDVO_CMD_STATUS_SUCCESS) {
2422 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2423 return;
2424 }
2425 sdvo_priv->max_hpos = data_value[0];
2426 sdvo_priv->cur_hpos = response;
2427 sdvo_priv->hpos_property =
2428 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2429 "hpos", 2);
2430 sdvo_priv->hpos_property->values[0] = 0;
2431 sdvo_priv->hpos_property->values[1] = data_value[0];
2432 drm_connector_attach_property(connector,
2433 sdvo_priv->hpos_property,
2434 sdvo_priv->cur_hpos);
2435 DRM_DEBUG_KMS("h_position: max %d, "
2436 "default %d, current %d\n",
2437 data_value[0], data_value[1], response);
2438 }
2439 if (sdvo_data.position_v) {
21d40d37 2440 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2441 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
21d40d37 2442 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2443 &data_value, 4);
2444 if (status != SDVO_CMD_STATUS_SUCCESS) {
2445 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2446 return;
2447 }
21d40d37 2448 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2449 SDVO_CMD_GET_POSITION_V, NULL, 0);
21d40d37 2450 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2451 &response, 2);
2452 if (status != SDVO_CMD_STATUS_SUCCESS) {
2453 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2454 return;
2455 }
2456 sdvo_priv->max_vpos = data_value[0];
2457 sdvo_priv->cur_vpos = response;
2458 sdvo_priv->vpos_property =
2459 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2460 "vpos", 2);
2461 sdvo_priv->vpos_property->values[0] = 0;
2462 sdvo_priv->vpos_property->values[1] = data_value[0];
2463 drm_connector_attach_property(connector,
2464 sdvo_priv->vpos_property,
2465 sdvo_priv->cur_vpos);
2466 DRM_DEBUG_KMS("v_position: max %d, "
2467 "default %d, current %d\n",
2468 data_value[0], data_value[1], response);
2469 }
2470 }
2471 if (sdvo_priv->is_tv) {
2472 if (sdvo_data.saturation) {
21d40d37 2473 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2474 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
21d40d37 2475 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2476 &data_value, 4);
2477 if (status != SDVO_CMD_STATUS_SUCCESS) {
2478 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2479 return;
2480 }
21d40d37 2481 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2482 SDVO_CMD_GET_SATURATION, NULL, 0);
21d40d37 2483 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2484 &response, 2);
2485 if (status != SDVO_CMD_STATUS_SUCCESS) {
2486 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2487 return;
2488 }
2489 sdvo_priv->max_saturation = data_value[0];
2490 sdvo_priv->cur_saturation = response;
2491 sdvo_priv->saturation_property =
2492 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2493 "saturation", 2);
2494 sdvo_priv->saturation_property->values[0] = 0;
2495 sdvo_priv->saturation_property->values[1] =
2496 data_value[0];
2497 drm_connector_attach_property(connector,
2498 sdvo_priv->saturation_property,
2499 sdvo_priv->cur_saturation);
2500 DRM_DEBUG_KMS("saturation: max %d, "
2501 "default %d, current %d\n",
2502 data_value[0], data_value[1], response);
2503 }
2504 if (sdvo_data.contrast) {
21d40d37 2505 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2506 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
21d40d37 2507 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2508 &data_value, 4);
2509 if (status != SDVO_CMD_STATUS_SUCCESS) {
2510 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2511 return;
2512 }
21d40d37 2513 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2514 SDVO_CMD_GET_CONTRAST, NULL, 0);
21d40d37 2515 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2516 &response, 2);
2517 if (status != SDVO_CMD_STATUS_SUCCESS) {
2518 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2519 return;
2520 }
2521 sdvo_priv->max_contrast = data_value[0];
2522 sdvo_priv->cur_contrast = response;
2523 sdvo_priv->contrast_property =
2524 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2525 "contrast", 2);
2526 sdvo_priv->contrast_property->values[0] = 0;
2527 sdvo_priv->contrast_property->values[1] = data_value[0];
2528 drm_connector_attach_property(connector,
2529 sdvo_priv->contrast_property,
2530 sdvo_priv->cur_contrast);
2531 DRM_DEBUG_KMS("contrast: max %d, "
2532 "default %d, current %d\n",
2533 data_value[0], data_value[1], response);
2534 }
2535 if (sdvo_data.hue) {
21d40d37 2536 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2537 SDVO_CMD_GET_MAX_HUE, NULL, 0);
21d40d37 2538 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2539 &data_value, 4);
2540 if (status != SDVO_CMD_STATUS_SUCCESS) {
2541 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2542 return;
2543 }
21d40d37 2544 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2545 SDVO_CMD_GET_HUE, NULL, 0);
21d40d37 2546 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2547 &response, 2);
2548 if (status != SDVO_CMD_STATUS_SUCCESS) {
2549 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2550 return;
2551 }
2552 sdvo_priv->max_hue = data_value[0];
2553 sdvo_priv->cur_hue = response;
2554 sdvo_priv->hue_property =
2555 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2556 "hue", 2);
2557 sdvo_priv->hue_property->values[0] = 0;
2558 sdvo_priv->hue_property->values[1] =
2559 data_value[0];
2560 drm_connector_attach_property(connector,
2561 sdvo_priv->hue_property,
2562 sdvo_priv->cur_hue);
2563 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2564 data_value[0], data_value[1], response);
2565 }
2566 }
d0cbde93 2567 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
b9219c5e 2568 if (sdvo_data.brightness) {
21d40d37 2569 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2570 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
21d40d37 2571 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2572 &data_value, 4);
2573 if (status != SDVO_CMD_STATUS_SUCCESS) {
2574 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2575 return;
2576 }
21d40d37 2577 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2578 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
21d40d37 2579 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2580 &response, 2);
2581 if (status != SDVO_CMD_STATUS_SUCCESS) {
2582 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2583 return;
2584 }
2585 sdvo_priv->max_brightness = data_value[0];
2586 sdvo_priv->cur_brightness = response;
2587 sdvo_priv->brightness_property =
2588 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2589 "brightness", 2);
2590 sdvo_priv->brightness_property->values[0] = 0;
2591 sdvo_priv->brightness_property->values[1] =
2592 data_value[0];
2593 drm_connector_attach_property(connector,
2594 sdvo_priv->brightness_property,
2595 sdvo_priv->cur_brightness);
2596 DRM_DEBUG_KMS("brightness: max %d, "
2597 "default %d, current %d\n",
2598 data_value[0], data_value[1], response);
2599 }
2600 }
2601 return;
2602}
2603
c751ce4f 2604bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2605{
b01f2c3a 2606 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2607 struct drm_connector *connector;
21d40d37 2608 struct intel_encoder *intel_encoder;
79e53945 2609 struct intel_sdvo_priv *sdvo_priv;
f9c10a9b 2610
79e53945
JB		 2611 u8 ch[0x40];
2612 int i;
79e53945 2613
21d40d37
EA		 2614 intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2615 if (!intel_encoder) {
7d57382e 2616 return false;
79e53945
JB		 2617 }
2618
21d40d37 2619 sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1);
c751ce4f 2620 sdvo_priv->sdvo_reg = sdvo_reg;
308cd3a2 2621
21d40d37
EA		 2622 intel_encoder->dev_priv = sdvo_priv;
2623 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2624
79e53945 2625 /* setup the DDC bus. */
c751ce4f 2626 if (sdvo_reg == SDVOB)
21d40d37 2627 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
308cd3a2 2628 else
21d40d37 2629 intel_encoder->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
308cd3a2 2630
21d40d37 2631 if (!intel_encoder->i2c_bus)
ad5b2a6d 2632 goto err_inteloutput;
79e53945 2633
c751ce4f 2634 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2635
308cd3a2 2636 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2637 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2638
79e53945
JB		 2639 /* Read the regs to test if we can talk to the device */
2640 for (i = 0; i < 0x40; i++) {
21d40d37 2641 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) {
8a4c47f3 2642 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
c751ce4f 2643 sdvo_reg == SDVOB ? 'B' : 'C');
79e53945
JB		 2644 goto err_i2c;
2645 }
2646 }
2647
619ac3b7 2648 /* setup the DDC bus. */
c751ce4f 2649 if (sdvo_reg == SDVOB) {
21d40d37 2650 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
57cdaf90
KP		 2651 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2652 "SDVOB/VGA DDC BUS");
b01f2c3a 2653 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2654 } else {
21d40d37 2655 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
57cdaf90
KP		 2656 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2657 "SDVOC/VGA DDC BUS");
b01f2c3a 2658 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2659 }
619ac3b7 2660
21d40d37 2661 if (intel_encoder->ddc_bus == NULL)
619ac3b7
ML		 2662 goto err_i2c;
2663
308cd3a2 2664 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2665 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2666
af901ca1 2667 /* In default case sdvo lvds is false */
21d40d37 2668 intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps);
79e53945 2669
21d40d37 2670 if (intel_sdvo_output_setup(intel_encoder,
fb7a46f3 2671 sdvo_priv->caps.output_flags) != true) {
51c8b407 2672 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
c751ce4f 2673 sdvo_reg == SDVOB ? 'B' : 'C');
79e53945
JB		 2674 goto err_i2c;
2675 }
2676
fb7a46f3 2677
21d40d37 2678 connector = &intel_encoder->base;
ad5b2a6d 2679 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
fb7a46f3 2680 connector->connector_type);
2681
ad5b2a6d
JB		 2682 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2683 connector->interlace_allowed = 0;
2684 connector->doublescan_allowed = 0;
2685 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2686
21d40d37
EA		 2687 drm_encoder_init(dev, &intel_encoder->enc,
2688 &intel_sdvo_enc_funcs, intel_encoder->enc.encoder_type);
fb7a46f3 2689
21d40d37 2690 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
79e53945 2691
21d40d37 2692 drm_mode_connector_attach_encoder(&intel_encoder->base, &intel_encoder->enc);
d0cbde93 2693 if (sdvo_priv->is_tv)
ce6feabd 2694 intel_sdvo_tv_create_property(connector);
d0cbde93
ZY		 2695
2696 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
b9219c5e 2697 intel_sdvo_create_enhance_property(connector);
d0cbde93 2698
79e53945
JB		 2699 drm_sysfs_connector_add(connector);
2700
e2f0ba97
JB		 2701 intel_sdvo_select_ddc_bus(sdvo_priv);
2702
79e53945 2703 /* Set the input timing to the screen. Assume always input 0. */
21d40d37 2704 intel_sdvo_set_target_input(intel_encoder, true, false);
79e53945 2705
21d40d37 2706 intel_sdvo_get_input_pixel_clock_range(intel_encoder,
79e53945
JB		 2707 &sdvo_priv->pixel_clock_min,
2708 &sdvo_priv->pixel_clock_max);
2709
2710
8a4c47f3 2711 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2712 "clock range %dMHz - %dMHz, "
2713 "input 1: %c, input 2: %c, "
2714 "output 1: %c, output 2: %c\n",
2715 SDVO_NAME(sdvo_priv),
2716 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2717 sdvo_priv->caps.device_rev_id,
2718 sdvo_priv->pixel_clock_min / 1000,
2719 sdvo_priv->pixel_clock_max / 1000,
2720 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2721 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2722 /* check currently supported outputs */
2723 sdvo_priv->caps.output_flags &
79e53945 2724 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
342dc382 2725 sdvo_priv->caps.output_flags &
79e53945
JB		 2726 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2727
7d57382e 2728 return true;
79e53945
JB		 2729
2730err_i2c:
57cdaf90
KP		 2731 if (sdvo_priv->analog_ddc_bus != NULL)
2732 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
21d40d37
EA		 2733 if (intel_encoder->ddc_bus != NULL)
2734 intel_i2c_destroy(intel_encoder->ddc_bus);
2735 if (intel_encoder->i2c_bus != NULL)
2736 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2737err_inteloutput:
21d40d37 2738 kfree(intel_encoder);
79e53945 2739
7d57382e 2740 return false;
79e53945 2741}
Linux kernel - Deliverables
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