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drm/i915: clean up pipe bpp confusion
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
83 * i830_sdvo_get_capabilities()
84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
890f3359 205static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 206{
4ef69c7a 207 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
212 return container_of(intel_attached_encoder(connector),
213 struct intel_sdvo, base);
214}
215
615fb93f
CW		 216static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
217{
218 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
219}
220
fb7a46f3 221static bool
ea5b213a 222intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 223static bool
224intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
225 struct intel_sdvo_connector *intel_sdvo_connector,
226 int type);
227static bool
228intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
229 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 230
79e53945
JB		 231/**
232 * Writes the SDVOB or SDVOC with the given value, but always writes both
233 * SDVOB and SDVOC to work around apparent hardware issues (according to
234 * comments in the BIOS).
235 */
ea5b213a 236static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 237{
4ef69c7a 238 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 239 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 240 u32 bval = val, cval = val;
241 int i;
242
ea5b213a
CW		 243 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
244 I915_WRITE(intel_sdvo->sdvo_reg, val);
245 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 246 return;
247 }
248
e2debe91
PZ		 249 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
250 cval = I915_READ(GEN3_SDVOC);
251 else
252 bval = I915_READ(GEN3_SDVOB);
253
79e53945
JB		 254 /*
255 * Write the registers twice for luck. Sometimes,
256 * writing them only once doesn't appear to 'stick'.
257 * The BIOS does this too. Yay, magic
258 */
259 for (i = 0; i < 2; i++)
260 {
e2debe91
PZ		 261 I915_WRITE(GEN3_SDVOB, bval);
262 I915_READ(GEN3_SDVOB);
263 I915_WRITE(GEN3_SDVOC, cval);
264 I915_READ(GEN3_SDVOC);
79e53945
JB		 265 }
266}
267
32aad86f 268static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 269{
79e53945
JB		 270 struct i2c_msg msgs[] = {
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = 0,
274 .len = 1,
e957d772 275 .buf = &addr,
79e53945
JB		 276 },
277 {
e957d772 278 .addr = intel_sdvo->slave_addr,
79e53945
JB		 279 .flags = I2C_M_RD,
280 .len = 1,
e957d772 281 .buf = ch,
79e53945
JB		 282 }
283 };
32aad86f 284 int ret;
79e53945 285
f899fc64 286 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 287 return true;
79e53945 288
8a4c47f3 289 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 290 return false;
291}
292
79e53945
JB		 293#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
294/** Mapping of command numbers to names, for debug output */
005568be 295static const struct _sdvo_cmd_name {
e2f0ba97 296 u8 cmd;
2e88e40b 297 const char *name;
79e53945 298} sdvo_cmd_names[] = {
0206e353
AJ		 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
342
343 /* Add the op code for SDVO enhancements */
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
388
389 /* HDMI op code */
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 410};
411
eef4eacb 412#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 413
ea5b213a 414static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 415 const void *args, int args_len)
79e53945 416{
79e53945
JB		 417 int i;
418
8a4c47f3 419 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 420 SDVO_NAME(intel_sdvo), cmd);
79e53945 421 for (i = 0; i < args_len; i++)
342dc382 422 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 423 for (; i < 8; i++)
342dc382 424 DRM_LOG_KMS(" ");
04ad327f 425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 426 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 427 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 428 break;
429 }
430 }
04ad327f 431 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 432 DRM_LOG_KMS("(%02X)", cmd);
433 DRM_LOG_KMS("\n");
79e53945 434}
79e53945 435
e957d772
CW		 436static const char *cmd_status_names[] = {
437 "Power on",
438 "Success",
439 "Not supported",
440 "Invalid arg",
441 "Pending",
442 "Target not specified",
443 "Scaling not supported"
444};
445
32aad86f
CW		 446static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
447 const void *args, int args_len)
79e53945 448{
3bf3f452
BW		 449 u8 *buf, status;
450 struct i2c_msg *msgs;
451 int i, ret = true;
452
0274df3e 453 /* Would be simpler to allocate both in one go ? */
5c67eeb6 454 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 455 if (!buf)
456 return false;
457
458 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 459 if (!msgs) {
460 kfree(buf);
3bf3f452 461 return false;
0274df3e 462 }
79e53945 463
ea5b213a 464 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 465
466 for (i = 0; i < args_len; i++) {
e957d772
CW		 467 msgs[i].addr = intel_sdvo->slave_addr;
468 msgs[i].flags = 0;
469 msgs[i].len = 2;
470 msgs[i].buf = buf + 2 *i;
471 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
472 buf[2*i + 1] = ((u8*)args)[i];
473 }
474 msgs[i].addr = intel_sdvo->slave_addr;
475 msgs[i].flags = 0;
476 msgs[i].len = 2;
477 msgs[i].buf = buf + 2*i;
478 buf[2*i + 0] = SDVO_I2C_OPCODE;
479 buf[2*i + 1] = cmd;
480
481 /* the following two are to read the response */
482 status = SDVO_I2C_CMD_STATUS;
483 msgs[i+1].addr = intel_sdvo->slave_addr;
484 msgs[i+1].flags = 0;
485 msgs[i+1].len = 1;
486 msgs[i+1].buf = &status;
487
488 msgs[i+2].addr = intel_sdvo->slave_addr;
489 msgs[i+2].flags = I2C_M_RD;
490 msgs[i+2].len = 1;
491 msgs[i+2].buf = &status;
492
493 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
494 if (ret < 0) {
495 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 496 ret = false;
497 goto out;
e957d772
CW		 498 }
499 if (ret != i+3) {
500 /* failure in I2C transfer */
501 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 502 ret = false;
e957d772
CW		 503 }
504
3bf3f452
BW		 505out:
506 kfree(msgs);
507 kfree(buf);
508 return ret;
79e53945
JB		 509}
510
b5c616a7
CW		 511static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
512 void *response, int response_len)
79e53945 513{
fc37381c 514 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 515 u8 status;
33b52961 516 int i;
79e53945 517
d121a5d2
CW		 518 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
519
b5c616a7
CW		 520 /*
521 * The documentation states that all commands will be
522 * processed within 15µs, and that we need only poll
523 * the status byte a maximum of 3 times in order for the
524 * command to be complete.
525 *
526 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 527 *
528 * Also beware that the first response by many devices is to
529 * reply PENDING and stall for time. TVs are notorious for
530 * requiring longer than specified to complete their replies.
531 * Originally (in the DDX long ago), the delay was only ever 15ms
532 * with an additional delay of 30ms applied for TVs added later after
533 * many experiments. To accommodate both sets of delays, we do a
534 * sequence of slow checks if the device is falling behind and fails
535 * to reply within 5*15µs.
b5c616a7 536 */
d121a5d2
CW		 537 if (!intel_sdvo_read_byte(intel_sdvo,
538 SDVO_I2C_CMD_STATUS,
539 &status))
540 goto log_fail;
541
fc37381c
CW		 542 while (status == SDVO_CMD_STATUS_PENDING && --retry) {
543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
b5c616a7
CW		 548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
d121a5d2
CW		 551 goto log_fail;
552 }
b5c616a7 553
79e53945 554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 556 else
342dc382 557 DRM_LOG_KMS("(??? %d)", status);
79e53945 558
b5c616a7
CW		 559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
79e53945 561
b5c616a7
CW		 562 /* Read the command response */
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
e957d772 568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 569 }
b5c616a7 570 DRM_LOG_KMS("\n");
b5c616a7 571 return true;
79e53945 572
b5c616a7 573log_fail:
d121a5d2 574 DRM_LOG_KMS("... failed\n");
b5c616a7 575 return false;
79e53945
JB		 576}
577
b358d0a6 578static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 579{
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586}
587
e957d772
CW		 588static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
79e53945 590{
d121a5d2 591 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
79e53945
JB		 595}
596
32aad86f 597static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 598{
d121a5d2
CW		 599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 603}
79e53945 604
32aad86f
CW		 605static bool
606intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607{
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
79e53945 610
32aad86f
CW		 611 return intel_sdvo_read_response(intel_sdvo, value, len);
612}
79e53945 613
32aad86f
CW		 614static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615{
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
79e53945
JB		 620}
621
622/**
623 * Return whether each input is trained.
624 *
625 * This function is making an assumption about the layout of the response,
626 * which should be checked against the docs.
627 */
ea5b213a 628static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 629{
630 struct intel_sdvo_get_trained_inputs_response response;
79e53945 631
1a3665c8 632 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
79e53945
JB		 635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640}
641
ea5b213a 642static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 643 u16 outputs)
644{
32aad86f
CW		 645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
79e53945
JB		 648}
649
4ac41f47
DV		 650static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652{
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656}
657
ea5b213a 658static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 659 int mode)
660{
32aad86f 661 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
32aad86f
CW		 678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 680}
681
ea5b213a 682static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int *clock_min,
684 int *clock_max)
685{
686 struct intel_sdvo_pixel_clock_range clocks;
79e53945 687
1a3665c8 688 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
79e53945
JB		 692 return false;
693
694 /* Convert the values from units of 10 kHz to kHz. */
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
79e53945
JB		 697 return true;
698}
699
ea5b213a 700static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 701 u16 outputs)
702{
32aad86f
CW		 703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
79e53945
JB		 706}
707
ea5b213a 708static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 709 struct intel_sdvo_dtd *dtd)
710{
32aad86f
CW		 711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 713}
714
ea5b213a 715static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 716 struct intel_sdvo_dtd *dtd)
717{
ea5b213a 718 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 719 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
720}
721
ea5b213a 722static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 723 struct intel_sdvo_dtd *dtd)
724{
ea5b213a 725 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 726 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
727}
728
e2f0ba97 729static bool
ea5b213a 730intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 731 uint16_t clock,
732 uint16_t width,
733 uint16_t height)
734{
735 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 736
e642c6f1 737 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 738 args.clock = clock;
739 args.width = width;
740 args.height = height;
e642c6f1 741 args.interlace = 0;
12682a97 742
ea5b213a
CW		 743 if (intel_sdvo->is_lvds &&
744 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
745 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 746 args.scaled = 1;
747
32aad86f
CW		 748 return intel_sdvo_set_value(intel_sdvo,
749 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
750 &args, sizeof(args));
e2f0ba97
JB		 751}
752
ea5b213a 753static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 754 struct intel_sdvo_dtd *dtd)
755{
1a3665c8
CW		 756 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
757 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 758 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
759 &dtd->part1, sizeof(dtd->part1)) &&
760 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
761 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 762}
79e53945 763
ea5b213a 764static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 765{
32aad86f 766 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 767}
768
e2f0ba97 769static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 770 const struct drm_display_mode *mode)
79e53945 771{
e2f0ba97
JB		 772 uint16_t width, height;
773 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
774 uint16_t h_sync_offset, v_sync_offset;
6651819b 775 int mode_clock;
79e53945 776
c6ebd4c0
DV		 777 width = mode->hdisplay;
778 height = mode->vdisplay;
79e53945
JB		 779
780 /* do some mode translations */
c6ebd4c0
DV		 781 h_blank_len = mode->htotal - mode->hdisplay;
782 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 783
c6ebd4c0
DV		 784 v_blank_len = mode->vtotal - mode->vdisplay;
785 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 786
c6ebd4c0
DV		 787 h_sync_offset = mode->hsync_start - mode->hdisplay;
788 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 789
6651819b 790 mode_clock = mode->clock;
6651819b
DV		 791 mode_clock /= 10;
792 dtd->part1.clock = mode_clock;
793
e2f0ba97
JB		 794 dtd->part1.h_active = width & 0xff;
795 dtd->part1.h_blank = h_blank_len & 0xff;
796 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 797 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 798 dtd->part1.v_active = height & 0xff;
799 dtd->part1.v_blank = v_blank_len & 0xff;
800 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 801 ((v_blank_len >> 8) & 0xf);
802
171a9e96 803 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 804 dtd->part2.h_sync_width = h_sync_len & 0xff;
805 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 806 (v_sync_len & 0xf);
e2f0ba97 807 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 808 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
809 ((v_sync_len & 0x30) >> 4);
810
e2f0ba97 811 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 812 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
813 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 814 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 815 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 816 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 817 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 818
819 dtd->part2.sdvo_flags = 0;
820 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
821 dtd->part2.reserved = 0;
822}
823
824static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 825 const struct intel_sdvo_dtd *dtd)
e2f0ba97 826{
e2f0ba97
JB		 827 mode->hdisplay = dtd->part1.h_active;
828 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
829 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 830 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 831 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
832 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
833 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
834 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
835
836 mode->vdisplay = dtd->part1.v_active;
837 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
838 mode->vsync_start = mode->vdisplay;
839 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 840 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 841 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
842 mode->vsync_end = mode->vsync_start +
843 (dtd->part2.v_sync_off_width & 0xf);
844 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
845 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
846 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
847
848 mode->clock = dtd->part1.clock * 10;
849
171a9e96 850 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 851 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
852 mode->flags |= DRM_MODE_FLAG_INTERLACE;
853 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 854 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 855 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 856 mode->flags |= DRM_MODE_FLAG_PVSYNC;
857}
858
e27d8538 859static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 860{
e27d8538 861 struct intel_sdvo_encode encode;
e2f0ba97 862
1a3665c8 863 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 864 return intel_sdvo_get_value(intel_sdvo,
865 SDVO_CMD_GET_SUPP_ENCODE,
866 &encode, sizeof(encode));
e2f0ba97
JB		 867}
868
ea5b213a 869static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 870 uint8_t mode)
e2f0ba97 871{
32aad86f 872 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 873}
874
ea5b213a 875static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 876 uint8_t mode)
877{
32aad86f 878 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 879}
880
881#if 0
ea5b213a 882static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 883{
884 int i, j;
885 uint8_t set_buf_index[2];
886 uint8_t av_split;
887 uint8_t buf_size;
888 uint8_t buf[48];
889 uint8_t *pos;
890
32aad86f 891 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 892
893 for (i = 0; i <= av_split; i++) {
894 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 895 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 896 set_buf_index, 2);
c751ce4f
EA		 897 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
898 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 899
900 pos = buf;
901 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 902 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 903 NULL, 0);
c751ce4f 904 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 905 pos += 8;
906 }
907 }
908}
909#endif
910
b6e0e543
DV		 911static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
912 unsigned if_index, uint8_t tx_rate,
913 uint8_t *data, unsigned length)
914{
915 uint8_t set_buf_index[2] = { if_index, 0 };
916 uint8_t hbuf_size, tmp[8];
917 int i;
918
919 if (!intel_sdvo_set_value(intel_sdvo,
920 SDVO_CMD_SET_HBUF_INDEX,
921 set_buf_index, 2))
922 return false;
923
924 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
925 &hbuf_size, 1))
926 return false;
927
928 /* Buffer size is 0 based, hooray! */
929 hbuf_size++;
930
931 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
932 if_index, length, hbuf_size);
933
934 for (i = 0; i < hbuf_size; i += 8) {
935 memset(tmp, 0, 8);
936 if (i < length)
937 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
938
939 if (!intel_sdvo_set_value(intel_sdvo,
940 SDVO_CMD_SET_HBUF_DATA,
941 tmp, 8))
942 return false;
943 }
944
945 return intel_sdvo_set_value(intel_sdvo,
946 SDVO_CMD_SET_HBUF_TXRATE,
947 &tx_rate, 1);
948}
949
abedc077
VS		 950static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
951 const struct drm_display_mode *adjusted_mode)
e2f0ba97
JB		 952{
953 struct dip_infoframe avi_if = {
954 .type = DIP_TYPE_AVI,
3c17fe4b 955 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 956 .len = DIP_LEN_AVI,
957 };
81014b9d 958 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
50f3b016 959 struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
3c17fe4b 960
abedc077 961 if (intel_sdvo->rgb_quant_range_selectable) {
50f3b016 962 if (intel_crtc->config.limited_color_range)
abedc077
VS		 963 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
964 else
965 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
966 }
967
96b219fa
VS		 968 avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
969
3c17fe4b
DH		 970 intel_dip_infoframe_csum(&avi_if);
971
81014b9d
DV		 972 /* sdvo spec says that the ecc is handled by the hw, and it looks like
973 * we must not send the ecc field, either. */
974 memcpy(sdvo_data, &avi_if, 3);
975 sdvo_data[3] = avi_if.checksum;
976 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
977
b6e0e543
DV		 978 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
979 SDVO_HBUF_TX_VSYNC,
980 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 981}
982
32aad86f 983static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 984{
ce6feabd 985 struct intel_sdvo_tv_format format;
40039750 986 uint32_t format_map;
ce6feabd 987
40039750 988 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 989 memset(&format, 0, sizeof(format));
32aad86f 990 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 991
32aad86f
CW		 992 BUILD_BUG_ON(sizeof(format) != 6);
993 return intel_sdvo_set_value(intel_sdvo,
994 SDVO_CMD_SET_TV_FORMAT,
995 &format, sizeof(format));
7026d4ac
ZW		 996}
997
32aad86f
CW		 998static bool
999intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1000 const struct drm_display_mode *mode)
e2f0ba97 1001{
32aad86f 1002 struct intel_sdvo_dtd output_dtd;
79e53945 1003
32aad86f
CW		 1004 if (!intel_sdvo_set_target_output(intel_sdvo,
1005 intel_sdvo->attached_output))
1006 return false;
e2f0ba97 1007
32aad86f
CW		 1008 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1009 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1010 return false;
e2f0ba97 1011
32aad86f
CW		 1012 return true;
1013}
1014
c9a29698
DV		 1015/* Asks the sdvo controller for the preferred input mode given the output mode.
1016 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1017static bool
c9a29698 1018intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1019 const struct drm_display_mode *mode,
c9a29698 1020 struct drm_display_mode *adjusted_mode)
32aad86f 1021{
c9a29698
DV		 1022 struct intel_sdvo_dtd input_dtd;
1023
32aad86f
CW		 1024 /* Reset the input timing to the screen. Assume always input 0. */
1025 if (!intel_sdvo_set_target_input(intel_sdvo))
1026 return false;
e2f0ba97 1027
32aad86f
CW		 1028 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1029 mode->clock / 10,
1030 mode->hdisplay,
1031 mode->vdisplay))
1032 return false;
e2f0ba97 1033
32aad86f 1034 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1035 &input_dtd))
32aad86f 1036 return false;
e2f0ba97 1037
c9a29698 1038 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1039 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1040
32aad86f
CW		 1041 return true;
1042}
12682a97 1043
6cc5f341
DV		 1044static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1045 struct intel_crtc_config *pipe_config)
32aad86f 1046{
6cc5f341
DV		 1047 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1048 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1049 struct drm_display_mode *mode = &pipe_config->requested_mode;
12682a97 1050
5d2d38dd
DV		 1051 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1052 pipe_config->pipe_bpp = 8*3;
1053
5bfe2ac0
DV		 1054 if (HAS_PCH_SPLIT(encoder->base.dev))
1055 pipe_config->has_pch_encoder = true;
1056
32aad86f
CW		 1057 /* We need to construct preferred input timings based on our
1058 * output timings. To do that, we have to set the output
1059 * timings, even though this isn't really the right place in
1060 * the sequence to do it. Oh well.
1061 */
1062 if (intel_sdvo->is_tv) {
1063 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1064 return false;
12682a97 1065
c9a29698
DV		 1066 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1067 mode,
1068 adjusted_mode);
ea5b213a 1069 } else if (intel_sdvo->is_lvds) {
32aad86f 1070 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1071 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1072 return false;
12682a97 1073
c9a29698
DV		 1074 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1075 mode,
1076 adjusted_mode);
e2f0ba97 1077 }
32aad86f
CW		 1078
1079 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1080 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1081 */
6cc5f341
DV		 1082 pipe_config->pixel_multiplier =
1083 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1084 adjusted_mode->clock *= pipe_config->pixel_multiplier;
32aad86f 1085
55bc60db
VS		 1086 if (intel_sdvo->color_range_auto) {
1087 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1088 /* FIXME: This bit is only valid when using TMDS encoding and 8
1089 * bit per color mode. */
55bc60db 1090 if (intel_sdvo->has_hdmi_monitor &&
18316c8c 1091 drm_match_cea_mode(adjusted_mode) > 1)
4f3a8bc7 1092 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1093 else
1094 intel_sdvo->color_range = 0;
1095 }
1096
3685a8f3 1097 if (intel_sdvo->color_range)
50f3b016 1098 pipe_config->limited_color_range = true;
3685a8f3 1099
e2f0ba97
JB		 1100 return true;
1101}
1102
6cc5f341 1103static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
e2f0ba97 1104{
6cc5f341 1105 struct drm_device *dev = intel_encoder->base.dev;
e2f0ba97 1106 struct drm_i915_private *dev_priv = dev->dev_private;
6cc5f341 1107 struct drm_crtc *crtc = intel_encoder->base.crtc;
e2f0ba97 1108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 1109 struct drm_display_mode *adjusted_mode =
1110 &intel_crtc->config.adjusted_mode;
1111 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
1112 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
6c9547ff 1113 u32 sdvox;
e2f0ba97 1114 struct intel_sdvo_in_out_map in_out;
6651819b 1115 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1116 int rate;
e2f0ba97
JB		 1117
1118 if (!mode)
1119 return;
1120
1121 /* First, set the input mapping for the first input to our controlled
1122 * output. This is only correct if we're a single-input device, in
1123 * which case the first input is the output from the appropriate SDVO
1124 * channel on the motherboard. In a two-input device, the first input
1125 * will be SDVOB and the second SDVOC.
1126 */
ea5b213a 1127 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1128 in_out.in1 = 0;
1129
c74696b9
PR		 1130 intel_sdvo_set_value(intel_sdvo,
1131 SDVO_CMD_SET_IN_OUT_MAP,
1132 &in_out, sizeof(in_out));
e2f0ba97 1133
6c9547ff
CW		 1134 /* Set the output timings to the screen */
1135 if (!intel_sdvo_set_target_output(intel_sdvo,
1136 intel_sdvo->attached_output))
1137 return;
e2f0ba97 1138
6651819b
DV		 1139 /* lvds has a special fixed output timing. */
1140 if (intel_sdvo->is_lvds)
1141 intel_sdvo_get_dtd_from_mode(&output_dtd,
1142 intel_sdvo->sdvo_lvds_fixed_mode);
1143 else
1144 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1145 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1146 DRM_INFO("Setting output timings on %s failed\n",
1147 SDVO_NAME(intel_sdvo));
79e53945
JB		 1148
1149 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1150 if (!intel_sdvo_set_target_input(intel_sdvo))
1151 return;
79e53945 1152
97aaf910
CW		 1153 if (intel_sdvo->has_hdmi_monitor) {
1154 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1155 intel_sdvo_set_colorimetry(intel_sdvo,
1156 SDVO_COLORIMETRY_RGB256);
abedc077 1157 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1158 } else
1159 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1160
6c9547ff
CW		 1161 if (intel_sdvo->is_tv &&
1162 !intel_sdvo_set_tv_format(intel_sdvo))
1163 return;
e2f0ba97 1164
6651819b
DV		 1165 /* We have tried to get input timing in mode_fixup, and filled into
1166 * adjusted_mode.
1167 */
1168 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
e751823d
EE		 1169 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1170 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1171 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1172 DRM_INFO("Setting input timings on %s failed\n",
1173 SDVO_NAME(intel_sdvo));
79e53945 1174
6cc5f341 1175 switch (intel_crtc->config.pixel_multiplier) {
6c9547ff 1176 default:
32aad86f
CW		 1177 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1178 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1179 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1180 }
32aad86f
CW		 1181 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1182 return;
79e53945
JB		 1183
1184 /* Set the SDVO control regs. */
a6c45cf0 1185 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1186 /* The real mode polarity is set by the SDVO commands, using
1187 * struct intel_sdvo_dtd. */
1188 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1189 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1190 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1191 if (INTEL_INFO(dev)->gen < 5)
1192 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1193 } else {
6c9547ff 1194 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1195 switch (intel_sdvo->sdvo_reg) {
e2debe91 1196 case GEN3_SDVOB:
e2f0ba97
JB		 1197 sdvox &= SDVOB_PRESERVE_MASK;
1198 break;
e2debe91 1199 case GEN3_SDVOC:
e2f0ba97
JB		 1200 sdvox &= SDVOC_PRESERVE_MASK;
1201 break;
1202 }
1203 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1204 }
3573c410
PZ		 1205
1206 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
dc0fa718 1207 sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
3573c410 1208 else
dc0fa718 1209 sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
3573c410 1210
da79de97 1211 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1212 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1213
a6c45cf0 1214 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1215 /* done in crtc_mode_set as the dpll_md reg must be written early */
1216 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1217 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1218 } else {
6cc5f341
DV		 1219 sdvox |= (intel_crtc->config.pixel_multiplier - 1)
1220 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1221 }
1222
6714afb1
CW		 1223 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1224 INTEL_INFO(dev)->gen < 5)
12682a97 1225 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1226 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1227}
1228
4ac41f47 1229static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1230{
4ac41f47
DV		 1231 struct intel_sdvo_connector *intel_sdvo_connector =
1232 to_intel_sdvo_connector(&connector->base);
1233 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1234 u16 active_outputs;
1235
1236 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1237
1238 if (active_outputs & intel_sdvo_connector->output_flag)
1239 return true;
1240 else
1241 return false;
1242}
1243
1244static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1245 enum pipe *pipe)
1246{
1247 struct drm_device *dev = encoder->base.dev;
79e53945 1248 struct drm_i915_private *dev_priv = dev->dev_private;
4ac41f47
DV		 1249 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1250 u32 tmp;
1251
1252 tmp = I915_READ(intel_sdvo->sdvo_reg);
1253
1254 if (!(tmp & SDVO_ENABLE))
1255 return false;
1256
1257 if (HAS_PCH_CPT(dev))
1258 *pipe = PORT_TO_PIPE_CPT(tmp);
1259 else
1260 *pipe = PORT_TO_PIPE(tmp);
1261
1262 return true;
1263}
1264
ce22c320
DV		 1265static void intel_disable_sdvo(struct intel_encoder *encoder)
1266{
1267 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1268 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1269 u32 temp;
1270
1271 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1272 if (0)
1273 intel_sdvo_set_encoder_power_state(intel_sdvo,
1274 DRM_MODE_DPMS_OFF);
1275
1276 temp = I915_READ(intel_sdvo->sdvo_reg);
1277 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1278 /* HW workaround for IBX, we need to move the port to
1279 * transcoder A before disabling it. */
1280 if (HAS_PCH_IBX(encoder->base.dev)) {
1281 struct drm_crtc *crtc = encoder->base.crtc;
1282 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1283
1284 if (temp & SDVO_PIPE_B_SELECT) {
1285 temp &= ~SDVO_PIPE_B_SELECT;
1286 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1287 POSTING_READ(intel_sdvo->sdvo_reg);
1288
1289 /* Again we need to write this twice. */
1290 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1291 POSTING_READ(intel_sdvo->sdvo_reg);
1292
1293 /* Transcoder selection bits only update
1294 * effectively on vblank. */
1295 if (crtc)
1296 intel_wait_for_vblank(encoder->base.dev, pipe);
1297 else
1298 msleep(50);
1299 }
1300 }
1301
ce22c320
DV		 1302 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1303 }
1304}
1305
1306static void intel_enable_sdvo(struct intel_encoder *encoder)
1307{
1308 struct drm_device *dev = encoder->base.dev;
1309 struct drm_i915_private *dev_priv = dev->dev_private;
1310 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1311 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1312 u32 temp;
ce22c320
DV		 1313 bool input1, input2;
1314 int i;
1315 u8 status;
1316
1317 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1318 if ((temp & SDVO_ENABLE) == 0) {
1319 /* HW workaround for IBX, we need to move the port
dc0fa718
PZ		 1320 * to transcoder A before disabling it, so restore it here. */
1321 if (HAS_PCH_IBX(dev))
1322 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
776ca7cf 1323
ce22c320 1324 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1325 }
ce22c320
DV		 1326 for (i = 0; i < 2; i++)
1327 intel_wait_for_vblank(dev, intel_crtc->pipe);
1328
1329 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1330 /* Warn if the device reported failure to sync.
1331 * A lot of SDVO devices fail to notify of sync, but it's
1332 * a given it the status is a success, we succeeded.
1333 */
1334 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1335 DRM_DEBUG_KMS("First %s output reported failure to "
1336 "sync\n", SDVO_NAME(intel_sdvo));
1337 }
1338
1339 if (0)
1340 intel_sdvo_set_encoder_power_state(intel_sdvo,
1341 DRM_MODE_DPMS_ON);
1342 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1343}
1344
b2cabb0e 1345static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1346{
b2cabb0e
DV		 1347 struct drm_crtc *crtc;
1348 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1349
1350 /* dvo supports only 2 dpms states. */
1351 if (mode != DRM_MODE_DPMS_ON)
1352 mode = DRM_MODE_DPMS_OFF;
1353
1354 if (mode == connector->dpms)
1355 return;
1356
1357 connector->dpms = mode;
1358
1359 /* Only need to change hw state when actually enabled */
1360 crtc = intel_sdvo->base.base.crtc;
1361 if (!crtc) {
1362 intel_sdvo->base.connectors_active = false;
1363 return;
1364 }
79e53945
JB		 1365
1366 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1367 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1368 if (0)
ea5b213a 1369 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1370
b2cabb0e
DV		 1371 intel_sdvo->base.connectors_active = false;
1372
1373 intel_crtc_update_dpms(crtc);
79e53945 1374 } else {
b2cabb0e
DV		 1375 intel_sdvo->base.connectors_active = true;
1376
1377 intel_crtc_update_dpms(crtc);
79e53945
JB		 1378
1379 if (0)
ea5b213a
CW		 1380 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1381 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1382 }
0a91ca29 1383
b980514c 1384 intel_modeset_check_state(connector->dev);
79e53945
JB		 1385}
1386
79e53945
JB		 1387static int intel_sdvo_mode_valid(struct drm_connector *connector,
1388 struct drm_display_mode *mode)
1389{
df0e9248 1390 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1391
1392 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1393 return MODE_NO_DBLESCAN;
1394
ea5b213a 1395 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1396 return MODE_CLOCK_LOW;
1397
ea5b213a 1398 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1399 return MODE_CLOCK_HIGH;
1400
8545423a 1401 if (intel_sdvo->is_lvds) {
ea5b213a 1402 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1403 return MODE_PANEL;
1404
ea5b213a 1405 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1406 return MODE_PANEL;
1407 }
1408
79e53945
JB		 1409 return MODE_OK;
1410}
1411
ea5b213a 1412static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1413{
1a3665c8 1414 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1415 if (!intel_sdvo_get_value(intel_sdvo,
1416 SDVO_CMD_GET_DEVICE_CAPS,
1417 caps, sizeof(*caps)))
1418 return false;
1419
1420 DRM_DEBUG_KMS("SDVO capabilities:\n"
1421 " vendor_id: %d\n"
1422 " device_id: %d\n"
1423 " device_rev_id: %d\n"
1424 " sdvo_version_major: %d\n"
1425 " sdvo_version_minor: %d\n"
1426 " sdvo_inputs_mask: %d\n"
1427 " smooth_scaling: %d\n"
1428 " sharp_scaling: %d\n"
1429 " up_scaling: %d\n"
1430 " down_scaling: %d\n"
1431 " stall_support: %d\n"
1432 " output_flags: %d\n",
1433 caps->vendor_id,
1434 caps->device_id,
1435 caps->device_rev_id,
1436 caps->sdvo_version_major,
1437 caps->sdvo_version_minor,
1438 caps->sdvo_inputs_mask,
1439 caps->smooth_scaling,
1440 caps->sharp_scaling,
1441 caps->up_scaling,
1442 caps->down_scaling,
1443 caps->stall_support,
1444 caps->output_flags);
1445
1446 return true;
79e53945
JB		 1447}
1448
5fa7ac9c 1449static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1450{
768b107e 1451 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1452 uint16_t hotplug;
79e53945 1453
768b107e
DV		 1454 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1455 * on the line. */
1456 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1457 return 0;
768b107e 1458
5fa7ac9c
JN		 1459 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1460 &hotplug, sizeof(hotplug)))
1461 return 0;
768b107e 1462
5fa7ac9c 1463 return hotplug;
79e53945
JB		 1464}
1465
cc68c81a 1466static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1467{
cc68c81a 1468 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1469
5fa7ac9c
JN		 1470 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1471 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1472}
1473
fb7a46f3 1474static bool
ea5b213a 1475intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1476{
bc65212c 1477 /* Is there more than one type of output? */
2294488d 1478 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1479}
1480
f899fc64 1481static struct edid *
e957d772 1482intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1483{
e957d772
CW		 1484 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1485 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1486}
1487
ff482d83
CW		 1488/* Mac mini hack -- use the same DDC as the analog connector */
1489static struct edid *
1490intel_sdvo_get_analog_edid(struct drm_connector *connector)
1491{
f899fc64 1492 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1493
0c1dab89 1494 return drm_get_edid(connector,
3bd7d909
DK		 1495 intel_gmbus_get_adapter(dev_priv,
1496 dev_priv->crt_ddc_pin));
ff482d83
CW		 1497}
1498
c43b5634 1499static enum drm_connector_status
8bf38485 1500intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1501{
df0e9248 1502 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1503 enum drm_connector_status status;
1504 struct edid *edid;
9dff6af8 1505
e957d772 1506 edid = intel_sdvo_get_edid(connector);
57cdaf90 1507
ea5b213a 1508 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1509 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1510
7c3f0a27
ZY		 1511 /*
1512 * Don't use the 1 as the argument of DDC bus switch to get
1513 * the EDID. It is used for SDVO SPD ROM.
1514 */
9d1a903d 1515 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1516 intel_sdvo->ddc_bus = ddc;
1517 edid = intel_sdvo_get_edid(connector);
1518 if (edid)
7c3f0a27 1519 break;
7c3f0a27 1520 }
e957d772
CW		 1521 /*
1522 * If we found the EDID on the other bus,
1523 * assume that is the correct DDC bus.
1524 */
1525 if (edid == NULL)
1526 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1527 }
9d1a903d
CW		 1528
1529 /*
1530 * When there is no edid and no monitor is connected with VGA
1531 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1532 */
ff482d83
CW		 1533 if (edid == NULL)
1534 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1535
2f551c84 1536 status = connector_status_unknown;
9dff6af8 1537 if (edid != NULL) {
149c36a3 1538 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1539 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1540 status = connector_status_connected;
da79de97
CW		 1541 if (intel_sdvo->is_hdmi) {
1542 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1543 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1544 intel_sdvo->rgb_quant_range_selectable =
1545 drm_rgb_quant_range_selectable(edid);
da79de97 1546 }
13946743
CW		 1547 } else
1548 status = connector_status_disconnected;
9d1a903d
CW		 1549 kfree(edid);
1550 }
7f36e7ed
CW		 1551
1552 if (status == connector_status_connected) {
1553 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1554 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1555 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1556 }
1557
2b8d33f7 1558 return status;
9dff6af8
ML		 1559}
1560
52220085
CW		 1561static bool
1562intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1563 struct edid *edid)
1564{
1565 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1566 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1567
1568 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1569 connector_is_digital, monitor_is_digital);
1570 return connector_is_digital == monitor_is_digital;
1571}
1572
7b334fcb 1573static enum drm_connector_status
930a9e28 1574intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1575{
fb7a46f3 1576 uint16_t response;
df0e9248 1577 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1578 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1579 enum drm_connector_status ret;
79e53945 1580
fc37381c
CW		 1581 if (!intel_sdvo_get_value(intel_sdvo,
1582 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1583 &response, 2))
32aad86f 1584 return connector_status_unknown;
79e53945 1585
e957d772
CW		 1586 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1587 response & 0xff, response >> 8,
1588 intel_sdvo_connector->output_flag);
e2f0ba97 1589
fb7a46f3 1590 if (response == 0)
79e53945 1591 return connector_status_disconnected;
fb7a46f3 1592
ea5b213a 1593 intel_sdvo->attached_output = response;
14571b4c 1594
97aaf910
CW		 1595 intel_sdvo->has_hdmi_monitor = false;
1596 intel_sdvo->has_hdmi_audio = false;
abedc077 1597 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1598
615fb93f 1599 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1600 ret = connector_status_disconnected;
13946743 1601 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1602 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1603 else {
1604 struct edid *edid;
1605
1606 /* if we have an edid check it matches the connection */
1607 edid = intel_sdvo_get_edid(connector);
1608 if (edid == NULL)
1609 edid = intel_sdvo_get_analog_edid(connector);
1610 if (edid != NULL) {
52220085
CW		 1611 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1612 edid))
13946743 1613 ret = connector_status_connected;
52220085
CW		 1614 else
1615 ret = connector_status_disconnected;
1616
13946743
CW		 1617 kfree(edid);
1618 } else
1619 ret = connector_status_connected;
1620 }
14571b4c
ZW		 1621
1622 /* May update encoder flag for like clock for SDVO TV, etc.*/
1623 if (ret == connector_status_connected) {
ea5b213a
CW		 1624 intel_sdvo->is_tv = false;
1625 intel_sdvo->is_lvds = false;
1626 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1627
1628 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1629 intel_sdvo->is_tv = true;
1630 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1631 }
1632 if (response & SDVO_LVDS_MASK)
8545423a 1633 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1634 }
14571b4c
ZW		 1635
1636 return ret;
79e53945
JB		 1637}
1638
e2f0ba97 1639static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1640{
ff482d83 1641 struct edid *edid;
79e53945
JB		 1642
1643 /* set the bus switch and get the modes */
e957d772 1644 edid = intel_sdvo_get_edid(connector);
79e53945 1645
57cdaf90
KP		 1646 /*
1647 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1648 * link between analog and digital outputs. So, if the regular SDVO
1649 * DDC fails, check to see if the analog output is disconnected, in
1650 * which case we'll look there for the digital DDC data.
e2f0ba97 1651 */
f899fc64
CW		 1652 if (edid == NULL)
1653 edid = intel_sdvo_get_analog_edid(connector);
1654
ff482d83 1655 if (edid != NULL) {
52220085
CW		 1656 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1657 edid)) {
0c1dab89
CW		 1658 drm_mode_connector_update_edid_property(connector, edid);
1659 drm_add_edid_modes(connector, edid);
1660 }
13946743 1661
ff482d83 1662 kfree(edid);
e2f0ba97 1663 }
e2f0ba97
JB		 1664}
1665
1666/*
1667 * Set of SDVO TV modes.
1668 * Note! This is in reply order (see loop in get_tv_modes).
1669 * XXX: all 60Hz refresh?
1670 */
b1f559ec 1671static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1672 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1673 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1674 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1675 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1676 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1678 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1679 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1680 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1681 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1682 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1683 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1684 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1685 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1686 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1687 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1688 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1690 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1691 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1693 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1694 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1696 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1697 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1698 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1699 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1700 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1701 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1702 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1703 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1705 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1706 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1708 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1709 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1710 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1711 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1712 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1713 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1714 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1715 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1716 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1717 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1718 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1720 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1721 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1722 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1723 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1724 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1725 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1726 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1727 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1728 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1729};
1730
1731static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1732{
df0e9248 1733 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1734 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1735 uint32_t reply = 0, format_map = 0;
1736 int i;
e2f0ba97
JB		 1737
1738 /* Read the list of supported input resolutions for the selected TV
1739 * format.
1740 */
40039750 1741 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1742 memcpy(&tv_res, &format_map,
32aad86f 1743 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1744
32aad86f
CW		 1745 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1746 return;
ce6feabd 1747
32aad86f 1748 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1749 if (!intel_sdvo_write_cmd(intel_sdvo,
1750 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1751 &tv_res, sizeof(tv_res)))
1752 return;
1753 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1754 return;
1755
1756 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1757 if (reply & (1 << i)) {
1758 struct drm_display_mode *nmode;
1759 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1760 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1761 if (nmode)
1762 drm_mode_probed_add(connector, nmode);
1763 }
e2f0ba97
JB		 1764}
1765
7086c87f
ML		 1766static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1767{
df0e9248 1768 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1769 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1770 struct drm_display_mode *newmode;
7086c87f
ML		 1771
1772 /*
1773 * Attempt to get the mode list from DDC.
1774 * Assume that the preferred modes are
1775 * arranged in priority order.
1776 */
f899fc64 1777 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1778 if (list_empty(&connector->probed_modes) == false)
12682a97 1779 goto end;
7086c87f
ML		 1780
1781 /* Fetch modes from VBT */
1782 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1783 newmode = drm_mode_duplicate(connector->dev,
1784 dev_priv->sdvo_lvds_vbt_mode);
1785 if (newmode != NULL) {
1786 /* Guarantee the mode is preferred */
1787 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1788 DRM_MODE_TYPE_DRIVER);
1789 drm_mode_probed_add(connector, newmode);
1790 }
1791 }
12682a97 1792
1793end:
1794 list_for_each_entry(newmode, &connector->probed_modes, head) {
1795 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1796 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1797 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1798
8545423a 1799 intel_sdvo->is_lvds = true;
12682a97 1800 break;
1801 }
1802 }
1803
7086c87f
ML		 1804}
1805
e2f0ba97
JB		 1806static int intel_sdvo_get_modes(struct drm_connector *connector)
1807{
615fb93f 1808 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1809
615fb93f 1810 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1811 intel_sdvo_get_tv_modes(connector);
615fb93f 1812 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1813 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1814 else
1815 intel_sdvo_get_ddc_modes(connector);
1816
32aad86f 1817 return !list_empty(&connector->probed_modes);
79e53945
JB		 1818}
1819
fcc8d672
CW		 1820static void
1821intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1822{
615fb93f 1823 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1824 struct drm_device *dev = connector->dev;
1825
c5521706
CW		 1826 if (intel_sdvo_connector->left)
1827 drm_property_destroy(dev, intel_sdvo_connector->left);
1828 if (intel_sdvo_connector->right)
1829 drm_property_destroy(dev, intel_sdvo_connector->right);
1830 if (intel_sdvo_connector->top)
1831 drm_property_destroy(dev, intel_sdvo_connector->top);
1832 if (intel_sdvo_connector->bottom)
1833 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1834 if (intel_sdvo_connector->hpos)
1835 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1836 if (intel_sdvo_connector->vpos)
1837 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1838 if (intel_sdvo_connector->saturation)
1839 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1840 if (intel_sdvo_connector->contrast)
1841 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1842 if (intel_sdvo_connector->hue)
1843 drm_property_destroy(dev, intel_sdvo_connector->hue);
1844 if (intel_sdvo_connector->sharpness)
1845 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1846 if (intel_sdvo_connector->flicker_filter)
1847 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1848 if (intel_sdvo_connector->flicker_filter_2d)
1849 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1850 if (intel_sdvo_connector->flicker_filter_adaptive)
1851 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1852 if (intel_sdvo_connector->tv_luma_filter)
1853 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1854 if (intel_sdvo_connector->tv_chroma_filter)
1855 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1856 if (intel_sdvo_connector->dot_crawl)
1857 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1858 if (intel_sdvo_connector->brightness)
1859 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1860}
1861
79e53945
JB		 1862static void intel_sdvo_destroy(struct drm_connector *connector)
1863{
615fb93f 1864 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1865
c5521706 1866 if (intel_sdvo_connector->tv_format)
ce6feabd 1867 drm_property_destroy(connector->dev,
c5521706 1868 intel_sdvo_connector->tv_format);
b9219c5e 1869
d2a82a6f 1870 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1871 drm_sysfs_connector_remove(connector);
1872 drm_connector_cleanup(connector);
4b745b1e 1873 kfree(intel_sdvo_connector);
79e53945
JB		 1874}
1875
1aad7ac0
CW		 1876static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1877{
1878 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1879 struct edid *edid;
1880 bool has_audio = false;
1881
1882 if (!intel_sdvo->is_hdmi)
1883 return false;
1884
1885 edid = intel_sdvo_get_edid(connector);
1886 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1887 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 1888 kfree(edid);
1aad7ac0
CW		 1889
1890 return has_audio;
1891}
1892
ce6feabd
ZY		 1893static int
1894intel_sdvo_set_property(struct drm_connector *connector,
1895 struct drm_property *property,
1896 uint64_t val)
1897{
df0e9248 1898 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1899 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1900 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1901 uint16_t temp_value;
32aad86f
CW		 1902 uint8_t cmd;
1903 int ret;
ce6feabd 1904
662595df 1905 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 1906 if (ret)
1907 return ret;
ce6feabd 1908
3f43c48d 1909 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1910 int i = val;
1911 bool has_audio;
1912
1913 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1914 return 0;
1915
1aad7ac0 1916 intel_sdvo_connector->force_audio = i;
7f36e7ed 1917
c3e5f67b 1918 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1919 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1920 else
c3e5f67b 1921 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1922
1aad7ac0 1923 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1924 return 0;
7f36e7ed 1925
1aad7ac0 1926 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1927 goto done;
1928 }
1929
e953fd7b 1930 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 1931 switch (val) {
1932 case INTEL_BROADCAST_RGB_AUTO:
1933 intel_sdvo->color_range_auto = true;
1934 break;
1935 case INTEL_BROADCAST_RGB_FULL:
1936 intel_sdvo->color_range_auto = false;
1937 intel_sdvo->color_range = 0;
1938 break;
1939 case INTEL_BROADCAST_RGB_LIMITED:
1940 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 1941 /* FIXME: this bit is only valid when using TMDS
1942 * encoding and 8 bit per color mode. */
1943 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1944 break;
1945 default:
1946 return -EINVAL;
1947 }
7f36e7ed
CW		 1948 goto done;
1949 }
1950
c5521706
CW		 1951#define CHECK_PROPERTY(name, NAME) \
1952 if (intel_sdvo_connector->name == property) { \
1953 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1954 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1955 cmd = SDVO_CMD_SET_##NAME; \
1956 intel_sdvo_connector->cur_##name = temp_value; \
1957 goto set_value; \
1958 }
1959
1960 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1961 if (val >= TV_FORMAT_NUM)
1962 return -EINVAL;
1963
40039750 1964 if (intel_sdvo->tv_format_index ==
615fb93f 1965 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1966 return 0;
ce6feabd 1967
40039750 1968 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1969 goto done;
32aad86f 1970 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1971 temp_value = val;
c5521706 1972 if (intel_sdvo_connector->left == property) {
662595df 1973 drm_object_property_set_value(&connector->base,
c5521706 1974 intel_sdvo_connector->right, val);
615fb93f 1975 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1976 return 0;
b9219c5e 1977
615fb93f
CW		 1978 intel_sdvo_connector->left_margin = temp_value;
1979 intel_sdvo_connector->right_margin = temp_value;
1980 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1981 intel_sdvo_connector->left_margin;
b9219c5e 1982 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1983 goto set_value;
1984 } else if (intel_sdvo_connector->right == property) {
662595df 1985 drm_object_property_set_value(&connector->base,
c5521706 1986 intel_sdvo_connector->left, val);
615fb93f 1987 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1988 return 0;
b9219c5e 1989
615fb93f
CW		 1990 intel_sdvo_connector->left_margin = temp_value;
1991 intel_sdvo_connector->right_margin = temp_value;
1992 temp_value = intel_sdvo_connector->max_hscan -
1993 intel_sdvo_connector->left_margin;
b9219c5e 1994 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1995 goto set_value;
1996 } else if (intel_sdvo_connector->top == property) {
662595df 1997 drm_object_property_set_value(&connector->base,
c5521706 1998 intel_sdvo_connector->bottom, val);
615fb93f 1999 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2000 return 0;
b9219c5e 2001
615fb93f
CW		 2002 intel_sdvo_connector->top_margin = temp_value;
2003 intel_sdvo_connector->bottom_margin = temp_value;
2004 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2005 intel_sdvo_connector->top_margin;
b9219c5e 2006 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2007 goto set_value;
2008 } else if (intel_sdvo_connector->bottom == property) {
662595df 2009 drm_object_property_set_value(&connector->base,
c5521706 2010 intel_sdvo_connector->top, val);
615fb93f 2011 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2012 return 0;
2013
615fb93f
CW		 2014 intel_sdvo_connector->top_margin = temp_value;
2015 intel_sdvo_connector->bottom_margin = temp_value;
2016 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2017 intel_sdvo_connector->top_margin;
b9219c5e 2018 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2019 goto set_value;
2020 }
2021 CHECK_PROPERTY(hpos, HPOS)
2022 CHECK_PROPERTY(vpos, VPOS)
2023 CHECK_PROPERTY(saturation, SATURATION)
2024 CHECK_PROPERTY(contrast, CONTRAST)
2025 CHECK_PROPERTY(hue, HUE)
2026 CHECK_PROPERTY(brightness, BRIGHTNESS)
2027 CHECK_PROPERTY(sharpness, SHARPNESS)
2028 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2029 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2030 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2031 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2032 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2033 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2034 }
b9219c5e 2035
c5521706 2036 return -EINVAL; /* unknown property */
b9219c5e 2037
c5521706
CW		 2038set_value:
2039 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2040 return -EIO;
b9219c5e 2041
b9219c5e 2042
c5521706 2043done:
c0c36b94
CW		 2044 if (intel_sdvo->base.base.crtc)
2045 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2046
32aad86f 2047 return 0;
c5521706 2048#undef CHECK_PROPERTY
ce6feabd
ZY		 2049}
2050
79e53945 2051static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2052 .dpms = intel_sdvo_dpms,
79e53945
JB		 2053 .detect = intel_sdvo_detect,
2054 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2055 .set_property = intel_sdvo_set_property,
79e53945
JB		 2056 .destroy = intel_sdvo_destroy,
2057};
2058
2059static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2060 .get_modes = intel_sdvo_get_modes,
2061 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2062 .best_encoder = intel_best_encoder,
79e53945
JB		 2063};
2064
b358d0a6 2065static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2066{
890f3359 2067 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 2068
ea5b213a 2069 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2070 drm_mode_destroy(encoder->dev,
ea5b213a 2071 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2072
e957d772 2073 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2074 intel_encoder_destroy(encoder);
79e53945
JB		 2075}
2076
2077static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2078 .destroy = intel_sdvo_enc_destroy,
2079};
2080
b66d8424
CW		 2081static void
2082intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2083{
2084 uint16_t mask = 0;
2085 unsigned int num_bits;
2086
2087 /* Make a mask of outputs less than or equal to our own priority in the
2088 * list.
2089 */
2090 switch (sdvo->controlled_output) {
2091 case SDVO_OUTPUT_LVDS1:
2092 mask |= SDVO_OUTPUT_LVDS1;
2093 case SDVO_OUTPUT_LVDS0:
2094 mask |= SDVO_OUTPUT_LVDS0;
2095 case SDVO_OUTPUT_TMDS1:
2096 mask |= SDVO_OUTPUT_TMDS1;
2097 case SDVO_OUTPUT_TMDS0:
2098 mask |= SDVO_OUTPUT_TMDS0;
2099 case SDVO_OUTPUT_RGB1:
2100 mask |= SDVO_OUTPUT_RGB1;
2101 case SDVO_OUTPUT_RGB0:
2102 mask |= SDVO_OUTPUT_RGB0;
2103 break;
2104 }
2105
2106 /* Count bits to find what number we are in the priority list. */
2107 mask &= sdvo->caps.output_flags;
2108 num_bits = hweight16(mask);
2109 /* If more than 3 outputs, default to DDC bus 3 for now. */
2110 if (num_bits > 3)
2111 num_bits = 3;
2112
2113 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2114 sdvo->ddc_bus = 1 << num_bits;
2115}
79e53945 2116
e2f0ba97
JB		 2117/**
2118 * Choose the appropriate DDC bus for control bus switch command for this
2119 * SDVO output based on the controlled output.
2120 *
2121 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2122 * outputs, then LVDS outputs.
2123 */
2124static void
b1083333 2125intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2126 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2127{
b1083333 2128 struct sdvo_device_mapping *mapping;
e2f0ba97 2129
eef4eacb 2130 if (sdvo->is_sdvob)
b1083333
AJ		 2131 mapping = &(dev_priv->sdvo_mappings[0]);
2132 else
2133 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2134
b66d8424
CW		 2135 if (mapping->initialized)
2136 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2137 else
2138 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2139}
2140
e957d772
CW		 2141static void
2142intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2143 struct intel_sdvo *sdvo, u32 reg)
2144{
2145 struct sdvo_device_mapping *mapping;
46eb3036 2146 u8 pin;
e957d772 2147
eef4eacb 2148 if (sdvo->is_sdvob)
e957d772
CW		 2149 mapping = &dev_priv->sdvo_mappings[0];
2150 else
2151 mapping = &dev_priv->sdvo_mappings[1];
2152
6cb1612a 2153 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2154 pin = mapping->i2c_pin;
6cb1612a
JN		 2155 else
2156 pin = GMBUS_PORT_DPB;
e957d772 2157
6cb1612a
JN		 2158 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2159
2160 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2161 * our code totally fails once we start using gmbus. Hence fall back to
2162 * bit banging for now. */
2163 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2164}
2165
fbfcc4f3
JN		 2166/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2167static void
2168intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2169{
2170 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2171}
2172
e2f0ba97 2173static bool
e27d8538 2174intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2175{
97aaf910 2176 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2177}
2178
714605e4 2179static u8
eef4eacb 2180intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2181{
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2183 struct sdvo_device_mapping *my_mapping, *other_mapping;
2184
eef4eacb 2185 if (sdvo->is_sdvob) {
714605e4 2186 my_mapping = &dev_priv->sdvo_mappings[0];
2187 other_mapping = &dev_priv->sdvo_mappings[1];
2188 } else {
2189 my_mapping = &dev_priv->sdvo_mappings[1];
2190 other_mapping = &dev_priv->sdvo_mappings[0];
2191 }
2192
2193 /* If the BIOS described our SDVO device, take advantage of it. */
2194 if (my_mapping->slave_addr)
2195 return my_mapping->slave_addr;
2196
2197 /* If the BIOS only described a different SDVO device, use the
2198 * address that it isn't using.
2199 */
2200 if (other_mapping->slave_addr) {
2201 if (other_mapping->slave_addr == 0x70)
2202 return 0x72;
2203 else
2204 return 0x70;
2205 }
2206
2207 /* No SDVO device info is found for another DVO port,
2208 * so use mapping assumption we had before BIOS parsing.
2209 */
eef4eacb 2210 if (sdvo->is_sdvob)
714605e4 2211 return 0x70;
2212 else
2213 return 0x72;
2214}
2215
14571b4c 2216static void
df0e9248
CW		 2217intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2218 struct intel_sdvo *encoder)
14571b4c 2219{
df0e9248
CW		 2220 drm_connector_init(encoder->base.base.dev,
2221 &connector->base.base,
2222 &intel_sdvo_connector_funcs,
2223 connector->base.base.connector_type);
6070a4a9 2224
df0e9248
CW		 2225 drm_connector_helper_add(&connector->base.base,
2226 &intel_sdvo_connector_helper_funcs);
14571b4c 2227
8f4839e2 2228 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2229 connector->base.base.doublescan_allowed = 0;
2230 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2231 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2232
df0e9248
CW		 2233 intel_connector_attach_encoder(&connector->base, &encoder->base);
2234 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2235}
6070a4a9 2236
7f36e7ed 2237static void
55bc60db
VS		 2238intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2239 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2240{
2241 struct drm_device *dev = connector->base.base.dev;
2242
3f43c48d 2243 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2244 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2245 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2246 intel_sdvo->color_range_auto = true;
2247 }
7f36e7ed
CW		 2248}
2249
fb7a46f3 2250static bool
ea5b213a 2251intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2252{
4ef69c7a 2253 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2254 struct drm_connector *connector;
cc68c81a 2255 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2256 struct intel_connector *intel_connector;
615fb93f 2257 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2258
615fb93f
CW		 2259 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2260 if (!intel_sdvo_connector)
14571b4c
ZW		 2261 return false;
2262
14571b4c 2263 if (device == 0) {
ea5b213a 2264 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2265 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2266 } else if (device == 1) {
ea5b213a 2267 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2268 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2269 }
2270
615fb93f 2271 intel_connector = &intel_sdvo_connector->base;
14571b4c 2272 connector = &intel_connector->base;
5fa7ac9c
JN		 2273 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2274 intel_sdvo_connector->output_flag) {
cc68c81a 2275 connector->polled = DRM_CONNECTOR_POLL_HPD;
5fa7ac9c 2276 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2277 /* Some SDVO devices have one-shot hotplug interrupts.
2278 * Ensure that they get re-enabled when an interrupt happens.
2279 */
2280 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2281 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2282 } else {
cc68c81a 2283 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2284 }
14571b4c
ZW		 2285 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2286 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2287
e27d8538 2288 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2289 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2290 intel_sdvo->is_hdmi = true;
14571b4c 2291 }
14571b4c 2292
df0e9248 2293 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221 2294 if (intel_sdvo->is_hdmi)
55bc60db 2295 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2296
2297 return true;
2298}
2299
2300static bool
ea5b213a 2301intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2302{
4ef69c7a
CW		 2303 struct drm_encoder *encoder = &intel_sdvo->base.base;
2304 struct drm_connector *connector;
2305 struct intel_connector *intel_connector;
2306 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2307
615fb93f
CW		 2308 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2309 if (!intel_sdvo_connector)
2310 return false;
14571b4c 2311
615fb93f 2312 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2313 connector = &intel_connector->base;
2314 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2315 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2316
4ef69c7a
CW		 2317 intel_sdvo->controlled_output |= type;
2318 intel_sdvo_connector->output_flag = type;
14571b4c 2319
4ef69c7a
CW		 2320 intel_sdvo->is_tv = true;
2321 intel_sdvo->base.needs_tv_clock = true;
14571b4c 2322
df0e9248 2323 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2324
4ef69c7a 2325 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2326 goto err;
14571b4c 2327
4ef69c7a 2328 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2329 goto err;
14571b4c 2330
4ef69c7a 2331 return true;
32aad86f
CW		 2332
2333err:
123d5c01 2334 intel_sdvo_destroy(connector);
32aad86f 2335 return false;
14571b4c
ZW		 2336}
2337
2338static bool
ea5b213a 2339intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2340{
4ef69c7a
CW		 2341 struct drm_encoder *encoder = &intel_sdvo->base.base;
2342 struct drm_connector *connector;
2343 struct intel_connector *intel_connector;
2344 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2345
615fb93f
CW		 2346 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2347 if (!intel_sdvo_connector)
2348 return false;
14571b4c 2349
615fb93f 2350 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2351 connector = &intel_connector->base;
eb1f8e4f 2352 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2353 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2354 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2355
2356 if (device == 0) {
2357 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2358 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2359 } else if (device == 1) {
2360 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2361 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2362 }
2363
df0e9248
CW		 2364 intel_sdvo_connector_init(intel_sdvo_connector,
2365 intel_sdvo);
4ef69c7a 2366 return true;
14571b4c
ZW		 2367}
2368
2369static bool
ea5b213a 2370intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2371{
4ef69c7a
CW		 2372 struct drm_encoder *encoder = &intel_sdvo->base.base;
2373 struct drm_connector *connector;
2374 struct intel_connector *intel_connector;
2375 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2376
615fb93f
CW		 2377 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2378 if (!intel_sdvo_connector)
2379 return false;
14571b4c 2380
615fb93f
CW		 2381 intel_connector = &intel_sdvo_connector->base;
2382 connector = &intel_connector->base;
4ef69c7a
CW		 2383 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2384 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2385
2386 if (device == 0) {
2387 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2388 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2389 } else if (device == 1) {
2390 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2391 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2392 }
2393
df0e9248 2394 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2395 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2396 goto err;
2397
2398 return true;
2399
2400err:
123d5c01 2401 intel_sdvo_destroy(connector);
32aad86f 2402 return false;
14571b4c
ZW		 2403}
2404
2405static bool
ea5b213a 2406intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2407{
ea5b213a
CW		 2408 intel_sdvo->is_tv = false;
2409 intel_sdvo->base.needs_tv_clock = false;
2410 intel_sdvo->is_lvds = false;
fb7a46f3 2411
14571b4c 2412 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2413
14571b4c 2414 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2415 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2416 return false;
2417
2418 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2419 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2420 return false;
2421
2422 /* TV has no XXX1 function block */
a1f4b7ff 2423 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2424 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2425 return false;
2426
2427 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2428 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2429 return false;
fb7a46f3 2430
a0b1c7a5
CW		 2431 if (flags & SDVO_OUTPUT_YPRPB0)
2432 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2433 return false;
2434
14571b4c 2435 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2436 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2437 return false;
2438
2439 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2440 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2441 return false;
2442
2443 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2444 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2445 return false;
2446
2447 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2448 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2449 return false;
fb7a46f3 2450
14571b4c 2451 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2452 unsigned char bytes[2];
2453
ea5b213a
CW		 2454 intel_sdvo->controlled_output = 0;
2455 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2456 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2457 SDVO_NAME(intel_sdvo),
51c8b407 2458 bytes[0], bytes[1]);
14571b4c 2459 return false;
fb7a46f3 2460 }
27f8227b 2461 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2462
14571b4c 2463 return true;
fb7a46f3 2464}
2465
d0ddfbd3
JN		 2466static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2467{
2468 struct drm_device *dev = intel_sdvo->base.base.dev;
2469 struct drm_connector *connector, *tmp;
2470
2471 list_for_each_entry_safe(connector, tmp,
2472 &dev->mode_config.connector_list, head) {
2473 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2474 intel_sdvo_destroy(connector);
2475 }
2476}
2477
32aad86f
CW		 2478static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2479 struct intel_sdvo_connector *intel_sdvo_connector,
2480 int type)
ce6feabd 2481{
4ef69c7a 2482 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2483 struct intel_sdvo_tv_format format;
2484 uint32_t format_map, i;
ce6feabd 2485
32aad86f
CW		 2486 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2487 return false;
ce6feabd 2488
1a3665c8 2489 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2490 if (!intel_sdvo_get_value(intel_sdvo,
2491 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2492 &format, sizeof(format)))
2493 return false;
ce6feabd 2494
32aad86f 2495 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2496
2497 if (format_map == 0)
32aad86f 2498 return false;
ce6feabd 2499
615fb93f 2500 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2501 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2502 if (format_map & (1 << i))
2503 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2504
2505
c5521706 2506 intel_sdvo_connector->tv_format =
32aad86f
CW		 2507 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2508 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2509 if (!intel_sdvo_connector->tv_format)
fcc8d672 2510 return false;
ce6feabd 2511
615fb93f 2512 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2513 drm_property_add_enum(
c5521706 2514 intel_sdvo_connector->tv_format, i,
40039750 2515 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2516
40039750 2517 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2518 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2519 intel_sdvo_connector->tv_format, 0);
32aad86f 2520 return true;
ce6feabd
ZY		 2521
2522}
2523
c5521706
CW		 2524#define ENHANCEMENT(name, NAME) do { \
2525 if (enhancements.name) { \
2526 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2527 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2528 return false; \
2529 intel_sdvo_connector->max_##name = data_value[0]; \
2530 intel_sdvo_connector->cur_##name = response; \
2531 intel_sdvo_connector->name = \
d9bc3c02 2532 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2533 if (!intel_sdvo_connector->name) return false; \
662595df 2534 drm_object_attach_property(&connector->base, \
c5521706
CW		 2535 intel_sdvo_connector->name, \
2536 intel_sdvo_connector->cur_##name); \
2537 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2538 data_value[0], data_value[1], response); \
2539 } \
0206e353 2540} while (0)
c5521706
CW		 2541
2542static bool
2543intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2544 struct intel_sdvo_connector *intel_sdvo_connector,
2545 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2546{
4ef69c7a 2547 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2548 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2549 uint16_t response, data_value[2];
2550
c5521706
CW		 2551 /* when horizontal overscan is supported, Add the left/right property */
2552 if (enhancements.overscan_h) {
2553 if (!intel_sdvo_get_value(intel_sdvo,
2554 SDVO_CMD_GET_MAX_OVERSCAN_H,
2555 &data_value, 4))
2556 return false;
32aad86f 2557
c5521706
CW		 2558 if (!intel_sdvo_get_value(intel_sdvo,
2559 SDVO_CMD_GET_OVERSCAN_H,
2560 &response, 2))
2561 return false;
fcc8d672 2562
c5521706
CW		 2563 intel_sdvo_connector->max_hscan = data_value[0];
2564 intel_sdvo_connector->left_margin = data_value[0] - response;
2565 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2566 intel_sdvo_connector->left =
d9bc3c02 2567 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2568 if (!intel_sdvo_connector->left)
2569 return false;
fcc8d672 2570
662595df 2571 drm_object_attach_property(&connector->base,
c5521706
CW		 2572 intel_sdvo_connector->left,
2573 intel_sdvo_connector->left_margin);
fcc8d672 2574
c5521706 2575 intel_sdvo_connector->right =
d9bc3c02 2576 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2577 if (!intel_sdvo_connector->right)
2578 return false;
32aad86f 2579
662595df 2580 drm_object_attach_property(&connector->base,
c5521706
CW		 2581 intel_sdvo_connector->right,
2582 intel_sdvo_connector->right_margin);
2583 DRM_DEBUG_KMS("h_overscan: max %d, "
2584 "default %d, current %d\n",
2585 data_value[0], data_value[1], response);
2586 }
32aad86f 2587
c5521706
CW		 2588 if (enhancements.overscan_v) {
2589 if (!intel_sdvo_get_value(intel_sdvo,
2590 SDVO_CMD_GET_MAX_OVERSCAN_V,
2591 &data_value, 4))
2592 return false;
fcc8d672 2593
c5521706
CW		 2594 if (!intel_sdvo_get_value(intel_sdvo,
2595 SDVO_CMD_GET_OVERSCAN_V,
2596 &response, 2))
2597 return false;
32aad86f 2598
c5521706
CW		 2599 intel_sdvo_connector->max_vscan = data_value[0];
2600 intel_sdvo_connector->top_margin = data_value[0] - response;
2601 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2602 intel_sdvo_connector->top =
d9bc3c02
SH		 2603 drm_property_create_range(dev, 0,
2604 "top_margin", 0, data_value[0]);
c5521706
CW		 2605 if (!intel_sdvo_connector->top)
2606 return false;
32aad86f 2607
662595df 2608 drm_object_attach_property(&connector->base,
c5521706
CW		 2609 intel_sdvo_connector->top,
2610 intel_sdvo_connector->top_margin);
fcc8d672 2611
c5521706 2612 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2613 drm_property_create_range(dev, 0,
2614 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2615 if (!intel_sdvo_connector->bottom)
2616 return false;
32aad86f 2617
662595df 2618 drm_object_attach_property(&connector->base,
c5521706
CW		 2619 intel_sdvo_connector->bottom,
2620 intel_sdvo_connector->bottom_margin);
2621 DRM_DEBUG_KMS("v_overscan: max %d, "
2622 "default %d, current %d\n",
2623 data_value[0], data_value[1], response);
2624 }
32aad86f 2625
c5521706
CW		 2626 ENHANCEMENT(hpos, HPOS);
2627 ENHANCEMENT(vpos, VPOS);
2628 ENHANCEMENT(saturation, SATURATION);
2629 ENHANCEMENT(contrast, CONTRAST);
2630 ENHANCEMENT(hue, HUE);
2631 ENHANCEMENT(sharpness, SHARPNESS);
2632 ENHANCEMENT(brightness, BRIGHTNESS);
2633 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2634 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2635 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2636 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2637 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2638
e044218a
CW		 2639 if (enhancements.dot_crawl) {
2640 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2641 return false;
2642
2643 intel_sdvo_connector->max_dot_crawl = 1;
2644 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2645 intel_sdvo_connector->dot_crawl =
d9bc3c02 2646 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2647 if (!intel_sdvo_connector->dot_crawl)
2648 return false;
2649
662595df 2650 drm_object_attach_property(&connector->base,
e044218a
CW		 2651 intel_sdvo_connector->dot_crawl,
2652 intel_sdvo_connector->cur_dot_crawl);
2653 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2654 }
2655
c5521706
CW		 2656 return true;
2657}
32aad86f 2658
c5521706
CW		 2659static bool
2660intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2661 struct intel_sdvo_connector *intel_sdvo_connector,
2662 struct intel_sdvo_enhancements_reply enhancements)
2663{
4ef69c7a 2664 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2665 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2666 uint16_t response, data_value[2];
32aad86f 2667
c5521706 2668 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2669
c5521706
CW		 2670 return true;
2671}
2672#undef ENHANCEMENT
32aad86f 2673
c5521706
CW		 2674static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2675 struct intel_sdvo_connector *intel_sdvo_connector)
2676{
2677 union {
2678 struct intel_sdvo_enhancements_reply reply;
2679 uint16_t response;
2680 } enhancements;
32aad86f 2681
1a3665c8
CW		 2682 BUILD_BUG_ON(sizeof(enhancements) != 2);
2683
cf9a2f3a
CW		 2684 enhancements.response = 0;
2685 intel_sdvo_get_value(intel_sdvo,
2686 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2687 &enhancements, sizeof(enhancements));
c5521706
CW		 2688 if (enhancements.response == 0) {
2689 DRM_DEBUG_KMS("No enhancement is supported\n");
2690 return true;
b9219c5e 2691 }
32aad86f 2692
c5521706
CW		 2693 if (IS_TV(intel_sdvo_connector))
2694 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2695 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2696 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2697 else
2698 return true;
e957d772
CW		 2699}
2700
2701static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2702 struct i2c_msg *msgs,
2703 int num)
2704{
2705 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2706
e957d772
CW		 2707 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2708 return -EIO;
2709
2710 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2711}
2712
2713static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2714{
2715 struct intel_sdvo *sdvo = adapter->algo_data;
2716 return sdvo->i2c->algo->functionality(sdvo->i2c);
2717}
2718
2719static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2720 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2721 .functionality = intel_sdvo_ddc_proxy_func
2722};
2723
2724static bool
2725intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2726 struct drm_device *dev)
2727{
2728 sdvo->ddc.owner = THIS_MODULE;
2729 sdvo->ddc.class = I2C_CLASS_DDC;
2730 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2731 sdvo->ddc.dev.parent = &dev->pdev->dev;
2732 sdvo->ddc.algo_data = sdvo;
2733 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2734
2735 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2736}
2737
eef4eacb 2738bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2739{
b01f2c3a 2740 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2741 struct intel_encoder *intel_encoder;
ea5b213a 2742 struct intel_sdvo *intel_sdvo;
084b612e 2743 u32 hotplug_mask;
79e53945 2744 int i;
79e53945 2745
ea5b213a
CW		 2746 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2747 if (!intel_sdvo)
7d57382e 2748 return false;
79e53945 2749
56184e3d 2750 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2751 intel_sdvo->is_sdvob = is_sdvob;
2752 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2753 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2754 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2755 goto err_i2c_bus;
e957d772 2756
56184e3d 2757 /* encoder type will be decided later */
ea5b213a 2758 intel_encoder = &intel_sdvo->base;
21d40d37 2759 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2760 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2761
79e53945
JB		 2762 /* Read the regs to test if we can talk to the device */
2763 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2764 u8 byte;
2765
2766 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2767 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2768 SDVO_NAME(intel_sdvo));
f899fc64 2769 goto err;
79e53945
JB		 2770 }
2771 }
2772
084b612e
CW		 2773 hotplug_mask = 0;
2774 if (IS_G4X(dev)) {
2775 hotplug_mask = intel_sdvo->is_sdvob ?
2776 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2777 } else if (IS_GEN4(dev)) {
2778 hotplug_mask = intel_sdvo->is_sdvob ?
2779 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2780 } else {
2781 hotplug_mask = intel_sdvo->is_sdvob ?
2782 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2783 }
619ac3b7 2784
4f770a5b
EE		 2785 /* Only enable the hotplug irq if we need it, to work around noisy
2786 * hotplug lines.
2787 */
1d843f9d
EE		 2788 if (intel_sdvo->hotplug_active)
2789 intel_encoder->hpd_pin = HPD_SDVO_B ? HPD_SDVO_B : HPD_SDVO_C;
2790
6cc5f341 2791 intel_encoder->compute_config = intel_sdvo_compute_config;
ce22c320 2792 intel_encoder->disable = intel_disable_sdvo;
6cc5f341 2793 intel_encoder->mode_set = intel_sdvo_mode_set;
ce22c320 2794 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2795 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
ce22c320 2796
af901ca1 2797 /* In default case sdvo lvds is false */
32aad86f 2798 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2799 goto err;
79e53945 2800
ea5b213a
CW		 2801 if (intel_sdvo_output_setup(intel_sdvo,
2802 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2803 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2804 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 2805 /* Output_setup can leave behind connectors! */
2806 goto err_output;
79e53945
JB		 2807 }
2808
e506d6fd
DV		 2809 /*
2810 * Cloning SDVO with anything is often impossible, since the SDVO
2811 * encoder can request a special input timing mode. And even if that's
2812 * not the case we have evidence that cloning a plain unscaled mode with
2813 * VGA doesn't really work. Furthermore the cloning flags are way too
2814 * simplistic anyway to express such constraints, so just give up on
2815 * cloning for SDVO encoders.
2816 */
2817 intel_sdvo->base.cloneable = false;
2818
ea5b213a 2819 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2820
79e53945 2821 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2822 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 2823 goto err_output;
79e53945 2824
32aad86f
CW		 2825 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2826 &intel_sdvo->pixel_clock_min,
2827 &intel_sdvo->pixel_clock_max))
d0ddfbd3 2828 goto err_output;
79e53945 2829
8a4c47f3 2830 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2831 "clock range %dMHz - %dMHz, "
2832 "input 1: %c, input 2: %c, "
2833 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2834 SDVO_NAME(intel_sdvo),
2835 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2836 intel_sdvo->caps.device_rev_id,
2837 intel_sdvo->pixel_clock_min / 1000,
2838 intel_sdvo->pixel_clock_max / 1000,
2839 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2840 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2841 /* check currently supported outputs */
ea5b213a 2842 intel_sdvo->caps.output_flags &
79e53945 2843 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2844 intel_sdvo->caps.output_flags &
79e53945 2845 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2846 return true;
79e53945 2847
d0ddfbd3
JN		 2848err_output:
2849 intel_sdvo_output_cleanup(intel_sdvo);
2850
f899fc64 2851err:
373a3cf7 2852 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2853 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2854err_i2c_bus:
2855 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2856 kfree(intel_sdvo);
79e53945 2857
7d57382e 2858 return false;
79e53945 2859}
Linux kernel - Deliverables
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