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drm/i915: reuse the sdvo tv clock adjustment in ilk mode_set
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
2e88e40b 56static const char *tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 77 uint32_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
100 uint8_t hotplug_active[2];
101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
12682a97 129
7086c87f 130 /**
6c9547ff
CW		 131 * This is set if we detect output of sdvo device as LVDS and
132 * have a valid fixed mode to use with the panel.
7086c87f
ML		 133 */
134 bool is_lvds;
e2f0ba97 135
12682a97 136 /**
137 * This is sdvo fixed pannel mode pointer
138 */
139 struct drm_display_mode *sdvo_lvds_fixed_mode;
140
c751ce4f 141 /* DDC bus used by this SDVO encoder */
e2f0ba97 142 uint8_t ddc_bus;
14571b4c
ZW		 143};
144
145struct intel_sdvo_connector {
615fb93f
CW		 146 struct intel_connector base;
147
14571b4c
ZW		 148 /* Mark the type of connector */
149 uint16_t output_flag;
150
c3e5f67b 151 enum hdmi_force_audio force_audio;
7f36e7ed 152
14571b4c 153 /* This contains all current supported TV format */
40039750 154 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 155 int format_supported_num;
c5521706 156 struct drm_property *tv_format;
14571b4c 157
b9219c5e 158 /* add the property for the SDVO-TV */
c5521706
CW		 159 struct drm_property *left;
160 struct drm_property *right;
161 struct drm_property *top;
162 struct drm_property *bottom;
163 struct drm_property *hpos;
164 struct drm_property *vpos;
165 struct drm_property *contrast;
166 struct drm_property *saturation;
167 struct drm_property *hue;
168 struct drm_property *sharpness;
169 struct drm_property *flicker_filter;
170 struct drm_property *flicker_filter_adaptive;
171 struct drm_property *flicker_filter_2d;
172 struct drm_property *tv_chroma_filter;
173 struct drm_property *tv_luma_filter;
e044218a 174 struct drm_property *dot_crawl;
b9219c5e
ZY		 175
176 /* add the property for the SDVO-TV/LVDS */
c5521706 177 struct drm_property *brightness;
b9219c5e
ZY		 178
179 /* Add variable to record current setting for the above property */
180 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 181
b9219c5e
ZY		 182 /* this is to get the range of margin.*/
183 u32 max_hscan, max_vscan;
184 u32 max_hpos, cur_hpos;
185 u32 max_vpos, cur_vpos;
186 u32 cur_brightness, max_brightness;
187 u32 cur_contrast, max_contrast;
188 u32 cur_saturation, max_saturation;
189 u32 cur_hue, max_hue;
c5521706
CW		 190 u32 cur_sharpness, max_sharpness;
191 u32 cur_flicker_filter, max_flicker_filter;
192 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
193 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
194 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
195 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 196 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 197};
198
890f3359 199static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 200{
4ef69c7a 201 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 202}
203
df0e9248
CW		 204static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
205{
206 return container_of(intel_attached_encoder(connector),
207 struct intel_sdvo, base);
208}
209
615fb93f
CW		 210static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
211{
212 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
213}
214
fb7a46f3 215static bool
ea5b213a 216intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 217static bool
218intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
219 struct intel_sdvo_connector *intel_sdvo_connector,
220 int type);
221static bool
222intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
223 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 224
79e53945
JB		 225/**
226 * Writes the SDVOB or SDVOC with the given value, but always writes both
227 * SDVOB and SDVOC to work around apparent hardware issues (according to
228 * comments in the BIOS).
229 */
ea5b213a 230static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 231{
4ef69c7a 232 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 233 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 234 u32 bval = val, cval = val;
235 int i;
236
ea5b213a
CW		 237 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
238 I915_WRITE(intel_sdvo->sdvo_reg, val);
239 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 240 return;
241 }
242
ea5b213a 243 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 244 cval = I915_READ(SDVOC);
245 } else {
246 bval = I915_READ(SDVOB);
247 }
248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
253 for (i = 0; i < 2; i++)
254 {
255 I915_WRITE(SDVOB, bval);
256 I915_READ(SDVOB);
257 I915_WRITE(SDVOC, cval);
258 I915_READ(SDVOC);
259 }
260}
261
32aad86f 262static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 263{
79e53945
JB		 264 struct i2c_msg msgs[] = {
265 {
e957d772 266 .addr = intel_sdvo->slave_addr,
79e53945
JB		 267 .flags = 0,
268 .len = 1,
e957d772 269 .buf = &addr,
79e53945
JB		 270 },
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = I2C_M_RD,
274 .len = 1,
e957d772 275 .buf = ch,
79e53945
JB		 276 }
277 };
32aad86f 278 int ret;
79e53945 279
f899fc64 280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 281 return true;
79e53945 282
8a4c47f3 283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 284 return false;
285}
286
79e53945
JB		 287#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288/** Mapping of command numbers to names, for debug output */
005568be 289static const struct _sdvo_cmd_name {
e2f0ba97 290 u8 cmd;
2e88e40b 291 const char *name;
79e53945 292} sdvo_cmd_names[] = {
0206e353
AJ		 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 404};
405
eef4eacb 406#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 407
ea5b213a 408static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 409 const void *args, int args_len)
79e53945 410{
79e53945
JB		 411 int i;
412
8a4c47f3 413 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 414 SDVO_NAME(intel_sdvo), cmd);
79e53945 415 for (i = 0; i < args_len; i++)
342dc382 416 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 417 for (; i < 8; i++)
342dc382 418 DRM_LOG_KMS(" ");
04ad327f 419 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 420 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 421 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 422 break;
423 }
424 }
04ad327f 425 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 426 DRM_LOG_KMS("(%02X)", cmd);
427 DRM_LOG_KMS("\n");
79e53945 428}
79e53945 429
e957d772
CW		 430static const char *cmd_status_names[] = {
431 "Power on",
432 "Success",
433 "Not supported",
434 "Invalid arg",
435 "Pending",
436 "Target not specified",
437 "Scaling not supported"
438};
439
32aad86f
CW		 440static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
441 const void *args, int args_len)
79e53945 442{
3bf3f452
BW		 443 u8 *buf, status;
444 struct i2c_msg *msgs;
445 int i, ret = true;
446
447 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
448 if (!buf)
449 return false;
450
451 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
452 if (!msgs)
453 return false;
79e53945 454
ea5b213a 455 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 456
457 for (i = 0; i < args_len; i++) {
e957d772
CW		 458 msgs[i].addr = intel_sdvo->slave_addr;
459 msgs[i].flags = 0;
460 msgs[i].len = 2;
461 msgs[i].buf = buf + 2 *i;
462 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
463 buf[2*i + 1] = ((u8*)args)[i];
464 }
465 msgs[i].addr = intel_sdvo->slave_addr;
466 msgs[i].flags = 0;
467 msgs[i].len = 2;
468 msgs[i].buf = buf + 2*i;
469 buf[2*i + 0] = SDVO_I2C_OPCODE;
470 buf[2*i + 1] = cmd;
471
472 /* the following two are to read the response */
473 status = SDVO_I2C_CMD_STATUS;
474 msgs[i+1].addr = intel_sdvo->slave_addr;
475 msgs[i+1].flags = 0;
476 msgs[i+1].len = 1;
477 msgs[i+1].buf = &status;
478
479 msgs[i+2].addr = intel_sdvo->slave_addr;
480 msgs[i+2].flags = I2C_M_RD;
481 msgs[i+2].len = 1;
482 msgs[i+2].buf = &status;
483
484 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
485 if (ret < 0) {
486 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 487 ret = false;
488 goto out;
e957d772
CW		 489 }
490 if (ret != i+3) {
491 /* failure in I2C transfer */
492 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 493 ret = false;
e957d772
CW		 494 }
495
3bf3f452
BW		 496out:
497 kfree(msgs);
498 kfree(buf);
499 return ret;
79e53945
JB		 500}
501
b5c616a7
CW		 502static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
503 void *response, int response_len)
79e53945 504{
b5c616a7
CW		 505 u8 retry = 5;
506 u8 status;
33b52961 507 int i;
79e53945 508
d121a5d2
CW		 509 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
510
b5c616a7
CW		 511 /*
512 * The documentation states that all commands will be
513 * processed within 15µs, and that we need only poll
514 * the status byte a maximum of 3 times in order for the
515 * command to be complete.
516 *
517 * Check 5 times in case the hardware failed to read the docs.
518 */
d121a5d2
CW		 519 if (!intel_sdvo_read_byte(intel_sdvo,
520 SDVO_I2C_CMD_STATUS,
521 &status))
522 goto log_fail;
523
524 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
525 udelay(15);
b5c616a7
CW		 526 if (!intel_sdvo_read_byte(intel_sdvo,
527 SDVO_I2C_CMD_STATUS,
528 &status))
d121a5d2
CW		 529 goto log_fail;
530 }
b5c616a7 531
79e53945 532 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 533 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 534 else
342dc382 535 DRM_LOG_KMS("(??? %d)", status);
79e53945 536
b5c616a7
CW		 537 if (status != SDVO_CMD_STATUS_SUCCESS)
538 goto log_fail;
79e53945 539
b5c616a7
CW		 540 /* Read the command response */
541 for (i = 0; i < response_len; i++) {
542 if (!intel_sdvo_read_byte(intel_sdvo,
543 SDVO_I2C_RETURN_0 + i,
544 &((u8 *)response)[i]))
545 goto log_fail;
e957d772 546 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 547 }
b5c616a7 548 DRM_LOG_KMS("\n");
b5c616a7 549 return true;
79e53945 550
b5c616a7 551log_fail:
d121a5d2 552 DRM_LOG_KMS("... failed\n");
b5c616a7 553 return false;
79e53945
JB		 554}
555
b358d0a6 556static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 557{
558 if (mode->clock >= 100000)
559 return 1;
560 else if (mode->clock >= 50000)
561 return 2;
562 else
563 return 4;
564}
565
e957d772
CW		 566static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
567 u8 ddc_bus)
79e53945 568{
d121a5d2 569 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 570 return intel_sdvo_write_cmd(intel_sdvo,
571 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
572 &ddc_bus, 1);
79e53945
JB		 573}
574
32aad86f 575static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 576{
d121a5d2
CW		 577 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
578 return false;
579
580 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 581}
79e53945 582
32aad86f
CW		 583static bool
584intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
585{
586 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
587 return false;
79e53945 588
32aad86f
CW		 589 return intel_sdvo_read_response(intel_sdvo, value, len);
590}
79e53945 591
32aad86f
CW		 592static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
593{
594 struct intel_sdvo_set_target_input_args targets = {0};
595 return intel_sdvo_set_value(intel_sdvo,
596 SDVO_CMD_SET_TARGET_INPUT,
597 &targets, sizeof(targets));
79e53945
JB		 598}
599
600/**
601 * Return whether each input is trained.
602 *
603 * This function is making an assumption about the layout of the response,
604 * which should be checked against the docs.
605 */
ea5b213a 606static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 607{
608 struct intel_sdvo_get_trained_inputs_response response;
79e53945 609
1a3665c8 610 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 611 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
612 &response, sizeof(response)))
79e53945
JB		 613 return false;
614
615 *input_1 = response.input0_trained;
616 *input_2 = response.input1_trained;
617 return true;
618}
619
ea5b213a 620static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 621 u16 outputs)
622{
32aad86f
CW		 623 return intel_sdvo_set_value(intel_sdvo,
624 SDVO_CMD_SET_ACTIVE_OUTPUTS,
625 &outputs, sizeof(outputs));
79e53945
JB		 626}
627
ea5b213a 628static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 629 int mode)
630{
32aad86f 631 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 632
633 switch (mode) {
634 case DRM_MODE_DPMS_ON:
635 state = SDVO_ENCODER_STATE_ON;
636 break;
637 case DRM_MODE_DPMS_STANDBY:
638 state = SDVO_ENCODER_STATE_STANDBY;
639 break;
640 case DRM_MODE_DPMS_SUSPEND:
641 state = SDVO_ENCODER_STATE_SUSPEND;
642 break;
643 case DRM_MODE_DPMS_OFF:
644 state = SDVO_ENCODER_STATE_OFF;
645 break;
646 }
647
32aad86f
CW		 648 return intel_sdvo_set_value(intel_sdvo,
649 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 650}
651
ea5b213a 652static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 653 int *clock_min,
654 int *clock_max)
655{
656 struct intel_sdvo_pixel_clock_range clocks;
79e53945 657
1a3665c8 658 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 659 if (!intel_sdvo_get_value(intel_sdvo,
660 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
661 &clocks, sizeof(clocks)))
79e53945
JB		 662 return false;
663
664 /* Convert the values from units of 10 kHz to kHz. */
665 *clock_min = clocks.min * 10;
666 *clock_max = clocks.max * 10;
79e53945
JB		 667 return true;
668}
669
ea5b213a 670static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 671 u16 outputs)
672{
32aad86f
CW		 673 return intel_sdvo_set_value(intel_sdvo,
674 SDVO_CMD_SET_TARGET_OUTPUT,
675 &outputs, sizeof(outputs));
79e53945
JB		 676}
677
ea5b213a 678static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 679 struct intel_sdvo_dtd *dtd)
680{
32aad86f
CW		 681 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
682 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 683}
684
ea5b213a 685static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 686 struct intel_sdvo_dtd *dtd)
687{
ea5b213a 688 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 689 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
690}
691
ea5b213a 692static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 693 struct intel_sdvo_dtd *dtd)
694{
ea5b213a 695 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 696 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
697}
698
e2f0ba97 699static bool
ea5b213a 700intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 701 uint16_t clock,
702 uint16_t width,
703 uint16_t height)
704{
705 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 706
e642c6f1 707 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 708 args.clock = clock;
709 args.width = width;
710 args.height = height;
e642c6f1 711 args.interlace = 0;
12682a97 712
ea5b213a
CW		 713 if (intel_sdvo->is_lvds &&
714 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
715 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 716 args.scaled = 1;
717
32aad86f
CW		 718 return intel_sdvo_set_value(intel_sdvo,
719 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
720 &args, sizeof(args));
e2f0ba97
JB		 721}
722
ea5b213a 723static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 724 struct intel_sdvo_dtd *dtd)
725{
1a3665c8
CW		 726 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
727 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 728 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
729 &dtd->part1, sizeof(dtd->part1)) &&
730 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
731 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 732}
79e53945 733
ea5b213a 734static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 735{
32aad86f 736 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 737}
738
e2f0ba97 739static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 740 const struct drm_display_mode *mode)
79e53945 741{
e2f0ba97
JB		 742 uint16_t width, height;
743 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
744 uint16_t h_sync_offset, v_sync_offset;
6651819b 745 int mode_clock;
79e53945 746
c6ebd4c0
DV		 747 width = mode->hdisplay;
748 height = mode->vdisplay;
79e53945
JB		 749
750 /* do some mode translations */
c6ebd4c0
DV		 751 h_blank_len = mode->htotal - mode->hdisplay;
752 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 753
c6ebd4c0
DV		 754 v_blank_len = mode->vtotal - mode->vdisplay;
755 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 756
c6ebd4c0
DV		 757 h_sync_offset = mode->hsync_start - mode->hdisplay;
758 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 759
6651819b
DV		 760 mode_clock = mode->clock;
761 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
762 mode_clock /= 10;
763 dtd->part1.clock = mode_clock;
764
e2f0ba97
JB		 765 dtd->part1.h_active = width & 0xff;
766 dtd->part1.h_blank = h_blank_len & 0xff;
767 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 768 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 769 dtd->part1.v_active = height & 0xff;
770 dtd->part1.v_blank = v_blank_len & 0xff;
771 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 772 ((v_blank_len >> 8) & 0xf);
773
171a9e96 774 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 775 dtd->part2.h_sync_width = h_sync_len & 0xff;
776 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 777 (v_sync_len & 0xf);
e2f0ba97 778 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 779 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
780 ((v_sync_len & 0x30) >> 4);
781
e2f0ba97 782 dtd->part2.dtd_flags = 0x18;
79e53945 783 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 784 dtd->part2.dtd_flags |= 0x2;
79e53945 785 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 786 dtd->part2.dtd_flags |= 0x4;
787
788 dtd->part2.sdvo_flags = 0;
789 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
790 dtd->part2.reserved = 0;
791}
792
793static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 794 const struct intel_sdvo_dtd *dtd)
e2f0ba97 795{
e2f0ba97
JB		 796 mode->hdisplay = dtd->part1.h_active;
797 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
798 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 799 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 800 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
801 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
802 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
803 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
804
805 mode->vdisplay = dtd->part1.v_active;
806 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
807 mode->vsync_start = mode->vdisplay;
808 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 809 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 810 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
811 mode->vsync_end = mode->vsync_start +
812 (dtd->part2.v_sync_off_width & 0xf);
813 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
814 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
815 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
816
817 mode->clock = dtd->part1.clock * 10;
818
171a9e96 819 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 820 if (dtd->part2.dtd_flags & 0x2)
821 mode->flags |= DRM_MODE_FLAG_PHSYNC;
822 if (dtd->part2.dtd_flags & 0x4)
823 mode->flags |= DRM_MODE_FLAG_PVSYNC;
824}
825
e27d8538 826static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 827{
e27d8538 828 struct intel_sdvo_encode encode;
e2f0ba97 829
1a3665c8 830 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 831 return intel_sdvo_get_value(intel_sdvo,
832 SDVO_CMD_GET_SUPP_ENCODE,
833 &encode, sizeof(encode));
e2f0ba97
JB		 834}
835
ea5b213a 836static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 837 uint8_t mode)
e2f0ba97 838{
32aad86f 839 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 840}
841
ea5b213a 842static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 843 uint8_t mode)
844{
32aad86f 845 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 846}
847
848#if 0
ea5b213a 849static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 850{
851 int i, j;
852 uint8_t set_buf_index[2];
853 uint8_t av_split;
854 uint8_t buf_size;
855 uint8_t buf[48];
856 uint8_t *pos;
857
32aad86f 858 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 859
860 for (i = 0; i <= av_split; i++) {
861 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 862 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 863 set_buf_index, 2);
c751ce4f
EA		 864 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
865 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 866
867 pos = buf;
868 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 869 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 870 NULL, 0);
c751ce4f 871 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 872 pos += 8;
873 }
874 }
875}
876#endif
877
3c17fe4b 878static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 879{
880 struct dip_infoframe avi_if = {
881 .type = DIP_TYPE_AVI,
3c17fe4b 882 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 883 .len = DIP_LEN_AVI,
884 };
3c17fe4b
DH		 885 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
886 uint8_t set_buf_index[2] = { 1, 0 };
81014b9d
DV		 887 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
888 uint64_t *data = (uint64_t *)sdvo_data;
3c17fe4b
DH		 889 unsigned i;
890
891 intel_dip_infoframe_csum(&avi_if);
892
81014b9d
DV		 893 /* sdvo spec says that the ecc is handled by the hw, and it looks like
894 * we must not send the ecc field, either. */
895 memcpy(sdvo_data, &avi_if, 3);
896 sdvo_data[3] = avi_if.checksum;
897 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
898
d121a5d2
CW		 899 if (!intel_sdvo_set_value(intel_sdvo,
900 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 901 set_buf_index, 2))
902 return false;
903
81014b9d 904 for (i = 0; i < sizeof(sdvo_data); i += 8) {
d121a5d2
CW		 905 if (!intel_sdvo_set_value(intel_sdvo,
906 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 907 data, 8))
908 return false;
909 data++;
910 }
e2f0ba97 911
d121a5d2
CW		 912 return intel_sdvo_set_value(intel_sdvo,
913 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 914 &tx_rate, 1);
e2f0ba97
JB		 915}
916
32aad86f 917static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 918{
ce6feabd 919 struct intel_sdvo_tv_format format;
40039750 920 uint32_t format_map;
ce6feabd 921
40039750 922 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 923 memset(&format, 0, sizeof(format));
32aad86f 924 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 925
32aad86f
CW		 926 BUILD_BUG_ON(sizeof(format) != 6);
927 return intel_sdvo_set_value(intel_sdvo,
928 SDVO_CMD_SET_TV_FORMAT,
929 &format, sizeof(format));
7026d4ac
ZW		 930}
931
32aad86f
CW		 932static bool
933intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
934 struct drm_display_mode *mode)
e2f0ba97 935{
32aad86f 936 struct intel_sdvo_dtd output_dtd;
79e53945 937
32aad86f
CW		 938 if (!intel_sdvo_set_target_output(intel_sdvo,
939 intel_sdvo->attached_output))
940 return false;
e2f0ba97 941
32aad86f
CW		 942 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
943 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
944 return false;
e2f0ba97 945
32aad86f
CW		 946 return true;
947}
948
c9a29698
DV		 949/* Asks the sdvo controller for the preferred input mode given the output mode.
950 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 951static bool
c9a29698
DV		 952intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
953 struct drm_display_mode *mode,
954 struct drm_display_mode *adjusted_mode)
32aad86f 955{
c9a29698
DV		 956 struct intel_sdvo_dtd input_dtd;
957
32aad86f
CW		 958 /* Reset the input timing to the screen. Assume always input 0. */
959 if (!intel_sdvo_set_target_input(intel_sdvo))
960 return false;
e2f0ba97 961
32aad86f
CW		 962 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
963 mode->clock / 10,
964 mode->hdisplay,
965 mode->vdisplay))
966 return false;
e2f0ba97 967
32aad86f 968 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 969 &input_dtd))
32aad86f 970 return false;
e2f0ba97 971
c9a29698 972 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
79e53945 973
32aad86f
CW		 974 return true;
975}
12682a97 976
32aad86f
CW		 977static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
978 struct drm_display_mode *mode,
979 struct drm_display_mode *adjusted_mode)
980{
890f3359 981 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 982 int multiplier;
12682a97 983
32aad86f
CW		 984 /* We need to construct preferred input timings based on our
985 * output timings. To do that, we have to set the output
986 * timings, even though this isn't really the right place in
987 * the sequence to do it. Oh well.
988 */
989 if (intel_sdvo->is_tv) {
990 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
991 return false;
12682a97 992
c9a29698
DV		 993 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
994 mode,
995 adjusted_mode);
ea5b213a 996 } else if (intel_sdvo->is_lvds) {
32aad86f 997 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 998 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 999 return false;
12682a97 1000
c9a29698
DV		 1001 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1002 mode,
1003 adjusted_mode);
e2f0ba97 1004 }
32aad86f
CW		 1005
1006 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1007 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1008 */
6c9547ff
CW		 1009 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1010 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1011
e2f0ba97
JB		 1012 return true;
1013}
1014
1015static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1016 struct drm_display_mode *mode,
1017 struct drm_display_mode *adjusted_mode)
1018{
1019 struct drm_device *dev = encoder->dev;
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 struct drm_crtc *crtc = encoder->crtc;
1022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1023 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1024 u32 sdvox;
e2f0ba97 1025 struct intel_sdvo_in_out_map in_out;
6651819b 1026 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1027 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1028 int rate;
e2f0ba97
JB		 1029
1030 if (!mode)
1031 return;
1032
1033 /* First, set the input mapping for the first input to our controlled
1034 * output. This is only correct if we're a single-input device, in
1035 * which case the first input is the output from the appropriate SDVO
1036 * channel on the motherboard. In a two-input device, the first input
1037 * will be SDVOB and the second SDVOC.
1038 */
ea5b213a 1039 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1040 in_out.in1 = 0;
1041
c74696b9
PR		 1042 intel_sdvo_set_value(intel_sdvo,
1043 SDVO_CMD_SET_IN_OUT_MAP,
1044 &in_out, sizeof(in_out));
e2f0ba97 1045
6c9547ff
CW		 1046 /* Set the output timings to the screen */
1047 if (!intel_sdvo_set_target_output(intel_sdvo,
1048 intel_sdvo->attached_output))
1049 return;
e2f0ba97 1050
6651819b
DV		 1051 /* lvds has a special fixed output timing. */
1052 if (intel_sdvo->is_lvds)
1053 intel_sdvo_get_dtd_from_mode(&output_dtd,
1054 intel_sdvo->sdvo_lvds_fixed_mode);
1055 else
1056 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1057 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1058 DRM_INFO("Setting output timings on %s failed\n",
1059 SDVO_NAME(intel_sdvo));
79e53945
JB		 1060
1061 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1062 if (!intel_sdvo_set_target_input(intel_sdvo))
1063 return;
79e53945 1064
97aaf910
CW		 1065 if (intel_sdvo->has_hdmi_monitor) {
1066 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1067 intel_sdvo_set_colorimetry(intel_sdvo,
1068 SDVO_COLORIMETRY_RGB256);
1069 intel_sdvo_set_avi_infoframe(intel_sdvo);
1070 } else
1071 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1072
6c9547ff
CW		 1073 if (intel_sdvo->is_tv &&
1074 !intel_sdvo_set_tv_format(intel_sdvo))
1075 return;
e2f0ba97 1076
6651819b
DV		 1077 /* We have tried to get input timing in mode_fixup, and filled into
1078 * adjusted_mode.
1079 */
1080 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c8d4bb54
DV		 1081 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1082 DRM_INFO("Setting input timings on %s failed\n",
1083 SDVO_NAME(intel_sdvo));
79e53945 1084
6c9547ff
CW		 1085 switch (pixel_multiplier) {
1086 default:
32aad86f
CW		 1087 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1088 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1089 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1090 }
32aad86f
CW		 1091 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1092 return;
79e53945
JB		 1093
1094 /* Set the SDVO control regs. */
a6c45cf0 1095 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1096 /* The real mode polarity is set by the SDVO commands, using
1097 * struct intel_sdvo_dtd. */
1098 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1099 if (intel_sdvo->is_hdmi)
1100 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1101 if (INTEL_INFO(dev)->gen < 5)
1102 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1103 } else {
6c9547ff 1104 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1105 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1106 case SDVOB:
1107 sdvox &= SDVOB_PRESERVE_MASK;
1108 break;
1109 case SDVOC:
1110 sdvox &= SDVOC_PRESERVE_MASK;
1111 break;
1112 }
1113 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1114 }
3573c410
PZ		 1115
1116 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1117 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1118 else
1119 sdvox |= TRANSCODER(intel_crtc->pipe);
1120
da79de97 1121 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1122 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1123
a6c45cf0 1124 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1125 /* done in crtc_mode_set as the dpll_md reg must be written early */
1126 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1127 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1128 } else {
6c9547ff 1129 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1130 }
1131
6714afb1
CW		 1132 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1133 INTEL_INFO(dev)->gen < 5)
12682a97 1134 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1135 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1136}
1137
1138static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1139{
1140 struct drm_device *dev = encoder->dev;
1141 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1142 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1143 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1144 u32 temp;
1145
1146 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1147 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1148 if (0)
ea5b213a 1149 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1150
1151 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1152 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1153 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1154 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1155 }
1156 }
1157 } else {
1158 bool input1, input2;
1159 int i;
1160 u8 status;
1161
ea5b213a 1162 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1163 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1164 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1165 for (i = 0; i < 2; i++)
9d0498a2 1166 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1167
32aad86f 1168 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1169 /* Warn if the device reported failure to sync.
1170 * A lot of SDVO devices fail to notify of sync, but it's
1171 * a given it the status is a success, we succeeded.
1172 */
1173 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1174 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1175 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1176 }
1177
1178 if (0)
ea5b213a
CW		 1179 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1180 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1181 }
1182 return;
1183}
1184
79e53945
JB		 1185static int intel_sdvo_mode_valid(struct drm_connector *connector,
1186 struct drm_display_mode *mode)
1187{
df0e9248 1188 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1189
1190 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1191 return MODE_NO_DBLESCAN;
1192
ea5b213a 1193 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1194 return MODE_CLOCK_LOW;
1195
ea5b213a 1196 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1197 return MODE_CLOCK_HIGH;
1198
8545423a 1199 if (intel_sdvo->is_lvds) {
ea5b213a 1200 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1201 return MODE_PANEL;
1202
ea5b213a 1203 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1204 return MODE_PANEL;
1205 }
1206
79e53945
JB		 1207 return MODE_OK;
1208}
1209
ea5b213a 1210static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1211{
1a3665c8 1212 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1213 if (!intel_sdvo_get_value(intel_sdvo,
1214 SDVO_CMD_GET_DEVICE_CAPS,
1215 caps, sizeof(*caps)))
1216 return false;
1217
1218 DRM_DEBUG_KMS("SDVO capabilities:\n"
1219 " vendor_id: %d\n"
1220 " device_id: %d\n"
1221 " device_rev_id: %d\n"
1222 " sdvo_version_major: %d\n"
1223 " sdvo_version_minor: %d\n"
1224 " sdvo_inputs_mask: %d\n"
1225 " smooth_scaling: %d\n"
1226 " sharp_scaling: %d\n"
1227 " up_scaling: %d\n"
1228 " down_scaling: %d\n"
1229 " stall_support: %d\n"
1230 " output_flags: %d\n",
1231 caps->vendor_id,
1232 caps->device_id,
1233 caps->device_rev_id,
1234 caps->sdvo_version_major,
1235 caps->sdvo_version_minor,
1236 caps->sdvo_inputs_mask,
1237 caps->smooth_scaling,
1238 caps->sharp_scaling,
1239 caps->up_scaling,
1240 caps->down_scaling,
1241 caps->stall_support,
1242 caps->output_flags);
1243
1244 return true;
79e53945
JB		 1245}
1246
cc68c81a 1247static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945
JB		 1248{
1249 u8 response[2];
79e53945 1250
32aad86f
CW		 1251 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1252 &response, 2) && response[0];
79e53945
JB		 1253}
1254
cc68c81a 1255static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1256{
cc68c81a 1257 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1258
cc68c81a 1259 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1260}
1261
fb7a46f3 1262static bool
ea5b213a 1263intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1264{
bc65212c 1265 /* Is there more than one type of output? */
2294488d 1266 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1267}
1268
f899fc64 1269static struct edid *
e957d772 1270intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1271{
e957d772
CW		 1272 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1273 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1274}
1275
ff482d83
CW		 1276/* Mac mini hack -- use the same DDC as the analog connector */
1277static struct edid *
1278intel_sdvo_get_analog_edid(struct drm_connector *connector)
1279{
f899fc64 1280 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1281
0c1dab89 1282 return drm_get_edid(connector,
3bd7d909
DK		 1283 intel_gmbus_get_adapter(dev_priv,
1284 dev_priv->crt_ddc_pin));
ff482d83
CW		 1285}
1286
c43b5634 1287static enum drm_connector_status
8bf38485 1288intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1289{
df0e9248 1290 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1291 enum drm_connector_status status;
1292 struct edid *edid;
9dff6af8 1293
e957d772 1294 edid = intel_sdvo_get_edid(connector);
57cdaf90 1295
ea5b213a 1296 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1297 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1298
7c3f0a27
ZY		 1299 /*
1300 * Don't use the 1 as the argument of DDC bus switch to get
1301 * the EDID. It is used for SDVO SPD ROM.
1302 */
9d1a903d 1303 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1304 intel_sdvo->ddc_bus = ddc;
1305 edid = intel_sdvo_get_edid(connector);
1306 if (edid)
7c3f0a27 1307 break;
7c3f0a27 1308 }
e957d772
CW		 1309 /*
1310 * If we found the EDID on the other bus,
1311 * assume that is the correct DDC bus.
1312 */
1313 if (edid == NULL)
1314 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1315 }
9d1a903d
CW		 1316
1317 /*
1318 * When there is no edid and no monitor is connected with VGA
1319 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1320 */
ff482d83
CW		 1321 if (edid == NULL)
1322 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1323
2f551c84 1324 status = connector_status_unknown;
9dff6af8 1325 if (edid != NULL) {
149c36a3 1326 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1327 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1328 status = connector_status_connected;
da79de97
CW		 1329 if (intel_sdvo->is_hdmi) {
1330 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1331 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1332 }
13946743
CW		 1333 } else
1334 status = connector_status_disconnected;
149c36a3 1335 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1336 kfree(edid);
1337 }
7f36e7ed
CW		 1338
1339 if (status == connector_status_connected) {
1340 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1341 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1342 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1343 }
1344
2b8d33f7 1345 return status;
9dff6af8
ML		 1346}
1347
52220085
CW		 1348static bool
1349intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1350 struct edid *edid)
1351{
1352 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1353 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1354
1355 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1356 connector_is_digital, monitor_is_digital);
1357 return connector_is_digital == monitor_is_digital;
1358}
1359
7b334fcb 1360static enum drm_connector_status
930a9e28 1361intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1362{
fb7a46f3 1363 uint16_t response;
df0e9248 1364 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1365 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1366 enum drm_connector_status ret;
79e53945 1367
32aad86f 1368 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1369 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1370 return connector_status_unknown;
ba84cd1f
CW		 1371
1372 /* add 30ms delay when the output type might be TV */
a0b1c7a5 1373 if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
d09c23de 1374 mdelay(30);
ba84cd1f 1375
32aad86f
CW		 1376 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1377 return connector_status_unknown;
79e53945 1378
e957d772
CW		 1379 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1380 response & 0xff, response >> 8,
1381 intel_sdvo_connector->output_flag);
e2f0ba97 1382
fb7a46f3 1383 if (response == 0)
79e53945 1384 return connector_status_disconnected;
fb7a46f3 1385
ea5b213a 1386 intel_sdvo->attached_output = response;
14571b4c 1387
97aaf910
CW		 1388 intel_sdvo->has_hdmi_monitor = false;
1389 intel_sdvo->has_hdmi_audio = false;
1390
615fb93f 1391 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1392 ret = connector_status_disconnected;
13946743 1393 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1394 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1395 else {
1396 struct edid *edid;
1397
1398 /* if we have an edid check it matches the connection */
1399 edid = intel_sdvo_get_edid(connector);
1400 if (edid == NULL)
1401 edid = intel_sdvo_get_analog_edid(connector);
1402 if (edid != NULL) {
52220085
CW		 1403 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1404 edid))
13946743 1405 ret = connector_status_connected;
52220085
CW		 1406 else
1407 ret = connector_status_disconnected;
1408
13946743
CW		 1409 connector->display_info.raw_edid = NULL;
1410 kfree(edid);
1411 } else
1412 ret = connector_status_connected;
1413 }
14571b4c
ZW		 1414
1415 /* May update encoder flag for like clock for SDVO TV, etc.*/
1416 if (ret == connector_status_connected) {
ea5b213a
CW		 1417 intel_sdvo->is_tv = false;
1418 intel_sdvo->is_lvds = false;
1419 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1420
1421 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1422 intel_sdvo->is_tv = true;
1423 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1424 }
1425 if (response & SDVO_LVDS_MASK)
8545423a 1426 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1427 }
14571b4c
ZW		 1428
1429 return ret;
79e53945
JB		 1430}
1431
e2f0ba97 1432static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1433{
ff482d83 1434 struct edid *edid;
79e53945
JB		 1435
1436 /* set the bus switch and get the modes */
e957d772 1437 edid = intel_sdvo_get_edid(connector);
79e53945 1438
57cdaf90
KP		 1439 /*
1440 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1441 * link between analog and digital outputs. So, if the regular SDVO
1442 * DDC fails, check to see if the analog output is disconnected, in
1443 * which case we'll look there for the digital DDC data.
e2f0ba97 1444 */
f899fc64
CW		 1445 if (edid == NULL)
1446 edid = intel_sdvo_get_analog_edid(connector);
1447
ff482d83 1448 if (edid != NULL) {
52220085
CW		 1449 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1450 edid)) {
0c1dab89
CW		 1451 drm_mode_connector_update_edid_property(connector, edid);
1452 drm_add_edid_modes(connector, edid);
1453 }
13946743 1454
ff482d83
CW		 1455 connector->display_info.raw_edid = NULL;
1456 kfree(edid);
e2f0ba97 1457 }
e2f0ba97
JB		 1458}
1459
1460/*
1461 * Set of SDVO TV modes.
1462 * Note! This is in reply order (see loop in get_tv_modes).
1463 * XXX: all 60Hz refresh?
1464 */
b1f559ec 1465static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1466 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1467 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1469 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1470 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1472 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1473 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1475 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1476 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1478 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1479 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1481 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1482 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1484 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1485 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1487 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1488 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1490 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1491 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1493 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1494 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1496 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1497 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1499 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1500 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1502 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1503 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1505 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1506 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1508 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1509 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1511 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1512 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1514 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1515 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1517 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1518 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1520 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1521 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1523};
1524
1525static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1526{
df0e9248 1527 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1528 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1529 uint32_t reply = 0, format_map = 0;
1530 int i;
e2f0ba97
JB		 1531
1532 /* Read the list of supported input resolutions for the selected TV
1533 * format.
1534 */
40039750 1535 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1536 memcpy(&tv_res, &format_map,
32aad86f 1537 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1538
32aad86f
CW		 1539 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1540 return;
ce6feabd 1541
32aad86f 1542 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1543 if (!intel_sdvo_write_cmd(intel_sdvo,
1544 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1545 &tv_res, sizeof(tv_res)))
1546 return;
1547 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1548 return;
1549
1550 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1551 if (reply & (1 << i)) {
1552 struct drm_display_mode *nmode;
1553 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1554 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1555 if (nmode)
1556 drm_mode_probed_add(connector, nmode);
1557 }
e2f0ba97
JB		 1558}
1559
7086c87f
ML		 1560static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1561{
df0e9248 1562 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1563 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1564 struct drm_display_mode *newmode;
7086c87f
ML		 1565
1566 /*
1567 * Attempt to get the mode list from DDC.
1568 * Assume that the preferred modes are
1569 * arranged in priority order.
1570 */
f899fc64 1571 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1572 if (list_empty(&connector->probed_modes) == false)
12682a97 1573 goto end;
7086c87f
ML		 1574
1575 /* Fetch modes from VBT */
1576 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1577 newmode = drm_mode_duplicate(connector->dev,
1578 dev_priv->sdvo_lvds_vbt_mode);
1579 if (newmode != NULL) {
1580 /* Guarantee the mode is preferred */
1581 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1582 DRM_MODE_TYPE_DRIVER);
1583 drm_mode_probed_add(connector, newmode);
1584 }
1585 }
12682a97 1586
1587end:
1588 list_for_each_entry(newmode, &connector->probed_modes, head) {
1589 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1590 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1591 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1592
8545423a 1593 intel_sdvo->is_lvds = true;
12682a97 1594 break;
1595 }
1596 }
1597
7086c87f
ML		 1598}
1599
e2f0ba97
JB		 1600static int intel_sdvo_get_modes(struct drm_connector *connector)
1601{
615fb93f 1602 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1603
615fb93f 1604 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1605 intel_sdvo_get_tv_modes(connector);
615fb93f 1606 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1607 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1608 else
1609 intel_sdvo_get_ddc_modes(connector);
1610
32aad86f 1611 return !list_empty(&connector->probed_modes);
79e53945
JB		 1612}
1613
fcc8d672
CW		 1614static void
1615intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1616{
615fb93f 1617 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1618 struct drm_device *dev = connector->dev;
1619
c5521706
CW		 1620 if (intel_sdvo_connector->left)
1621 drm_property_destroy(dev, intel_sdvo_connector->left);
1622 if (intel_sdvo_connector->right)
1623 drm_property_destroy(dev, intel_sdvo_connector->right);
1624 if (intel_sdvo_connector->top)
1625 drm_property_destroy(dev, intel_sdvo_connector->top);
1626 if (intel_sdvo_connector->bottom)
1627 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1628 if (intel_sdvo_connector->hpos)
1629 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1630 if (intel_sdvo_connector->vpos)
1631 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1632 if (intel_sdvo_connector->saturation)
1633 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1634 if (intel_sdvo_connector->contrast)
1635 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1636 if (intel_sdvo_connector->hue)
1637 drm_property_destroy(dev, intel_sdvo_connector->hue);
1638 if (intel_sdvo_connector->sharpness)
1639 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1640 if (intel_sdvo_connector->flicker_filter)
1641 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1642 if (intel_sdvo_connector->flicker_filter_2d)
1643 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1644 if (intel_sdvo_connector->flicker_filter_adaptive)
1645 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1646 if (intel_sdvo_connector->tv_luma_filter)
1647 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1648 if (intel_sdvo_connector->tv_chroma_filter)
1649 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1650 if (intel_sdvo_connector->dot_crawl)
1651 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1652 if (intel_sdvo_connector->brightness)
1653 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1654}
1655
79e53945
JB		 1656static void intel_sdvo_destroy(struct drm_connector *connector)
1657{
615fb93f 1658 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1659
c5521706 1660 if (intel_sdvo_connector->tv_format)
ce6feabd 1661 drm_property_destroy(connector->dev,
c5521706 1662 intel_sdvo_connector->tv_format);
b9219c5e 1663
d2a82a6f 1664 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1665 drm_sysfs_connector_remove(connector);
1666 drm_connector_cleanup(connector);
d2a82a6f 1667 kfree(connector);
79e53945
JB		 1668}
1669
1aad7ac0
CW		 1670static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1671{
1672 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1673 struct edid *edid;
1674 bool has_audio = false;
1675
1676 if (!intel_sdvo->is_hdmi)
1677 return false;
1678
1679 edid = intel_sdvo_get_edid(connector);
1680 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1681 has_audio = drm_detect_monitor_audio(edid);
1682
1683 return has_audio;
1684}
1685
ce6feabd
ZY		 1686static int
1687intel_sdvo_set_property(struct drm_connector *connector,
1688 struct drm_property *property,
1689 uint64_t val)
1690{
df0e9248 1691 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1692 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1693 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1694 uint16_t temp_value;
32aad86f
CW		 1695 uint8_t cmd;
1696 int ret;
ce6feabd
ZY		 1697
1698 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1699 if (ret)
1700 return ret;
ce6feabd 1701
3f43c48d 1702 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1703 int i = val;
1704 bool has_audio;
1705
1706 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1707 return 0;
1708
1aad7ac0 1709 intel_sdvo_connector->force_audio = i;
7f36e7ed 1710
c3e5f67b 1711 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1712 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1713 else
c3e5f67b 1714 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1715
1aad7ac0 1716 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1717 return 0;
7f36e7ed 1718
1aad7ac0 1719 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1720 goto done;
1721 }
1722
e953fd7b
CW		 1723 if (property == dev_priv->broadcast_rgb_property) {
1724 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1725 return 0;
1726
e953fd7b 1727 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1728 goto done;
1729 }
1730
c5521706
CW		 1731#define CHECK_PROPERTY(name, NAME) \
1732 if (intel_sdvo_connector->name == property) { \
1733 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1734 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1735 cmd = SDVO_CMD_SET_##NAME; \
1736 intel_sdvo_connector->cur_##name = temp_value; \
1737 goto set_value; \
1738 }
1739
1740 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1741 if (val >= TV_FORMAT_NUM)
1742 return -EINVAL;
1743
40039750 1744 if (intel_sdvo->tv_format_index ==
615fb93f 1745 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1746 return 0;
ce6feabd 1747
40039750 1748 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1749 goto done;
32aad86f 1750 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1751 temp_value = val;
c5521706 1752 if (intel_sdvo_connector->left == property) {
b9219c5e 1753 drm_connector_property_set_value(connector,
c5521706 1754 intel_sdvo_connector->right, val);
615fb93f 1755 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1756 return 0;
b9219c5e 1757
615fb93f
CW		 1758 intel_sdvo_connector->left_margin = temp_value;
1759 intel_sdvo_connector->right_margin = temp_value;
1760 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1761 intel_sdvo_connector->left_margin;
b9219c5e 1762 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1763 goto set_value;
1764 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1765 drm_connector_property_set_value(connector,
c5521706 1766 intel_sdvo_connector->left, val);
615fb93f 1767 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1768 return 0;
b9219c5e 1769
615fb93f
CW		 1770 intel_sdvo_connector->left_margin = temp_value;
1771 intel_sdvo_connector->right_margin = temp_value;
1772 temp_value = intel_sdvo_connector->max_hscan -
1773 intel_sdvo_connector->left_margin;
b9219c5e 1774 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1775 goto set_value;
1776 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1777 drm_connector_property_set_value(connector,
c5521706 1778 intel_sdvo_connector->bottom, val);
615fb93f 1779 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1780 return 0;
b9219c5e 1781
615fb93f
CW		 1782 intel_sdvo_connector->top_margin = temp_value;
1783 intel_sdvo_connector->bottom_margin = temp_value;
1784 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1785 intel_sdvo_connector->top_margin;
b9219c5e 1786 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1787 goto set_value;
1788 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1789 drm_connector_property_set_value(connector,
c5521706 1790 intel_sdvo_connector->top, val);
615fb93f 1791 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1792 return 0;
1793
615fb93f
CW		 1794 intel_sdvo_connector->top_margin = temp_value;
1795 intel_sdvo_connector->bottom_margin = temp_value;
1796 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1797 intel_sdvo_connector->top_margin;
b9219c5e 1798 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1799 goto set_value;
1800 }
1801 CHECK_PROPERTY(hpos, HPOS)
1802 CHECK_PROPERTY(vpos, VPOS)
1803 CHECK_PROPERTY(saturation, SATURATION)
1804 CHECK_PROPERTY(contrast, CONTRAST)
1805 CHECK_PROPERTY(hue, HUE)
1806 CHECK_PROPERTY(brightness, BRIGHTNESS)
1807 CHECK_PROPERTY(sharpness, SHARPNESS)
1808 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1809 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1810 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1811 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1812 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1813 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1814 }
b9219c5e 1815
c5521706 1816 return -EINVAL; /* unknown property */
b9219c5e 1817
c5521706
CW		 1818set_value:
1819 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1820 return -EIO;
b9219c5e 1821
b9219c5e 1822
c5521706 1823done:
df0e9248
CW		 1824 if (intel_sdvo->base.base.crtc) {
1825 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1826 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1827 crtc->y, crtc->fb);
1828 }
1829
32aad86f 1830 return 0;
c5521706 1831#undef CHECK_PROPERTY
ce6feabd
ZY		 1832}
1833
79e53945
JB		 1834static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1835 .dpms = intel_sdvo_dpms,
1836 .mode_fixup = intel_sdvo_mode_fixup,
1837 .prepare = intel_encoder_prepare,
1838 .mode_set = intel_sdvo_mode_set,
1839 .commit = intel_encoder_commit,
1840};
1841
1842static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1843 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1844 .detect = intel_sdvo_detect,
1845 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1846 .set_property = intel_sdvo_set_property,
79e53945
JB		 1847 .destroy = intel_sdvo_destroy,
1848};
1849
1850static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1851 .get_modes = intel_sdvo_get_modes,
1852 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1853 .best_encoder = intel_best_encoder,
79e53945
JB		 1854};
1855
b358d0a6 1856static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1857{
890f3359 1858 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1859
ea5b213a 1860 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1861 drm_mode_destroy(encoder->dev,
ea5b213a 1862 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1863
e957d772 1864 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1865 intel_encoder_destroy(encoder);
79e53945
JB		 1866}
1867
1868static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1869 .destroy = intel_sdvo_enc_destroy,
1870};
1871
b66d8424
CW		 1872static void
1873intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1874{
1875 uint16_t mask = 0;
1876 unsigned int num_bits;
1877
1878 /* Make a mask of outputs less than or equal to our own priority in the
1879 * list.
1880 */
1881 switch (sdvo->controlled_output) {
1882 case SDVO_OUTPUT_LVDS1:
1883 mask |= SDVO_OUTPUT_LVDS1;
1884 case SDVO_OUTPUT_LVDS0:
1885 mask |= SDVO_OUTPUT_LVDS0;
1886 case SDVO_OUTPUT_TMDS1:
1887 mask |= SDVO_OUTPUT_TMDS1;
1888 case SDVO_OUTPUT_TMDS0:
1889 mask |= SDVO_OUTPUT_TMDS0;
1890 case SDVO_OUTPUT_RGB1:
1891 mask |= SDVO_OUTPUT_RGB1;
1892 case SDVO_OUTPUT_RGB0:
1893 mask |= SDVO_OUTPUT_RGB0;
1894 break;
1895 }
1896
1897 /* Count bits to find what number we are in the priority list. */
1898 mask &= sdvo->caps.output_flags;
1899 num_bits = hweight16(mask);
1900 /* If more than 3 outputs, default to DDC bus 3 for now. */
1901 if (num_bits > 3)
1902 num_bits = 3;
1903
1904 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1905 sdvo->ddc_bus = 1 << num_bits;
1906}
79e53945 1907
e2f0ba97
JB		 1908/**
1909 * Choose the appropriate DDC bus for control bus switch command for this
1910 * SDVO output based on the controlled output.
1911 *
1912 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1913 * outputs, then LVDS outputs.
1914 */
1915static void
b1083333 1916intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1917 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1918{
b1083333 1919 struct sdvo_device_mapping *mapping;
e2f0ba97 1920
eef4eacb 1921 if (sdvo->is_sdvob)
b1083333
AJ		 1922 mapping = &(dev_priv->sdvo_mappings[0]);
1923 else
1924 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1925
b66d8424
CW		 1926 if (mapping->initialized)
1927 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1928 else
1929 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1930}
1931
e957d772
CW		 1932static void
1933intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1934 struct intel_sdvo *sdvo, u32 reg)
1935{
1936 struct sdvo_device_mapping *mapping;
46eb3036 1937 u8 pin;
e957d772 1938
eef4eacb 1939 if (sdvo->is_sdvob)
e957d772
CW		 1940 mapping = &dev_priv->sdvo_mappings[0];
1941 else
1942 mapping = &dev_priv->sdvo_mappings[1];
1943
1944 pin = GMBUS_PORT_DPB;
46eb3036 1945 if (mapping->initialized)
e957d772 1946 pin = mapping->i2c_pin;
e957d772 1947
3bd7d909
DK		 1948 if (intel_gmbus_is_port_valid(pin)) {
1949 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
d5090b96 1950 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1951 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1952 } else {
3bd7d909 1953 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
46eb3036 1954 }
e957d772
CW		 1955}
1956
e2f0ba97 1957static bool
e27d8538 1958intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1959{
97aaf910 1960 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1961}
1962
714605e4 1963static u8
eef4eacb 1964intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 1965{
1966 struct drm_i915_private *dev_priv = dev->dev_private;
1967 struct sdvo_device_mapping *my_mapping, *other_mapping;
1968
eef4eacb 1969 if (sdvo->is_sdvob) {
714605e4 1970 my_mapping = &dev_priv->sdvo_mappings[0];
1971 other_mapping = &dev_priv->sdvo_mappings[1];
1972 } else {
1973 my_mapping = &dev_priv->sdvo_mappings[1];
1974 other_mapping = &dev_priv->sdvo_mappings[0];
1975 }
1976
1977 /* If the BIOS described our SDVO device, take advantage of it. */
1978 if (my_mapping->slave_addr)
1979 return my_mapping->slave_addr;
1980
1981 /* If the BIOS only described a different SDVO device, use the
1982 * address that it isn't using.
1983 */
1984 if (other_mapping->slave_addr) {
1985 if (other_mapping->slave_addr == 0x70)
1986 return 0x72;
1987 else
1988 return 0x70;
1989 }
1990
1991 /* No SDVO device info is found for another DVO port,
1992 * so use mapping assumption we had before BIOS parsing.
1993 */
eef4eacb 1994 if (sdvo->is_sdvob)
714605e4 1995 return 0x70;
1996 else
1997 return 0x72;
1998}
1999
14571b4c 2000static void
df0e9248
CW		 2001intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2002 struct intel_sdvo *encoder)
14571b4c 2003{
df0e9248
CW		 2004 drm_connector_init(encoder->base.base.dev,
2005 &connector->base.base,
2006 &intel_sdvo_connector_funcs,
2007 connector->base.base.connector_type);
6070a4a9 2008
df0e9248
CW		 2009 drm_connector_helper_add(&connector->base.base,
2010 &intel_sdvo_connector_helper_funcs);
14571b4c 2011
8f4839e2 2012 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2013 connector->base.base.doublescan_allowed = 0;
2014 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2015
df0e9248
CW		 2016 intel_connector_attach_encoder(&connector->base, &encoder->base);
2017 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2018}
6070a4a9 2019
7f36e7ed
CW		 2020static void
2021intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2022{
2023 struct drm_device *dev = connector->base.base.dev;
2024
3f43c48d 2025 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2026 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2027 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2028}
2029
fb7a46f3 2030static bool
ea5b213a 2031intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2032{
4ef69c7a 2033 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2034 struct drm_connector *connector;
cc68c81a 2035 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2036 struct intel_connector *intel_connector;
615fb93f 2037 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2038
615fb93f
CW		 2039 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2040 if (!intel_sdvo_connector)
14571b4c
ZW		 2041 return false;
2042
14571b4c 2043 if (device == 0) {
ea5b213a 2044 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2045 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2046 } else if (device == 1) {
ea5b213a 2047 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2048 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2049 }
2050
615fb93f 2051 intel_connector = &intel_sdvo_connector->base;
14571b4c 2052 connector = &intel_connector->base;
cc68c81a
SF		 2053 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2054 connector->polled = DRM_CONNECTOR_POLL_HPD;
2055 intel_sdvo->hotplug_active[0] |= 1 << device;
2056 /* Some SDVO devices have one-shot hotplug interrupts.
2057 * Ensure that they get re-enabled when an interrupt happens.
2058 */
2059 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2060 intel_sdvo_enable_hotplug(intel_encoder);
2061 }
2062 else
2063 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2064 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2065 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2066
e27d8538 2067 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2068 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2069 intel_sdvo->is_hdmi = true;
14571b4c 2070 }
ea5b213a
CW		 2071 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2072 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2073
df0e9248 2074 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2075 if (intel_sdvo->is_hdmi)
2076 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2077
2078 return true;
2079}
2080
2081static bool
ea5b213a 2082intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2083{
4ef69c7a
CW		 2084 struct drm_encoder *encoder = &intel_sdvo->base.base;
2085 struct drm_connector *connector;
2086 struct intel_connector *intel_connector;
2087 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2088
615fb93f
CW		 2089 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2090 if (!intel_sdvo_connector)
2091 return false;
14571b4c 2092
615fb93f 2093 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2094 connector = &intel_connector->base;
2095 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2096 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2097
4ef69c7a
CW		 2098 intel_sdvo->controlled_output |= type;
2099 intel_sdvo_connector->output_flag = type;
14571b4c 2100
4ef69c7a
CW		 2101 intel_sdvo->is_tv = true;
2102 intel_sdvo->base.needs_tv_clock = true;
2103 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2104
df0e9248 2105 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2106
4ef69c7a 2107 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2108 goto err;
14571b4c 2109
4ef69c7a 2110 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2111 goto err;
14571b4c 2112
4ef69c7a 2113 return true;
32aad86f
CW		 2114
2115err:
123d5c01 2116 intel_sdvo_destroy(connector);
32aad86f 2117 return false;
14571b4c
ZW		 2118}
2119
2120static bool
ea5b213a 2121intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2122{
4ef69c7a
CW		 2123 struct drm_encoder *encoder = &intel_sdvo->base.base;
2124 struct drm_connector *connector;
2125 struct intel_connector *intel_connector;
2126 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2127
615fb93f
CW		 2128 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2129 if (!intel_sdvo_connector)
2130 return false;
14571b4c 2131
615fb93f 2132 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2133 connector = &intel_connector->base;
eb1f8e4f 2134 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2135 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2136 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2137
2138 if (device == 0) {
2139 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2140 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2141 } else if (device == 1) {
2142 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2143 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2144 }
2145
2146 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2147 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2148
df0e9248
CW		 2149 intel_sdvo_connector_init(intel_sdvo_connector,
2150 intel_sdvo);
4ef69c7a 2151 return true;
14571b4c
ZW		 2152}
2153
2154static bool
ea5b213a 2155intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2156{
4ef69c7a
CW		 2157 struct drm_encoder *encoder = &intel_sdvo->base.base;
2158 struct drm_connector *connector;
2159 struct intel_connector *intel_connector;
2160 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2161
615fb93f
CW		 2162 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2163 if (!intel_sdvo_connector)
2164 return false;
14571b4c 2165
615fb93f
CW		 2166 intel_connector = &intel_sdvo_connector->base;
2167 connector = &intel_connector->base;
4ef69c7a
CW		 2168 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2169 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2170
2171 if (device == 0) {
2172 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2173 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2174 } else if (device == 1) {
2175 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2176 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2177 }
2178
2179 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2180 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2181
df0e9248 2182 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2183 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2184 goto err;
2185
2186 return true;
2187
2188err:
123d5c01 2189 intel_sdvo_destroy(connector);
32aad86f 2190 return false;
14571b4c
ZW		 2191}
2192
2193static bool
ea5b213a 2194intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2195{
ea5b213a
CW		 2196 intel_sdvo->is_tv = false;
2197 intel_sdvo->base.needs_tv_clock = false;
2198 intel_sdvo->is_lvds = false;
fb7a46f3 2199
14571b4c 2200 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2201
14571b4c 2202 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2203 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2204 return false;
2205
2206 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2207 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2208 return false;
2209
2210 /* TV has no XXX1 function block */
a1f4b7ff 2211 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2212 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2213 return false;
2214
2215 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2216 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2217 return false;
fb7a46f3 2218
a0b1c7a5
CW		 2219 if (flags & SDVO_OUTPUT_YPRPB0)
2220 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2221 return false;
2222
14571b4c 2223 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2224 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2225 return false;
2226
2227 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2228 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2229 return false;
2230
2231 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2232 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2233 return false;
2234
2235 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2236 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2237 return false;
fb7a46f3 2238
14571b4c 2239 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2240 unsigned char bytes[2];
2241
ea5b213a
CW		 2242 intel_sdvo->controlled_output = 0;
2243 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2244 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2245 SDVO_NAME(intel_sdvo),
51c8b407 2246 bytes[0], bytes[1]);
14571b4c 2247 return false;
fb7a46f3 2248 }
27f8227b 2249 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2250
14571b4c 2251 return true;
fb7a46f3 2252}
2253
32aad86f
CW		 2254static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2255 struct intel_sdvo_connector *intel_sdvo_connector,
2256 int type)
ce6feabd 2257{
4ef69c7a 2258 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2259 struct intel_sdvo_tv_format format;
2260 uint32_t format_map, i;
ce6feabd 2261
32aad86f
CW		 2262 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2263 return false;
ce6feabd 2264
1a3665c8 2265 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2266 if (!intel_sdvo_get_value(intel_sdvo,
2267 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2268 &format, sizeof(format)))
2269 return false;
ce6feabd 2270
32aad86f 2271 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2272
2273 if (format_map == 0)
32aad86f 2274 return false;
ce6feabd 2275
615fb93f 2276 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2277 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2278 if (format_map & (1 << i))
2279 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2280
2281
c5521706 2282 intel_sdvo_connector->tv_format =
32aad86f
CW		 2283 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2284 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2285 if (!intel_sdvo_connector->tv_format)
fcc8d672 2286 return false;
ce6feabd 2287
615fb93f 2288 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2289 drm_property_add_enum(
c5521706 2290 intel_sdvo_connector->tv_format, i,
40039750 2291 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2292
40039750 2293 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2294 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2295 intel_sdvo_connector->tv_format, 0);
32aad86f 2296 return true;
ce6feabd
ZY		 2297
2298}
2299
c5521706
CW		 2300#define ENHANCEMENT(name, NAME) do { \
2301 if (enhancements.name) { \
2302 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2303 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2304 return false; \
2305 intel_sdvo_connector->max_##name = data_value[0]; \
2306 intel_sdvo_connector->cur_##name = response; \
2307 intel_sdvo_connector->name = \
d9bc3c02 2308 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2309 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2310 drm_connector_attach_property(connector, \
2311 intel_sdvo_connector->name, \
2312 intel_sdvo_connector->cur_##name); \
2313 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2314 data_value[0], data_value[1], response); \
2315 } \
0206e353 2316} while (0)
c5521706
CW		 2317
2318static bool
2319intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2320 struct intel_sdvo_connector *intel_sdvo_connector,
2321 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2322{
4ef69c7a 2323 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2324 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2325 uint16_t response, data_value[2];
2326
c5521706
CW		 2327 /* when horizontal overscan is supported, Add the left/right property */
2328 if (enhancements.overscan_h) {
2329 if (!intel_sdvo_get_value(intel_sdvo,
2330 SDVO_CMD_GET_MAX_OVERSCAN_H,
2331 &data_value, 4))
2332 return false;
32aad86f 2333
c5521706
CW		 2334 if (!intel_sdvo_get_value(intel_sdvo,
2335 SDVO_CMD_GET_OVERSCAN_H,
2336 &response, 2))
2337 return false;
fcc8d672 2338
c5521706
CW		 2339 intel_sdvo_connector->max_hscan = data_value[0];
2340 intel_sdvo_connector->left_margin = data_value[0] - response;
2341 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2342 intel_sdvo_connector->left =
d9bc3c02 2343 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2344 if (!intel_sdvo_connector->left)
2345 return false;
fcc8d672 2346
c5521706
CW		 2347 drm_connector_attach_property(connector,
2348 intel_sdvo_connector->left,
2349 intel_sdvo_connector->left_margin);
fcc8d672 2350
c5521706 2351 intel_sdvo_connector->right =
d9bc3c02 2352 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2353 if (!intel_sdvo_connector->right)
2354 return false;
32aad86f 2355
c5521706
CW		 2356 drm_connector_attach_property(connector,
2357 intel_sdvo_connector->right,
2358 intel_sdvo_connector->right_margin);
2359 DRM_DEBUG_KMS("h_overscan: max %d, "
2360 "default %d, current %d\n",
2361 data_value[0], data_value[1], response);
2362 }
32aad86f 2363
c5521706
CW		 2364 if (enhancements.overscan_v) {
2365 if (!intel_sdvo_get_value(intel_sdvo,
2366 SDVO_CMD_GET_MAX_OVERSCAN_V,
2367 &data_value, 4))
2368 return false;
fcc8d672 2369
c5521706
CW		 2370 if (!intel_sdvo_get_value(intel_sdvo,
2371 SDVO_CMD_GET_OVERSCAN_V,
2372 &response, 2))
2373 return false;
32aad86f 2374
c5521706
CW		 2375 intel_sdvo_connector->max_vscan = data_value[0];
2376 intel_sdvo_connector->top_margin = data_value[0] - response;
2377 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2378 intel_sdvo_connector->top =
d9bc3c02
SH		 2379 drm_property_create_range(dev, 0,
2380 "top_margin", 0, data_value[0]);
c5521706
CW		 2381 if (!intel_sdvo_connector->top)
2382 return false;
32aad86f 2383
c5521706
CW		 2384 drm_connector_attach_property(connector,
2385 intel_sdvo_connector->top,
2386 intel_sdvo_connector->top_margin);
fcc8d672 2387
c5521706 2388 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2389 drm_property_create_range(dev, 0,
2390 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2391 if (!intel_sdvo_connector->bottom)
2392 return false;
32aad86f 2393
c5521706
CW		 2394 drm_connector_attach_property(connector,
2395 intel_sdvo_connector->bottom,
2396 intel_sdvo_connector->bottom_margin);
2397 DRM_DEBUG_KMS("v_overscan: max %d, "
2398 "default %d, current %d\n",
2399 data_value[0], data_value[1], response);
2400 }
32aad86f 2401
c5521706
CW		 2402 ENHANCEMENT(hpos, HPOS);
2403 ENHANCEMENT(vpos, VPOS);
2404 ENHANCEMENT(saturation, SATURATION);
2405 ENHANCEMENT(contrast, CONTRAST);
2406 ENHANCEMENT(hue, HUE);
2407 ENHANCEMENT(sharpness, SHARPNESS);
2408 ENHANCEMENT(brightness, BRIGHTNESS);
2409 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2410 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2411 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2412 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2413 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2414
e044218a
CW		 2415 if (enhancements.dot_crawl) {
2416 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2417 return false;
2418
2419 intel_sdvo_connector->max_dot_crawl = 1;
2420 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2421 intel_sdvo_connector->dot_crawl =
d9bc3c02 2422 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2423 if (!intel_sdvo_connector->dot_crawl)
2424 return false;
2425
e044218a
CW		 2426 drm_connector_attach_property(connector,
2427 intel_sdvo_connector->dot_crawl,
2428 intel_sdvo_connector->cur_dot_crawl);
2429 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2430 }
2431
c5521706
CW		 2432 return true;
2433}
32aad86f 2434
c5521706
CW		 2435static bool
2436intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2437 struct intel_sdvo_connector *intel_sdvo_connector,
2438 struct intel_sdvo_enhancements_reply enhancements)
2439{
4ef69c7a 2440 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2441 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2442 uint16_t response, data_value[2];
32aad86f 2443
c5521706 2444 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2445
c5521706
CW		 2446 return true;
2447}
2448#undef ENHANCEMENT
32aad86f 2449
c5521706
CW		 2450static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2451 struct intel_sdvo_connector *intel_sdvo_connector)
2452{
2453 union {
2454 struct intel_sdvo_enhancements_reply reply;
2455 uint16_t response;
2456 } enhancements;
32aad86f 2457
1a3665c8
CW		 2458 BUILD_BUG_ON(sizeof(enhancements) != 2);
2459
cf9a2f3a
CW		 2460 enhancements.response = 0;
2461 intel_sdvo_get_value(intel_sdvo,
2462 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2463 &enhancements, sizeof(enhancements));
c5521706
CW		 2464 if (enhancements.response == 0) {
2465 DRM_DEBUG_KMS("No enhancement is supported\n");
2466 return true;
b9219c5e 2467 }
32aad86f 2468
c5521706
CW		 2469 if (IS_TV(intel_sdvo_connector))
2470 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2471 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2472 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2473 else
2474 return true;
e957d772
CW		 2475}
2476
2477static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2478 struct i2c_msg *msgs,
2479 int num)
2480{
2481 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2482
e957d772
CW		 2483 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2484 return -EIO;
2485
2486 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2487}
2488
2489static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2490{
2491 struct intel_sdvo *sdvo = adapter->algo_data;
2492 return sdvo->i2c->algo->functionality(sdvo->i2c);
2493}
2494
2495static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2496 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2497 .functionality = intel_sdvo_ddc_proxy_func
2498};
2499
2500static bool
2501intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2502 struct drm_device *dev)
2503{
2504 sdvo->ddc.owner = THIS_MODULE;
2505 sdvo->ddc.class = I2C_CLASS_DDC;
2506 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2507 sdvo->ddc.dev.parent = &dev->pdev->dev;
2508 sdvo->ddc.algo_data = sdvo;
2509 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2510
2511 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2512}
2513
eef4eacb 2514bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2515{
b01f2c3a 2516 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2517 struct intel_encoder *intel_encoder;
ea5b213a 2518 struct intel_sdvo *intel_sdvo;
084b612e 2519 u32 hotplug_mask;
79e53945 2520 int i;
79e53945 2521
ea5b213a
CW		 2522 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2523 if (!intel_sdvo)
7d57382e 2524 return false;
79e53945 2525
56184e3d 2526 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2527 intel_sdvo->is_sdvob = is_sdvob;
2528 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2529 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2530 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2531 kfree(intel_sdvo);
2532 return false;
2533 }
2534
56184e3d 2535 /* encoder type will be decided later */
ea5b213a 2536 intel_encoder = &intel_sdvo->base;
21d40d37 2537 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2538 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2539
79e53945
JB		 2540 /* Read the regs to test if we can talk to the device */
2541 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2542 u8 byte;
2543
2544 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2545 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2546 SDVO_NAME(intel_sdvo));
f899fc64 2547 goto err;
79e53945
JB		 2548 }
2549 }
2550
084b612e
CW		 2551 hotplug_mask = 0;
2552 if (IS_G4X(dev)) {
2553 hotplug_mask = intel_sdvo->is_sdvob ?
2554 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2555 } else if (IS_GEN4(dev)) {
2556 hotplug_mask = intel_sdvo->is_sdvob ?
2557 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2558 } else {
2559 hotplug_mask = intel_sdvo->is_sdvob ?
2560 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2561 }
2562 dev_priv->hotplug_supported_mask |= hotplug_mask;
619ac3b7 2563
4ef69c7a 2564 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2565
af901ca1 2566 /* In default case sdvo lvds is false */
32aad86f 2567 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2568 goto err;
79e53945 2569
cc68c81a
SF		 2570 /* Set up hotplug command - note paranoia about contents of reply.
2571 * We assume that the hardware is in a sane state, and only touch
2572 * the bits we think we understand.
2573 */
2574 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2575 &intel_sdvo->hotplug_active, 2);
2576 intel_sdvo->hotplug_active[0] &= ~0x3;
2577
ea5b213a
CW		 2578 if (intel_sdvo_output_setup(intel_sdvo,
2579 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2580 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2581 SDVO_NAME(intel_sdvo));
f899fc64 2582 goto err;
79e53945
JB		 2583 }
2584
ea5b213a 2585 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2586
79e53945 2587 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2588 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2589 goto err;
79e53945 2590
32aad86f
CW		 2591 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2592 &intel_sdvo->pixel_clock_min,
2593 &intel_sdvo->pixel_clock_max))
f899fc64 2594 goto err;
79e53945 2595
8a4c47f3 2596 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2597 "clock range %dMHz - %dMHz, "
2598 "input 1: %c, input 2: %c, "
2599 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2600 SDVO_NAME(intel_sdvo),
2601 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2602 intel_sdvo->caps.device_rev_id,
2603 intel_sdvo->pixel_clock_min / 1000,
2604 intel_sdvo->pixel_clock_max / 1000,
2605 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2606 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2607 /* check currently supported outputs */
ea5b213a 2608 intel_sdvo->caps.output_flags &
79e53945 2609 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2610 intel_sdvo->caps.output_flags &
79e53945 2611 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2612 return true;
79e53945 2613
f899fc64 2614err:
373a3cf7 2615 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2616 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2617 kfree(intel_sdvo);
79e53945 2618
7d57382e 2619 return false;
79e53945 2620}
Linux kernel - Deliverables
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