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drm/i915/dp: do not write DP_TRAINING_PATTERN_SET all the time
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
19d415a2 83 * intel_sdvo_get_capabilities()
e2f0ba97 84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
8aca63aa 205static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 206{
8aca63aa 207 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
8aca63aa 212 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 213}
214
615fb93f
CW		 215static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
216{
217 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
218}
219
fb7a46f3 220static bool
ea5b213a 221intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 222static bool
223intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
224 struct intel_sdvo_connector *intel_sdvo_connector,
225 int type);
226static bool
227intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
228 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 229
79e53945
JB		 230/**
231 * Writes the SDVOB or SDVOC with the given value, but always writes both
232 * SDVOB and SDVOC to work around apparent hardware issues (according to
233 * comments in the BIOS).
234 */
ea5b213a 235static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 236{
4ef69c7a 237 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 238 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 239 u32 bval = val, cval = val;
240 int i;
241
ea5b213a
CW		 242 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
243 I915_WRITE(intel_sdvo->sdvo_reg, val);
244 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 245 return;
246 }
247
e2debe91
PZ		 248 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
249 cval = I915_READ(GEN3_SDVOC);
250 else
251 bval = I915_READ(GEN3_SDVOB);
252
79e53945
JB		 253 /*
254 * Write the registers twice for luck. Sometimes,
255 * writing them only once doesn't appear to 'stick'.
256 * The BIOS does this too. Yay, magic
257 */
258 for (i = 0; i < 2; i++)
259 {
e2debe91
PZ		 260 I915_WRITE(GEN3_SDVOB, bval);
261 I915_READ(GEN3_SDVOB);
262 I915_WRITE(GEN3_SDVOC, cval);
263 I915_READ(GEN3_SDVOC);
79e53945
JB		 264 }
265}
266
32aad86f 267static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 268{
79e53945
JB		 269 struct i2c_msg msgs[] = {
270 {
e957d772 271 .addr = intel_sdvo->slave_addr,
79e53945
JB		 272 .flags = 0,
273 .len = 1,
e957d772 274 .buf = &addr,
79e53945
JB		 275 },
276 {
e957d772 277 .addr = intel_sdvo->slave_addr,
79e53945
JB		 278 .flags = I2C_M_RD,
279 .len = 1,
e957d772 280 .buf = ch,
79e53945
JB		 281 }
282 };
32aad86f 283 int ret;
79e53945 284
f899fc64 285 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 286 return true;
79e53945 287
8a4c47f3 288 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 289 return false;
290}
291
79e53945
JB		 292#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
293/** Mapping of command numbers to names, for debug output */
005568be 294static const struct _sdvo_cmd_name {
e2f0ba97 295 u8 cmd;
2e88e40b 296 const char *name;
79e53945 297} sdvo_cmd_names[] = {
0206e353
AJ		 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
341
342 /* Add the op code for SDVO enhancements */
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
387
388 /* HDMI op code */
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 409};
410
eef4eacb 411#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 412
ea5b213a 413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 414 const void *args, int args_len)
79e53945 415{
79e53945
JB		 416 int i;
417
8a4c47f3 418 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 419 SDVO_NAME(intel_sdvo), cmd);
79e53945 420 for (i = 0; i < args_len; i++)
342dc382 421 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 422 for (; i < 8; i++)
342dc382 423 DRM_LOG_KMS(" ");
04ad327f 424 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 425 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 426 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 427 break;
428 }
429 }
04ad327f 430 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 431 DRM_LOG_KMS("(%02X)", cmd);
432 DRM_LOG_KMS("\n");
79e53945 433}
79e53945 434
e957d772
CW		 435static const char *cmd_status_names[] = {
436 "Power on",
437 "Success",
438 "Not supported",
439 "Invalid arg",
440 "Pending",
441 "Target not specified",
442 "Scaling not supported"
443};
444
32aad86f
CW		 445static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
446 const void *args, int args_len)
79e53945 447{
3bf3f452
BW		 448 u8 *buf, status;
449 struct i2c_msg *msgs;
450 int i, ret = true;
451
0274df3e 452 /* Would be simpler to allocate both in one go ? */
5c67eeb6 453 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 454 if (!buf)
455 return false;
456
457 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 458 if (!msgs) {
459 kfree(buf);
3bf3f452 460 return false;
0274df3e 461 }
79e53945 462
ea5b213a 463 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 464
465 for (i = 0; i < args_len; i++) {
e957d772
CW		 466 msgs[i].addr = intel_sdvo->slave_addr;
467 msgs[i].flags = 0;
468 msgs[i].len = 2;
469 msgs[i].buf = buf + 2 *i;
470 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
471 buf[2*i + 1] = ((u8*)args)[i];
472 }
473 msgs[i].addr = intel_sdvo->slave_addr;
474 msgs[i].flags = 0;
475 msgs[i].len = 2;
476 msgs[i].buf = buf + 2*i;
477 buf[2*i + 0] = SDVO_I2C_OPCODE;
478 buf[2*i + 1] = cmd;
479
480 /* the following two are to read the response */
481 status = SDVO_I2C_CMD_STATUS;
482 msgs[i+1].addr = intel_sdvo->slave_addr;
483 msgs[i+1].flags = 0;
484 msgs[i+1].len = 1;
485 msgs[i+1].buf = &status;
486
487 msgs[i+2].addr = intel_sdvo->slave_addr;
488 msgs[i+2].flags = I2C_M_RD;
489 msgs[i+2].len = 1;
490 msgs[i+2].buf = &status;
491
492 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
493 if (ret < 0) {
494 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 495 ret = false;
496 goto out;
e957d772
CW		 497 }
498 if (ret != i+3) {
499 /* failure in I2C transfer */
500 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 501 ret = false;
e957d772
CW		 502 }
503
3bf3f452
BW		 504out:
505 kfree(msgs);
506 kfree(buf);
507 return ret;
79e53945
JB		 508}
509
b5c616a7
CW		 510static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
511 void *response, int response_len)
79e53945 512{
fc37381c 513 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 514 u8 status;
33b52961 515 int i;
79e53945 516
d121a5d2
CW		 517 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
518
b5c616a7
CW		 519 /*
520 * The documentation states that all commands will be
521 * processed within 15µs, and that we need only poll
522 * the status byte a maximum of 3 times in order for the
523 * command to be complete.
524 *
525 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 526 *
527 * Also beware that the first response by many devices is to
528 * reply PENDING and stall for time. TVs are notorious for
529 * requiring longer than specified to complete their replies.
530 * Originally (in the DDX long ago), the delay was only ever 15ms
531 * with an additional delay of 30ms applied for TVs added later after
532 * many experiments. To accommodate both sets of delays, we do a
533 * sequence of slow checks if the device is falling behind and fails
534 * to reply within 5*15µs.
b5c616a7 535 */
d121a5d2
CW		 536 if (!intel_sdvo_read_byte(intel_sdvo,
537 SDVO_I2C_CMD_STATUS,
538 &status))
539 goto log_fail;
540
1ad87e72 541 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 542 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
b5c616a7
CW		 548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
d121a5d2
CW		 551 goto log_fail;
552 }
b5c616a7 553
79e53945 554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 556 else
342dc382 557 DRM_LOG_KMS("(??? %d)", status);
79e53945 558
b5c616a7
CW		 559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
79e53945 561
b5c616a7
CW		 562 /* Read the command response */
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
e957d772 568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 569 }
b5c616a7 570 DRM_LOG_KMS("\n");
b5c616a7 571 return true;
79e53945 572
b5c616a7 573log_fail:
d121a5d2 574 DRM_LOG_KMS("... failed\n");
b5c616a7 575 return false;
79e53945
JB		 576}
577
b358d0a6 578static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 579{
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586}
587
e957d772
CW		 588static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
79e53945 590{
d121a5d2 591 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
79e53945
JB		 595}
596
32aad86f 597static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 598{
d121a5d2
CW		 599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 603}
79e53945 604
32aad86f
CW		 605static bool
606intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607{
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
79e53945 610
32aad86f
CW		 611 return intel_sdvo_read_response(intel_sdvo, value, len);
612}
79e53945 613
32aad86f
CW		 614static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615{
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
79e53945
JB		 620}
621
622/**
623 * Return whether each input is trained.
624 *
625 * This function is making an assumption about the layout of the response,
626 * which should be checked against the docs.
627 */
ea5b213a 628static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 629{
630 struct intel_sdvo_get_trained_inputs_response response;
79e53945 631
1a3665c8 632 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
79e53945
JB		 635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640}
641
ea5b213a 642static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 643 u16 outputs)
644{
32aad86f
CW		 645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
79e53945
JB		 648}
649
4ac41f47
DV		 650static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652{
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656}
657
ea5b213a 658static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 659 int mode)
660{
32aad86f 661 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
32aad86f
CW		 678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 680}
681
ea5b213a 682static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int *clock_min,
684 int *clock_max)
685{
686 struct intel_sdvo_pixel_clock_range clocks;
79e53945 687
1a3665c8 688 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
79e53945
JB		 692 return false;
693
694 /* Convert the values from units of 10 kHz to kHz. */
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
79e53945
JB		 697 return true;
698}
699
ea5b213a 700static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 701 u16 outputs)
702{
32aad86f
CW		 703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
79e53945
JB		 706}
707
ea5b213a 708static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 709 struct intel_sdvo_dtd *dtd)
710{
32aad86f
CW		 711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 713}
714
045ac3b5
JB		 715static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
716 struct intel_sdvo_dtd *dtd)
717{
718 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
720}
721
ea5b213a 722static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 723 struct intel_sdvo_dtd *dtd)
724{
ea5b213a 725 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 726 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
727}
728
ea5b213a 729static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 730 struct intel_sdvo_dtd *dtd)
731{
ea5b213a 732 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 733 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
734}
735
045ac3b5
JB		 736static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
737 struct intel_sdvo_dtd *dtd)
738{
739 return intel_sdvo_get_timing(intel_sdvo,
740 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
741}
742
e2f0ba97 743static bool
ea5b213a 744intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 745 uint16_t clock,
746 uint16_t width,
747 uint16_t height)
748{
749 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 750
e642c6f1 751 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 752 args.clock = clock;
753 args.width = width;
754 args.height = height;
e642c6f1 755 args.interlace = 0;
12682a97 756
ea5b213a
CW		 757 if (intel_sdvo->is_lvds &&
758 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
759 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 760 args.scaled = 1;
761
32aad86f
CW		 762 return intel_sdvo_set_value(intel_sdvo,
763 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
764 &args, sizeof(args));
e2f0ba97
JB		 765}
766
ea5b213a 767static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 768 struct intel_sdvo_dtd *dtd)
769{
1a3665c8
CW		 770 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
771 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 772 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
773 &dtd->part1, sizeof(dtd->part1)) &&
774 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
775 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 776}
79e53945 777
ea5b213a 778static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 779{
32aad86f 780 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 781}
782
e2f0ba97 783static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 784 const struct drm_display_mode *mode)
79e53945 785{
e2f0ba97
JB		 786 uint16_t width, height;
787 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
788 uint16_t h_sync_offset, v_sync_offset;
6651819b 789 int mode_clock;
79e53945 790
1c4a814e
DV		 791 memset(dtd, 0, sizeof(*dtd));
792
c6ebd4c0
DV		 793 width = mode->hdisplay;
794 height = mode->vdisplay;
79e53945
JB		 795
796 /* do some mode translations */
c6ebd4c0
DV		 797 h_blank_len = mode->htotal - mode->hdisplay;
798 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 799
c6ebd4c0
DV		 800 v_blank_len = mode->vtotal - mode->vdisplay;
801 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 802
c6ebd4c0
DV		 803 h_sync_offset = mode->hsync_start - mode->hdisplay;
804 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 805
6651819b 806 mode_clock = mode->clock;
6651819b
DV		 807 mode_clock /= 10;
808 dtd->part1.clock = mode_clock;
809
e2f0ba97
JB		 810 dtd->part1.h_active = width & 0xff;
811 dtd->part1.h_blank = h_blank_len & 0xff;
812 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 813 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 814 dtd->part1.v_active = height & 0xff;
815 dtd->part1.v_blank = v_blank_len & 0xff;
816 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 817 ((v_blank_len >> 8) & 0xf);
818
171a9e96 819 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 820 dtd->part2.h_sync_width = h_sync_len & 0xff;
821 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 822 (v_sync_len & 0xf);
e2f0ba97 823 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 824 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
825 ((v_sync_len & 0x30) >> 4);
826
e2f0ba97 827 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 828 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
829 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 830 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 831 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 832 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 833 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 834
e2f0ba97 835 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 836}
837
1c4a814e 838static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 839 const struct intel_sdvo_dtd *dtd)
e2f0ba97 840{
1c4a814e
DV		 841 struct drm_display_mode mode = {};
842
843 mode.hdisplay = dtd->part1.h_active;
844 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
845 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
846 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
847 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
848 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
849 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
850 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
851
852 mode.vdisplay = dtd->part1.v_active;
853 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
854 mode.vsync_start = mode.vdisplay;
855 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
856 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
857 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
858 mode.vsync_end = mode.vsync_start +
e2f0ba97 859 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 860 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
861 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
862 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 863
1c4a814e 864 mode.clock = dtd->part1.clock * 10;
e2f0ba97 865
59d92bfa 866 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 867 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 868 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 869 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 870 else
1c4a814e 871 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 872 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 873 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 874 else
1c4a814e
DV		 875 mode.flags |= DRM_MODE_FLAG_NVSYNC;
876
877 drm_mode_set_crtcinfo(&mode, 0);
878
879 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 880}
881
e27d8538 882static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 883{
e27d8538 884 struct intel_sdvo_encode encode;
e2f0ba97 885
1a3665c8 886 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 887 return intel_sdvo_get_value(intel_sdvo,
888 SDVO_CMD_GET_SUPP_ENCODE,
889 &encode, sizeof(encode));
e2f0ba97
JB		 890}
891
ea5b213a 892static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 893 uint8_t mode)
e2f0ba97 894{
32aad86f 895 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 896}
897
ea5b213a 898static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 899 uint8_t mode)
900{
32aad86f 901 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 902}
903
904#if 0
ea5b213a 905static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 906{
907 int i, j;
908 uint8_t set_buf_index[2];
909 uint8_t av_split;
910 uint8_t buf_size;
911 uint8_t buf[48];
912 uint8_t *pos;
913
32aad86f 914 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 915
916 for (i = 0; i <= av_split; i++) {
917 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 918 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 919 set_buf_index, 2);
c751ce4f
EA		 920 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
921 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 922
923 pos = buf;
924 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 925 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 926 NULL, 0);
c751ce4f 927 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 928 pos += 8;
929 }
930 }
931}
932#endif
933
b6e0e543
DV		 934static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
935 unsigned if_index, uint8_t tx_rate,
936 uint8_t *data, unsigned length)
937{
938 uint8_t set_buf_index[2] = { if_index, 0 };
939 uint8_t hbuf_size, tmp[8];
940 int i;
941
942 if (!intel_sdvo_set_value(intel_sdvo,
943 SDVO_CMD_SET_HBUF_INDEX,
944 set_buf_index, 2))
945 return false;
946
947 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
948 &hbuf_size, 1))
949 return false;
950
951 /* Buffer size is 0 based, hooray! */
952 hbuf_size++;
953
954 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
955 if_index, length, hbuf_size);
956
957 for (i = 0; i < hbuf_size; i += 8) {
958 memset(tmp, 0, 8);
959 if (i < length)
960 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
961
962 if (!intel_sdvo_set_value(intel_sdvo,
963 SDVO_CMD_SET_HBUF_DATA,
964 tmp, 8))
965 return false;
966 }
967
968 return intel_sdvo_set_value(intel_sdvo,
969 SDVO_CMD_SET_HBUF_TXRATE,
970 &tx_rate, 1);
971}
972
abedc077
VS		 973static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
974 const struct drm_display_mode *adjusted_mode)
e2f0ba97 975{
15dcd350
DL		 976 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
977 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
979 union hdmi_infoframe frame;
980 int ret;
981 ssize_t len;
982
983 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
984 adjusted_mode);
985 if (ret < 0) {
986 DRM_ERROR("couldn't fill AVI infoframe\n");
987 return false;
988 }
3c17fe4b 989
abedc077 990 if (intel_sdvo->rgb_quant_range_selectable) {
50f3b016 991 if (intel_crtc->config.limited_color_range)
15dcd350
DL		 992 frame.avi.quantization_range =
993 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 994 else
15dcd350
DL		 995 frame.avi.quantization_range =
996 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 997 }
998
15dcd350
DL		 999 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1000 if (len < 0)
1001 return false;
81014b9d 1002
b6e0e543
DV		 1003 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1004 SDVO_HBUF_TX_VSYNC,
1005 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1006}
1007
32aad86f 1008static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 1009{
ce6feabd 1010 struct intel_sdvo_tv_format format;
40039750 1011 uint32_t format_map;
ce6feabd 1012
40039750 1013 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1014 memset(&format, 0, sizeof(format));
32aad86f 1015 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1016
32aad86f
CW		 1017 BUILD_BUG_ON(sizeof(format) != 6);
1018 return intel_sdvo_set_value(intel_sdvo,
1019 SDVO_CMD_SET_TV_FORMAT,
1020 &format, sizeof(format));
7026d4ac
ZW		 1021}
1022
32aad86f
CW		 1023static bool
1024intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1025 const struct drm_display_mode *mode)
e2f0ba97 1026{
32aad86f 1027 struct intel_sdvo_dtd output_dtd;
79e53945 1028
32aad86f
CW		 1029 if (!intel_sdvo_set_target_output(intel_sdvo,
1030 intel_sdvo->attached_output))
1031 return false;
e2f0ba97 1032
32aad86f
CW		 1033 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1034 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1035 return false;
e2f0ba97 1036
32aad86f
CW		 1037 return true;
1038}
1039
c9a29698
DV		 1040/* Asks the sdvo controller for the preferred input mode given the output mode.
1041 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1042static bool
c9a29698 1043intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1044 const struct drm_display_mode *mode,
c9a29698 1045 struct drm_display_mode *adjusted_mode)
32aad86f 1046{
c9a29698
DV		 1047 struct intel_sdvo_dtd input_dtd;
1048
32aad86f
CW		 1049 /* Reset the input timing to the screen. Assume always input 0. */
1050 if (!intel_sdvo_set_target_input(intel_sdvo))
1051 return false;
e2f0ba97 1052
32aad86f
CW		 1053 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1054 mode->clock / 10,
1055 mode->hdisplay,
1056 mode->vdisplay))
1057 return false;
e2f0ba97 1058
32aad86f 1059 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1060 &input_dtd))
32aad86f 1061 return false;
e2f0ba97 1062
c9a29698 1063 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1064 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1065
32aad86f
CW		 1066 return true;
1067}
12682a97 1068
70484559
DV		 1069static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1070{
3c52f4eb 1071 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1072 struct dpll *clock = &pipe_config->dpll;
1073
1074 /* SDVO TV has fixed PLL values depend on its clock range,
1075 this mirrors vbios setting. */
1076 if (dotclock >= 100000 && dotclock < 140500) {
1077 clock->p1 = 2;
1078 clock->p2 = 10;
1079 clock->n = 3;
1080 clock->m1 = 16;
1081 clock->m2 = 8;
1082 } else if (dotclock >= 140500 && dotclock <= 200000) {
1083 clock->p1 = 1;
1084 clock->p2 = 10;
1085 clock->n = 6;
1086 clock->m1 = 12;
1087 clock->m2 = 8;
1088 } else {
1089 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1090 }
1091
1092 pipe_config->clock_set = true;
1093}
1094
6cc5f341
DV		 1095static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1096 struct intel_crtc_config *pipe_config)
32aad86f 1097{
8aca63aa 1098 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
6cc5f341
DV		 1099 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1100 struct drm_display_mode *mode = &pipe_config->requested_mode;
12682a97 1101
5d2d38dd
DV		 1102 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1103 pipe_config->pipe_bpp = 8*3;
1104
5bfe2ac0
DV		 1105 if (HAS_PCH_SPLIT(encoder->base.dev))
1106 pipe_config->has_pch_encoder = true;
1107
32aad86f
CW		 1108 /* We need to construct preferred input timings based on our
1109 * output timings. To do that, we have to set the output
1110 * timings, even though this isn't really the right place in
1111 * the sequence to do it. Oh well.
1112 */
1113 if (intel_sdvo->is_tv) {
1114 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1115 return false;
12682a97 1116
c9a29698
DV		 1117 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1118 mode,
1119 adjusted_mode);
09ede541 1120 pipe_config->sdvo_tv_clock = true;
ea5b213a 1121 } else if (intel_sdvo->is_lvds) {
32aad86f 1122 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1123 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1124 return false;
12682a97 1125
c9a29698
DV		 1126 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1127 mode,
1128 adjusted_mode);
e2f0ba97 1129 }
32aad86f
CW		 1130
1131 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1132 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1133 */
6cc5f341
DV		 1134 pipe_config->pixel_multiplier =
1135 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1136
55bc60db
VS		 1137 if (intel_sdvo->color_range_auto) {
1138 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1139 /* FIXME: This bit is only valid when using TMDS encoding and 8
1140 * bit per color mode. */
55bc60db 1141 if (intel_sdvo->has_hdmi_monitor &&
18316c8c 1142 drm_match_cea_mode(adjusted_mode) > 1)
4f3a8bc7 1143 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1144 else
1145 intel_sdvo->color_range = 0;
1146 }
1147
3685a8f3 1148 if (intel_sdvo->color_range)
50f3b016 1149 pipe_config->limited_color_range = true;
3685a8f3 1150
70484559
DV		 1151 /* Clock computation needs to happen after pixel multiplier. */
1152 if (intel_sdvo->is_tv)
1153 i9xx_adjust_sdvo_tv_clock(pipe_config);
1154
e2f0ba97
JB		 1155 return true;
1156}
1157
6cc5f341 1158static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
e2f0ba97 1159{
6cc5f341 1160 struct drm_device *dev = intel_encoder->base.dev;
e2f0ba97 1161 struct drm_i915_private *dev_priv = dev->dev_private;
eeb47937 1162 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
6cc5f341 1163 struct drm_display_mode *adjusted_mode =
eeb47937
DV		 1164 &crtc->config.adjusted_mode;
1165 struct drm_display_mode *mode = &crtc->config.requested_mode;
8aca63aa 1166 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1167 u32 sdvox;
e2f0ba97 1168 struct intel_sdvo_in_out_map in_out;
6651819b 1169 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1170 int rate;
e2f0ba97
JB		 1171
1172 if (!mode)
1173 return;
1174
1175 /* First, set the input mapping for the first input to our controlled
1176 * output. This is only correct if we're a single-input device, in
1177 * which case the first input is the output from the appropriate SDVO
1178 * channel on the motherboard. In a two-input device, the first input
1179 * will be SDVOB and the second SDVOC.
1180 */
ea5b213a 1181 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1182 in_out.in1 = 0;
1183
c74696b9
PR		 1184 intel_sdvo_set_value(intel_sdvo,
1185 SDVO_CMD_SET_IN_OUT_MAP,
1186 &in_out, sizeof(in_out));
e2f0ba97 1187
6c9547ff
CW		 1188 /* Set the output timings to the screen */
1189 if (!intel_sdvo_set_target_output(intel_sdvo,
1190 intel_sdvo->attached_output))
1191 return;
e2f0ba97 1192
6651819b
DV		 1193 /* lvds has a special fixed output timing. */
1194 if (intel_sdvo->is_lvds)
1195 intel_sdvo_get_dtd_from_mode(&output_dtd,
1196 intel_sdvo->sdvo_lvds_fixed_mode);
1197 else
1198 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1199 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1200 DRM_INFO("Setting output timings on %s failed\n",
1201 SDVO_NAME(intel_sdvo));
79e53945
JB		 1202
1203 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1204 if (!intel_sdvo_set_target_input(intel_sdvo))
1205 return;
79e53945 1206
97aaf910
CW		 1207 if (intel_sdvo->has_hdmi_monitor) {
1208 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1209 intel_sdvo_set_colorimetry(intel_sdvo,
1210 SDVO_COLORIMETRY_RGB256);
abedc077 1211 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1212 } else
1213 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1214
6c9547ff
CW		 1215 if (intel_sdvo->is_tv &&
1216 !intel_sdvo_set_tv_format(intel_sdvo))
1217 return;
e2f0ba97 1218
6651819b 1219 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1220
e751823d
EE		 1221 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1222 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1223 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1224 DRM_INFO("Setting input timings on %s failed\n",
1225 SDVO_NAME(intel_sdvo));
79e53945 1226
eeb47937 1227 switch (crtc->config.pixel_multiplier) {
6c9547ff 1228 default:
ef1b460d 1229 WARN(1, "unknown pixel mutlipler specified\n");
32aad86f
CW		 1230 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1231 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1232 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1233 }
32aad86f
CW		 1234 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1235 return;
79e53945
JB		 1236
1237 /* Set the SDVO control regs. */
a6c45cf0 1238 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1239 /* The real mode polarity is set by the SDVO commands, using
1240 * struct intel_sdvo_dtd. */
1241 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1242 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1243 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1244 if (INTEL_INFO(dev)->gen < 5)
1245 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1246 } else {
6c9547ff 1247 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1248 switch (intel_sdvo->sdvo_reg) {
e2debe91 1249 case GEN3_SDVOB:
e2f0ba97
JB		 1250 sdvox &= SDVOB_PRESERVE_MASK;
1251 break;
e2debe91 1252 case GEN3_SDVOC:
e2f0ba97
JB		 1253 sdvox &= SDVOC_PRESERVE_MASK;
1254 break;
1255 }
1256 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1257 }
3573c410
PZ		 1258
1259 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
eeb47937 1260 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1261 else
eeb47937 1262 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1263
da79de97 1264 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1265 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1266
a6c45cf0 1267 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1268 /* done in crtc_mode_set as the dpll_md reg must be written early */
1269 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1270 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1271 } else {
eeb47937 1272 sdvox |= (crtc->config.pixel_multiplier - 1)
6cc5f341 1273 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1274 }
1275
6714afb1
CW		 1276 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1277 INTEL_INFO(dev)->gen < 5)
12682a97 1278 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1279 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1280}
1281
4ac41f47 1282static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1283{
4ac41f47
DV		 1284 struct intel_sdvo_connector *intel_sdvo_connector =
1285 to_intel_sdvo_connector(&connector->base);
1286 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1287 u16 active_outputs = 0;
4ac41f47
DV		 1288
1289 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1290
1291 if (active_outputs & intel_sdvo_connector->output_flag)
1292 return true;
1293 else
1294 return false;
1295}
1296
1297static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1298 enum pipe *pipe)
1299{
1300 struct drm_device *dev = encoder->base.dev;
79e53945 1301 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1302 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1303 u16 active_outputs = 0;
4ac41f47
DV		 1304 u32 tmp;
1305
1306 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1307 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1308
7a7d1fb7 1309 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1310 return false;
1311
1312 if (HAS_PCH_CPT(dev))
1313 *pipe = PORT_TO_PIPE_CPT(tmp);
1314 else
1315 *pipe = PORT_TO_PIPE(tmp);
1316
1317 return true;
1318}
1319
045ac3b5
JB		 1320static void intel_sdvo_get_config(struct intel_encoder *encoder,
1321 struct intel_crtc_config *pipe_config)
1322{
6c49f241
DV		 1323 struct drm_device *dev = encoder->base.dev;
1324 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1325 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1326 struct intel_sdvo_dtd dtd;
6c49f241 1327 int encoder_pixel_multiplier = 0;
18442d08 1328 int dotclock;
6c49f241
DV		 1329 u32 flags = 0, sdvox;
1330 u8 val;
045ac3b5
JB		 1331 bool ret;
1332
1333 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1334 if (!ret) {
bb760063
DV		 1335 /* Some sdvo encoders are not spec compliant and don't
1336 * implement the mandatory get_timings function. */
045ac3b5 1337 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1338 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1339 } else {
1340 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1341 flags |= DRM_MODE_FLAG_PHSYNC;
1342 else
1343 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1344
bb760063
DV		 1345 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1346 flags |= DRM_MODE_FLAG_PVSYNC;
1347 else
1348 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1349 }
1350
045ac3b5 1351 pipe_config->adjusted_mode.flags |= flags;
045ac3b5 1352
fdafa9e2
DV		 1353 /*
1354 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1355 * the sdvo port register, on all other platforms it is part of the dpll
1356 * state. Since the general pipe state readout happens before the
1357 * encoder->get_config we so already have a valid pixel multplier on all
1358 * other platfroms.
1359 */
6c49f241
DV		 1360 if (IS_I915G(dev) || IS_I915GM(dev)) {
1361 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1362 pipe_config->pixel_multiplier =
1363 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1364 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1365 }
045ac3b5 1366
18442d08
VS		 1367 dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier;
1368
1369 if (HAS_PCH_SPLIT(dev))
1370 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1371
241bfc38 1372 pipe_config->adjusted_mode.crtc_clock = dotclock;
18442d08 1373
6c49f241 1374 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1375 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1376 &val, 1)) {
1377 switch (val) {
1378 case SDVO_CLOCK_RATE_MULT_1X:
1379 encoder_pixel_multiplier = 1;
1380 break;
1381 case SDVO_CLOCK_RATE_MULT_2X:
1382 encoder_pixel_multiplier = 2;
1383 break;
1384 case SDVO_CLOCK_RATE_MULT_4X:
1385 encoder_pixel_multiplier = 4;
1386 break;
1387 }
6c49f241 1388 }
fdafa9e2 1389
6c49f241
DV		 1390 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1391 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1392 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1393}
1394
ce22c320
DV		 1395static void intel_disable_sdvo(struct intel_encoder *encoder)
1396{
1397 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
8aca63aa 1398 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320
DV		 1399 u32 temp;
1400
1401 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1402 if (0)
1403 intel_sdvo_set_encoder_power_state(intel_sdvo,
1404 DRM_MODE_DPMS_OFF);
1405
1406 temp = I915_READ(intel_sdvo->sdvo_reg);
1407 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1408 /* HW workaround for IBX, we need to move the port to
1409 * transcoder A before disabling it. */
1410 if (HAS_PCH_IBX(encoder->base.dev)) {
1411 struct drm_crtc *crtc = encoder->base.crtc;
1412 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1413
1414 if (temp & SDVO_PIPE_B_SELECT) {
1415 temp &= ~SDVO_PIPE_B_SELECT;
1416 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1417 POSTING_READ(intel_sdvo->sdvo_reg);
1418
1419 /* Again we need to write this twice. */
1420 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1421 POSTING_READ(intel_sdvo->sdvo_reg);
1422
1423 /* Transcoder selection bits only update
1424 * effectively on vblank. */
1425 if (crtc)
1426 intel_wait_for_vblank(encoder->base.dev, pipe);
1427 else
1428 msleep(50);
1429 }
1430 }
1431
ce22c320
DV		 1432 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1433 }
1434}
1435
1436static void intel_enable_sdvo(struct intel_encoder *encoder)
1437{
1438 struct drm_device *dev = encoder->base.dev;
1439 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1440 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1441 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1442 u32 temp;
ce22c320
DV		 1443 bool input1, input2;
1444 int i;
1445 u8 status;
1446
1447 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1448 if ((temp & SDVO_ENABLE) == 0) {
1449 /* HW workaround for IBX, we need to move the port
dc0fa718
PZ		 1450 * to transcoder A before disabling it, so restore it here. */
1451 if (HAS_PCH_IBX(dev))
1452 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
776ca7cf 1453
ce22c320 1454 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1455 }
ce22c320
DV		 1456 for (i = 0; i < 2; i++)
1457 intel_wait_for_vblank(dev, intel_crtc->pipe);
1458
1459 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1460 /* Warn if the device reported failure to sync.
1461 * A lot of SDVO devices fail to notify of sync, but it's
1462 * a given it the status is a success, we succeeded.
1463 */
1464 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1465 DRM_DEBUG_KMS("First %s output reported failure to "
1466 "sync\n", SDVO_NAME(intel_sdvo));
1467 }
1468
1469 if (0)
1470 intel_sdvo_set_encoder_power_state(intel_sdvo,
1471 DRM_MODE_DPMS_ON);
1472 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1473}
1474
6b1c087b 1475/* Special dpms function to support cloning between dvo/sdvo/crt. */
b2cabb0e 1476static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1477{
b2cabb0e
DV		 1478 struct drm_crtc *crtc;
1479 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1480
1481 /* dvo supports only 2 dpms states. */
1482 if (mode != DRM_MODE_DPMS_ON)
1483 mode = DRM_MODE_DPMS_OFF;
1484
1485 if (mode == connector->dpms)
1486 return;
1487
1488 connector->dpms = mode;
1489
1490 /* Only need to change hw state when actually enabled */
1491 crtc = intel_sdvo->base.base.crtc;
1492 if (!crtc) {
1493 intel_sdvo->base.connectors_active = false;
1494 return;
1495 }
79e53945 1496
6b1c087b
JN		 1497 /* We set active outputs manually below in case pipe dpms doesn't change
1498 * due to cloning. */
79e53945 1499 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1500 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1501 if (0)
ea5b213a 1502 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1503
b2cabb0e
DV		 1504 intel_sdvo->base.connectors_active = false;
1505
1506 intel_crtc_update_dpms(crtc);
79e53945 1507 } else {
b2cabb0e
DV		 1508 intel_sdvo->base.connectors_active = true;
1509
1510 intel_crtc_update_dpms(crtc);
79e53945
JB		 1511
1512 if (0)
ea5b213a
CW		 1513 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1514 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1515 }
0a91ca29 1516
b980514c 1517 intel_modeset_check_state(connector->dev);
79e53945
JB		 1518}
1519
79e53945
JB		 1520static int intel_sdvo_mode_valid(struct drm_connector *connector,
1521 struct drm_display_mode *mode)
1522{
df0e9248 1523 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1524
1525 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1526 return MODE_NO_DBLESCAN;
1527
ea5b213a 1528 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1529 return MODE_CLOCK_LOW;
1530
ea5b213a 1531 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1532 return MODE_CLOCK_HIGH;
1533
8545423a 1534 if (intel_sdvo->is_lvds) {
ea5b213a 1535 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1536 return MODE_PANEL;
1537
ea5b213a 1538 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1539 return MODE_PANEL;
1540 }
1541
79e53945
JB		 1542 return MODE_OK;
1543}
1544
ea5b213a 1545static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1546{
1a3665c8 1547 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1548 if (!intel_sdvo_get_value(intel_sdvo,
1549 SDVO_CMD_GET_DEVICE_CAPS,
1550 caps, sizeof(*caps)))
1551 return false;
1552
1553 DRM_DEBUG_KMS("SDVO capabilities:\n"
1554 " vendor_id: %d\n"
1555 " device_id: %d\n"
1556 " device_rev_id: %d\n"
1557 " sdvo_version_major: %d\n"
1558 " sdvo_version_minor: %d\n"
1559 " sdvo_inputs_mask: %d\n"
1560 " smooth_scaling: %d\n"
1561 " sharp_scaling: %d\n"
1562 " up_scaling: %d\n"
1563 " down_scaling: %d\n"
1564 " stall_support: %d\n"
1565 " output_flags: %d\n",
1566 caps->vendor_id,
1567 caps->device_id,
1568 caps->device_rev_id,
1569 caps->sdvo_version_major,
1570 caps->sdvo_version_minor,
1571 caps->sdvo_inputs_mask,
1572 caps->smooth_scaling,
1573 caps->sharp_scaling,
1574 caps->up_scaling,
1575 caps->down_scaling,
1576 caps->stall_support,
1577 caps->output_flags);
1578
1579 return true;
79e53945
JB		 1580}
1581
5fa7ac9c 1582static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1583{
768b107e 1584 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1585 uint16_t hotplug;
79e53945 1586
768b107e
DV		 1587 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1588 * on the line. */
1589 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1590 return 0;
768b107e 1591
5fa7ac9c
JN		 1592 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1593 &hotplug, sizeof(hotplug)))
1594 return 0;
768b107e 1595
5fa7ac9c 1596 return hotplug;
79e53945
JB		 1597}
1598
cc68c81a 1599static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1600{
8aca63aa 1601 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1602
5fa7ac9c
JN		 1603 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1604 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1605}
1606
fb7a46f3 1607static bool
ea5b213a 1608intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1609{
bc65212c 1610 /* Is there more than one type of output? */
2294488d 1611 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1612}
1613
f899fc64 1614static struct edid *
e957d772 1615intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1616{
e957d772
CW		 1617 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1618 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1619}
1620
ff482d83
CW		 1621/* Mac mini hack -- use the same DDC as the analog connector */
1622static struct edid *
1623intel_sdvo_get_analog_edid(struct drm_connector *connector)
1624{
f899fc64 1625 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1626
0c1dab89 1627 return drm_get_edid(connector,
3bd7d909 1628 intel_gmbus_get_adapter(dev_priv,
41aa3448 1629 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1630}
1631
c43b5634 1632static enum drm_connector_status
8bf38485 1633intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1634{
df0e9248 1635 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1636 enum drm_connector_status status;
1637 struct edid *edid;
9dff6af8 1638
e957d772 1639 edid = intel_sdvo_get_edid(connector);
57cdaf90 1640
ea5b213a 1641 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1642 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1643
7c3f0a27
ZY		 1644 /*
1645 * Don't use the 1 as the argument of DDC bus switch to get
1646 * the EDID. It is used for SDVO SPD ROM.
1647 */
9d1a903d 1648 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1649 intel_sdvo->ddc_bus = ddc;
1650 edid = intel_sdvo_get_edid(connector);
1651 if (edid)
7c3f0a27 1652 break;
7c3f0a27 1653 }
e957d772
CW		 1654 /*
1655 * If we found the EDID on the other bus,
1656 * assume that is the correct DDC bus.
1657 */
1658 if (edid == NULL)
1659 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1660 }
9d1a903d
CW		 1661
1662 /*
1663 * When there is no edid and no monitor is connected with VGA
1664 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1665 */
ff482d83
CW		 1666 if (edid == NULL)
1667 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1668
2f551c84 1669 status = connector_status_unknown;
9dff6af8 1670 if (edid != NULL) {
149c36a3 1671 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1672 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1673 status = connector_status_connected;
da79de97
CW		 1674 if (intel_sdvo->is_hdmi) {
1675 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1676 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1677 intel_sdvo->rgb_quant_range_selectable =
1678 drm_rgb_quant_range_selectable(edid);
da79de97 1679 }
13946743
CW		 1680 } else
1681 status = connector_status_disconnected;
9d1a903d
CW		 1682 kfree(edid);
1683 }
7f36e7ed
CW		 1684
1685 if (status == connector_status_connected) {
1686 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1687 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1688 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1689 }
1690
2b8d33f7 1691 return status;
9dff6af8
ML		 1692}
1693
52220085
CW		 1694static bool
1695intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1696 struct edid *edid)
1697{
1698 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1699 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1700
1701 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1702 connector_is_digital, monitor_is_digital);
1703 return connector_is_digital == monitor_is_digital;
1704}
1705
7b334fcb 1706static enum drm_connector_status
930a9e28 1707intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1708{
fb7a46f3 1709 uint16_t response;
df0e9248 1710 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1711 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1712 enum drm_connector_status ret;
79e53945 1713
164c8598
CW		 1714 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1715 connector->base.id, drm_get_connector_name(connector));
1716
fc37381c
CW		 1717 if (!intel_sdvo_get_value(intel_sdvo,
1718 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1719 &response, 2))
32aad86f 1720 return connector_status_unknown;
79e53945 1721
e957d772
CW		 1722 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1723 response & 0xff, response >> 8,
1724 intel_sdvo_connector->output_flag);
e2f0ba97 1725
fb7a46f3 1726 if (response == 0)
79e53945 1727 return connector_status_disconnected;
fb7a46f3 1728
ea5b213a 1729 intel_sdvo->attached_output = response;
14571b4c 1730
97aaf910
CW		 1731 intel_sdvo->has_hdmi_monitor = false;
1732 intel_sdvo->has_hdmi_audio = false;
abedc077 1733 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1734
615fb93f 1735 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1736 ret = connector_status_disconnected;
13946743 1737 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1738 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1739 else {
1740 struct edid *edid;
1741
1742 /* if we have an edid check it matches the connection */
1743 edid = intel_sdvo_get_edid(connector);
1744 if (edid == NULL)
1745 edid = intel_sdvo_get_analog_edid(connector);
1746 if (edid != NULL) {
52220085
CW		 1747 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1748 edid))
13946743 1749 ret = connector_status_connected;
52220085
CW		 1750 else
1751 ret = connector_status_disconnected;
1752
13946743
CW		 1753 kfree(edid);
1754 } else
1755 ret = connector_status_connected;
1756 }
14571b4c
ZW		 1757
1758 /* May update encoder flag for like clock for SDVO TV, etc.*/
1759 if (ret == connector_status_connected) {
ea5b213a
CW		 1760 intel_sdvo->is_tv = false;
1761 intel_sdvo->is_lvds = false;
14571b4c 1762
09ede541 1763 if (response & SDVO_TV_MASK)
ea5b213a 1764 intel_sdvo->is_tv = true;
14571b4c 1765 if (response & SDVO_LVDS_MASK)
8545423a 1766 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1767 }
14571b4c
ZW		 1768
1769 return ret;
79e53945
JB		 1770}
1771
e2f0ba97 1772static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1773{
ff482d83 1774 struct edid *edid;
79e53945 1775
46a3f4a3
CW		 1776 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1777 connector->base.id, drm_get_connector_name(connector));
1778
79e53945 1779 /* set the bus switch and get the modes */
e957d772 1780 edid = intel_sdvo_get_edid(connector);
79e53945 1781
57cdaf90
KP		 1782 /*
1783 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1784 * link between analog and digital outputs. So, if the regular SDVO
1785 * DDC fails, check to see if the analog output is disconnected, in
1786 * which case we'll look there for the digital DDC data.
e2f0ba97 1787 */
f899fc64
CW		 1788 if (edid == NULL)
1789 edid = intel_sdvo_get_analog_edid(connector);
1790
ff482d83 1791 if (edid != NULL) {
52220085
CW		 1792 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1793 edid)) {
0c1dab89
CW		 1794 drm_mode_connector_update_edid_property(connector, edid);
1795 drm_add_edid_modes(connector, edid);
1796 }
13946743 1797
ff482d83 1798 kfree(edid);
e2f0ba97 1799 }
e2f0ba97
JB		 1800}
1801
1802/*
1803 * Set of SDVO TV modes.
1804 * Note! This is in reply order (see loop in get_tv_modes).
1805 * XXX: all 60Hz refresh?
1806 */
b1f559ec 1807static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1808 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1809 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1810 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1811 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1812 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1814 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1815 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1817 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1818 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1820 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1821 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1823 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1824 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1826 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1827 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1829 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1830 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1832 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1833 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1835 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1836 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1838 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1839 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1841 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1842 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1844 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1845 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1847 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1848 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1850 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1851 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1853 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1854 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1856 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1857 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1859 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1860 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1862 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1863 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1865};
1866
1867static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1868{
df0e9248 1869 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1870 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1871 uint32_t reply = 0, format_map = 0;
1872 int i;
e2f0ba97 1873
46a3f4a3
CW		 1874 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1875 connector->base.id, drm_get_connector_name(connector));
1876
e2f0ba97
JB		 1877 /* Read the list of supported input resolutions for the selected TV
1878 * format.
1879 */
40039750 1880 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1881 memcpy(&tv_res, &format_map,
32aad86f 1882 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1883
32aad86f
CW		 1884 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1885 return;
ce6feabd 1886
32aad86f 1887 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1888 if (!intel_sdvo_write_cmd(intel_sdvo,
1889 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1890 &tv_res, sizeof(tv_res)))
1891 return;
1892 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1893 return;
1894
1895 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1896 if (reply & (1 << i)) {
1897 struct drm_display_mode *nmode;
1898 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1899 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1900 if (nmode)
1901 drm_mode_probed_add(connector, nmode);
1902 }
e2f0ba97
JB		 1903}
1904
7086c87f
ML		 1905static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1906{
df0e9248 1907 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1908 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1909 struct drm_display_mode *newmode;
7086c87f 1910
46a3f4a3
CW		 1911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1912 connector->base.id, drm_get_connector_name(connector));
1913
7086c87f 1914 /*
c3456fb3 1915 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 1916 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 1917 */
41aa3448 1918 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1919 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1920 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1921 if (newmode != NULL) {
1922 /* Guarantee the mode is preferred */
1923 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1924 DRM_MODE_TYPE_DRIVER);
1925 drm_mode_probed_add(connector, newmode);
1926 }
1927 }
12682a97 1928
4300a0f8
DA		 1929 /*
1930 * Attempt to get the mode list from DDC.
1931 * Assume that the preferred modes are
1932 * arranged in priority order.
1933 */
1934 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1935
12682a97 1936 list_for_each_entry(newmode, &connector->probed_modes, head) {
1937 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1938 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1939 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1940
8545423a 1941 intel_sdvo->is_lvds = true;
12682a97 1942 break;
1943 }
1944 }
7086c87f
ML		 1945}
1946
e2f0ba97
JB		 1947static int intel_sdvo_get_modes(struct drm_connector *connector)
1948{
615fb93f 1949 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1950
615fb93f 1951 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1952 intel_sdvo_get_tv_modes(connector);
615fb93f 1953 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1954 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1955 else
1956 intel_sdvo_get_ddc_modes(connector);
1957
32aad86f 1958 return !list_empty(&connector->probed_modes);
79e53945
JB		 1959}
1960
fcc8d672
CW		 1961static void
1962intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1963{
615fb93f 1964 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1965 struct drm_device *dev = connector->dev;
1966
c5521706
CW		 1967 if (intel_sdvo_connector->left)
1968 drm_property_destroy(dev, intel_sdvo_connector->left);
1969 if (intel_sdvo_connector->right)
1970 drm_property_destroy(dev, intel_sdvo_connector->right);
1971 if (intel_sdvo_connector->top)
1972 drm_property_destroy(dev, intel_sdvo_connector->top);
1973 if (intel_sdvo_connector->bottom)
1974 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1975 if (intel_sdvo_connector->hpos)
1976 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1977 if (intel_sdvo_connector->vpos)
1978 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1979 if (intel_sdvo_connector->saturation)
1980 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1981 if (intel_sdvo_connector->contrast)
1982 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1983 if (intel_sdvo_connector->hue)
1984 drm_property_destroy(dev, intel_sdvo_connector->hue);
1985 if (intel_sdvo_connector->sharpness)
1986 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1987 if (intel_sdvo_connector->flicker_filter)
1988 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1989 if (intel_sdvo_connector->flicker_filter_2d)
1990 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1991 if (intel_sdvo_connector->flicker_filter_adaptive)
1992 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1993 if (intel_sdvo_connector->tv_luma_filter)
1994 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1995 if (intel_sdvo_connector->tv_chroma_filter)
1996 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1997 if (intel_sdvo_connector->dot_crawl)
1998 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1999 if (intel_sdvo_connector->brightness)
2000 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 2001}
2002
79e53945
JB		 2003static void intel_sdvo_destroy(struct drm_connector *connector)
2004{
615fb93f 2005 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 2006
c5521706 2007 if (intel_sdvo_connector->tv_format)
ce6feabd 2008 drm_property_destroy(connector->dev,
c5521706 2009 intel_sdvo_connector->tv_format);
b9219c5e 2010
d2a82a6f 2011 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 2012 drm_sysfs_connector_remove(connector);
2013 drm_connector_cleanup(connector);
4b745b1e 2014 kfree(intel_sdvo_connector);
79e53945
JB		 2015}
2016
1aad7ac0
CW		 2017static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
2018{
2019 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2020 struct edid *edid;
2021 bool has_audio = false;
2022
2023 if (!intel_sdvo->is_hdmi)
2024 return false;
2025
2026 edid = intel_sdvo_get_edid(connector);
2027 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2028 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 2029 kfree(edid);
1aad7ac0
CW		 2030
2031 return has_audio;
2032}
2033
ce6feabd
ZY		 2034static int
2035intel_sdvo_set_property(struct drm_connector *connector,
2036 struct drm_property *property,
2037 uint64_t val)
2038{
df0e9248 2039 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 2040 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 2041 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 2042 uint16_t temp_value;
32aad86f
CW		 2043 uint8_t cmd;
2044 int ret;
ce6feabd 2045
662595df 2046 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 2047 if (ret)
2048 return ret;
ce6feabd 2049
3f43c48d 2050 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2051 int i = val;
2052 bool has_audio;
2053
2054 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 2055 return 0;
2056
1aad7ac0 2057 intel_sdvo_connector->force_audio = i;
7f36e7ed 2058
c3e5f67b 2059 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2060 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2061 else
c3e5f67b 2062 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 2063
1aad7ac0 2064 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 2065 return 0;
7f36e7ed 2066
1aad7ac0 2067 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 2068 goto done;
2069 }
2070
e953fd7b 2071 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2072 bool old_auto = intel_sdvo->color_range_auto;
2073 uint32_t old_range = intel_sdvo->color_range;
2074
55bc60db
VS		 2075 switch (val) {
2076 case INTEL_BROADCAST_RGB_AUTO:
2077 intel_sdvo->color_range_auto = true;
2078 break;
2079 case INTEL_BROADCAST_RGB_FULL:
2080 intel_sdvo->color_range_auto = false;
2081 intel_sdvo->color_range = 0;
2082 break;
2083 case INTEL_BROADCAST_RGB_LIMITED:
2084 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 2085 /* FIXME: this bit is only valid when using TMDS
2086 * encoding and 8 bit per color mode. */
2087 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 2088 break;
2089 default:
2090 return -EINVAL;
2091 }
ae4edb80
DV		 2092
2093 if (old_auto == intel_sdvo->color_range_auto &&
2094 old_range == intel_sdvo->color_range)
2095 return 0;
2096
7f36e7ed
CW		 2097 goto done;
2098 }
2099
c5521706
CW		 2100#define CHECK_PROPERTY(name, NAME) \
2101 if (intel_sdvo_connector->name == property) { \
2102 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2103 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2104 cmd = SDVO_CMD_SET_##NAME; \
2105 intel_sdvo_connector->cur_##name = temp_value; \
2106 goto set_value; \
2107 }
2108
2109 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 2110 if (val >= TV_FORMAT_NUM)
2111 return -EINVAL;
2112
40039750 2113 if (intel_sdvo->tv_format_index ==
615fb93f 2114 intel_sdvo_connector->tv_format_supported[val])
32aad86f 2115 return 0;
ce6feabd 2116
40039750 2117 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 2118 goto done;
32aad86f 2119 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2120 temp_value = val;
c5521706 2121 if (intel_sdvo_connector->left == property) {
662595df 2122 drm_object_property_set_value(&connector->base,
c5521706 2123 intel_sdvo_connector->right, val);
615fb93f 2124 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2125 return 0;
b9219c5e 2126
615fb93f
CW		 2127 intel_sdvo_connector->left_margin = temp_value;
2128 intel_sdvo_connector->right_margin = temp_value;
2129 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2130 intel_sdvo_connector->left_margin;
b9219c5e 2131 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2132 goto set_value;
2133 } else if (intel_sdvo_connector->right == property) {
662595df 2134 drm_object_property_set_value(&connector->base,
c5521706 2135 intel_sdvo_connector->left, val);
615fb93f 2136 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2137 return 0;
b9219c5e 2138
615fb93f
CW		 2139 intel_sdvo_connector->left_margin = temp_value;
2140 intel_sdvo_connector->right_margin = temp_value;
2141 temp_value = intel_sdvo_connector->max_hscan -
2142 intel_sdvo_connector->left_margin;
b9219c5e 2143 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2144 goto set_value;
2145 } else if (intel_sdvo_connector->top == property) {
662595df 2146 drm_object_property_set_value(&connector->base,
c5521706 2147 intel_sdvo_connector->bottom, val);
615fb93f 2148 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2149 return 0;
b9219c5e 2150
615fb93f
CW		 2151 intel_sdvo_connector->top_margin = temp_value;
2152 intel_sdvo_connector->bottom_margin = temp_value;
2153 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2154 intel_sdvo_connector->top_margin;
b9219c5e 2155 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2156 goto set_value;
2157 } else if (intel_sdvo_connector->bottom == property) {
662595df 2158 drm_object_property_set_value(&connector->base,
c5521706 2159 intel_sdvo_connector->top, val);
615fb93f 2160 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2161 return 0;
2162
615fb93f
CW		 2163 intel_sdvo_connector->top_margin = temp_value;
2164 intel_sdvo_connector->bottom_margin = temp_value;
2165 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2166 intel_sdvo_connector->top_margin;
b9219c5e 2167 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2168 goto set_value;
2169 }
2170 CHECK_PROPERTY(hpos, HPOS)
2171 CHECK_PROPERTY(vpos, VPOS)
2172 CHECK_PROPERTY(saturation, SATURATION)
2173 CHECK_PROPERTY(contrast, CONTRAST)
2174 CHECK_PROPERTY(hue, HUE)
2175 CHECK_PROPERTY(brightness, BRIGHTNESS)
2176 CHECK_PROPERTY(sharpness, SHARPNESS)
2177 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2178 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2179 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2180 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2181 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2182 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2183 }
b9219c5e 2184
c5521706 2185 return -EINVAL; /* unknown property */
b9219c5e 2186
c5521706
CW		 2187set_value:
2188 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2189 return -EIO;
b9219c5e 2190
b9219c5e 2191
c5521706 2192done:
c0c36b94
CW		 2193 if (intel_sdvo->base.base.crtc)
2194 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2195
32aad86f 2196 return 0;
c5521706 2197#undef CHECK_PROPERTY
ce6feabd
ZY		 2198}
2199
79e53945 2200static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2201 .dpms = intel_sdvo_dpms,
79e53945
JB		 2202 .detect = intel_sdvo_detect,
2203 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2204 .set_property = intel_sdvo_set_property,
79e53945
JB		 2205 .destroy = intel_sdvo_destroy,
2206};
2207
2208static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2209 .get_modes = intel_sdvo_get_modes,
2210 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2211 .best_encoder = intel_best_encoder,
79e53945
JB		 2212};
2213
b358d0a6 2214static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2215{
8aca63aa 2216 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2217
ea5b213a 2218 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2219 drm_mode_destroy(encoder->dev,
ea5b213a 2220 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2221
e957d772 2222 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2223 intel_encoder_destroy(encoder);
79e53945
JB		 2224}
2225
2226static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2227 .destroy = intel_sdvo_enc_destroy,
2228};
2229
b66d8424
CW		 2230static void
2231intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2232{
2233 uint16_t mask = 0;
2234 unsigned int num_bits;
2235
2236 /* Make a mask of outputs less than or equal to our own priority in the
2237 * list.
2238 */
2239 switch (sdvo->controlled_output) {
2240 case SDVO_OUTPUT_LVDS1:
2241 mask |= SDVO_OUTPUT_LVDS1;
2242 case SDVO_OUTPUT_LVDS0:
2243 mask |= SDVO_OUTPUT_LVDS0;
2244 case SDVO_OUTPUT_TMDS1:
2245 mask |= SDVO_OUTPUT_TMDS1;
2246 case SDVO_OUTPUT_TMDS0:
2247 mask |= SDVO_OUTPUT_TMDS0;
2248 case SDVO_OUTPUT_RGB1:
2249 mask |= SDVO_OUTPUT_RGB1;
2250 case SDVO_OUTPUT_RGB0:
2251 mask |= SDVO_OUTPUT_RGB0;
2252 break;
2253 }
2254
2255 /* Count bits to find what number we are in the priority list. */
2256 mask &= sdvo->caps.output_flags;
2257 num_bits = hweight16(mask);
2258 /* If more than 3 outputs, default to DDC bus 3 for now. */
2259 if (num_bits > 3)
2260 num_bits = 3;
2261
2262 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2263 sdvo->ddc_bus = 1 << num_bits;
2264}
79e53945 2265
e2f0ba97
JB		 2266/**
2267 * Choose the appropriate DDC bus for control bus switch command for this
2268 * SDVO output based on the controlled output.
2269 *
2270 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2271 * outputs, then LVDS outputs.
2272 */
2273static void
b1083333 2274intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2275 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2276{
b1083333 2277 struct sdvo_device_mapping *mapping;
e2f0ba97 2278
eef4eacb 2279 if (sdvo->is_sdvob)
b1083333
AJ		 2280 mapping = &(dev_priv->sdvo_mappings[0]);
2281 else
2282 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2283
b66d8424
CW		 2284 if (mapping->initialized)
2285 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2286 else
2287 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2288}
2289
e957d772
CW		 2290static void
2291intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2292 struct intel_sdvo *sdvo, u32 reg)
2293{
2294 struct sdvo_device_mapping *mapping;
46eb3036 2295 u8 pin;
e957d772 2296
eef4eacb 2297 if (sdvo->is_sdvob)
e957d772
CW		 2298 mapping = &dev_priv->sdvo_mappings[0];
2299 else
2300 mapping = &dev_priv->sdvo_mappings[1];
2301
6cb1612a 2302 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2303 pin = mapping->i2c_pin;
6cb1612a
JN		 2304 else
2305 pin = GMBUS_PORT_DPB;
e957d772 2306
6cb1612a
JN		 2307 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2308
2309 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2310 * our code totally fails once we start using gmbus. Hence fall back to
2311 * bit banging for now. */
2312 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2313}
2314
fbfcc4f3
JN		 2315/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2316static void
2317intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2318{
2319 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2320}
2321
e2f0ba97 2322static bool
e27d8538 2323intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2324{
97aaf910 2325 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2326}
2327
714605e4 2328static u8
eef4eacb 2329intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2330{
2331 struct drm_i915_private *dev_priv = dev->dev_private;
2332 struct sdvo_device_mapping *my_mapping, *other_mapping;
2333
eef4eacb 2334 if (sdvo->is_sdvob) {
714605e4 2335 my_mapping = &dev_priv->sdvo_mappings[0];
2336 other_mapping = &dev_priv->sdvo_mappings[1];
2337 } else {
2338 my_mapping = &dev_priv->sdvo_mappings[1];
2339 other_mapping = &dev_priv->sdvo_mappings[0];
2340 }
2341
2342 /* If the BIOS described our SDVO device, take advantage of it. */
2343 if (my_mapping->slave_addr)
2344 return my_mapping->slave_addr;
2345
2346 /* If the BIOS only described a different SDVO device, use the
2347 * address that it isn't using.
2348 */
2349 if (other_mapping->slave_addr) {
2350 if (other_mapping->slave_addr == 0x70)
2351 return 0x72;
2352 else
2353 return 0x70;
2354 }
2355
2356 /* No SDVO device info is found for another DVO port,
2357 * so use mapping assumption we had before BIOS parsing.
2358 */
eef4eacb 2359 if (sdvo->is_sdvob)
714605e4 2360 return 0x70;
2361 else
2362 return 0x72;
2363}
2364
14571b4c 2365static void
df0e9248
CW		 2366intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2367 struct intel_sdvo *encoder)
14571b4c 2368{
df0e9248
CW		 2369 drm_connector_init(encoder->base.base.dev,
2370 &connector->base.base,
2371 &intel_sdvo_connector_funcs,
2372 connector->base.base.connector_type);
6070a4a9 2373
df0e9248
CW		 2374 drm_connector_helper_add(&connector->base.base,
2375 &intel_sdvo_connector_helper_funcs);
14571b4c 2376
8f4839e2 2377 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2378 connector->base.base.doublescan_allowed = 0;
2379 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2380 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2381
df0e9248
CW		 2382 intel_connector_attach_encoder(&connector->base, &encoder->base);
2383 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2384}
6070a4a9 2385
7f36e7ed 2386static void
55bc60db
VS		 2387intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2388 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2389{
2390 struct drm_device *dev = connector->base.base.dev;
2391
3f43c48d 2392 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2393 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2394 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2395 intel_sdvo->color_range_auto = true;
2396 }
7f36e7ed
CW		 2397}
2398
fb7a46f3 2399static bool
ea5b213a 2400intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2401{
4ef69c7a 2402 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2403 struct drm_connector *connector;
cc68c81a 2404 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2405 struct intel_connector *intel_connector;
615fb93f 2406 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2407
46a3f4a3
CW		 2408 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2409
b14c5679 2410 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f 2411 if (!intel_sdvo_connector)
14571b4c
ZW		 2412 return false;
2413
14571b4c 2414 if (device == 0) {
ea5b213a 2415 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2416 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2417 } else if (device == 1) {
ea5b213a 2418 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2419 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2420 }
2421
615fb93f 2422 intel_connector = &intel_sdvo_connector->base;
14571b4c 2423 connector = &intel_connector->base;
5fa7ac9c
JN		 2424 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2425 intel_sdvo_connector->output_flag) {
5fa7ac9c 2426 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2427 /* Some SDVO devices have one-shot hotplug interrupts.
2428 * Ensure that they get re-enabled when an interrupt happens.
2429 */
2430 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2431 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2432 } else {
821450c6 2433 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2434 }
14571b4c
ZW		 2435 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2436 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2437
e27d8538 2438 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2439 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2440 intel_sdvo->is_hdmi = true;
14571b4c 2441 }
14571b4c 2442
df0e9248 2443 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221 2444 if (intel_sdvo->is_hdmi)
55bc60db 2445 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2446
2447 return true;
2448}
2449
2450static bool
ea5b213a 2451intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2452{
4ef69c7a
CW		 2453 struct drm_encoder *encoder = &intel_sdvo->base.base;
2454 struct drm_connector *connector;
2455 struct intel_connector *intel_connector;
2456 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2457
46a3f4a3
CW		 2458 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2459
b14c5679 2460 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f
CW		 2461 if (!intel_sdvo_connector)
2462 return false;
14571b4c 2463
615fb93f 2464 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2465 connector = &intel_connector->base;
2466 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2467 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2468
4ef69c7a
CW		 2469 intel_sdvo->controlled_output |= type;
2470 intel_sdvo_connector->output_flag = type;
14571b4c 2471
4ef69c7a 2472 intel_sdvo->is_tv = true;
14571b4c 2473
df0e9248 2474 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2475
4ef69c7a 2476 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2477 goto err;
14571b4c 2478
4ef69c7a 2479 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2480 goto err;
14571b4c 2481
4ef69c7a 2482 return true;
32aad86f
CW		 2483
2484err:
123d5c01 2485 intel_sdvo_destroy(connector);
32aad86f 2486 return false;
14571b4c
ZW		 2487}
2488
2489static bool
ea5b213a 2490intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2491{
4ef69c7a
CW		 2492 struct drm_encoder *encoder = &intel_sdvo->base.base;
2493 struct drm_connector *connector;
2494 struct intel_connector *intel_connector;
2495 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2496
46a3f4a3
CW		 2497 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2498
b14c5679 2499 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f
CW		 2500 if (!intel_sdvo_connector)
2501 return false;
14571b4c 2502
615fb93f 2503 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2504 connector = &intel_connector->base;
821450c6 2505 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2506 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2507 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2508
2509 if (device == 0) {
2510 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2511 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2512 } else if (device == 1) {
2513 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2514 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2515 }
2516
df0e9248
CW		 2517 intel_sdvo_connector_init(intel_sdvo_connector,
2518 intel_sdvo);
4ef69c7a 2519 return true;
14571b4c
ZW		 2520}
2521
2522static bool
ea5b213a 2523intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2524{
4ef69c7a
CW		 2525 struct drm_encoder *encoder = &intel_sdvo->base.base;
2526 struct drm_connector *connector;
2527 struct intel_connector *intel_connector;
2528 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2529
46a3f4a3
CW		 2530 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2531
b14c5679 2532 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f
CW		 2533 if (!intel_sdvo_connector)
2534 return false;
14571b4c 2535
615fb93f
CW		 2536 intel_connector = &intel_sdvo_connector->base;
2537 connector = &intel_connector->base;
4ef69c7a
CW		 2538 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2539 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2540
2541 if (device == 0) {
2542 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2543 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2544 } else if (device == 1) {
2545 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2546 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2547 }
2548
df0e9248 2549 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2550 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2551 goto err;
2552
2553 return true;
2554
2555err:
123d5c01 2556 intel_sdvo_destroy(connector);
32aad86f 2557 return false;
14571b4c
ZW		 2558}
2559
2560static bool
ea5b213a 2561intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2562{
ea5b213a 2563 intel_sdvo->is_tv = false;
ea5b213a 2564 intel_sdvo->is_lvds = false;
fb7a46f3 2565
14571b4c 2566 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2567
14571b4c 2568 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2569 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2570 return false;
2571
2572 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2573 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2574 return false;
2575
2576 /* TV has no XXX1 function block */
a1f4b7ff 2577 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2578 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2579 return false;
2580
2581 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2582 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2583 return false;
fb7a46f3 2584
a0b1c7a5
CW		 2585 if (flags & SDVO_OUTPUT_YPRPB0)
2586 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2587 return false;
2588
14571b4c 2589 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2590 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2591 return false;
2592
2593 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2594 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2595 return false;
2596
2597 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2598 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2599 return false;
2600
2601 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2602 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2603 return false;
fb7a46f3 2604
14571b4c 2605 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2606 unsigned char bytes[2];
2607
ea5b213a
CW		 2608 intel_sdvo->controlled_output = 0;
2609 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2610 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2611 SDVO_NAME(intel_sdvo),
51c8b407 2612 bytes[0], bytes[1]);
14571b4c 2613 return false;
fb7a46f3 2614 }
27f8227b 2615 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2616
14571b4c 2617 return true;
fb7a46f3 2618}
2619
d0ddfbd3
JN		 2620static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2621{
2622 struct drm_device *dev = intel_sdvo->base.base.dev;
2623 struct drm_connector *connector, *tmp;
2624
2625 list_for_each_entry_safe(connector, tmp,
2626 &dev->mode_config.connector_list, head) {
2627 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2628 intel_sdvo_destroy(connector);
2629 }
2630}
2631
32aad86f
CW		 2632static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2633 struct intel_sdvo_connector *intel_sdvo_connector,
2634 int type)
ce6feabd 2635{
4ef69c7a 2636 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2637 struct intel_sdvo_tv_format format;
2638 uint32_t format_map, i;
ce6feabd 2639
32aad86f
CW		 2640 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2641 return false;
ce6feabd 2642
1a3665c8 2643 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2644 if (!intel_sdvo_get_value(intel_sdvo,
2645 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2646 &format, sizeof(format)))
2647 return false;
ce6feabd 2648
32aad86f 2649 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2650
2651 if (format_map == 0)
32aad86f 2652 return false;
ce6feabd 2653
615fb93f 2654 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2655 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2656 if (format_map & (1 << i))
2657 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2658
2659
c5521706 2660 intel_sdvo_connector->tv_format =
32aad86f
CW		 2661 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2662 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2663 if (!intel_sdvo_connector->tv_format)
fcc8d672 2664 return false;
ce6feabd 2665
615fb93f 2666 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2667 drm_property_add_enum(
c5521706 2668 intel_sdvo_connector->tv_format, i,
40039750 2669 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2670
40039750 2671 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2672 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2673 intel_sdvo_connector->tv_format, 0);
32aad86f 2674 return true;
ce6feabd
ZY		 2675
2676}
2677
c5521706
CW		 2678#define ENHANCEMENT(name, NAME) do { \
2679 if (enhancements.name) { \
2680 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2681 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2682 return false; \
2683 intel_sdvo_connector->max_##name = data_value[0]; \
2684 intel_sdvo_connector->cur_##name = response; \
2685 intel_sdvo_connector->name = \
d9bc3c02 2686 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2687 if (!intel_sdvo_connector->name) return false; \
662595df 2688 drm_object_attach_property(&connector->base, \
c5521706
CW		 2689 intel_sdvo_connector->name, \
2690 intel_sdvo_connector->cur_##name); \
2691 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2692 data_value[0], data_value[1], response); \
2693 } \
0206e353 2694} while (0)
c5521706
CW		 2695
2696static bool
2697intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2698 struct intel_sdvo_connector *intel_sdvo_connector,
2699 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2700{
4ef69c7a 2701 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2702 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2703 uint16_t response, data_value[2];
2704
c5521706
CW		 2705 /* when horizontal overscan is supported, Add the left/right property */
2706 if (enhancements.overscan_h) {
2707 if (!intel_sdvo_get_value(intel_sdvo,
2708 SDVO_CMD_GET_MAX_OVERSCAN_H,
2709 &data_value, 4))
2710 return false;
32aad86f 2711
c5521706
CW		 2712 if (!intel_sdvo_get_value(intel_sdvo,
2713 SDVO_CMD_GET_OVERSCAN_H,
2714 &response, 2))
2715 return false;
fcc8d672 2716
c5521706
CW		 2717 intel_sdvo_connector->max_hscan = data_value[0];
2718 intel_sdvo_connector->left_margin = data_value[0] - response;
2719 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2720 intel_sdvo_connector->left =
d9bc3c02 2721 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2722 if (!intel_sdvo_connector->left)
2723 return false;
fcc8d672 2724
662595df 2725 drm_object_attach_property(&connector->base,
c5521706
CW		 2726 intel_sdvo_connector->left,
2727 intel_sdvo_connector->left_margin);
fcc8d672 2728
c5521706 2729 intel_sdvo_connector->right =
d9bc3c02 2730 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2731 if (!intel_sdvo_connector->right)
2732 return false;
32aad86f 2733
662595df 2734 drm_object_attach_property(&connector->base,
c5521706
CW		 2735 intel_sdvo_connector->right,
2736 intel_sdvo_connector->right_margin);
2737 DRM_DEBUG_KMS("h_overscan: max %d, "
2738 "default %d, current %d\n",
2739 data_value[0], data_value[1], response);
2740 }
32aad86f 2741
c5521706
CW		 2742 if (enhancements.overscan_v) {
2743 if (!intel_sdvo_get_value(intel_sdvo,
2744 SDVO_CMD_GET_MAX_OVERSCAN_V,
2745 &data_value, 4))
2746 return false;
fcc8d672 2747
c5521706
CW		 2748 if (!intel_sdvo_get_value(intel_sdvo,
2749 SDVO_CMD_GET_OVERSCAN_V,
2750 &response, 2))
2751 return false;
32aad86f 2752
c5521706
CW		 2753 intel_sdvo_connector->max_vscan = data_value[0];
2754 intel_sdvo_connector->top_margin = data_value[0] - response;
2755 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2756 intel_sdvo_connector->top =
d9bc3c02
SH		 2757 drm_property_create_range(dev, 0,
2758 "top_margin", 0, data_value[0]);
c5521706
CW		 2759 if (!intel_sdvo_connector->top)
2760 return false;
32aad86f 2761
662595df 2762 drm_object_attach_property(&connector->base,
c5521706
CW		 2763 intel_sdvo_connector->top,
2764 intel_sdvo_connector->top_margin);
fcc8d672 2765
c5521706 2766 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2767 drm_property_create_range(dev, 0,
2768 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2769 if (!intel_sdvo_connector->bottom)
2770 return false;
32aad86f 2771
662595df 2772 drm_object_attach_property(&connector->base,
c5521706
CW		 2773 intel_sdvo_connector->bottom,
2774 intel_sdvo_connector->bottom_margin);
2775 DRM_DEBUG_KMS("v_overscan: max %d, "
2776 "default %d, current %d\n",
2777 data_value[0], data_value[1], response);
2778 }
32aad86f 2779
c5521706
CW		 2780 ENHANCEMENT(hpos, HPOS);
2781 ENHANCEMENT(vpos, VPOS);
2782 ENHANCEMENT(saturation, SATURATION);
2783 ENHANCEMENT(contrast, CONTRAST);
2784 ENHANCEMENT(hue, HUE);
2785 ENHANCEMENT(sharpness, SHARPNESS);
2786 ENHANCEMENT(brightness, BRIGHTNESS);
2787 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2788 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2789 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2790 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2791 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2792
e044218a
CW		 2793 if (enhancements.dot_crawl) {
2794 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2795 return false;
2796
2797 intel_sdvo_connector->max_dot_crawl = 1;
2798 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2799 intel_sdvo_connector->dot_crawl =
d9bc3c02 2800 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2801 if (!intel_sdvo_connector->dot_crawl)
2802 return false;
2803
662595df 2804 drm_object_attach_property(&connector->base,
e044218a
CW		 2805 intel_sdvo_connector->dot_crawl,
2806 intel_sdvo_connector->cur_dot_crawl);
2807 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2808 }
2809
c5521706
CW		 2810 return true;
2811}
32aad86f 2812
c5521706
CW		 2813static bool
2814intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2815 struct intel_sdvo_connector *intel_sdvo_connector,
2816 struct intel_sdvo_enhancements_reply enhancements)
2817{
4ef69c7a 2818 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2819 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2820 uint16_t response, data_value[2];
32aad86f 2821
c5521706 2822 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2823
c5521706
CW		 2824 return true;
2825}
2826#undef ENHANCEMENT
32aad86f 2827
c5521706
CW		 2828static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2829 struct intel_sdvo_connector *intel_sdvo_connector)
2830{
2831 union {
2832 struct intel_sdvo_enhancements_reply reply;
2833 uint16_t response;
2834 } enhancements;
32aad86f 2835
1a3665c8
CW		 2836 BUILD_BUG_ON(sizeof(enhancements) != 2);
2837
cf9a2f3a
CW		 2838 enhancements.response = 0;
2839 intel_sdvo_get_value(intel_sdvo,
2840 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2841 &enhancements, sizeof(enhancements));
c5521706
CW		 2842 if (enhancements.response == 0) {
2843 DRM_DEBUG_KMS("No enhancement is supported\n");
2844 return true;
b9219c5e 2845 }
32aad86f 2846
c5521706
CW		 2847 if (IS_TV(intel_sdvo_connector))
2848 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2849 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2850 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2851 else
2852 return true;
e957d772
CW		 2853}
2854
2855static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2856 struct i2c_msg *msgs,
2857 int num)
2858{
2859 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2860
e957d772
CW		 2861 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2862 return -EIO;
2863
2864 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2865}
2866
2867static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2868{
2869 struct intel_sdvo *sdvo = adapter->algo_data;
2870 return sdvo->i2c->algo->functionality(sdvo->i2c);
2871}
2872
2873static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2874 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2875 .functionality = intel_sdvo_ddc_proxy_func
2876};
2877
2878static bool
2879intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2880 struct drm_device *dev)
2881{
2882 sdvo->ddc.owner = THIS_MODULE;
2883 sdvo->ddc.class = I2C_CLASS_DDC;
2884 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2885 sdvo->ddc.dev.parent = &dev->pdev->dev;
2886 sdvo->ddc.algo_data = sdvo;
2887 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2888
2889 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2890}
2891
eef4eacb 2892bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2893{
b01f2c3a 2894 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2895 struct intel_encoder *intel_encoder;
ea5b213a 2896 struct intel_sdvo *intel_sdvo;
79e53945 2897 int i;
b14c5679 2898 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 2899 if (!intel_sdvo)
7d57382e 2900 return false;
79e53945 2901
56184e3d 2902 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2903 intel_sdvo->is_sdvob = is_sdvob;
2904 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2905 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2906 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2907 goto err_i2c_bus;
e957d772 2908
56184e3d 2909 /* encoder type will be decided later */
ea5b213a 2910 intel_encoder = &intel_sdvo->base;
21d40d37 2911 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2912 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2913
79e53945
JB		 2914 /* Read the regs to test if we can talk to the device */
2915 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2916 u8 byte;
2917
2918 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2919 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2920 SDVO_NAME(intel_sdvo));
f899fc64 2921 goto err;
79e53945
JB		 2922 }
2923 }
2924
6cc5f341 2925 intel_encoder->compute_config = intel_sdvo_compute_config;
ce22c320 2926 intel_encoder->disable = intel_disable_sdvo;
6cc5f341 2927 intel_encoder->mode_set = intel_sdvo_mode_set;
ce22c320 2928 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2929 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 2930 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 2931
af901ca1 2932 /* In default case sdvo lvds is false */
32aad86f 2933 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2934 goto err;
79e53945 2935
ea5b213a
CW		 2936 if (intel_sdvo_output_setup(intel_sdvo,
2937 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2938 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2939 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 2940 /* Output_setup can leave behind connectors! */
2941 goto err_output;
79e53945
JB		 2942 }
2943
7ba220ce
CW		 2944 /* Only enable the hotplug irq if we need it, to work around noisy
2945 * hotplug lines.
2946 */
2947 if (intel_sdvo->hotplug_active) {
2948 intel_encoder->hpd_pin =
2949 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
2950 }
2951
e506d6fd
DV		 2952 /*
2953 * Cloning SDVO with anything is often impossible, since the SDVO
2954 * encoder can request a special input timing mode. And even if that's
2955 * not the case we have evidence that cloning a plain unscaled mode with
2956 * VGA doesn't really work. Furthermore the cloning flags are way too
2957 * simplistic anyway to express such constraints, so just give up on
2958 * cloning for SDVO encoders.
2959 */
2960 intel_sdvo->base.cloneable = false;
2961
ea5b213a 2962 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2963
79e53945 2964 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2965 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 2966 goto err_output;
79e53945 2967
32aad86f
CW		 2968 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2969 &intel_sdvo->pixel_clock_min,
2970 &intel_sdvo->pixel_clock_max))
d0ddfbd3 2971 goto err_output;
79e53945 2972
8a4c47f3 2973 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2974 "clock range %dMHz - %dMHz, "
2975 "input 1: %c, input 2: %c, "
2976 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2977 SDVO_NAME(intel_sdvo),
2978 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2979 intel_sdvo->caps.device_rev_id,
2980 intel_sdvo->pixel_clock_min / 1000,
2981 intel_sdvo->pixel_clock_max / 1000,
2982 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2983 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2984 /* check currently supported outputs */
ea5b213a 2985 intel_sdvo->caps.output_flags &
79e53945 2986 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2987 intel_sdvo->caps.output_flags &
79e53945 2988 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2989 return true;
79e53945 2990
d0ddfbd3
JN		 2991err_output:
2992 intel_sdvo_output_cleanup(intel_sdvo);
2993
f899fc64 2994err:
373a3cf7 2995 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2996 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2997err_i2c_bus:
2998 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2999 kfree(intel_sdvo);
79e53945 3000
7d57382e 3001 return false;
79e53945 3002}
Linux kernel - Deliverables
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