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drm/i915: disable sdvo hotplug on i945g/gm
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
2e88e40b 56static const char *tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 77 int sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
100 uint8_t hotplug_active[2];
101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
ce6feabd 117 /* This is for current tv format name */
40039750 118 int tv_format_index;
ce6feabd 119
e2f0ba97
JB		 120 /**
121 * This is set if we treat the device as HDMI, instead of DVI.
122 */
123 bool is_hdmi;
da79de97
CW		 124 bool has_hdmi_monitor;
125 bool has_hdmi_audio;
12682a97 126
7086c87f 127 /**
6c9547ff
CW		 128 * This is set if we detect output of sdvo device as LVDS and
129 * have a valid fixed mode to use with the panel.
7086c87f
ML		 130 */
131 bool is_lvds;
e2f0ba97 132
12682a97 133 /**
134 * This is sdvo fixed pannel mode pointer
135 */
136 struct drm_display_mode *sdvo_lvds_fixed_mode;
137
c751ce4f 138 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 139 uint8_t ddc_bus;
140
6c9547ff
CW		 141 /* Input timings for adjusted_mode */
142 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 143};
144
145struct intel_sdvo_connector {
615fb93f
CW		 146 struct intel_connector base;
147
14571b4c
ZW		 148 /* Mark the type of connector */
149 uint16_t output_flag;
150
c3e5f67b 151 enum hdmi_force_audio force_audio;
7f36e7ed 152
14571b4c 153 /* This contains all current supported TV format */
40039750 154 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 155 int format_supported_num;
c5521706 156 struct drm_property *tv_format;
14571b4c 157
b9219c5e 158 /* add the property for the SDVO-TV */
c5521706
CW		 159 struct drm_property *left;
160 struct drm_property *right;
161 struct drm_property *top;
162 struct drm_property *bottom;
163 struct drm_property *hpos;
164 struct drm_property *vpos;
165 struct drm_property *contrast;
166 struct drm_property *saturation;
167 struct drm_property *hue;
168 struct drm_property *sharpness;
169 struct drm_property *flicker_filter;
170 struct drm_property *flicker_filter_adaptive;
171 struct drm_property *flicker_filter_2d;
172 struct drm_property *tv_chroma_filter;
173 struct drm_property *tv_luma_filter;
e044218a 174 struct drm_property *dot_crawl;
b9219c5e
ZY		 175
176 /* add the property for the SDVO-TV/LVDS */
c5521706 177 struct drm_property *brightness;
b9219c5e
ZY		 178
179 /* Add variable to record current setting for the above property */
180 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 181
b9219c5e
ZY		 182 /* this is to get the range of margin.*/
183 u32 max_hscan, max_vscan;
184 u32 max_hpos, cur_hpos;
185 u32 max_vpos, cur_vpos;
186 u32 cur_brightness, max_brightness;
187 u32 cur_contrast, max_contrast;
188 u32 cur_saturation, max_saturation;
189 u32 cur_hue, max_hue;
c5521706
CW		 190 u32 cur_sharpness, max_sharpness;
191 u32 cur_flicker_filter, max_flicker_filter;
192 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
193 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
194 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
195 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 196 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 197};
198
890f3359 199static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 200{
4ef69c7a 201 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 202}
203
df0e9248
CW		 204static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
205{
206 return container_of(intel_attached_encoder(connector),
207 struct intel_sdvo, base);
208}
209
615fb93f
CW		 210static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
211{
212 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
213}
214
fb7a46f3 215static bool
ea5b213a 216intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 217static bool
218intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
219 struct intel_sdvo_connector *intel_sdvo_connector,
220 int type);
221static bool
222intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
223 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 224
79e53945
JB		 225/**
226 * Writes the SDVOB or SDVOC with the given value, but always writes both
227 * SDVOB and SDVOC to work around apparent hardware issues (according to
228 * comments in the BIOS).
229 */
ea5b213a 230static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 231{
4ef69c7a 232 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 233 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 234 u32 bval = val, cval = val;
235 int i;
236
ea5b213a
CW		 237 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
238 I915_WRITE(intel_sdvo->sdvo_reg, val);
239 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 240 return;
241 }
242
ea5b213a 243 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 244 cval = I915_READ(SDVOC);
245 } else {
246 bval = I915_READ(SDVOB);
247 }
248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
253 for (i = 0; i < 2; i++)
254 {
255 I915_WRITE(SDVOB, bval);
256 I915_READ(SDVOB);
257 I915_WRITE(SDVOC, cval);
258 I915_READ(SDVOC);
259 }
260}
261
32aad86f 262static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 263{
79e53945
JB		 264 struct i2c_msg msgs[] = {
265 {
e957d772 266 .addr = intel_sdvo->slave_addr,
79e53945
JB		 267 .flags = 0,
268 .len = 1,
e957d772 269 .buf = &addr,
79e53945
JB		 270 },
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = I2C_M_RD,
274 .len = 1,
e957d772 275 .buf = ch,
79e53945
JB		 276 }
277 };
32aad86f 278 int ret;
79e53945 279
f899fc64 280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 281 return true;
79e53945 282
8a4c47f3 283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 284 return false;
285}
286
79e53945
JB		 287#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288/** Mapping of command numbers to names, for debug output */
005568be 289static const struct _sdvo_cmd_name {
e2f0ba97 290 u8 cmd;
2e88e40b 291 const char *name;
79e53945 292} sdvo_cmd_names[] = {
0206e353
AJ		 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 404};
405
461ed3ca 406#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 407#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 408
ea5b213a 409static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 410 const void *args, int args_len)
79e53945 411{
79e53945
JB		 412 int i;
413
8a4c47f3 414 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 415 SDVO_NAME(intel_sdvo), cmd);
79e53945 416 for (i = 0; i < args_len; i++)
342dc382 417 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 418 for (; i < 8; i++)
342dc382 419 DRM_LOG_KMS(" ");
04ad327f 420 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 421 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 422 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 423 break;
424 }
425 }
04ad327f 426 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 427 DRM_LOG_KMS("(%02X)", cmd);
428 DRM_LOG_KMS("\n");
79e53945 429}
79e53945 430
e957d772
CW		 431static const char *cmd_status_names[] = {
432 "Power on",
433 "Success",
434 "Not supported",
435 "Invalid arg",
436 "Pending",
437 "Target not specified",
438 "Scaling not supported"
439};
440
32aad86f
CW		 441static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
442 const void *args, int args_len)
79e53945 443{
e957d772
CW		 444 u8 buf[args_len*2 + 2], status;
445 struct i2c_msg msgs[args_len + 3];
446 int i, ret;
79e53945 447
ea5b213a 448 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 449
450 for (i = 0; i < args_len; i++) {
e957d772
CW		 451 msgs[i].addr = intel_sdvo->slave_addr;
452 msgs[i].flags = 0;
453 msgs[i].len = 2;
454 msgs[i].buf = buf + 2 *i;
455 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
456 buf[2*i + 1] = ((u8*)args)[i];
457 }
458 msgs[i].addr = intel_sdvo->slave_addr;
459 msgs[i].flags = 0;
460 msgs[i].len = 2;
461 msgs[i].buf = buf + 2*i;
462 buf[2*i + 0] = SDVO_I2C_OPCODE;
463 buf[2*i + 1] = cmd;
464
465 /* the following two are to read the response */
466 status = SDVO_I2C_CMD_STATUS;
467 msgs[i+1].addr = intel_sdvo->slave_addr;
468 msgs[i+1].flags = 0;
469 msgs[i+1].len = 1;
470 msgs[i+1].buf = &status;
471
472 msgs[i+2].addr = intel_sdvo->slave_addr;
473 msgs[i+2].flags = I2C_M_RD;
474 msgs[i+2].len = 1;
475 msgs[i+2].buf = &status;
476
477 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
478 if (ret < 0) {
479 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
480 return false;
481 }
482 if (ret != i+3) {
483 /* failure in I2C transfer */
484 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
485 return false;
486 }
487
e957d772 488 return true;
79e53945
JB		 489}
490
b5c616a7
CW		 491static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
492 void *response, int response_len)
79e53945 493{
b5c616a7
CW		 494 u8 retry = 5;
495 u8 status;
33b52961 496 int i;
79e53945 497
d121a5d2
CW		 498 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
499
b5c616a7
CW		 500 /*
501 * The documentation states that all commands will be
502 * processed within 15µs, and that we need only poll
503 * the status byte a maximum of 3 times in order for the
504 * command to be complete.
505 *
506 * Check 5 times in case the hardware failed to read the docs.
507 */
d121a5d2
CW		 508 if (!intel_sdvo_read_byte(intel_sdvo,
509 SDVO_I2C_CMD_STATUS,
510 &status))
511 goto log_fail;
512
513 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
514 udelay(15);
b5c616a7
CW		 515 if (!intel_sdvo_read_byte(intel_sdvo,
516 SDVO_I2C_CMD_STATUS,
517 &status))
d121a5d2
CW		 518 goto log_fail;
519 }
b5c616a7 520
79e53945 521 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 522 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 523 else
342dc382 524 DRM_LOG_KMS("(??? %d)", status);
79e53945 525
b5c616a7
CW		 526 if (status != SDVO_CMD_STATUS_SUCCESS)
527 goto log_fail;
79e53945 528
b5c616a7
CW		 529 /* Read the command response */
530 for (i = 0; i < response_len; i++) {
531 if (!intel_sdvo_read_byte(intel_sdvo,
532 SDVO_I2C_RETURN_0 + i,
533 &((u8 *)response)[i]))
534 goto log_fail;
e957d772 535 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 536 }
b5c616a7 537 DRM_LOG_KMS("\n");
b5c616a7 538 return true;
79e53945 539
b5c616a7 540log_fail:
d121a5d2 541 DRM_LOG_KMS("... failed\n");
b5c616a7 542 return false;
79e53945
JB		 543}
544
b358d0a6 545static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 546{
547 if (mode->clock >= 100000)
548 return 1;
549 else if (mode->clock >= 50000)
550 return 2;
551 else
552 return 4;
553}
554
e957d772
CW		 555static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
556 u8 ddc_bus)
79e53945 557{
d121a5d2 558 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 559 return intel_sdvo_write_cmd(intel_sdvo,
560 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
561 &ddc_bus, 1);
79e53945
JB		 562}
563
32aad86f 564static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 565{
d121a5d2
CW		 566 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
567 return false;
568
569 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 570}
79e53945 571
32aad86f
CW		 572static bool
573intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
574{
575 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
576 return false;
79e53945 577
32aad86f
CW		 578 return intel_sdvo_read_response(intel_sdvo, value, len);
579}
79e53945 580
32aad86f
CW		 581static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
582{
583 struct intel_sdvo_set_target_input_args targets = {0};
584 return intel_sdvo_set_value(intel_sdvo,
585 SDVO_CMD_SET_TARGET_INPUT,
586 &targets, sizeof(targets));
79e53945
JB		 587}
588
589/**
590 * Return whether each input is trained.
591 *
592 * This function is making an assumption about the layout of the response,
593 * which should be checked against the docs.
594 */
ea5b213a 595static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 596{
597 struct intel_sdvo_get_trained_inputs_response response;
79e53945 598
1a3665c8 599 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 600 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
601 &response, sizeof(response)))
79e53945
JB		 602 return false;
603
604 *input_1 = response.input0_trained;
605 *input_2 = response.input1_trained;
606 return true;
607}
608
ea5b213a 609static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 610 u16 outputs)
611{
32aad86f
CW		 612 return intel_sdvo_set_value(intel_sdvo,
613 SDVO_CMD_SET_ACTIVE_OUTPUTS,
614 &outputs, sizeof(outputs));
79e53945
JB		 615}
616
ea5b213a 617static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 618 int mode)
619{
32aad86f 620 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 621
622 switch (mode) {
623 case DRM_MODE_DPMS_ON:
624 state = SDVO_ENCODER_STATE_ON;
625 break;
626 case DRM_MODE_DPMS_STANDBY:
627 state = SDVO_ENCODER_STATE_STANDBY;
628 break;
629 case DRM_MODE_DPMS_SUSPEND:
630 state = SDVO_ENCODER_STATE_SUSPEND;
631 break;
632 case DRM_MODE_DPMS_OFF:
633 state = SDVO_ENCODER_STATE_OFF;
634 break;
635 }
636
32aad86f
CW		 637 return intel_sdvo_set_value(intel_sdvo,
638 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 639}
640
ea5b213a 641static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 642 int *clock_min,
643 int *clock_max)
644{
645 struct intel_sdvo_pixel_clock_range clocks;
79e53945 646
1a3665c8 647 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 648 if (!intel_sdvo_get_value(intel_sdvo,
649 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
650 &clocks, sizeof(clocks)))
79e53945
JB		 651 return false;
652
653 /* Convert the values from units of 10 kHz to kHz. */
654 *clock_min = clocks.min * 10;
655 *clock_max = clocks.max * 10;
79e53945
JB		 656 return true;
657}
658
ea5b213a 659static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 660 u16 outputs)
661{
32aad86f
CW		 662 return intel_sdvo_set_value(intel_sdvo,
663 SDVO_CMD_SET_TARGET_OUTPUT,
664 &outputs, sizeof(outputs));
79e53945
JB		 665}
666
ea5b213a 667static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 668 struct intel_sdvo_dtd *dtd)
669{
32aad86f
CW		 670 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
671 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 672}
673
ea5b213a 674static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 675 struct intel_sdvo_dtd *dtd)
676{
ea5b213a 677 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 678 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
679}
680
ea5b213a 681static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 682 struct intel_sdvo_dtd *dtd)
683{
ea5b213a 684 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 685 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
686}
687
e2f0ba97 688static bool
ea5b213a 689intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 690 uint16_t clock,
691 uint16_t width,
692 uint16_t height)
693{
694 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 695
e642c6f1 696 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 697 args.clock = clock;
698 args.width = width;
699 args.height = height;
e642c6f1 700 args.interlace = 0;
12682a97 701
ea5b213a
CW		 702 if (intel_sdvo->is_lvds &&
703 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
704 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 705 args.scaled = 1;
706
32aad86f
CW		 707 return intel_sdvo_set_value(intel_sdvo,
708 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
709 &args, sizeof(args));
e2f0ba97
JB		 710}
711
ea5b213a 712static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 713 struct intel_sdvo_dtd *dtd)
714{
1a3665c8
CW		 715 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
716 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 717 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
718 &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
720 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 721}
79e53945 722
ea5b213a 723static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 724{
32aad86f 725 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 726}
727
e2f0ba97 728static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 729 const struct drm_display_mode *mode)
79e53945 730{
e2f0ba97
JB		 731 uint16_t width, height;
732 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
733 uint16_t h_sync_offset, v_sync_offset;
6651819b 734 int mode_clock;
79e53945
JB		 735
736 width = mode->crtc_hdisplay;
737 height = mode->crtc_vdisplay;
738
739 /* do some mode translations */
740 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
741 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
742
743 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
744 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
745
746 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
747 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
748
6651819b
DV		 749 mode_clock = mode->clock;
750 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
751 mode_clock /= 10;
752 dtd->part1.clock = mode_clock;
753
e2f0ba97
JB		 754 dtd->part1.h_active = width & 0xff;
755 dtd->part1.h_blank = h_blank_len & 0xff;
756 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 757 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 758 dtd->part1.v_active = height & 0xff;
759 dtd->part1.v_blank = v_blank_len & 0xff;
760 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 761 ((v_blank_len >> 8) & 0xf);
762
171a9e96 763 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 764 dtd->part2.h_sync_width = h_sync_len & 0xff;
765 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 766 (v_sync_len & 0xf);
e2f0ba97 767 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 768 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
769 ((v_sync_len & 0x30) >> 4);
770
e2f0ba97 771 dtd->part2.dtd_flags = 0x18;
79e53945 772 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 773 dtd->part2.dtd_flags |= 0x2;
79e53945 774 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 775 dtd->part2.dtd_flags |= 0x4;
776
777 dtd->part2.sdvo_flags = 0;
778 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
779 dtd->part2.reserved = 0;
780}
781
782static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 783 const struct intel_sdvo_dtd *dtd)
e2f0ba97 784{
e2f0ba97
JB		 785 mode->hdisplay = dtd->part1.h_active;
786 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
787 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 788 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 789 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
790 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
791 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
792 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
793
794 mode->vdisplay = dtd->part1.v_active;
795 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
796 mode->vsync_start = mode->vdisplay;
797 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 798 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 799 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
800 mode->vsync_end = mode->vsync_start +
801 (dtd->part2.v_sync_off_width & 0xf);
802 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
803 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
804 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
805
806 mode->clock = dtd->part1.clock * 10;
807
171a9e96 808 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 809 if (dtd->part2.dtd_flags & 0x2)
810 mode->flags |= DRM_MODE_FLAG_PHSYNC;
811 if (dtd->part2.dtd_flags & 0x4)
812 mode->flags |= DRM_MODE_FLAG_PVSYNC;
813}
814
e27d8538 815static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 816{
e27d8538 817 struct intel_sdvo_encode encode;
e2f0ba97 818
1a3665c8 819 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 820 return intel_sdvo_get_value(intel_sdvo,
821 SDVO_CMD_GET_SUPP_ENCODE,
822 &encode, sizeof(encode));
e2f0ba97
JB		 823}
824
ea5b213a 825static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 826 uint8_t mode)
e2f0ba97 827{
32aad86f 828 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 829}
830
ea5b213a 831static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 832 uint8_t mode)
833{
32aad86f 834 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 835}
836
837#if 0
ea5b213a 838static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 839{
840 int i, j;
841 uint8_t set_buf_index[2];
842 uint8_t av_split;
843 uint8_t buf_size;
844 uint8_t buf[48];
845 uint8_t *pos;
846
32aad86f 847 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 848
849 for (i = 0; i <= av_split; i++) {
850 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 851 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 852 set_buf_index, 2);
c751ce4f
EA		 853 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
854 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 855
856 pos = buf;
857 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 858 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 859 NULL, 0);
c751ce4f 860 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 861 pos += 8;
862 }
863 }
864}
865#endif
866
3c17fe4b 867static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 868{
869 struct dip_infoframe avi_if = {
870 .type = DIP_TYPE_AVI,
3c17fe4b 871 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 872 .len = DIP_LEN_AVI,
873 };
3c17fe4b
DH		 874 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
875 uint8_t set_buf_index[2] = { 1, 0 };
876 uint64_t *data = (uint64_t *)&avi_if;
877 unsigned i;
878
879 intel_dip_infoframe_csum(&avi_if);
880
d121a5d2
CW		 881 if (!intel_sdvo_set_value(intel_sdvo,
882 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 883 set_buf_index, 2))
884 return false;
885
886 for (i = 0; i < sizeof(avi_if); i += 8) {
d121a5d2
CW		 887 if (!intel_sdvo_set_value(intel_sdvo,
888 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 889 data, 8))
890 return false;
891 data++;
892 }
e2f0ba97 893
d121a5d2
CW		 894 return intel_sdvo_set_value(intel_sdvo,
895 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 896 &tx_rate, 1);
e2f0ba97
JB		 897}
898
32aad86f 899static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 900{
ce6feabd 901 struct intel_sdvo_tv_format format;
40039750 902 uint32_t format_map;
ce6feabd 903
40039750 904 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 905 memset(&format, 0, sizeof(format));
32aad86f 906 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 907
32aad86f
CW		 908 BUILD_BUG_ON(sizeof(format) != 6);
909 return intel_sdvo_set_value(intel_sdvo,
910 SDVO_CMD_SET_TV_FORMAT,
911 &format, sizeof(format));
7026d4ac
ZW		 912}
913
32aad86f
CW		 914static bool
915intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
916 struct drm_display_mode *mode)
e2f0ba97 917{
32aad86f 918 struct intel_sdvo_dtd output_dtd;
79e53945 919
32aad86f
CW		 920 if (!intel_sdvo_set_target_output(intel_sdvo,
921 intel_sdvo->attached_output))
922 return false;
e2f0ba97 923
32aad86f
CW		 924 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
925 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
926 return false;
e2f0ba97 927
32aad86f
CW		 928 return true;
929}
930
931static bool
932intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
933 struct drm_display_mode *mode,
934 struct drm_display_mode *adjusted_mode)
935{
32aad86f
CW		 936 /* Reset the input timing to the screen. Assume always input 0. */
937 if (!intel_sdvo_set_target_input(intel_sdvo))
938 return false;
e2f0ba97 939
32aad86f
CW		 940 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
941 mode->clock / 10,
942 mode->hdisplay,
943 mode->vdisplay))
944 return false;
e2f0ba97 945
32aad86f 946 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 947 &intel_sdvo->input_dtd))
32aad86f 948 return false;
e2f0ba97 949
6c9547ff 950 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 951
32aad86f
CW		 952 return true;
953}
12682a97 954
32aad86f
CW		 955static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
956 struct drm_display_mode *mode,
957 struct drm_display_mode *adjusted_mode)
958{
890f3359 959 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 960 int multiplier;
12682a97 961
32aad86f
CW		 962 /* We need to construct preferred input timings based on our
963 * output timings. To do that, we have to set the output
964 * timings, even though this isn't really the right place in
965 * the sequence to do it. Oh well.
966 */
967 if (intel_sdvo->is_tv) {
968 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
969 return false;
12682a97 970
c74696b9
PR		 971 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
972 mode,
973 adjusted_mode);
ea5b213a 974 } else if (intel_sdvo->is_lvds) {
32aad86f 975 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 976 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 977 return false;
12682a97 978
c74696b9
PR		 979 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
980 mode,
981 adjusted_mode);
e2f0ba97 982 }
32aad86f
CW		 983
984 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 985 * SDVO device will factor out the multiplier during mode_set.
32aad86f 986 */
6c9547ff
CW		 987 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
988 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 989
e2f0ba97
JB		 990 return true;
991}
992
993static void intel_sdvo_mode_set(struct drm_encoder *encoder,
994 struct drm_display_mode *mode,
995 struct drm_display_mode *adjusted_mode)
996{
997 struct drm_device *dev = encoder->dev;
998 struct drm_i915_private *dev_priv = dev->dev_private;
999 struct drm_crtc *crtc = encoder->crtc;
1000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1001 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1002 u32 sdvox;
e2f0ba97 1003 struct intel_sdvo_in_out_map in_out;
6651819b 1004 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1005 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1006 int rate;
e2f0ba97
JB		 1007
1008 if (!mode)
1009 return;
1010
1011 /* First, set the input mapping for the first input to our controlled
1012 * output. This is only correct if we're a single-input device, in
1013 * which case the first input is the output from the appropriate SDVO
1014 * channel on the motherboard. In a two-input device, the first input
1015 * will be SDVOB and the second SDVOC.
1016 */
ea5b213a 1017 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1018 in_out.in1 = 0;
1019
c74696b9
PR		 1020 intel_sdvo_set_value(intel_sdvo,
1021 SDVO_CMD_SET_IN_OUT_MAP,
1022 &in_out, sizeof(in_out));
e2f0ba97 1023
6c9547ff
CW		 1024 /* Set the output timings to the screen */
1025 if (!intel_sdvo_set_target_output(intel_sdvo,
1026 intel_sdvo->attached_output))
1027 return;
e2f0ba97 1028
6651819b
DV		 1029 /* lvds has a special fixed output timing. */
1030 if (intel_sdvo->is_lvds)
1031 intel_sdvo_get_dtd_from_mode(&output_dtd,
1032 intel_sdvo->sdvo_lvds_fixed_mode);
1033 else
1034 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1035 (void) intel_sdvo_set_output_timing(intel_sdvo, &output_dtd);
79e53945
JB		 1036
1037 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1038 if (!intel_sdvo_set_target_input(intel_sdvo))
1039 return;
79e53945 1040
97aaf910
CW		 1041 if (intel_sdvo->has_hdmi_monitor) {
1042 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1043 intel_sdvo_set_colorimetry(intel_sdvo,
1044 SDVO_COLORIMETRY_RGB256);
1045 intel_sdvo_set_avi_infoframe(intel_sdvo);
1046 } else
1047 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1048
6c9547ff
CW		 1049 if (intel_sdvo->is_tv &&
1050 !intel_sdvo_set_tv_format(intel_sdvo))
1051 return;
e2f0ba97 1052
6651819b
DV		 1053 /* We have tried to get input timing in mode_fixup, and filled into
1054 * adjusted_mode.
1055 */
1056 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1057 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1058
6c9547ff
CW		 1059 switch (pixel_multiplier) {
1060 default:
32aad86f
CW		 1061 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1062 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1063 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1064 }
32aad86f
CW		 1065 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1066 return;
79e53945
JB		 1067
1068 /* Set the SDVO control regs. */
a6c45cf0 1069 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1070 /* The real mode polarity is set by the SDVO commands, using
1071 * struct intel_sdvo_dtd. */
1072 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1073 if (intel_sdvo->is_hdmi)
1074 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1075 if (INTEL_INFO(dev)->gen < 5)
1076 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1077 } else {
6c9547ff 1078 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1079 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1080 case SDVOB:
1081 sdvox &= SDVOB_PRESERVE_MASK;
1082 break;
1083 case SDVOC:
1084 sdvox &= SDVOC_PRESERVE_MASK;
1085 break;
1086 }
1087 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1088 }
3573c410
PZ		 1089
1090 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1091 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1092 else
1093 sdvox |= TRANSCODER(intel_crtc->pipe);
1094
da79de97 1095 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1096 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1097
a6c45cf0 1098 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1099 /* done in crtc_mode_set as the dpll_md reg must be written early */
1100 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1101 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1102 } else {
6c9547ff 1103 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1104 }
1105
6714afb1
CW		 1106 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1107 INTEL_INFO(dev)->gen < 5)
12682a97 1108 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1109 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1110}
1111
1112static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1113{
1114 struct drm_device *dev = encoder->dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1116 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1117 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1118 u32 temp;
1119
1120 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1121 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1122 if (0)
ea5b213a 1123 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1124
1125 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1126 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1127 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1128 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1129 }
1130 }
1131 } else {
1132 bool input1, input2;
1133 int i;
1134 u8 status;
1135
ea5b213a 1136 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1137 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1138 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1139 for (i = 0; i < 2; i++)
9d0498a2 1140 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1141
32aad86f 1142 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1143 /* Warn if the device reported failure to sync.
1144 * A lot of SDVO devices fail to notify of sync, but it's
1145 * a given it the status is a success, we succeeded.
1146 */
1147 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1148 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1149 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1150 }
1151
1152 if (0)
ea5b213a
CW		 1153 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1154 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1155 }
1156 return;
1157}
1158
79e53945
JB		 1159static int intel_sdvo_mode_valid(struct drm_connector *connector,
1160 struct drm_display_mode *mode)
1161{
df0e9248 1162 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1163
1164 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1165 return MODE_NO_DBLESCAN;
1166
ea5b213a 1167 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1168 return MODE_CLOCK_LOW;
1169
ea5b213a 1170 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1171 return MODE_CLOCK_HIGH;
1172
8545423a 1173 if (intel_sdvo->is_lvds) {
ea5b213a 1174 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1175 return MODE_PANEL;
1176
ea5b213a 1177 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1178 return MODE_PANEL;
1179 }
1180
79e53945
JB		 1181 return MODE_OK;
1182}
1183
ea5b213a 1184static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1185{
1a3665c8 1186 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1187 if (!intel_sdvo_get_value(intel_sdvo,
1188 SDVO_CMD_GET_DEVICE_CAPS,
1189 caps, sizeof(*caps)))
1190 return false;
1191
1192 DRM_DEBUG_KMS("SDVO capabilities:\n"
1193 " vendor_id: %d\n"
1194 " device_id: %d\n"
1195 " device_rev_id: %d\n"
1196 " sdvo_version_major: %d\n"
1197 " sdvo_version_minor: %d\n"
1198 " sdvo_inputs_mask: %d\n"
1199 " smooth_scaling: %d\n"
1200 " sharp_scaling: %d\n"
1201 " up_scaling: %d\n"
1202 " down_scaling: %d\n"
1203 " stall_support: %d\n"
1204 " output_flags: %d\n",
1205 caps->vendor_id,
1206 caps->device_id,
1207 caps->device_rev_id,
1208 caps->sdvo_version_major,
1209 caps->sdvo_version_minor,
1210 caps->sdvo_inputs_mask,
1211 caps->smooth_scaling,
1212 caps->sharp_scaling,
1213 caps->up_scaling,
1214 caps->down_scaling,
1215 caps->stall_support,
1216 caps->output_flags);
1217
1218 return true;
79e53945
JB		 1219}
1220
cc68c81a 1221static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945 1222{
768b107e 1223 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 1224 u8 response[2];
79e53945 1225
768b107e
DV		 1226 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1227 * on the line. */
1228 if (IS_I945G(dev) || IS_I945GM(dev))
1229 return false;
1230
32aad86f
CW		 1231 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1232 &response, 2) && response[0];
79e53945
JB		 1233}
1234
cc68c81a 1235static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1236{
cc68c81a 1237 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1238
cc68c81a 1239 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1240}
1241
fb7a46f3 1242static bool
ea5b213a 1243intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1244{
bc65212c 1245 /* Is there more than one type of output? */
2294488d 1246 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1247}
1248
f899fc64 1249static struct edid *
e957d772 1250intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1251{
e957d772
CW		 1252 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1253 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1254}
1255
ff482d83
CW		 1256/* Mac mini hack -- use the same DDC as the analog connector */
1257static struct edid *
1258intel_sdvo_get_analog_edid(struct drm_connector *connector)
1259{
f899fc64 1260 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1261
0c1dab89
CW		 1262 return drm_get_edid(connector,
1263 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
ff482d83
CW		 1264}
1265
2b8d33f7 1266enum drm_connector_status
8bf38485 1267intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1268{
df0e9248 1269 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1270 enum drm_connector_status status;
1271 struct edid *edid;
9dff6af8 1272
e957d772 1273 edid = intel_sdvo_get_edid(connector);
57cdaf90 1274
ea5b213a 1275 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1276 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1277
7c3f0a27
ZY		 1278 /*
1279 * Don't use the 1 as the argument of DDC bus switch to get
1280 * the EDID. It is used for SDVO SPD ROM.
1281 */
9d1a903d 1282 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1283 intel_sdvo->ddc_bus = ddc;
1284 edid = intel_sdvo_get_edid(connector);
1285 if (edid)
7c3f0a27 1286 break;
7c3f0a27 1287 }
e957d772
CW		 1288 /*
1289 * If we found the EDID on the other bus,
1290 * assume that is the correct DDC bus.
1291 */
1292 if (edid == NULL)
1293 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1294 }
9d1a903d
CW		 1295
1296 /*
1297 * When there is no edid and no monitor is connected with VGA
1298 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1299 */
ff482d83
CW		 1300 if (edid == NULL)
1301 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1302
2f551c84 1303 status = connector_status_unknown;
9dff6af8 1304 if (edid != NULL) {
149c36a3 1305 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1306 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1307 status = connector_status_connected;
da79de97
CW		 1308 if (intel_sdvo->is_hdmi) {
1309 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1310 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1311 }
13946743
CW		 1312 } else
1313 status = connector_status_disconnected;
149c36a3 1314 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1315 kfree(edid);
1316 }
7f36e7ed
CW		 1317
1318 if (status == connector_status_connected) {
1319 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1320 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1321 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1322 }
1323
2b8d33f7 1324 return status;
9dff6af8
ML		 1325}
1326
52220085
CW		 1327static bool
1328intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1329 struct edid *edid)
1330{
1331 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1332 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1333
1334 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1335 connector_is_digital, monitor_is_digital);
1336 return connector_is_digital == monitor_is_digital;
1337}
1338
7b334fcb 1339static enum drm_connector_status
930a9e28 1340intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1341{
fb7a46f3 1342 uint16_t response;
df0e9248 1343 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1344 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1345 enum drm_connector_status ret;
79e53945 1346
32aad86f 1347 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1348 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1349 return connector_status_unknown;
ba84cd1f
CW		 1350
1351 /* add 30ms delay when the output type might be TV */
1352 if (intel_sdvo->caps.output_flags &
1353 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
d09c23de 1354 mdelay(30);
ba84cd1f 1355
32aad86f
CW		 1356 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1357 return connector_status_unknown;
79e53945 1358
e957d772
CW		 1359 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1360 response & 0xff, response >> 8,
1361 intel_sdvo_connector->output_flag);
e2f0ba97 1362
fb7a46f3 1363 if (response == 0)
79e53945 1364 return connector_status_disconnected;
fb7a46f3 1365
ea5b213a 1366 intel_sdvo->attached_output = response;
14571b4c 1367
97aaf910
CW		 1368 intel_sdvo->has_hdmi_monitor = false;
1369 intel_sdvo->has_hdmi_audio = false;
1370
615fb93f 1371 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1372 ret = connector_status_disconnected;
13946743 1373 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1374 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1375 else {
1376 struct edid *edid;
1377
1378 /* if we have an edid check it matches the connection */
1379 edid = intel_sdvo_get_edid(connector);
1380 if (edid == NULL)
1381 edid = intel_sdvo_get_analog_edid(connector);
1382 if (edid != NULL) {
52220085
CW		 1383 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1384 edid))
13946743 1385 ret = connector_status_connected;
52220085
CW		 1386 else
1387 ret = connector_status_disconnected;
1388
13946743
CW		 1389 connector->display_info.raw_edid = NULL;
1390 kfree(edid);
1391 } else
1392 ret = connector_status_connected;
1393 }
14571b4c
ZW		 1394
1395 /* May update encoder flag for like clock for SDVO TV, etc.*/
1396 if (ret == connector_status_connected) {
ea5b213a
CW		 1397 intel_sdvo->is_tv = false;
1398 intel_sdvo->is_lvds = false;
1399 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1400
1401 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1402 intel_sdvo->is_tv = true;
1403 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1404 }
1405 if (response & SDVO_LVDS_MASK)
8545423a 1406 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1407 }
14571b4c
ZW		 1408
1409 return ret;
79e53945
JB		 1410}
1411
e2f0ba97 1412static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1413{
ff482d83 1414 struct edid *edid;
79e53945
JB		 1415
1416 /* set the bus switch and get the modes */
e957d772 1417 edid = intel_sdvo_get_edid(connector);
79e53945 1418
57cdaf90
KP		 1419 /*
1420 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1421 * link between analog and digital outputs. So, if the regular SDVO
1422 * DDC fails, check to see if the analog output is disconnected, in
1423 * which case we'll look there for the digital DDC data.
e2f0ba97 1424 */
f899fc64
CW		 1425 if (edid == NULL)
1426 edid = intel_sdvo_get_analog_edid(connector);
1427
ff482d83 1428 if (edid != NULL) {
52220085
CW		 1429 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1430 edid)) {
0c1dab89
CW		 1431 drm_mode_connector_update_edid_property(connector, edid);
1432 drm_add_edid_modes(connector, edid);
1433 }
13946743 1434
ff482d83
CW		 1435 connector->display_info.raw_edid = NULL;
1436 kfree(edid);
e2f0ba97 1437 }
e2f0ba97
JB		 1438}
1439
1440/*
1441 * Set of SDVO TV modes.
1442 * Note! This is in reply order (see loop in get_tv_modes).
1443 * XXX: all 60Hz refresh?
1444 */
b1f559ec 1445static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1446 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1447 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1449 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1450 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1452 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1453 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1455 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1456 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1458 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1459 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1461 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1462 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1464 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1465 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1467 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1468 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1470 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1471 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1473 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1474 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1476 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1477 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1479 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1480 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1482 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1483 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1485 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1486 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1488 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1489 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1491 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1492 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1494 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1495 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1497 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1498 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1500 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1501 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1503};
1504
1505static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1506{
df0e9248 1507 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1508 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1509 uint32_t reply = 0, format_map = 0;
1510 int i;
e2f0ba97
JB		 1511
1512 /* Read the list of supported input resolutions for the selected TV
1513 * format.
1514 */
40039750 1515 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1516 memcpy(&tv_res, &format_map,
32aad86f 1517 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1518
32aad86f
CW		 1519 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1520 return;
ce6feabd 1521
32aad86f 1522 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1523 if (!intel_sdvo_write_cmd(intel_sdvo,
1524 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1525 &tv_res, sizeof(tv_res)))
1526 return;
1527 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1528 return;
1529
1530 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1531 if (reply & (1 << i)) {
1532 struct drm_display_mode *nmode;
1533 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1534 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1535 if (nmode)
1536 drm_mode_probed_add(connector, nmode);
1537 }
e2f0ba97
JB		 1538}
1539
7086c87f
ML		 1540static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1541{
df0e9248 1542 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1543 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1544 struct drm_display_mode *newmode;
7086c87f
ML		 1545
1546 /*
1547 * Attempt to get the mode list from DDC.
1548 * Assume that the preferred modes are
1549 * arranged in priority order.
1550 */
f899fc64 1551 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1552 if (list_empty(&connector->probed_modes) == false)
12682a97 1553 goto end;
7086c87f
ML		 1554
1555 /* Fetch modes from VBT */
1556 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1557 newmode = drm_mode_duplicate(connector->dev,
1558 dev_priv->sdvo_lvds_vbt_mode);
1559 if (newmode != NULL) {
1560 /* Guarantee the mode is preferred */
1561 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1562 DRM_MODE_TYPE_DRIVER);
1563 drm_mode_probed_add(connector, newmode);
1564 }
1565 }
12682a97 1566
1567end:
1568 list_for_each_entry(newmode, &connector->probed_modes, head) {
1569 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1570 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1571 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1572
1573 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1574 0);
1575
8545423a 1576 intel_sdvo->is_lvds = true;
12682a97 1577 break;
1578 }
1579 }
1580
7086c87f
ML		 1581}
1582
e2f0ba97
JB		 1583static int intel_sdvo_get_modes(struct drm_connector *connector)
1584{
615fb93f 1585 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1586
615fb93f 1587 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1588 intel_sdvo_get_tv_modes(connector);
615fb93f 1589 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1590 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1591 else
1592 intel_sdvo_get_ddc_modes(connector);
1593
32aad86f 1594 return !list_empty(&connector->probed_modes);
79e53945
JB		 1595}
1596
fcc8d672
CW		 1597static void
1598intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1599{
615fb93f 1600 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1601 struct drm_device *dev = connector->dev;
1602
c5521706
CW		 1603 if (intel_sdvo_connector->left)
1604 drm_property_destroy(dev, intel_sdvo_connector->left);
1605 if (intel_sdvo_connector->right)
1606 drm_property_destroy(dev, intel_sdvo_connector->right);
1607 if (intel_sdvo_connector->top)
1608 drm_property_destroy(dev, intel_sdvo_connector->top);
1609 if (intel_sdvo_connector->bottom)
1610 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1611 if (intel_sdvo_connector->hpos)
1612 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1613 if (intel_sdvo_connector->vpos)
1614 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1615 if (intel_sdvo_connector->saturation)
1616 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1617 if (intel_sdvo_connector->contrast)
1618 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1619 if (intel_sdvo_connector->hue)
1620 drm_property_destroy(dev, intel_sdvo_connector->hue);
1621 if (intel_sdvo_connector->sharpness)
1622 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1623 if (intel_sdvo_connector->flicker_filter)
1624 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1625 if (intel_sdvo_connector->flicker_filter_2d)
1626 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1627 if (intel_sdvo_connector->flicker_filter_adaptive)
1628 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1629 if (intel_sdvo_connector->tv_luma_filter)
1630 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1631 if (intel_sdvo_connector->tv_chroma_filter)
1632 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1633 if (intel_sdvo_connector->dot_crawl)
1634 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1635 if (intel_sdvo_connector->brightness)
1636 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1637}
1638
79e53945
JB		 1639static void intel_sdvo_destroy(struct drm_connector *connector)
1640{
615fb93f 1641 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1642
c5521706 1643 if (intel_sdvo_connector->tv_format)
ce6feabd 1644 drm_property_destroy(connector->dev,
c5521706 1645 intel_sdvo_connector->tv_format);
b9219c5e 1646
d2a82a6f 1647 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1648 drm_sysfs_connector_remove(connector);
1649 drm_connector_cleanup(connector);
d2a82a6f 1650 kfree(connector);
79e53945
JB		 1651}
1652
1aad7ac0
CW		 1653static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1654{
1655 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1656 struct edid *edid;
1657 bool has_audio = false;
1658
1659 if (!intel_sdvo->is_hdmi)
1660 return false;
1661
1662 edid = intel_sdvo_get_edid(connector);
1663 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1664 has_audio = drm_detect_monitor_audio(edid);
1665
1666 return has_audio;
1667}
1668
ce6feabd
ZY		 1669static int
1670intel_sdvo_set_property(struct drm_connector *connector,
1671 struct drm_property *property,
1672 uint64_t val)
1673{
df0e9248 1674 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1675 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1676 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1677 uint16_t temp_value;
32aad86f
CW		 1678 uint8_t cmd;
1679 int ret;
ce6feabd
ZY		 1680
1681 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1682 if (ret)
1683 return ret;
ce6feabd 1684
3f43c48d 1685 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1686 int i = val;
1687 bool has_audio;
1688
1689 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1690 return 0;
1691
1aad7ac0 1692 intel_sdvo_connector->force_audio = i;
7f36e7ed 1693
c3e5f67b 1694 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1695 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1696 else
c3e5f67b 1697 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1698
1aad7ac0 1699 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1700 return 0;
7f36e7ed 1701
1aad7ac0 1702 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1703 goto done;
1704 }
1705
e953fd7b
CW		 1706 if (property == dev_priv->broadcast_rgb_property) {
1707 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1708 return 0;
1709
e953fd7b 1710 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1711 goto done;
1712 }
1713
c5521706
CW		 1714#define CHECK_PROPERTY(name, NAME) \
1715 if (intel_sdvo_connector->name == property) { \
1716 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1717 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1718 cmd = SDVO_CMD_SET_##NAME; \
1719 intel_sdvo_connector->cur_##name = temp_value; \
1720 goto set_value; \
1721 }
1722
1723 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1724 if (val >= TV_FORMAT_NUM)
1725 return -EINVAL;
1726
40039750 1727 if (intel_sdvo->tv_format_index ==
615fb93f 1728 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1729 return 0;
ce6feabd 1730
40039750 1731 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1732 goto done;
32aad86f 1733 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1734 temp_value = val;
c5521706 1735 if (intel_sdvo_connector->left == property) {
b9219c5e 1736 drm_connector_property_set_value(connector,
c5521706 1737 intel_sdvo_connector->right, val);
615fb93f 1738 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1739 return 0;
b9219c5e 1740
615fb93f
CW		 1741 intel_sdvo_connector->left_margin = temp_value;
1742 intel_sdvo_connector->right_margin = temp_value;
1743 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1744 intel_sdvo_connector->left_margin;
b9219c5e 1745 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1746 goto set_value;
1747 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1748 drm_connector_property_set_value(connector,
c5521706 1749 intel_sdvo_connector->left, val);
615fb93f 1750 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1751 return 0;
b9219c5e 1752
615fb93f
CW		 1753 intel_sdvo_connector->left_margin = temp_value;
1754 intel_sdvo_connector->right_margin = temp_value;
1755 temp_value = intel_sdvo_connector->max_hscan -
1756 intel_sdvo_connector->left_margin;
b9219c5e 1757 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1758 goto set_value;
1759 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1760 drm_connector_property_set_value(connector,
c5521706 1761 intel_sdvo_connector->bottom, val);
615fb93f 1762 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1763 return 0;
b9219c5e 1764
615fb93f
CW		 1765 intel_sdvo_connector->top_margin = temp_value;
1766 intel_sdvo_connector->bottom_margin = temp_value;
1767 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1768 intel_sdvo_connector->top_margin;
b9219c5e 1769 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1770 goto set_value;
1771 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1772 drm_connector_property_set_value(connector,
c5521706 1773 intel_sdvo_connector->top, val);
615fb93f 1774 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1775 return 0;
1776
615fb93f
CW		 1777 intel_sdvo_connector->top_margin = temp_value;
1778 intel_sdvo_connector->bottom_margin = temp_value;
1779 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1780 intel_sdvo_connector->top_margin;
b9219c5e 1781 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1782 goto set_value;
1783 }
1784 CHECK_PROPERTY(hpos, HPOS)
1785 CHECK_PROPERTY(vpos, VPOS)
1786 CHECK_PROPERTY(saturation, SATURATION)
1787 CHECK_PROPERTY(contrast, CONTRAST)
1788 CHECK_PROPERTY(hue, HUE)
1789 CHECK_PROPERTY(brightness, BRIGHTNESS)
1790 CHECK_PROPERTY(sharpness, SHARPNESS)
1791 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1792 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1793 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1794 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1795 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1796 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1797 }
b9219c5e 1798
c5521706 1799 return -EINVAL; /* unknown property */
b9219c5e 1800
c5521706
CW		 1801set_value:
1802 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1803 return -EIO;
b9219c5e 1804
b9219c5e 1805
c5521706 1806done:
df0e9248
CW		 1807 if (intel_sdvo->base.base.crtc) {
1808 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1809 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1810 crtc->y, crtc->fb);
1811 }
1812
32aad86f 1813 return 0;
c5521706 1814#undef CHECK_PROPERTY
ce6feabd
ZY		 1815}
1816
79e53945
JB		 1817static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1818 .dpms = intel_sdvo_dpms,
1819 .mode_fixup = intel_sdvo_mode_fixup,
1820 .prepare = intel_encoder_prepare,
1821 .mode_set = intel_sdvo_mode_set,
1822 .commit = intel_encoder_commit,
1823};
1824
1825static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1826 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1827 .detect = intel_sdvo_detect,
1828 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1829 .set_property = intel_sdvo_set_property,
79e53945
JB		 1830 .destroy = intel_sdvo_destroy,
1831};
1832
1833static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1834 .get_modes = intel_sdvo_get_modes,
1835 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1836 .best_encoder = intel_best_encoder,
79e53945
JB		 1837};
1838
b358d0a6 1839static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1840{
890f3359 1841 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1842
ea5b213a 1843 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1844 drm_mode_destroy(encoder->dev,
ea5b213a 1845 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1846
e957d772 1847 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1848 intel_encoder_destroy(encoder);
79e53945
JB		 1849}
1850
1851static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1852 .destroy = intel_sdvo_enc_destroy,
1853};
1854
b66d8424
CW		 1855static void
1856intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1857{
1858 uint16_t mask = 0;
1859 unsigned int num_bits;
1860
1861 /* Make a mask of outputs less than or equal to our own priority in the
1862 * list.
1863 */
1864 switch (sdvo->controlled_output) {
1865 case SDVO_OUTPUT_LVDS1:
1866 mask |= SDVO_OUTPUT_LVDS1;
1867 case SDVO_OUTPUT_LVDS0:
1868 mask |= SDVO_OUTPUT_LVDS0;
1869 case SDVO_OUTPUT_TMDS1:
1870 mask |= SDVO_OUTPUT_TMDS1;
1871 case SDVO_OUTPUT_TMDS0:
1872 mask |= SDVO_OUTPUT_TMDS0;
1873 case SDVO_OUTPUT_RGB1:
1874 mask |= SDVO_OUTPUT_RGB1;
1875 case SDVO_OUTPUT_RGB0:
1876 mask |= SDVO_OUTPUT_RGB0;
1877 break;
1878 }
1879
1880 /* Count bits to find what number we are in the priority list. */
1881 mask &= sdvo->caps.output_flags;
1882 num_bits = hweight16(mask);
1883 /* If more than 3 outputs, default to DDC bus 3 for now. */
1884 if (num_bits > 3)
1885 num_bits = 3;
1886
1887 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1888 sdvo->ddc_bus = 1 << num_bits;
1889}
79e53945 1890
e2f0ba97
JB		 1891/**
1892 * Choose the appropriate DDC bus for control bus switch command for this
1893 * SDVO output based on the controlled output.
1894 *
1895 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1896 * outputs, then LVDS outputs.
1897 */
1898static void
b1083333 1899intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1900 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1901{
b1083333 1902 struct sdvo_device_mapping *mapping;
e2f0ba97 1903
b1083333
AJ		 1904 if (IS_SDVOB(reg))
1905 mapping = &(dev_priv->sdvo_mappings[0]);
1906 else
1907 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1908
b66d8424
CW		 1909 if (mapping->initialized)
1910 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1911 else
1912 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1913}
1914
e957d772
CW		 1915static void
1916intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1917 struct intel_sdvo *sdvo, u32 reg)
1918{
1919 struct sdvo_device_mapping *mapping;
46eb3036 1920 u8 pin;
e957d772
CW		 1921
1922 if (IS_SDVOB(reg))
1923 mapping = &dev_priv->sdvo_mappings[0];
1924 else
1925 mapping = &dev_priv->sdvo_mappings[1];
1926
1927 pin = GMBUS_PORT_DPB;
46eb3036 1928 if (mapping->initialized)
e957d772 1929 pin = mapping->i2c_pin;
e957d772 1930
63abf3ed
CW		 1931 if (pin < GMBUS_NUM_PORTS) {
1932 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
d5090b96 1933 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1934 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1935 } else {
63abf3ed 1936 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
46eb3036 1937 }
e957d772
CW		 1938}
1939
e2f0ba97 1940static bool
e27d8538 1941intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1942{
97aaf910 1943 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1944}
1945
714605e4 1946static u8
c751ce4f 1947intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 1948{
1949 struct drm_i915_private *dev_priv = dev->dev_private;
1950 struct sdvo_device_mapping *my_mapping, *other_mapping;
1951
461ed3ca 1952 if (IS_SDVOB(sdvo_reg)) {
714605e4 1953 my_mapping = &dev_priv->sdvo_mappings[0];
1954 other_mapping = &dev_priv->sdvo_mappings[1];
1955 } else {
1956 my_mapping = &dev_priv->sdvo_mappings[1];
1957 other_mapping = &dev_priv->sdvo_mappings[0];
1958 }
1959
1960 /* If the BIOS described our SDVO device, take advantage of it. */
1961 if (my_mapping->slave_addr)
1962 return my_mapping->slave_addr;
1963
1964 /* If the BIOS only described a different SDVO device, use the
1965 * address that it isn't using.
1966 */
1967 if (other_mapping->slave_addr) {
1968 if (other_mapping->slave_addr == 0x70)
1969 return 0x72;
1970 else
1971 return 0x70;
1972 }
1973
1974 /* No SDVO device info is found for another DVO port,
1975 * so use mapping assumption we had before BIOS parsing.
1976 */
461ed3ca 1977 if (IS_SDVOB(sdvo_reg))
714605e4 1978 return 0x70;
1979 else
1980 return 0x72;
1981}
1982
14571b4c 1983static void
df0e9248
CW		 1984intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
1985 struct intel_sdvo *encoder)
14571b4c 1986{
df0e9248
CW		 1987 drm_connector_init(encoder->base.base.dev,
1988 &connector->base.base,
1989 &intel_sdvo_connector_funcs,
1990 connector->base.base.connector_type);
6070a4a9 1991
df0e9248
CW		 1992 drm_connector_helper_add(&connector->base.base,
1993 &intel_sdvo_connector_helper_funcs);
14571b4c 1994
8f4839e2 1995 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 1996 connector->base.base.doublescan_allowed = 0;
1997 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 1998
df0e9248
CW		 1999 intel_connector_attach_encoder(&connector->base, &encoder->base);
2000 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2001}
6070a4a9 2002
7f36e7ed
CW		 2003static void
2004intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2005{
2006 struct drm_device *dev = connector->base.base.dev;
2007
3f43c48d 2008 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2009 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2010 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2011}
2012
fb7a46f3 2013static bool
ea5b213a 2014intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2015{
4ef69c7a 2016 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2017 struct drm_connector *connector;
cc68c81a 2018 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2019 struct intel_connector *intel_connector;
615fb93f 2020 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2021
615fb93f
CW		 2022 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2023 if (!intel_sdvo_connector)
14571b4c
ZW		 2024 return false;
2025
14571b4c 2026 if (device == 0) {
ea5b213a 2027 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2028 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2029 } else if (device == 1) {
ea5b213a 2030 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2031 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2032 }
2033
615fb93f 2034 intel_connector = &intel_sdvo_connector->base;
14571b4c 2035 connector = &intel_connector->base;
cc68c81a
SF		 2036 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2037 connector->polled = DRM_CONNECTOR_POLL_HPD;
2038 intel_sdvo->hotplug_active[0] |= 1 << device;
2039 /* Some SDVO devices have one-shot hotplug interrupts.
2040 * Ensure that they get re-enabled when an interrupt happens.
2041 */
2042 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2043 intel_sdvo_enable_hotplug(intel_encoder);
2044 }
2045 else
2046 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2047 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2048 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2049
e27d8538 2050 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2051 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2052 intel_sdvo->is_hdmi = true;
14571b4c 2053 }
ea5b213a
CW		 2054 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2055 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2056
df0e9248 2057 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2058 if (intel_sdvo->is_hdmi)
2059 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2060
2061 return true;
2062}
2063
2064static bool
ea5b213a 2065intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2066{
4ef69c7a
CW		 2067 struct drm_encoder *encoder = &intel_sdvo->base.base;
2068 struct drm_connector *connector;
2069 struct intel_connector *intel_connector;
2070 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2071
615fb93f
CW		 2072 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2073 if (!intel_sdvo_connector)
2074 return false;
14571b4c 2075
615fb93f 2076 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2077 connector = &intel_connector->base;
2078 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2079 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2080
4ef69c7a
CW		 2081 intel_sdvo->controlled_output |= type;
2082 intel_sdvo_connector->output_flag = type;
14571b4c 2083
4ef69c7a
CW		 2084 intel_sdvo->is_tv = true;
2085 intel_sdvo->base.needs_tv_clock = true;
2086 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2087
df0e9248 2088 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2089
4ef69c7a 2090 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2091 goto err;
14571b4c 2092
4ef69c7a 2093 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2094 goto err;
14571b4c 2095
4ef69c7a 2096 return true;
32aad86f
CW		 2097
2098err:
123d5c01 2099 intel_sdvo_destroy(connector);
32aad86f 2100 return false;
14571b4c
ZW		 2101}
2102
2103static bool
ea5b213a 2104intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2105{
4ef69c7a
CW		 2106 struct drm_encoder *encoder = &intel_sdvo->base.base;
2107 struct drm_connector *connector;
2108 struct intel_connector *intel_connector;
2109 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2110
615fb93f
CW		 2111 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2112 if (!intel_sdvo_connector)
2113 return false;
14571b4c 2114
615fb93f 2115 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2116 connector = &intel_connector->base;
eb1f8e4f 2117 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2118 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2119 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2120
2121 if (device == 0) {
2122 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2123 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2124 } else if (device == 1) {
2125 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2126 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2127 }
2128
2129 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2130 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2131
df0e9248
CW		 2132 intel_sdvo_connector_init(intel_sdvo_connector,
2133 intel_sdvo);
4ef69c7a 2134 return true;
14571b4c
ZW		 2135}
2136
2137static bool
ea5b213a 2138intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2139{
4ef69c7a
CW		 2140 struct drm_encoder *encoder = &intel_sdvo->base.base;
2141 struct drm_connector *connector;
2142 struct intel_connector *intel_connector;
2143 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2144
615fb93f
CW		 2145 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2146 if (!intel_sdvo_connector)
2147 return false;
14571b4c 2148
615fb93f
CW		 2149 intel_connector = &intel_sdvo_connector->base;
2150 connector = &intel_connector->base;
4ef69c7a
CW		 2151 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2152 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2153
2154 if (device == 0) {
2155 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2156 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2157 } else if (device == 1) {
2158 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2159 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2160 }
2161
2162 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2163 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2164
df0e9248 2165 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2166 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2167 goto err;
2168
2169 return true;
2170
2171err:
123d5c01 2172 intel_sdvo_destroy(connector);
32aad86f 2173 return false;
14571b4c
ZW		 2174}
2175
2176static bool
ea5b213a 2177intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2178{
ea5b213a
CW		 2179 intel_sdvo->is_tv = false;
2180 intel_sdvo->base.needs_tv_clock = false;
2181 intel_sdvo->is_lvds = false;
fb7a46f3 2182
14571b4c 2183 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2184
14571b4c 2185 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2186 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2187 return false;
2188
2189 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2190 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2191 return false;
2192
2193 /* TV has no XXX1 function block */
a1f4b7ff 2194 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2195 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2196 return false;
2197
2198 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2199 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2200 return false;
fb7a46f3 2201
14571b4c 2202 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2203 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2204 return false;
2205
2206 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2207 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2208 return false;
2209
2210 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2211 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2212 return false;
2213
2214 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2215 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2216 return false;
fb7a46f3 2217
14571b4c 2218 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2219 unsigned char bytes[2];
2220
ea5b213a
CW		 2221 intel_sdvo->controlled_output = 0;
2222 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2223 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2224 SDVO_NAME(intel_sdvo),
51c8b407 2225 bytes[0], bytes[1]);
14571b4c 2226 return false;
fb7a46f3 2227 }
27f8227b 2228 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2229
14571b4c 2230 return true;
fb7a46f3 2231}
2232
32aad86f
CW		 2233static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2234 struct intel_sdvo_connector *intel_sdvo_connector,
2235 int type)
ce6feabd 2236{
4ef69c7a 2237 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2238 struct intel_sdvo_tv_format format;
2239 uint32_t format_map, i;
ce6feabd 2240
32aad86f
CW		 2241 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2242 return false;
ce6feabd 2243
1a3665c8 2244 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2245 if (!intel_sdvo_get_value(intel_sdvo,
2246 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2247 &format, sizeof(format)))
2248 return false;
ce6feabd 2249
32aad86f 2250 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2251
2252 if (format_map == 0)
32aad86f 2253 return false;
ce6feabd 2254
615fb93f 2255 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2256 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2257 if (format_map & (1 << i))
2258 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2259
2260
c5521706 2261 intel_sdvo_connector->tv_format =
32aad86f
CW		 2262 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2263 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2264 if (!intel_sdvo_connector->tv_format)
fcc8d672 2265 return false;
ce6feabd 2266
615fb93f 2267 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2268 drm_property_add_enum(
c5521706 2269 intel_sdvo_connector->tv_format, i,
40039750 2270 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2271
40039750 2272 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2273 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2274 intel_sdvo_connector->tv_format, 0);
32aad86f 2275 return true;
ce6feabd
ZY		 2276
2277}
2278
c5521706
CW		 2279#define ENHANCEMENT(name, NAME) do { \
2280 if (enhancements.name) { \
2281 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2282 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2283 return false; \
2284 intel_sdvo_connector->max_##name = data_value[0]; \
2285 intel_sdvo_connector->cur_##name = response; \
2286 intel_sdvo_connector->name = \
d9bc3c02 2287 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2288 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2289 drm_connector_attach_property(connector, \
2290 intel_sdvo_connector->name, \
2291 intel_sdvo_connector->cur_##name); \
2292 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2293 data_value[0], data_value[1], response); \
2294 } \
0206e353 2295} while (0)
c5521706
CW		 2296
2297static bool
2298intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2299 struct intel_sdvo_connector *intel_sdvo_connector,
2300 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2301{
4ef69c7a 2302 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2303 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2304 uint16_t response, data_value[2];
2305
c5521706
CW		 2306 /* when horizontal overscan is supported, Add the left/right property */
2307 if (enhancements.overscan_h) {
2308 if (!intel_sdvo_get_value(intel_sdvo,
2309 SDVO_CMD_GET_MAX_OVERSCAN_H,
2310 &data_value, 4))
2311 return false;
32aad86f 2312
c5521706
CW		 2313 if (!intel_sdvo_get_value(intel_sdvo,
2314 SDVO_CMD_GET_OVERSCAN_H,
2315 &response, 2))
2316 return false;
fcc8d672 2317
c5521706
CW		 2318 intel_sdvo_connector->max_hscan = data_value[0];
2319 intel_sdvo_connector->left_margin = data_value[0] - response;
2320 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2321 intel_sdvo_connector->left =
d9bc3c02 2322 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2323 if (!intel_sdvo_connector->left)
2324 return false;
fcc8d672 2325
c5521706
CW		 2326 drm_connector_attach_property(connector,
2327 intel_sdvo_connector->left,
2328 intel_sdvo_connector->left_margin);
fcc8d672 2329
c5521706 2330 intel_sdvo_connector->right =
d9bc3c02 2331 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2332 if (!intel_sdvo_connector->right)
2333 return false;
32aad86f 2334
c5521706
CW		 2335 drm_connector_attach_property(connector,
2336 intel_sdvo_connector->right,
2337 intel_sdvo_connector->right_margin);
2338 DRM_DEBUG_KMS("h_overscan: max %d, "
2339 "default %d, current %d\n",
2340 data_value[0], data_value[1], response);
2341 }
32aad86f 2342
c5521706
CW		 2343 if (enhancements.overscan_v) {
2344 if (!intel_sdvo_get_value(intel_sdvo,
2345 SDVO_CMD_GET_MAX_OVERSCAN_V,
2346 &data_value, 4))
2347 return false;
fcc8d672 2348
c5521706
CW		 2349 if (!intel_sdvo_get_value(intel_sdvo,
2350 SDVO_CMD_GET_OVERSCAN_V,
2351 &response, 2))
2352 return false;
32aad86f 2353
c5521706
CW		 2354 intel_sdvo_connector->max_vscan = data_value[0];
2355 intel_sdvo_connector->top_margin = data_value[0] - response;
2356 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2357 intel_sdvo_connector->top =
d9bc3c02
SH		 2358 drm_property_create_range(dev, 0,
2359 "top_margin", 0, data_value[0]);
c5521706
CW		 2360 if (!intel_sdvo_connector->top)
2361 return false;
32aad86f 2362
c5521706
CW		 2363 drm_connector_attach_property(connector,
2364 intel_sdvo_connector->top,
2365 intel_sdvo_connector->top_margin);
fcc8d672 2366
c5521706 2367 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2368 drm_property_create_range(dev, 0,
2369 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2370 if (!intel_sdvo_connector->bottom)
2371 return false;
32aad86f 2372
c5521706
CW		 2373 drm_connector_attach_property(connector,
2374 intel_sdvo_connector->bottom,
2375 intel_sdvo_connector->bottom_margin);
2376 DRM_DEBUG_KMS("v_overscan: max %d, "
2377 "default %d, current %d\n",
2378 data_value[0], data_value[1], response);
2379 }
32aad86f 2380
c5521706
CW		 2381 ENHANCEMENT(hpos, HPOS);
2382 ENHANCEMENT(vpos, VPOS);
2383 ENHANCEMENT(saturation, SATURATION);
2384 ENHANCEMENT(contrast, CONTRAST);
2385 ENHANCEMENT(hue, HUE);
2386 ENHANCEMENT(sharpness, SHARPNESS);
2387 ENHANCEMENT(brightness, BRIGHTNESS);
2388 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2389 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2390 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2391 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2392 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2393
e044218a
CW		 2394 if (enhancements.dot_crawl) {
2395 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2396 return false;
2397
2398 intel_sdvo_connector->max_dot_crawl = 1;
2399 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2400 intel_sdvo_connector->dot_crawl =
d9bc3c02 2401 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2402 if (!intel_sdvo_connector->dot_crawl)
2403 return false;
2404
e044218a
CW		 2405 drm_connector_attach_property(connector,
2406 intel_sdvo_connector->dot_crawl,
2407 intel_sdvo_connector->cur_dot_crawl);
2408 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2409 }
2410
c5521706
CW		 2411 return true;
2412}
32aad86f 2413
c5521706
CW		 2414static bool
2415intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2416 struct intel_sdvo_connector *intel_sdvo_connector,
2417 struct intel_sdvo_enhancements_reply enhancements)
2418{
4ef69c7a 2419 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2420 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2421 uint16_t response, data_value[2];
32aad86f 2422
c5521706 2423 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2424
c5521706
CW		 2425 return true;
2426}
2427#undef ENHANCEMENT
32aad86f 2428
c5521706
CW		 2429static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2430 struct intel_sdvo_connector *intel_sdvo_connector)
2431{
2432 union {
2433 struct intel_sdvo_enhancements_reply reply;
2434 uint16_t response;
2435 } enhancements;
32aad86f 2436
1a3665c8
CW		 2437 BUILD_BUG_ON(sizeof(enhancements) != 2);
2438
cf9a2f3a
CW		 2439 enhancements.response = 0;
2440 intel_sdvo_get_value(intel_sdvo,
2441 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2442 &enhancements, sizeof(enhancements));
c5521706
CW		 2443 if (enhancements.response == 0) {
2444 DRM_DEBUG_KMS("No enhancement is supported\n");
2445 return true;
b9219c5e 2446 }
32aad86f 2447
c5521706
CW		 2448 if (IS_TV(intel_sdvo_connector))
2449 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2450 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2451 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2452 else
2453 return true;
e957d772
CW		 2454}
2455
2456static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2457 struct i2c_msg *msgs,
2458 int num)
2459{
2460 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2461
e957d772
CW		 2462 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2463 return -EIO;
2464
2465 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2466}
2467
2468static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2469{
2470 struct intel_sdvo *sdvo = adapter->algo_data;
2471 return sdvo->i2c->algo->functionality(sdvo->i2c);
2472}
2473
2474static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2475 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2476 .functionality = intel_sdvo_ddc_proxy_func
2477};
2478
2479static bool
2480intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2481 struct drm_device *dev)
2482{
2483 sdvo->ddc.owner = THIS_MODULE;
2484 sdvo->ddc.class = I2C_CLASS_DDC;
2485 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2486 sdvo->ddc.dev.parent = &dev->pdev->dev;
2487 sdvo->ddc.algo_data = sdvo;
2488 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2489
2490 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2491}
2492
c751ce4f 2493bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2494{
b01f2c3a 2495 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2496 struct intel_encoder *intel_encoder;
ea5b213a 2497 struct intel_sdvo *intel_sdvo;
79e53945 2498 int i;
79e53945 2499
ea5b213a
CW		 2500 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2501 if (!intel_sdvo)
7d57382e 2502 return false;
79e53945 2503
56184e3d
CW		 2504 intel_sdvo->sdvo_reg = sdvo_reg;
2505 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2506 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2507 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2508 kfree(intel_sdvo);
2509 return false;
2510 }
2511
56184e3d 2512 /* encoder type will be decided later */
ea5b213a 2513 intel_encoder = &intel_sdvo->base;
21d40d37 2514 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2515 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2516
79e53945
JB		 2517 /* Read the regs to test if we can talk to the device */
2518 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2519 u8 byte;
2520
2521 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
8a4c47f3 2522 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2523 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2524 goto err;
79e53945
JB		 2525 }
2526 }
2527
f899fc64 2528 if (IS_SDVOB(sdvo_reg))
b01f2c3a 2529 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2530 else
b01f2c3a 2531 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2532
4ef69c7a 2533 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2534
af901ca1 2535 /* In default case sdvo lvds is false */
32aad86f 2536 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2537 goto err;
79e53945 2538
cc68c81a
SF		 2539 /* Set up hotplug command - note paranoia about contents of reply.
2540 * We assume that the hardware is in a sane state, and only touch
2541 * the bits we think we understand.
2542 */
2543 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2544 &intel_sdvo->hotplug_active, 2);
2545 intel_sdvo->hotplug_active[0] &= ~0x3;
2546
ea5b213a
CW		 2547 if (intel_sdvo_output_setup(intel_sdvo,
2548 intel_sdvo->caps.output_flags) != true) {
51c8b407 2549 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2550 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2551 goto err;
79e53945
JB		 2552 }
2553
ea5b213a 2554 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2555
79e53945 2556 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2557 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2558 goto err;
79e53945 2559
32aad86f
CW		 2560 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2561 &intel_sdvo->pixel_clock_min,
2562 &intel_sdvo->pixel_clock_max))
f899fc64 2563 goto err;
79e53945 2564
8a4c47f3 2565 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2566 "clock range %dMHz - %dMHz, "
2567 "input 1: %c, input 2: %c, "
2568 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2569 SDVO_NAME(intel_sdvo),
2570 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2571 intel_sdvo->caps.device_rev_id,
2572 intel_sdvo->pixel_clock_min / 1000,
2573 intel_sdvo->pixel_clock_max / 1000,
2574 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2575 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2576 /* check currently supported outputs */
ea5b213a 2577 intel_sdvo->caps.output_flags &
79e53945 2578 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2579 intel_sdvo->caps.output_flags &
79e53945 2580 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2581 return true;
79e53945 2582
f899fc64 2583err:
373a3cf7 2584 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2585 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2586 kfree(intel_sdvo);
79e53945 2587
7d57382e 2588 return false;
79e53945 2589}
Linux kernel - Deliverables
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