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drm/i915/sdvo: Poll command status 5 times without delay on read
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 51
79e53945 52
2e88e40b 53static const char *tv_format_names[] = {
ce6feabd
ZY		 54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61};
62
63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
ea5b213a
CW		 65struct intel_sdvo {
66 struct intel_encoder base;
67
f9c10a9b 68 u8 slave_addr;
e2f0ba97
JB		 69
70 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 71 int sdvo_reg;
79e53945 72
e2f0ba97
JB		 73 /* Active outputs controlled by this SDVO output */
74 uint16_t controlled_output;
79e53945 75
e2f0ba97
JB		 76 /*
77 * Capabilities of the SDVO device returned by
78 * i830_sdvo_get_capabilities()
79 */
79e53945 80 struct intel_sdvo_caps caps;
e2f0ba97
JB		 81
82 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 83 int pixel_clock_min, pixel_clock_max;
84
fb7a46f3 85 /*
86 * For multiple function SDVO device,
87 * this is for current attached outputs.
88 */
89 uint16_t attached_output;
90
e2f0ba97
JB		 91 /**
92 * This is set if we're going to treat the device as TV-out.
93 *
94 * While we have these nice friendly flags for output types that ought
95 * to decide this for us, the S-Video output on our HDMI+S-Video card
96 * shows up as RGB1 (VGA).
97 */
98 bool is_tv;
99
ce6feabd 100 /* This is for current tv format name */
40039750 101 int tv_format_index;
ce6feabd 102
e2f0ba97
JB		 103 /**
104 * This is set if we treat the device as HDMI, instead of DVI.
105 */
106 bool is_hdmi;
12682a97 107
7086c87f 108 /**
6c9547ff
CW		 109 * This is set if we detect output of sdvo device as LVDS and
110 * have a valid fixed mode to use with the panel.
7086c87f
ML		 111 */
112 bool is_lvds;
e2f0ba97 113
12682a97 114 /**
115 * This is sdvo fixed pannel mode pointer
116 */
117 struct drm_display_mode *sdvo_lvds_fixed_mode;
118
e2f0ba97
JB		 119 /*
120 * supported encoding mode, used to determine whether HDMI is
121 * supported
122 */
123 struct intel_sdvo_encode encode;
124
c751ce4f 125 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 126 uint8_t ddc_bus;
127
57cdaf90
KP		 128 /* Mac mini hack -- use the same DDC as the analog connector */
129 struct i2c_adapter *analog_ddc_bus;
130
6c9547ff
CW		 131 /* Input timings for adjusted_mode */
132 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 133};
134
135struct intel_sdvo_connector {
615fb93f
CW		 136 struct intel_connector base;
137
14571b4c
ZW		 138 /* Mark the type of connector */
139 uint16_t output_flag;
140
141 /* This contains all current supported TV format */
40039750 142 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 143 int format_supported_num;
c5521706 144 struct drm_property *tv_format;
14571b4c 145
b9219c5e 146 /* add the property for the SDVO-TV */
c5521706
CW		 147 struct drm_property *left;
148 struct drm_property *right;
149 struct drm_property *top;
150 struct drm_property *bottom;
151 struct drm_property *hpos;
152 struct drm_property *vpos;
153 struct drm_property *contrast;
154 struct drm_property *saturation;
155 struct drm_property *hue;
156 struct drm_property *sharpness;
157 struct drm_property *flicker_filter;
158 struct drm_property *flicker_filter_adaptive;
159 struct drm_property *flicker_filter_2d;
160 struct drm_property *tv_chroma_filter;
161 struct drm_property *tv_luma_filter;
e044218a 162 struct drm_property *dot_crawl;
b9219c5e
ZY		 163
164 /* add the property for the SDVO-TV/LVDS */
c5521706 165 struct drm_property *brightness;
b9219c5e
ZY		 166
167 /* Add variable to record current setting for the above property */
168 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 169
b9219c5e
ZY		 170 /* this is to get the range of margin.*/
171 u32 max_hscan, max_vscan;
172 u32 max_hpos, cur_hpos;
173 u32 max_vpos, cur_vpos;
174 u32 cur_brightness, max_brightness;
175 u32 cur_contrast, max_contrast;
176 u32 cur_saturation, max_saturation;
177 u32 cur_hue, max_hue;
c5521706
CW		 178 u32 cur_sharpness, max_sharpness;
179 u32 cur_flicker_filter, max_flicker_filter;
180 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
181 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
182 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
183 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 184 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 185};
186
ea5b213a
CW		 187static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
188{
4ef69c7a 189 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 190}
191
df0e9248
CW		 192static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
193{
194 return container_of(intel_attached_encoder(connector),
195 struct intel_sdvo, base);
196}
197
615fb93f
CW		 198static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
199{
200 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
201}
202
fb7a46f3 203static bool
ea5b213a 204intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 205static bool
206intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
207 struct intel_sdvo_connector *intel_sdvo_connector,
208 int type);
209static bool
210intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
211 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 212
79e53945
JB		 213/**
214 * Writes the SDVOB or SDVOC with the given value, but always writes both
215 * SDVOB and SDVOC to work around apparent hardware issues (according to
216 * comments in the BIOS).
217 */
ea5b213a 218static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 219{
4ef69c7a 220 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 221 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 222 u32 bval = val, cval = val;
223 int i;
224
ea5b213a
CW		 225 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
226 I915_WRITE(intel_sdvo->sdvo_reg, val);
227 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 228 return;
229 }
230
ea5b213a 231 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 232 cval = I915_READ(SDVOC);
233 } else {
234 bval = I915_READ(SDVOB);
235 }
236 /*
237 * Write the registers twice for luck. Sometimes,
238 * writing them only once doesn't appear to 'stick'.
239 * The BIOS does this too. Yay, magic
240 */
241 for (i = 0; i < 2; i++)
242 {
243 I915_WRITE(SDVOB, bval);
244 I915_READ(SDVOB);
245 I915_WRITE(SDVOC, cval);
246 I915_READ(SDVOC);
247 }
248}
249
32aad86f 250static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 251{
32aad86f 252 u8 out_buf[2] = { addr, 0 };
79e53945 253 u8 buf[2];
79e53945
JB		 254 struct i2c_msg msgs[] = {
255 {
ea5b213a 256 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 257 .flags = 0,
258 .len = 1,
259 .buf = out_buf,
260 },
261 {
ea5b213a 262 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 263 .flags = I2C_M_RD,
264 .len = 1,
265 .buf = buf,
266 }
267 };
32aad86f 268 int ret;
79e53945 269
ea5b213a 270 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
79e53945
JB		 271 {
272 *ch = buf[0];
273 return true;
274 }
275
8a4c47f3 276 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 277 return false;
278}
279
32aad86f 280static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
79e53945 281{
32aad86f 282 u8 out_buf[2] = { addr, ch };
79e53945
JB		 283 struct i2c_msg msgs[] = {
284 {
ea5b213a 285 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 286 .flags = 0,
287 .len = 2,
288 .buf = out_buf,
289 }
290 };
291
32aad86f 292 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
79e53945
JB		 293}
294
295#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
296/** Mapping of command numbers to names, for debug output */
005568be 297static const struct _sdvo_cmd_name {
e2f0ba97 298 u8 cmd;
2e88e40b 299 const char *name;
79e53945
JB		 300} sdvo_cmd_names[] = {
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
c5521706 344
b9219c5e 345 /* Add the op code for SDVO enhancements */
c5521706
CW		 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
b9219c5e
ZY		 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
c5521706
CW		 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
390
e2f0ba97
JB		 391 /* HDMI op code */
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 412};
413
461ed3ca 414#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 415#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 416
ea5b213a 417static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 418 const void *args, int args_len)
79e53945 419{
79e53945
JB		 420 int i;
421
8a4c47f3 422 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 423 SDVO_NAME(intel_sdvo), cmd);
79e53945 424 for (i = 0; i < args_len; i++)
342dc382 425 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 426 for (; i < 8; i++)
342dc382 427 DRM_LOG_KMS(" ");
04ad327f 428 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 429 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 430 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 431 break;
432 }
433 }
04ad327f 434 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 435 DRM_LOG_KMS("(%02X)", cmd);
436 DRM_LOG_KMS("\n");
79e53945 437}
79e53945 438
32aad86f
CW		 439static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
440 const void *args, int args_len)
79e53945
JB		 441{
442 int i;
443
ea5b213a 444 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 445
446 for (i = 0; i < args_len; i++) {
32aad86f
CW		 447 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
448 ((u8*)args)[i]))
449 return false;
79e53945
JB		 450 }
451
32aad86f 452 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 453}
454
79e53945
JB		 455static const char *cmd_status_names[] = {
456 "Power on",
457 "Success",
458 "Not supported",
459 "Invalid arg",
460 "Pending",
461 "Target not specified",
462 "Scaling not supported"
463};
464
b5c616a7
CW		 465static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
466 void *response, int response_len)
79e53945 467{
b5c616a7
CW		 468 u8 retry = 5;
469 u8 status;
33b52961 470 int i;
79e53945 471
b5c616a7
CW		 472 /*
473 * The documentation states that all commands will be
474 * processed within 15µs, and that we need only poll
475 * the status byte a maximum of 3 times in order for the
476 * command to be complete.
477 *
478 * Check 5 times in case the hardware failed to read the docs.
479 */
480 do {
481 if (!intel_sdvo_read_byte(intel_sdvo,
482 SDVO_I2C_CMD_STATUS,
483 &status))
484 return false;
485 } while (status == SDVO_CMD_STATUS_PENDING && --retry);
486
ea5b213a 487 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 488 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 489 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 490 else
342dc382 491 DRM_LOG_KMS("(??? %d)", status);
79e53945 492
b5c616a7
CW		 493 if (status != SDVO_CMD_STATUS_SUCCESS)
494 goto log_fail;
79e53945 495
b5c616a7
CW		 496 /* Read the command response */
497 for (i = 0; i < response_len; i++) {
498 if (!intel_sdvo_read_byte(intel_sdvo,
499 SDVO_I2C_RETURN_0 + i,
500 &((u8 *)response)[i]))
501 goto log_fail;
502 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
503 }
79e53945 504
b5c616a7
CW		 505 for (; i < 8; i++)
506 DRM_LOG_KMS(" ");
507 DRM_LOG_KMS("\n");
79e53945 508
b5c616a7 509 return true;
79e53945 510
b5c616a7
CW		 511log_fail:
512 DRM_LOG_KMS("\n");
513 return false;
79e53945
JB		 514}
515
b358d0a6 516static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 517{
518 if (mode->clock >= 100000)
519 return 1;
520 else if (mode->clock >= 50000)
521 return 2;
522 else
523 return 4;
524}
525
526/**
6a304caf
ZY		 527 * Try to read the response after issuie the DDC switch command. But it
528 * is noted that we must do the action of reading response and issuing DDC
529 * switch command in one I2C transaction. Otherwise when we try to start
530 * another I2C transaction after issuing the DDC bus switch, it will be
531 * switched to the internal SDVO register.
79e53945 532 */
ea5b213a 533static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
b358d0a6 534 u8 target)
79e53945 535{
6a304caf
ZY		 536 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
537 struct i2c_msg msgs[] = {
538 {
ea5b213a 539 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 540 .flags = 0,
541 .len = 2,
542 .buf = out_buf,
543 },
544 /* the following two are to read the response */
545 {
ea5b213a 546 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 547 .flags = 0,
548 .len = 1,
549 .buf = cmd_buf,
550 },
551 {
ea5b213a 552 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 553 .flags = I2C_M_RD,
554 .len = 1,
555 .buf = ret_value,
556 },
557 };
558
ea5b213a 559 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
6a304caf
ZY		 560 &target, 1);
561 /* write the DDC switch command argument */
ea5b213a 562 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
6a304caf
ZY		 563
564 out_buf[0] = SDVO_I2C_OPCODE;
565 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
566 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
567 cmd_buf[1] = 0;
568 ret_value[0] = 0;
569 ret_value[1] = 0;
570
ea5b213a 571 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
6a304caf
ZY		 572 if (ret != 3) {
573 /* failure in I2C transfer */
574 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
575 return;
576 }
577 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
578 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
579 ret_value[0]);
580 return;
581 }
582 return;
79e53945
JB		 583}
584
32aad86f 585static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 586{
32aad86f
CW		 587 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
588 return false;
79e53945 589
32aad86f
CW		 590 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
591}
79e53945 592
32aad86f
CW		 593static bool
594intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
595{
596 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
597 return false;
79e53945 598
32aad86f
CW		 599 return intel_sdvo_read_response(intel_sdvo, value, len);
600}
79e53945 601
32aad86f
CW		 602static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
603{
604 struct intel_sdvo_set_target_input_args targets = {0};
605 return intel_sdvo_set_value(intel_sdvo,
606 SDVO_CMD_SET_TARGET_INPUT,
607 &targets, sizeof(targets));
79e53945
JB		 608}
609
610/**
611 * Return whether each input is trained.
612 *
613 * This function is making an assumption about the layout of the response,
614 * which should be checked against the docs.
615 */
ea5b213a 616static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 617{
618 struct intel_sdvo_get_trained_inputs_response response;
79e53945 619
32aad86f
CW		 620 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
621 &response, sizeof(response)))
79e53945
JB		 622 return false;
623
624 *input_1 = response.input0_trained;
625 *input_2 = response.input1_trained;
626 return true;
627}
628
ea5b213a 629static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 630 u16 outputs)
631{
32aad86f
CW		 632 return intel_sdvo_set_value(intel_sdvo,
633 SDVO_CMD_SET_ACTIVE_OUTPUTS,
634 &outputs, sizeof(outputs));
79e53945
JB		 635}
636
ea5b213a 637static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 638 int mode)
639{
32aad86f 640 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 641
642 switch (mode) {
643 case DRM_MODE_DPMS_ON:
644 state = SDVO_ENCODER_STATE_ON;
645 break;
646 case DRM_MODE_DPMS_STANDBY:
647 state = SDVO_ENCODER_STATE_STANDBY;
648 break;
649 case DRM_MODE_DPMS_SUSPEND:
650 state = SDVO_ENCODER_STATE_SUSPEND;
651 break;
652 case DRM_MODE_DPMS_OFF:
653 state = SDVO_ENCODER_STATE_OFF;
654 break;
655 }
656
32aad86f
CW		 657 return intel_sdvo_set_value(intel_sdvo,
658 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 659}
660
ea5b213a 661static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 662 int *clock_min,
663 int *clock_max)
664{
665 struct intel_sdvo_pixel_clock_range clocks;
79e53945 666
32aad86f
CW		 667 if (!intel_sdvo_get_value(intel_sdvo,
668 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
669 &clocks, sizeof(clocks)))
79e53945
JB		 670 return false;
671
672 /* Convert the values from units of 10 kHz to kHz. */
673 *clock_min = clocks.min * 10;
674 *clock_max = clocks.max * 10;
79e53945
JB		 675 return true;
676}
677
ea5b213a 678static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 679 u16 outputs)
680{
32aad86f
CW		 681 return intel_sdvo_set_value(intel_sdvo,
682 SDVO_CMD_SET_TARGET_OUTPUT,
683 &outputs, sizeof(outputs));
79e53945
JB		 684}
685
ea5b213a 686static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 687 struct intel_sdvo_dtd *dtd)
688{
32aad86f
CW		 689 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
690 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 691}
692
ea5b213a 693static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 694 struct intel_sdvo_dtd *dtd)
695{
ea5b213a 696 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 697 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
698}
699
ea5b213a 700static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 701 struct intel_sdvo_dtd *dtd)
702{
ea5b213a 703 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 704 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
705}
706
e2f0ba97 707static bool
ea5b213a 708intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 709 uint16_t clock,
710 uint16_t width,
711 uint16_t height)
712{
713 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 714
e642c6f1 715 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 716 args.clock = clock;
717 args.width = width;
718 args.height = height;
e642c6f1 719 args.interlace = 0;
12682a97 720
ea5b213a
CW		 721 if (intel_sdvo->is_lvds &&
722 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
723 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 724 args.scaled = 1;
725
32aad86f
CW		 726 return intel_sdvo_set_value(intel_sdvo,
727 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
728 &args, sizeof(args));
e2f0ba97
JB		 729}
730
ea5b213a 731static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 732 struct intel_sdvo_dtd *dtd)
733{
32aad86f
CW		 734 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
735 &dtd->part1, sizeof(dtd->part1)) &&
736 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
737 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 738}
79e53945 739
ea5b213a 740static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 741{
32aad86f 742 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 743}
744
e2f0ba97 745static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 746 const struct drm_display_mode *mode)
79e53945 747{
e2f0ba97
JB		 748 uint16_t width, height;
749 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
750 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 751
752 width = mode->crtc_hdisplay;
753 height = mode->crtc_vdisplay;
754
755 /* do some mode translations */
756 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
757 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
758
759 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
760 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
761
762 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
763 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
764
e2f0ba97
JB		 765 dtd->part1.clock = mode->clock / 10;
766 dtd->part1.h_active = width & 0xff;
767 dtd->part1.h_blank = h_blank_len & 0xff;
768 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 769 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 770 dtd->part1.v_active = height & 0xff;
771 dtd->part1.v_blank = v_blank_len & 0xff;
772 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 773 ((v_blank_len >> 8) & 0xf);
774
171a9e96 775 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 776 dtd->part2.h_sync_width = h_sync_len & 0xff;
777 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 778 (v_sync_len & 0xf);
e2f0ba97 779 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 780 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
781 ((v_sync_len & 0x30) >> 4);
782
e2f0ba97 783 dtd->part2.dtd_flags = 0x18;
79e53945 784 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 785 dtd->part2.dtd_flags |= 0x2;
79e53945 786 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 787 dtd->part2.dtd_flags |= 0x4;
788
789 dtd->part2.sdvo_flags = 0;
790 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
791 dtd->part2.reserved = 0;
792}
793
794static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 795 const struct intel_sdvo_dtd *dtd)
e2f0ba97 796{
e2f0ba97
JB		 797 mode->hdisplay = dtd->part1.h_active;
798 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
799 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 800 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 801 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
802 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
803 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
804 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
805
806 mode->vdisplay = dtd->part1.v_active;
807 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
808 mode->vsync_start = mode->vdisplay;
809 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 810 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 811 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
812 mode->vsync_end = mode->vsync_start +
813 (dtd->part2.v_sync_off_width & 0xf);
814 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
815 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
816 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
817
818 mode->clock = dtd->part1.clock * 10;
819
171a9e96 820 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 821 if (dtd->part2.dtd_flags & 0x2)
822 mode->flags |= DRM_MODE_FLAG_PHSYNC;
823 if (dtd->part2.dtd_flags & 0x4)
824 mode->flags |= DRM_MODE_FLAG_PVSYNC;
825}
826
ea5b213a 827static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 828 struct intel_sdvo_encode *encode)
829{
32aad86f
CW		 830 if (intel_sdvo_get_value(intel_sdvo,
831 SDVO_CMD_GET_SUPP_ENCODE,
832 encode, sizeof(*encode)))
833 return true;
e2f0ba97 834
32aad86f
CW		 835 /* non-support means DVI */
836 memset(encode, 0, sizeof(*encode));
837 return false;
e2f0ba97
JB		 838}
839
ea5b213a 840static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 841 uint8_t mode)
e2f0ba97 842{
32aad86f 843 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 844}
845
ea5b213a 846static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 847 uint8_t mode)
848{
32aad86f 849 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 850}
851
852#if 0
ea5b213a 853static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 854{
855 int i, j;
856 uint8_t set_buf_index[2];
857 uint8_t av_split;
858 uint8_t buf_size;
859 uint8_t buf[48];
860 uint8_t *pos;
861
32aad86f 862 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 863
864 for (i = 0; i <= av_split; i++) {
865 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 866 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 867 set_buf_index, 2);
c751ce4f
EA		 868 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
869 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 870
871 pos = buf;
872 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 873 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 874 NULL, 0);
c751ce4f 875 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 876 pos += 8;
877 }
878 }
879}
880#endif
881
32aad86f 882static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
c751ce4f
EA		 883 int index,
884 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 885{
886 uint8_t set_buf_index[2];
887
888 set_buf_index[0] = index;
889 set_buf_index[1] = 0;
890
32aad86f
CW		 891 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
892 set_buf_index, 2))
893 return false;
e2f0ba97
JB		 894
895 for (; size > 0; size -= 8) {
32aad86f
CW		 896 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
897 return false;
898
e2f0ba97
JB		 899 data += 8;
900 }
901
32aad86f 902 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 903}
904
905static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
906{
907 uint8_t csum = 0;
908 int i;
909
910 for (i = 0; i < size; i++)
911 csum += data[i];
912
913 return 0x100 - csum;
914}
915
916#define DIP_TYPE_AVI 0x82
917#define DIP_VERSION_AVI 0x2
918#define DIP_LEN_AVI 13
919
920struct dip_infoframe {
921 uint8_t type;
922 uint8_t version;
923 uint8_t len;
924 uint8_t checksum;
925 union {
926 struct {
927 /* Packet Byte #1 */
928 uint8_t S:2;
929 uint8_t B:2;
930 uint8_t A:1;
931 uint8_t Y:2;
932 uint8_t rsvd1:1;
933 /* Packet Byte #2 */
934 uint8_t R:4;
935 uint8_t M:2;
936 uint8_t C:2;
937 /* Packet Byte #3 */
938 uint8_t SC:2;
939 uint8_t Q:2;
940 uint8_t EC:3;
941 uint8_t ITC:1;
942 /* Packet Byte #4 */
943 uint8_t VIC:7;
944 uint8_t rsvd2:1;
945 /* Packet Byte #5 */
946 uint8_t PR:4;
947 uint8_t rsvd3:4;
948 /* Packet Byte #6~13 */
949 uint16_t top_bar_end;
950 uint16_t bottom_bar_start;
951 uint16_t left_bar_end;
952 uint16_t right_bar_start;
953 } avi;
954 struct {
955 /* Packet Byte #1 */
956 uint8_t channel_count:3;
957 uint8_t rsvd1:1;
958 uint8_t coding_type:4;
959 /* Packet Byte #2 */
960 uint8_t sample_size:2; /* SS0, SS1 */
961 uint8_t sample_frequency:3;
962 uint8_t rsvd2:3;
963 /* Packet Byte #3 */
964 uint8_t coding_type_private:5;
965 uint8_t rsvd3:3;
966 /* Packet Byte #4 */
967 uint8_t channel_allocation;
968 /* Packet Byte #5 */
969 uint8_t rsvd4:3;
970 uint8_t level_shift:4;
971 uint8_t downmix_inhibit:1;
972 } audio;
973 uint8_t payload[28];
974 } __attribute__ ((packed)) u;
975} __attribute__((packed));
976
32aad86f 977static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 978 struct drm_display_mode * mode)
979{
980 struct dip_infoframe avi_if = {
981 .type = DIP_TYPE_AVI,
982 .version = DIP_VERSION_AVI,
983 .len = DIP_LEN_AVI,
984 };
985
986 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
987 4 + avi_if.len);
32aad86f
CW		 988 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
989 4 + avi_if.len,
990 SDVO_HBUF_TX_VSYNC);
e2f0ba97
JB		 991}
992
32aad86f 993static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 994{
ce6feabd 995 struct intel_sdvo_tv_format format;
40039750 996 uint32_t format_map;
ce6feabd 997
40039750 998 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 999 memset(&format, 0, sizeof(format));
32aad86f 1000 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1001
32aad86f
CW		 1002 BUILD_BUG_ON(sizeof(format) != 6);
1003 return intel_sdvo_set_value(intel_sdvo,
1004 SDVO_CMD_SET_TV_FORMAT,
1005 &format, sizeof(format));
7026d4ac
ZW		 1006}
1007
32aad86f
CW		 1008static bool
1009intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1010 struct drm_display_mode *mode)
e2f0ba97 1011{
32aad86f 1012 struct intel_sdvo_dtd output_dtd;
79e53945 1013
32aad86f
CW		 1014 if (!intel_sdvo_set_target_output(intel_sdvo,
1015 intel_sdvo->attached_output))
1016 return false;
e2f0ba97 1017
32aad86f
CW		 1018 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1019 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1020 return false;
e2f0ba97 1021
32aad86f
CW		 1022 return true;
1023}
1024
1025static bool
1026intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1027 struct drm_display_mode *mode,
1028 struct drm_display_mode *adjusted_mode)
1029{
32aad86f
CW		 1030 /* Reset the input timing to the screen. Assume always input 0. */
1031 if (!intel_sdvo_set_target_input(intel_sdvo))
1032 return false;
e2f0ba97 1033
32aad86f
CW		 1034 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1035 mode->clock / 10,
1036 mode->hdisplay,
1037 mode->vdisplay))
1038 return false;
e2f0ba97 1039
32aad86f 1040 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 1041 &intel_sdvo->input_dtd))
32aad86f 1042 return false;
e2f0ba97 1043
6c9547ff 1044 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 1045
32aad86f 1046 drm_mode_set_crtcinfo(adjusted_mode, 0);
32aad86f
CW		 1047 return true;
1048}
12682a97 1049
32aad86f
CW		 1050static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1051 struct drm_display_mode *mode,
1052 struct drm_display_mode *adjusted_mode)
1053{
1054 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
6c9547ff 1055 int multiplier;
12682a97 1056
32aad86f
CW		 1057 /* We need to construct preferred input timings based on our
1058 * output timings. To do that, we have to set the output
1059 * timings, even though this isn't really the right place in
1060 * the sequence to do it. Oh well.
1061 */
1062 if (intel_sdvo->is_tv) {
1063 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1064 return false;
12682a97 1065
c74696b9
PR		 1066 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1067 mode,
1068 adjusted_mode);
ea5b213a 1069 } else if (intel_sdvo->is_lvds) {
32aad86f 1070 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1071 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1072 return false;
12682a97 1073
c74696b9
PR		 1074 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1075 mode,
1076 adjusted_mode);
e2f0ba97 1077 }
32aad86f
CW		 1078
1079 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1080 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1081 */
6c9547ff
CW		 1082 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1083 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1084
e2f0ba97
JB		 1085 return true;
1086}
1087
1088static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1089 struct drm_display_mode *mode,
1090 struct drm_display_mode *adjusted_mode)
1091{
1092 struct drm_device *dev = encoder->dev;
1093 struct drm_i915_private *dev_priv = dev->dev_private;
1094 struct drm_crtc *crtc = encoder->crtc;
1095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a 1096 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
6c9547ff 1097 u32 sdvox;
e2f0ba97
JB		 1098 struct intel_sdvo_in_out_map in_out;
1099 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 1100 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1101 int rate;
e2f0ba97
JB		 1102
1103 if (!mode)
1104 return;
1105
1106 /* First, set the input mapping for the first input to our controlled
1107 * output. This is only correct if we're a single-input device, in
1108 * which case the first input is the output from the appropriate SDVO
1109 * channel on the motherboard. In a two-input device, the first input
1110 * will be SDVOB and the second SDVOC.
1111 */
ea5b213a 1112 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1113 in_out.in1 = 0;
1114
c74696b9
PR		 1115 intel_sdvo_set_value(intel_sdvo,
1116 SDVO_CMD_SET_IN_OUT_MAP,
1117 &in_out, sizeof(in_out));
e2f0ba97 1118
6c9547ff
CW		 1119 /* Set the output timings to the screen */
1120 if (!intel_sdvo_set_target_output(intel_sdvo,
1121 intel_sdvo->attached_output))
1122 return;
e2f0ba97 1123
7026d4ac 1124 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1125 * adjusted_mode.
e2f0ba97 1126 */
6c9547ff
CW		 1127 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1128 input_dtd = intel_sdvo->input_dtd;
1129 } else {
e2f0ba97 1130 /* Set the output timing to the screen */
32aad86f
CW		 1131 if (!intel_sdvo_set_target_output(intel_sdvo,
1132 intel_sdvo->attached_output))
1133 return;
1134
6c9547ff 1135 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1136 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1137 }
79e53945
JB		 1138
1139 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1140 if (!intel_sdvo_set_target_input(intel_sdvo))
1141 return;
79e53945 1142
6c9547ff
CW		 1143 if (intel_sdvo->is_hdmi &&
1144 !intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1145 return;
7026d4ac 1146
6c9547ff
CW		 1147 if (intel_sdvo->is_tv &&
1148 !intel_sdvo_set_tv_format(intel_sdvo))
1149 return;
e2f0ba97 1150
c74696b9 1151 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1152
6c9547ff
CW		 1153 switch (pixel_multiplier) {
1154 default:
32aad86f
CW		 1155 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1156 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1157 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1158 }
32aad86f
CW		 1159 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1160 return;
79e53945
JB		 1161
1162 /* Set the SDVO control regs. */
e2f0ba97 1163 if (IS_I965G(dev)) {
6c9547ff 1164 sdvox = SDVO_BORDER_ENABLE;
81a14b46
AJ		 1165 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1166 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1167 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1168 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1169 } else {
6c9547ff 1170 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1171 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1172 case SDVOB:
1173 sdvox &= SDVOB_PRESERVE_MASK;
1174 break;
1175 case SDVOC:
1176 sdvox &= SDVOC_PRESERVE_MASK;
1177 break;
1178 }
1179 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1180 }
79e53945
JB		 1181 if (intel_crtc->pipe == 1)
1182 sdvox |= SDVO_PIPE_B_SELECT;
6c9547ff
CW		 1183 if (intel_sdvo->is_hdmi)
1184 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1185
79e53945 1186 if (IS_I965G(dev)) {
e2f0ba97
JB		 1187 /* done in crtc_mode_set as the dpll_md reg must be written early */
1188 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1189 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1190 } else {
6c9547ff 1191 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1192 }
1193
6c9547ff 1194 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1195 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1196 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1197}
1198
1199static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1200{
1201 struct drm_device *dev = encoder->dev;
1202 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1203 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
9d0498a2 1204 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1205 u32 temp;
1206
1207 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1208 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1209 if (0)
ea5b213a 1210 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1211
1212 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1213 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1214 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1215 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1216 }
1217 }
1218 } else {
1219 bool input1, input2;
1220 int i;
1221 u8 status;
1222
ea5b213a 1223 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1224 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1225 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1226 for (i = 0; i < 2; i++)
9d0498a2 1227 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1228
32aad86f 1229 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1230 /* Warn if the device reported failure to sync.
1231 * A lot of SDVO devices fail to notify of sync, but it's
1232 * a given it the status is a success, we succeeded.
1233 */
1234 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1235 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1236 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1237 }
1238
1239 if (0)
ea5b213a
CW		 1240 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1241 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1242 }
1243 return;
1244}
1245
79e53945
JB		 1246static int intel_sdvo_mode_valid(struct drm_connector *connector,
1247 struct drm_display_mode *mode)
1248{
df0e9248 1249 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1250
1251 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1252 return MODE_NO_DBLESCAN;
1253
ea5b213a 1254 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1255 return MODE_CLOCK_LOW;
1256
ea5b213a 1257 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1258 return MODE_CLOCK_HIGH;
1259
8545423a 1260 if (intel_sdvo->is_lvds) {
ea5b213a 1261 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1262 return MODE_PANEL;
1263
ea5b213a 1264 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1265 return MODE_PANEL;
1266 }
1267
79e53945
JB		 1268 return MODE_OK;
1269}
1270
ea5b213a 1271static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1272{
32aad86f 1273 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
79e53945
JB		 1274}
1275
d2a82a6f
ZW		 1276/* No use! */
1277#if 0
79e53945
JB		 1278struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1279{
1280 struct drm_connector *connector = NULL;
ea5b213a
CW		 1281 struct intel_sdvo *iout = NULL;
1282 struct intel_sdvo *sdvo;
79e53945
JB		 1283
1284 /* find the sdvo connector */
1285 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1286 iout = to_intel_sdvo(connector);
79e53945
JB		 1287
1288 if (iout->type != INTEL_OUTPUT_SDVO)
1289 continue;
1290
1291 sdvo = iout->dev_priv;
1292
c751ce4f 1293 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1294 return connector;
1295
c751ce4f 1296 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1297 return connector;
1298
1299 }
1300
1301 return NULL;
1302}
1303
1304int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1305{
1306 u8 response[2];
1307 u8 status;
ea5b213a 1308 struct intel_sdvo *intel_sdvo;
8a4c47f3 1309 DRM_DEBUG_KMS("\n");
79e53945
JB		 1310
1311 if (!connector)
1312 return 0;
1313
ea5b213a 1314 intel_sdvo = to_intel_sdvo(connector);
79e53945 1315
32aad86f
CW		 1316 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1317 &response, 2) && response[0];
79e53945
JB		 1318}
1319
1320void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1321{
1322 u8 response[2];
1323 u8 status;
ea5b213a 1324 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1325
ea5b213a
CW		 1326 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1327 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1328
1329 if (on) {
ea5b213a
CW		 1330 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1331 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1332
ea5b213a 1333 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1334 } else {
1335 response[0] = 0;
1336 response[1] = 0;
ea5b213a 1337 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1338 }
1339
ea5b213a
CW		 1340 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1341 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1342}
d2a82a6f 1343#endif
79e53945 1344
fb7a46f3 1345static bool
ea5b213a 1346intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1347{
fb7a46f3 1348 int caps = 0;
1349
ea5b213a 1350 if (intel_sdvo->caps.output_flags &
fb7a46f3 1351 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1352 caps++;
ea5b213a 1353 if (intel_sdvo->caps.output_flags &
fb7a46f3 1354 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1355 caps++;
ea5b213a 1356 if (intel_sdvo->caps.output_flags &
19e1f888 1357 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1358 caps++;
ea5b213a 1359 if (intel_sdvo->caps.output_flags &
fb7a46f3 1360 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1361 caps++;
ea5b213a 1362 if (intel_sdvo->caps.output_flags &
fb7a46f3 1363 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1364 caps++;
1365
ea5b213a 1366 if (intel_sdvo->caps.output_flags &
fb7a46f3 1367 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1368 caps++;
1369
ea5b213a 1370 if (intel_sdvo->caps.output_flags &
fb7a46f3 1371 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1372 caps++;
1373
1374 return (caps > 1);
1375}
1376
57cdaf90
KP		 1377static struct drm_connector *
1378intel_find_analog_connector(struct drm_device *dev)
1379{
1380 struct drm_connector *connector;
df0e9248
CW		 1381 struct intel_sdvo *encoder;
1382
1383 list_for_each_entry(encoder,
1384 &dev->mode_config.encoder_list,
1385 base.base.head) {
1386 if (encoder->base.type == INTEL_OUTPUT_ANALOG) {
1387 list_for_each_entry(connector,
1388 &dev->mode_config.connector_list,
1389 head) {
1390 if (&encoder->base ==
1391 intel_attached_encoder(connector))
d2a82a6f
ZW		 1392 return connector;
1393 }
1394 }
57cdaf90 1395 }
df0e9248 1396
57cdaf90
KP		 1397 return NULL;
1398}
1399
1400static int
1401intel_analog_is_connected(struct drm_device *dev)
1402{
1403 struct drm_connector *analog_connector;
57cdaf90 1404
32aad86f 1405 analog_connector = intel_find_analog_connector(dev);
57cdaf90
KP		 1406 if (!analog_connector)
1407 return false;
1408
1409 if (analog_connector->funcs->detect(analog_connector) ==
1410 connector_status_disconnected)
1411 return false;
1412
1413 return true;
1414}
1415
2b8d33f7 1416enum drm_connector_status
149c36a3 1417intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1418{
df0e9248 1419 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1420 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2b8d33f7 1421 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1422 struct edid *edid = NULL;
1423
ea5b213a 1424 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
57cdaf90 1425
7c3f0a27 1426 /* This is only applied to SDVO cards with multiple outputs */
ea5b213a 1427 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
7c3f0a27 1428 uint8_t saved_ddc, temp_ddc;
ea5b213a
CW		 1429 saved_ddc = intel_sdvo->ddc_bus;
1430 temp_ddc = intel_sdvo->ddc_bus >> 1;
7c3f0a27
ZY		 1431 /*
1432 * Don't use the 1 as the argument of DDC bus switch to get
1433 * the EDID. It is used for SDVO SPD ROM.
1434 */
1435 while(temp_ddc > 1) {
ea5b213a
CW		 1436 intel_sdvo->ddc_bus = temp_ddc;
1437 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
7c3f0a27
ZY		 1438 if (edid) {
1439 /*
1440 * When we can get the EDID, maybe it is the
1441 * correct DDC bus. Update it.
1442 */
ea5b213a 1443 intel_sdvo->ddc_bus = temp_ddc;
7c3f0a27
ZY		 1444 break;
1445 }
1446 temp_ddc >>= 1;
1447 }
1448 if (edid == NULL)
ea5b213a 1449 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1450 }
57cdaf90
KP		 1451 /* when there is no edid and no monitor is connected with VGA
1452 * port, try to use the CRT ddc to read the EDID for DVI-connector
1453 */
ea5b213a 1454 if (edid == NULL && intel_sdvo->analog_ddc_bus &&
d2a82a6f 1455 !intel_analog_is_connected(connector->dev))
ea5b213a 1456 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
149c36a3 1457
9dff6af8 1458 if (edid != NULL) {
149c36a3 1459 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
615fb93f 1460 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
2b8d33f7 1461
149c36a3
AJ		 1462 /* DDC bus is shared, match EDID to connector type */
1463 if (is_digital && need_digital)
ea5b213a 1464 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
149c36a3
AJ		 1465 else if (is_digital != need_digital)
1466 status = connector_status_disconnected;
2b8d33f7 1467
149c36a3
AJ		 1468 connector->display_info.raw_edid = NULL;
1469 } else
2b8d33f7 1470 status = connector_status_disconnected;
149c36a3
AJ		 1471
1472 kfree(edid);
2b8d33f7 1473
1474 return status;
9dff6af8
ML		 1475}
1476
79e53945
JB		 1477static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1478{
fb7a46f3 1479 uint16_t response;
df0e9248 1480 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1481 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1482 enum drm_connector_status ret;
79e53945 1483
32aad86f
CW		 1484 if (!intel_sdvo_write_cmd(intel_sdvo,
1485 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1486 return connector_status_unknown;
ea5b213a 1487 if (intel_sdvo->is_tv) {
d09c23de
ZY		 1488 /* add 30ms delay when the output type is SDVO-TV */
1489 mdelay(30);
1490 }
32aad86f
CW		 1491 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1492 return connector_status_unknown;
79e53945 1493
51c8b407 1494 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97 1495
fb7a46f3 1496 if (response == 0)
79e53945 1497 return connector_status_disconnected;
fb7a46f3 1498
ea5b213a 1499 intel_sdvo->attached_output = response;
14571b4c 1500
615fb93f 1501 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1502 ret = connector_status_disconnected;
149c36a3
AJ		 1503 else if (response & SDVO_TMDS_MASK)
1504 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1505 else
1506 ret = connector_status_connected;
1507
1508 /* May update encoder flag for like clock for SDVO TV, etc.*/
1509 if (ret == connector_status_connected) {
ea5b213a
CW		 1510 intel_sdvo->is_tv = false;
1511 intel_sdvo->is_lvds = false;
1512 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1513
1514 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1515 intel_sdvo->is_tv = true;
1516 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1517 }
1518 if (response & SDVO_LVDS_MASK)
8545423a 1519 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1520 }
14571b4c
ZW		 1521
1522 return ret;
79e53945
JB		 1523}
1524
e2f0ba97 1525static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1526{
df0e9248 1527 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
57cdaf90 1528 int num_modes;
79e53945
JB		 1529
1530 /* set the bus switch and get the modes */
ea5b213a 1531 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
79e53945 1532
57cdaf90
KP		 1533 /*
1534 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1535 * link between analog and digital outputs. So, if the regular SDVO
1536 * DDC fails, check to see if the analog output is disconnected, in
1537 * which case we'll look there for the digital DDC data.
e2f0ba97 1538 */
57cdaf90 1539 if (num_modes == 0 &&
ea5b213a 1540 intel_sdvo->analog_ddc_bus &&
d2a82a6f 1541 !intel_analog_is_connected(connector->dev)) {
57cdaf90
KP		 1542 /* Switch to the analog ddc bus and try that
1543 */
ea5b213a 1544 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
e2f0ba97 1545 }
e2f0ba97
JB		 1546}
1547
1548/*
1549 * Set of SDVO TV modes.
1550 * Note! This is in reply order (see loop in get_tv_modes).
1551 * XXX: all 60Hz refresh?
1552 */
1553struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1554 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1555 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1557 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1558 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1560 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1561 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1563 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1564 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1566 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1567 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1569 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1570 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1572 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1573 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1575 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1576 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1578 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1579 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1581 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1582 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1584 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1585 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1587 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1588 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1590 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1591 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1593 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1594 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1596 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1597 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1598 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1599 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1600 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1601 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1602 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1603 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1605 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1606 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1608 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1609 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1610 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1611};
1612
1613static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1614{
df0e9248 1615 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1616 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1617 uint32_t reply = 0, format_map = 0;
1618 int i;
e2f0ba97
JB		 1619
1620 /* Read the list of supported input resolutions for the selected TV
1621 * format.
1622 */
40039750 1623 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1624 memcpy(&tv_res, &format_map,
32aad86f 1625 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1626
32aad86f
CW		 1627 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1628 return;
ce6feabd 1629
32aad86f
CW		 1630 BUILD_BUG_ON(sizeof(tv_res) != 3);
1631 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1632 &tv_res, sizeof(tv_res)))
1633 return;
1634 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1635 return;
1636
1637 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1638 if (reply & (1 << i)) {
1639 struct drm_display_mode *nmode;
1640 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1641 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1642 if (nmode)
1643 drm_mode_probed_add(connector, nmode);
1644 }
e2f0ba97
JB		 1645}
1646
7086c87f
ML		 1647static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1648{
df0e9248 1649 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1650 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1651 struct drm_display_mode *newmode;
7086c87f
ML		 1652
1653 /*
1654 * Attempt to get the mode list from DDC.
1655 * Assume that the preferred modes are
1656 * arranged in priority order.
1657 */
ea5b213a 1658 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
7086c87f 1659 if (list_empty(&connector->probed_modes) == false)
12682a97 1660 goto end;
7086c87f
ML		 1661
1662 /* Fetch modes from VBT */
1663 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1664 newmode = drm_mode_duplicate(connector->dev,
1665 dev_priv->sdvo_lvds_vbt_mode);
1666 if (newmode != NULL) {
1667 /* Guarantee the mode is preferred */
1668 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1669 DRM_MODE_TYPE_DRIVER);
1670 drm_mode_probed_add(connector, newmode);
1671 }
1672 }
12682a97 1673
1674end:
1675 list_for_each_entry(newmode, &connector->probed_modes, head) {
1676 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1677 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1678 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1679
1680 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1681 0);
1682
8545423a 1683 intel_sdvo->is_lvds = true;
12682a97 1684 break;
1685 }
1686 }
1687
7086c87f
ML		 1688}
1689
e2f0ba97
JB		 1690static int intel_sdvo_get_modes(struct drm_connector *connector)
1691{
615fb93f 1692 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1693
615fb93f 1694 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1695 intel_sdvo_get_tv_modes(connector);
615fb93f 1696 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1697 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1698 else
1699 intel_sdvo_get_ddc_modes(connector);
1700
32aad86f 1701 return !list_empty(&connector->probed_modes);
79e53945
JB		 1702}
1703
fcc8d672
CW		 1704static void
1705intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1706{
615fb93f 1707 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1708 struct drm_device *dev = connector->dev;
1709
c5521706
CW		 1710 if (intel_sdvo_connector->left)
1711 drm_property_destroy(dev, intel_sdvo_connector->left);
1712 if (intel_sdvo_connector->right)
1713 drm_property_destroy(dev, intel_sdvo_connector->right);
1714 if (intel_sdvo_connector->top)
1715 drm_property_destroy(dev, intel_sdvo_connector->top);
1716 if (intel_sdvo_connector->bottom)
1717 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1718 if (intel_sdvo_connector->hpos)
1719 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1720 if (intel_sdvo_connector->vpos)
1721 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1722 if (intel_sdvo_connector->saturation)
1723 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1724 if (intel_sdvo_connector->contrast)
1725 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1726 if (intel_sdvo_connector->hue)
1727 drm_property_destroy(dev, intel_sdvo_connector->hue);
1728 if (intel_sdvo_connector->sharpness)
1729 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1730 if (intel_sdvo_connector->flicker_filter)
1731 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1732 if (intel_sdvo_connector->flicker_filter_2d)
1733 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1734 if (intel_sdvo_connector->flicker_filter_adaptive)
1735 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1736 if (intel_sdvo_connector->tv_luma_filter)
1737 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1738 if (intel_sdvo_connector->tv_chroma_filter)
1739 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1740 if (intel_sdvo_connector->dot_crawl)
1741 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1742 if (intel_sdvo_connector->brightness)
1743 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1744}
1745
79e53945
JB		 1746static void intel_sdvo_destroy(struct drm_connector *connector)
1747{
615fb93f 1748 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1749
c5521706 1750 if (intel_sdvo_connector->tv_format)
ce6feabd 1751 drm_property_destroy(connector->dev,
c5521706 1752 intel_sdvo_connector->tv_format);
b9219c5e 1753
d2a82a6f 1754 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1755 drm_sysfs_connector_remove(connector);
1756 drm_connector_cleanup(connector);
d2a82a6f 1757 kfree(connector);
79e53945
JB		 1758}
1759
ce6feabd
ZY		 1760static int
1761intel_sdvo_set_property(struct drm_connector *connector,
1762 struct drm_property *property,
1763 uint64_t val)
1764{
df0e9248 1765 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1766 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e 1767 uint16_t temp_value;
32aad86f
CW		 1768 uint8_t cmd;
1769 int ret;
ce6feabd
ZY		 1770
1771 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1772 if (ret)
1773 return ret;
ce6feabd 1774
c5521706
CW		 1775#define CHECK_PROPERTY(name, NAME) \
1776 if (intel_sdvo_connector->name == property) { \
1777 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1778 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1779 cmd = SDVO_CMD_SET_##NAME; \
1780 intel_sdvo_connector->cur_##name = temp_value; \
1781 goto set_value; \
1782 }
1783
1784 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1785 if (val >= TV_FORMAT_NUM)
1786 return -EINVAL;
1787
40039750 1788 if (intel_sdvo->tv_format_index ==
615fb93f 1789 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1790 return 0;
ce6feabd 1791
40039750 1792 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1793 goto done;
32aad86f 1794 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1795 temp_value = val;
c5521706 1796 if (intel_sdvo_connector->left == property) {
b9219c5e 1797 drm_connector_property_set_value(connector,
c5521706 1798 intel_sdvo_connector->right, val);
615fb93f 1799 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1800 return 0;
b9219c5e 1801
615fb93f
CW		 1802 intel_sdvo_connector->left_margin = temp_value;
1803 intel_sdvo_connector->right_margin = temp_value;
1804 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1805 intel_sdvo_connector->left_margin;
b9219c5e 1806 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1807 goto set_value;
1808 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1809 drm_connector_property_set_value(connector,
c5521706 1810 intel_sdvo_connector->left, val);
615fb93f 1811 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1812 return 0;
b9219c5e 1813
615fb93f
CW		 1814 intel_sdvo_connector->left_margin = temp_value;
1815 intel_sdvo_connector->right_margin = temp_value;
1816 temp_value = intel_sdvo_connector->max_hscan -
1817 intel_sdvo_connector->left_margin;
b9219c5e 1818 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1819 goto set_value;
1820 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1821 drm_connector_property_set_value(connector,
c5521706 1822 intel_sdvo_connector->bottom, val);
615fb93f 1823 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1824 return 0;
b9219c5e 1825
615fb93f
CW		 1826 intel_sdvo_connector->top_margin = temp_value;
1827 intel_sdvo_connector->bottom_margin = temp_value;
1828 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1829 intel_sdvo_connector->top_margin;
b9219c5e 1830 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1831 goto set_value;
1832 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1833 drm_connector_property_set_value(connector,
c5521706 1834 intel_sdvo_connector->top, val);
615fb93f 1835 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1836 return 0;
1837
615fb93f
CW		 1838 intel_sdvo_connector->top_margin = temp_value;
1839 intel_sdvo_connector->bottom_margin = temp_value;
1840 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1841 intel_sdvo_connector->top_margin;
b9219c5e 1842 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1843 goto set_value;
1844 }
1845 CHECK_PROPERTY(hpos, HPOS)
1846 CHECK_PROPERTY(vpos, VPOS)
1847 CHECK_PROPERTY(saturation, SATURATION)
1848 CHECK_PROPERTY(contrast, CONTRAST)
1849 CHECK_PROPERTY(hue, HUE)
1850 CHECK_PROPERTY(brightness, BRIGHTNESS)
1851 CHECK_PROPERTY(sharpness, SHARPNESS)
1852 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1853 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1854 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1855 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1856 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1857 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1858 }
b9219c5e 1859
c5521706 1860 return -EINVAL; /* unknown property */
b9219c5e 1861
c5521706
CW		 1862set_value:
1863 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1864 return -EIO;
b9219c5e 1865
b9219c5e 1866
c5521706 1867done:
df0e9248
CW		 1868 if (intel_sdvo->base.base.crtc) {
1869 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1870 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1871 crtc->y, crtc->fb);
1872 }
1873
32aad86f 1874 return 0;
c5521706 1875#undef CHECK_PROPERTY
ce6feabd
ZY		 1876}
1877
79e53945
JB		 1878static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1879 .dpms = intel_sdvo_dpms,
1880 .mode_fixup = intel_sdvo_mode_fixup,
1881 .prepare = intel_encoder_prepare,
1882 .mode_set = intel_sdvo_mode_set,
1883 .commit = intel_encoder_commit,
1884};
1885
1886static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1887 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1888 .detect = intel_sdvo_detect,
1889 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1890 .set_property = intel_sdvo_set_property,
79e53945
JB		 1891 .destroy = intel_sdvo_destroy,
1892};
1893
1894static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1895 .get_modes = intel_sdvo_get_modes,
1896 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1897 .best_encoder = intel_best_encoder,
79e53945
JB		 1898};
1899
b358d0a6 1900static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1901{
ea5b213a 1902 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
d2a82a6f 1903
ea5b213a
CW		 1904 if (intel_sdvo->analog_ddc_bus)
1905 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
d2a82a6f 1906
ea5b213a 1907 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1908 drm_mode_destroy(encoder->dev,
ea5b213a 1909 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1910
ea5b213a 1911 intel_encoder_destroy(encoder);
79e53945
JB		 1912}
1913
1914static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1915 .destroy = intel_sdvo_enc_destroy,
1916};
1917
b66d8424
CW		 1918static void
1919intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1920{
1921 uint16_t mask = 0;
1922 unsigned int num_bits;
1923
1924 /* Make a mask of outputs less than or equal to our own priority in the
1925 * list.
1926 */
1927 switch (sdvo->controlled_output) {
1928 case SDVO_OUTPUT_LVDS1:
1929 mask |= SDVO_OUTPUT_LVDS1;
1930 case SDVO_OUTPUT_LVDS0:
1931 mask |= SDVO_OUTPUT_LVDS0;
1932 case SDVO_OUTPUT_TMDS1:
1933 mask |= SDVO_OUTPUT_TMDS1;
1934 case SDVO_OUTPUT_TMDS0:
1935 mask |= SDVO_OUTPUT_TMDS0;
1936 case SDVO_OUTPUT_RGB1:
1937 mask |= SDVO_OUTPUT_RGB1;
1938 case SDVO_OUTPUT_RGB0:
1939 mask |= SDVO_OUTPUT_RGB0;
1940 break;
1941 }
1942
1943 /* Count bits to find what number we are in the priority list. */
1944 mask &= sdvo->caps.output_flags;
1945 num_bits = hweight16(mask);
1946 /* If more than 3 outputs, default to DDC bus 3 for now. */
1947 if (num_bits > 3)
1948 num_bits = 3;
1949
1950 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1951 sdvo->ddc_bus = 1 << num_bits;
1952}
79e53945 1953
e2f0ba97
JB		 1954/**
1955 * Choose the appropriate DDC bus for control bus switch command for this
1956 * SDVO output based on the controlled output.
1957 *
1958 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1959 * outputs, then LVDS outputs.
1960 */
1961static void
b1083333 1962intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1963 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1964{
b1083333 1965 struct sdvo_device_mapping *mapping;
e2f0ba97 1966
b1083333
AJ		 1967 if (IS_SDVOB(reg))
1968 mapping = &(dev_priv->sdvo_mappings[0]);
1969 else
1970 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1971
b66d8424
CW		 1972 if (mapping->initialized)
1973 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1974 else
1975 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1976}
1977
1978static bool
ea5b213a 1979intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1980{
32aad86f
CW		 1981 return intel_sdvo_set_target_output(intel_sdvo,
1982 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
1983 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1984 &intel_sdvo->is_hdmi, 1);
e2f0ba97
JB		 1985}
1986
ea5b213a
CW		 1987static struct intel_sdvo *
1988intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
619ac3b7
ML		 1989{
1990 struct drm_device *dev = chan->drm_dev;
d2a82a6f 1991 struct drm_encoder *encoder;
619ac3b7 1992
d2a82a6f 1993 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 1994 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1995 if (intel_sdvo->base.ddc_bus == &chan->adapter)
1996 return intel_sdvo;
619ac3b7 1997 }
ea5b213a 1998
32aad86f 1999 return NULL;
619ac3b7
ML		 2000}
2001
2002static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2003 struct i2c_msg msgs[], int num)
2004{
ea5b213a 2005 struct intel_sdvo *intel_sdvo;
619ac3b7 2006 struct i2c_algo_bit_data *algo_data;
f9c10a9b 2007 const struct i2c_algorithm *algo;
619ac3b7
ML		 2008
2009 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
ea5b213a
CW		 2010 intel_sdvo =
2011 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
2012 (algo_data->data));
2013 if (intel_sdvo == NULL)
619ac3b7
ML		 2014 return -EINVAL;
2015
ea5b213a 2016 algo = intel_sdvo->base.i2c_bus->algo;
619ac3b7 2017
ea5b213a 2018 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
619ac3b7
ML		 2019 return algo->master_xfer(i2c_adap, msgs, num);
2020}
2021
2022static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2023 .master_xfer = intel_sdvo_master_xfer,
2024};
2025
714605e4 2026static u8
c751ce4f 2027intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2028{
2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030 struct sdvo_device_mapping *my_mapping, *other_mapping;
2031
461ed3ca 2032 if (IS_SDVOB(sdvo_reg)) {
714605e4 2033 my_mapping = &dev_priv->sdvo_mappings[0];
2034 other_mapping = &dev_priv->sdvo_mappings[1];
2035 } else {
2036 my_mapping = &dev_priv->sdvo_mappings[1];
2037 other_mapping = &dev_priv->sdvo_mappings[0];
2038 }
2039
2040 /* If the BIOS described our SDVO device, take advantage of it. */
2041 if (my_mapping->slave_addr)
2042 return my_mapping->slave_addr;
2043
2044 /* If the BIOS only described a different SDVO device, use the
2045 * address that it isn't using.
2046 */
2047 if (other_mapping->slave_addr) {
2048 if (other_mapping->slave_addr == 0x70)
2049 return 0x72;
2050 else
2051 return 0x70;
2052 }
2053
2054 /* No SDVO device info is found for another DVO port,
2055 * so use mapping assumption we had before BIOS parsing.
2056 */
461ed3ca 2057 if (IS_SDVOB(sdvo_reg))
714605e4 2058 return 0x70;
2059 else
2060 return 0x72;
2061}
2062
14571b4c 2063static void
df0e9248
CW		 2064intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2065 struct intel_sdvo *encoder)
14571b4c 2066{
df0e9248
CW		 2067 drm_connector_init(encoder->base.base.dev,
2068 &connector->base.base,
2069 &intel_sdvo_connector_funcs,
2070 connector->base.base.connector_type);
6070a4a9 2071
df0e9248
CW		 2072 drm_connector_helper_add(&connector->base.base,
2073 &intel_sdvo_connector_helper_funcs);
14571b4c 2074
df0e9248
CW		 2075 connector->base.base.interlace_allowed = 0;
2076 connector->base.base.doublescan_allowed = 0;
2077 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2078
df0e9248
CW		 2079 intel_connector_attach_encoder(&connector->base, &encoder->base);
2080 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2081}
6070a4a9 2082
fb7a46f3 2083static bool
ea5b213a 2084intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2085{
4ef69c7a 2086 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c
ZW		 2087 struct drm_connector *connector;
2088 struct intel_connector *intel_connector;
615fb93f 2089 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2090
615fb93f
CW		 2091 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2092 if (!intel_sdvo_connector)
14571b4c
ZW		 2093 return false;
2094
14571b4c 2095 if (device == 0) {
ea5b213a 2096 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2097 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2098 } else if (device == 1) {
ea5b213a 2099 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2100 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2101 }
2102
615fb93f 2103 intel_connector = &intel_sdvo_connector->base;
14571b4c 2104 connector = &intel_connector->base;
eb1f8e4f 2105 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2106 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2107 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2108
ea5b213a
CW		 2109 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2110 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2111 && intel_sdvo->is_hdmi) {
14571b4c 2112 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2113 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2114 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2115 SDVO_COLORIMETRY_RGB256);
2116 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2117 }
ea5b213a
CW		 2118 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2119 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2120
df0e9248 2121 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c
ZW		 2122
2123 return true;
2124}
2125
2126static bool
ea5b213a 2127intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2128{
4ef69c7a
CW		 2129 struct drm_encoder *encoder = &intel_sdvo->base.base;
2130 struct drm_connector *connector;
2131 struct intel_connector *intel_connector;
2132 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2133
615fb93f
CW		 2134 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2135 if (!intel_sdvo_connector)
2136 return false;
14571b4c 2137
615fb93f 2138 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2139 connector = &intel_connector->base;
2140 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2141 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2142
4ef69c7a
CW		 2143 intel_sdvo->controlled_output |= type;
2144 intel_sdvo_connector->output_flag = type;
14571b4c 2145
4ef69c7a
CW		 2146 intel_sdvo->is_tv = true;
2147 intel_sdvo->base.needs_tv_clock = true;
2148 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2149
df0e9248 2150 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2151
4ef69c7a 2152 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2153 goto err;
14571b4c 2154
4ef69c7a 2155 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2156 goto err;
14571b4c 2157
4ef69c7a 2158 return true;
32aad86f
CW		 2159
2160err:
fcc8d672 2161 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2162 kfree(intel_sdvo_connector);
2163 return false;
14571b4c
ZW		 2164}
2165
2166static bool
ea5b213a 2167intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2168{
4ef69c7a
CW		 2169 struct drm_encoder *encoder = &intel_sdvo->base.base;
2170 struct drm_connector *connector;
2171 struct intel_connector *intel_connector;
2172 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2173
615fb93f
CW		 2174 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2175 if (!intel_sdvo_connector)
2176 return false;
14571b4c 2177
615fb93f 2178 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2179 connector = &intel_connector->base;
eb1f8e4f 2180 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2181 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2182 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2183
2184 if (device == 0) {
2185 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2186 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2187 } else if (device == 1) {
2188 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2189 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2190 }
2191
2192 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2193 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2194
df0e9248
CW		 2195 intel_sdvo_connector_init(intel_sdvo_connector,
2196 intel_sdvo);
4ef69c7a 2197 return true;
14571b4c
ZW		 2198}
2199
2200static bool
ea5b213a 2201intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2202{
4ef69c7a
CW		 2203 struct drm_encoder *encoder = &intel_sdvo->base.base;
2204 struct drm_connector *connector;
2205 struct intel_connector *intel_connector;
2206 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2207
615fb93f
CW		 2208 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2209 if (!intel_sdvo_connector)
2210 return false;
14571b4c 2211
615fb93f
CW		 2212 intel_connector = &intel_sdvo_connector->base;
2213 connector = &intel_connector->base;
4ef69c7a
CW		 2214 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2215 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2216
2217 if (device == 0) {
2218 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2219 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2220 } else if (device == 1) {
2221 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2222 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2223 }
2224
2225 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2226 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2227
df0e9248 2228 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2229 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2230 goto err;
2231
2232 return true;
2233
2234err:
fcc8d672 2235 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2236 kfree(intel_sdvo_connector);
2237 return false;
14571b4c
ZW		 2238}
2239
2240static bool
ea5b213a 2241intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2242{
ea5b213a
CW		 2243 intel_sdvo->is_tv = false;
2244 intel_sdvo->base.needs_tv_clock = false;
2245 intel_sdvo->is_lvds = false;
fb7a46f3 2246
14571b4c 2247 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2248
14571b4c 2249 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2250 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2251 return false;
2252
2253 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2254 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2255 return false;
2256
2257 /* TV has no XXX1 function block */
a1f4b7ff 2258 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2259 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2260 return false;
2261
2262 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2263 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2264 return false;
fb7a46f3 2265
14571b4c 2266 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2267 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2268 return false;
2269
2270 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2271 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2272 return false;
2273
2274 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2275 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2276 return false;
2277
2278 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2279 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2280 return false;
fb7a46f3 2281
14571b4c 2282 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2283 unsigned char bytes[2];
2284
ea5b213a
CW		 2285 intel_sdvo->controlled_output = 0;
2286 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2287 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2288 SDVO_NAME(intel_sdvo),
51c8b407 2289 bytes[0], bytes[1]);
14571b4c 2290 return false;
fb7a46f3 2291 }
ea5b213a 2292 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2293
14571b4c 2294 return true;
fb7a46f3 2295}
2296
32aad86f
CW		 2297static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2298 struct intel_sdvo_connector *intel_sdvo_connector,
2299 int type)
ce6feabd 2300{
4ef69c7a 2301 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2302 struct intel_sdvo_tv_format format;
2303 uint32_t format_map, i;
ce6feabd 2304
32aad86f
CW		 2305 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2306 return false;
ce6feabd 2307
32aad86f
CW		 2308 if (!intel_sdvo_get_value(intel_sdvo,
2309 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2310 &format, sizeof(format)))
2311 return false;
ce6feabd 2312
32aad86f 2313 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2314
2315 if (format_map == 0)
32aad86f 2316 return false;
ce6feabd 2317
615fb93f 2318 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2319 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2320 if (format_map & (1 << i))
2321 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2322
2323
c5521706 2324 intel_sdvo_connector->tv_format =
32aad86f
CW		 2325 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2326 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2327 if (!intel_sdvo_connector->tv_format)
fcc8d672 2328 return false;
ce6feabd 2329
615fb93f 2330 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2331 drm_property_add_enum(
c5521706 2332 intel_sdvo_connector->tv_format, i,
40039750 2333 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2334
40039750 2335 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2336 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2337 intel_sdvo_connector->tv_format, 0);
32aad86f 2338 return true;
ce6feabd
ZY		 2339
2340}
2341
c5521706
CW		 2342#define ENHANCEMENT(name, NAME) do { \
2343 if (enhancements.name) { \
2344 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2345 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2346 return false; \
2347 intel_sdvo_connector->max_##name = data_value[0]; \
2348 intel_sdvo_connector->cur_##name = response; \
2349 intel_sdvo_connector->name = \
2350 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2351 if (!intel_sdvo_connector->name) return false; \
2352 intel_sdvo_connector->name->values[0] = 0; \
2353 intel_sdvo_connector->name->values[1] = data_value[0]; \
2354 drm_connector_attach_property(connector, \
2355 intel_sdvo_connector->name, \
2356 intel_sdvo_connector->cur_##name); \
2357 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2358 data_value[0], data_value[1], response); \
2359 } \
2360} while(0)
2361
2362static bool
2363intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2364 struct intel_sdvo_connector *intel_sdvo_connector,
2365 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2366{
4ef69c7a 2367 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2368 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2369 uint16_t response, data_value[2];
2370
c5521706
CW		 2371 /* when horizontal overscan is supported, Add the left/right property */
2372 if (enhancements.overscan_h) {
2373 if (!intel_sdvo_get_value(intel_sdvo,
2374 SDVO_CMD_GET_MAX_OVERSCAN_H,
2375 &data_value, 4))
2376 return false;
32aad86f 2377
c5521706
CW		 2378 if (!intel_sdvo_get_value(intel_sdvo,
2379 SDVO_CMD_GET_OVERSCAN_H,
2380 &response, 2))
2381 return false;
fcc8d672 2382
c5521706
CW		 2383 intel_sdvo_connector->max_hscan = data_value[0];
2384 intel_sdvo_connector->left_margin = data_value[0] - response;
2385 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2386 intel_sdvo_connector->left =
2387 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2388 "left_margin", 2);
2389 if (!intel_sdvo_connector->left)
2390 return false;
fcc8d672 2391
c5521706
CW		 2392 intel_sdvo_connector->left->values[0] = 0;
2393 intel_sdvo_connector->left->values[1] = data_value[0];
2394 drm_connector_attach_property(connector,
2395 intel_sdvo_connector->left,
2396 intel_sdvo_connector->left_margin);
fcc8d672 2397
c5521706
CW		 2398 intel_sdvo_connector->right =
2399 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2400 "right_margin", 2);
2401 if (!intel_sdvo_connector->right)
2402 return false;
32aad86f 2403
c5521706
CW		 2404 intel_sdvo_connector->right->values[0] = 0;
2405 intel_sdvo_connector->right->values[1] = data_value[0];
2406 drm_connector_attach_property(connector,
2407 intel_sdvo_connector->right,
2408 intel_sdvo_connector->right_margin);
2409 DRM_DEBUG_KMS("h_overscan: max %d, "
2410 "default %d, current %d\n",
2411 data_value[0], data_value[1], response);
2412 }
32aad86f 2413
c5521706
CW		 2414 if (enhancements.overscan_v) {
2415 if (!intel_sdvo_get_value(intel_sdvo,
2416 SDVO_CMD_GET_MAX_OVERSCAN_V,
2417 &data_value, 4))
2418 return false;
fcc8d672 2419
c5521706
CW		 2420 if (!intel_sdvo_get_value(intel_sdvo,
2421 SDVO_CMD_GET_OVERSCAN_V,
2422 &response, 2))
2423 return false;
32aad86f 2424
c5521706
CW		 2425 intel_sdvo_connector->max_vscan = data_value[0];
2426 intel_sdvo_connector->top_margin = data_value[0] - response;
2427 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2428 intel_sdvo_connector->top =
2429 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2430 "top_margin", 2);
2431 if (!intel_sdvo_connector->top)
2432 return false;
32aad86f 2433
c5521706
CW		 2434 intel_sdvo_connector->top->values[0] = 0;
2435 intel_sdvo_connector->top->values[1] = data_value[0];
2436 drm_connector_attach_property(connector,
2437 intel_sdvo_connector->top,
2438 intel_sdvo_connector->top_margin);
fcc8d672 2439
c5521706
CW		 2440 intel_sdvo_connector->bottom =
2441 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2442 "bottom_margin", 2);
2443 if (!intel_sdvo_connector->bottom)
2444 return false;
32aad86f 2445
c5521706
CW		 2446 intel_sdvo_connector->bottom->values[0] = 0;
2447 intel_sdvo_connector->bottom->values[1] = data_value[0];
2448 drm_connector_attach_property(connector,
2449 intel_sdvo_connector->bottom,
2450 intel_sdvo_connector->bottom_margin);
2451 DRM_DEBUG_KMS("v_overscan: max %d, "
2452 "default %d, current %d\n",
2453 data_value[0], data_value[1], response);
2454 }
32aad86f 2455
c5521706
CW		 2456 ENHANCEMENT(hpos, HPOS);
2457 ENHANCEMENT(vpos, VPOS);
2458 ENHANCEMENT(saturation, SATURATION);
2459 ENHANCEMENT(contrast, CONTRAST);
2460 ENHANCEMENT(hue, HUE);
2461 ENHANCEMENT(sharpness, SHARPNESS);
2462 ENHANCEMENT(brightness, BRIGHTNESS);
2463 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2464 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2465 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2466 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2467 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2468
e044218a
CW		 2469 if (enhancements.dot_crawl) {
2470 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2471 return false;
2472
2473 intel_sdvo_connector->max_dot_crawl = 1;
2474 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2475 intel_sdvo_connector->dot_crawl =
2476 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2477 if (!intel_sdvo_connector->dot_crawl)
2478 return false;
2479
2480 intel_sdvo_connector->dot_crawl->values[0] = 0;
2481 intel_sdvo_connector->dot_crawl->values[1] = 1;
2482 drm_connector_attach_property(connector,
2483 intel_sdvo_connector->dot_crawl,
2484 intel_sdvo_connector->cur_dot_crawl);
2485 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2486 }
2487
c5521706
CW		 2488 return true;
2489}
32aad86f 2490
c5521706
CW		 2491static bool
2492intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2493 struct intel_sdvo_connector *intel_sdvo_connector,
2494 struct intel_sdvo_enhancements_reply enhancements)
2495{
4ef69c7a 2496 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2497 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2498 uint16_t response, data_value[2];
32aad86f 2499
c5521706 2500 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2501
c5521706
CW		 2502 return true;
2503}
2504#undef ENHANCEMENT
32aad86f 2505
c5521706
CW		 2506static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2507 struct intel_sdvo_connector *intel_sdvo_connector)
2508{
2509 union {
2510 struct intel_sdvo_enhancements_reply reply;
2511 uint16_t response;
2512 } enhancements;
32aad86f 2513
c5521706
CW		 2514 if (!intel_sdvo_get_value(intel_sdvo,
2515 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2516 &enhancements, sizeof(enhancements)))
2517 return false;
fcc8d672 2518
c5521706
CW		 2519 if (enhancements.response == 0) {
2520 DRM_DEBUG_KMS("No enhancement is supported\n");
2521 return true;
b9219c5e 2522 }
32aad86f 2523
c5521706
CW		 2524 if (IS_TV(intel_sdvo_connector))
2525 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2526 else if(IS_LVDS(intel_sdvo_connector))
2527 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2528 else
2529 return true;
fcc8d672 2530
b9219c5e
ZY		 2531}
2532
c751ce4f 2533bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2534{
b01f2c3a 2535 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2536 struct intel_encoder *intel_encoder;
ea5b213a 2537 struct intel_sdvo *intel_sdvo;
79e53945
JB		 2538 u8 ch[0x40];
2539 int i;
461ed3ca 2540 u32 i2c_reg, ddc_reg, analog_ddc_reg;
79e53945 2541
ea5b213a
CW		 2542 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2543 if (!intel_sdvo)
7d57382e 2544 return false;
79e53945 2545
ea5b213a 2546 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2547
ea5b213a 2548 intel_encoder = &intel_sdvo->base;
21d40d37 2549 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2550
461ed3ca
ZY		 2551 if (HAS_PCH_SPLIT(dev)) {
2552 i2c_reg = PCH_GPIOE;
2553 ddc_reg = PCH_GPIOE;
2554 analog_ddc_reg = PCH_GPIOA;
2555 } else {
2556 i2c_reg = GPIOE;
2557 ddc_reg = GPIOE;
2558 analog_ddc_reg = GPIOA;
2559 }
2560
79e53945 2561 /* setup the DDC bus. */
461ed3ca
ZY		 2562 if (IS_SDVOB(sdvo_reg))
2563 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
308cd3a2 2564 else
461ed3ca 2565 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
308cd3a2 2566
21d40d37 2567 if (!intel_encoder->i2c_bus)
ad5b2a6d 2568 goto err_inteloutput;
79e53945 2569
ea5b213a 2570 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2571
308cd3a2 2572 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2573 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2574
79e53945
JB		 2575 /* Read the regs to test if we can talk to the device */
2576 for (i = 0; i < 0x40; i++) {
ea5b213a 2577 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
8a4c47f3 2578 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2579 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2580 goto err_i2c;
2581 }
2582 }
2583
619ac3b7 2584 /* setup the DDC bus. */
461ed3ca
ZY		 2585 if (IS_SDVOB(sdvo_reg)) {
2586 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
ea5b213a 2587 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2588 "SDVOB/VGA DDC BUS");
b01f2c3a 2589 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2590 } else {
461ed3ca 2591 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
ea5b213a 2592 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2593 "SDVOC/VGA DDC BUS");
b01f2c3a 2594 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2595 }
32aad86f 2596 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
619ac3b7
ML		 2597 goto err_i2c;
2598
308cd3a2 2599 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2600 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2601
14571b4c 2602 /* encoder type will be decided later */
4ef69c7a
CW		 2603 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2604 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2605
af901ca1 2606 /* In default case sdvo lvds is false */
32aad86f
CW		 2607 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2608 goto err_enc;
79e53945 2609
ea5b213a
CW		 2610 if (intel_sdvo_output_setup(intel_sdvo,
2611 intel_sdvo->caps.output_flags) != true) {
51c8b407 2612 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2613 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
32aad86f 2614 goto err_enc;
79e53945
JB		 2615 }
2616
ea5b213a 2617 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2618
79e53945 2619 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 2620 if (!intel_sdvo_set_target_input(intel_sdvo))
2621 goto err_enc;
79e53945 2622
32aad86f
CW		 2623 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2624 &intel_sdvo->pixel_clock_min,
2625 &intel_sdvo->pixel_clock_max))
2626 goto err_enc;
79e53945 2627
8a4c47f3 2628 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2629 "clock range %dMHz - %dMHz, "
2630 "input 1: %c, input 2: %c, "
2631 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2632 SDVO_NAME(intel_sdvo),
2633 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2634 intel_sdvo->caps.device_rev_id,
2635 intel_sdvo->pixel_clock_min / 1000,
2636 intel_sdvo->pixel_clock_max / 1000,
2637 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2638 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2639 /* check currently supported outputs */
ea5b213a 2640 intel_sdvo->caps.output_flags &
79e53945 2641 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2642 intel_sdvo->caps.output_flags &
79e53945 2643 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2644 return true;
79e53945 2645
32aad86f 2646err_enc:
4ef69c7a 2647 drm_encoder_cleanup(&intel_encoder->base);
79e53945 2648err_i2c:
ea5b213a
CW		 2649 if (intel_sdvo->analog_ddc_bus != NULL)
2650 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
21d40d37
EA		 2651 if (intel_encoder->ddc_bus != NULL)
2652 intel_i2c_destroy(intel_encoder->ddc_bus);
2653 if (intel_encoder->i2c_bus != NULL)
2654 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2655err_inteloutput:
ea5b213a 2656 kfree(intel_sdvo);
79e53945 2657
7d57382e 2658 return false;
79e53945 2659}
Linux kernel - Deliverables
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