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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
79e53945 | 30 | #include <linux/delay.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 | 32 | #include <drm/drmP.h> |
c6f95f27 | 33 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
34 | #include <drm/drm_crtc.h> |
35 | #include <drm/drm_edid.h> | |
ea5b213a | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 JB |
38 | #include "i915_drv.h" |
39 | #include "intel_sdvo_regs.h" | |
40 | ||
14571b4c ZW |
41 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
42 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) | |
43 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) | |
a0b1c7a5 | 44 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
14571b4c ZW |
45 | |
46 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ | |
0206e353 | 47 | SDVO_TV_MASK) |
14571b4c ZW |
48 | |
49 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) | |
13946743 | 50 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
14571b4c | 51 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
32aad86f | 52 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
52220085 | 53 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
14571b4c | 54 | |
79e53945 | 55 | |
4d9194de | 56 | static const char * const tv_format_names[] = { |
ce6feabd ZY |
57 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
58 | "PAL_B" , "PAL_D" , "PAL_G" , | |
59 | "PAL_H" , "PAL_I" , "PAL_M" , | |
60 | "PAL_N" , "PAL_NC" , "PAL_60" , | |
61 | "SECAM_B" , "SECAM_D" , "SECAM_G" , | |
62 | "SECAM_K" , "SECAM_K1", "SECAM_L" , | |
63 | "SECAM_60" | |
64 | }; | |
65 | ||
53abb679 | 66 | #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) |
ce6feabd | 67 | |
ea5b213a CW |
68 | struct intel_sdvo { |
69 | struct intel_encoder base; | |
70 | ||
f899fc64 | 71 | struct i2c_adapter *i2c; |
f9c10a9b | 72 | u8 slave_addr; |
e2f0ba97 | 73 | |
e957d772 CW |
74 | struct i2c_adapter ddc; |
75 | ||
e2f0ba97 | 76 | /* Register for the SDVO device: SDVOB or SDVOC */ |
eef4eacb | 77 | uint32_t sdvo_reg; |
79e53945 | 78 | |
e2f0ba97 JB |
79 | /* Active outputs controlled by this SDVO output */ |
80 | uint16_t controlled_output; | |
79e53945 | 81 | |
e2f0ba97 JB |
82 | /* |
83 | * Capabilities of the SDVO device returned by | |
19d415a2 | 84 | * intel_sdvo_get_capabilities() |
e2f0ba97 | 85 | */ |
79e53945 | 86 | struct intel_sdvo_caps caps; |
e2f0ba97 JB |
87 | |
88 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
79e53945 JB |
89 | int pixel_clock_min, pixel_clock_max; |
90 | ||
fb7a46f3 | 91 | /* |
92 | * For multiple function SDVO device, | |
93 | * this is for current attached outputs. | |
94 | */ | |
95 | uint16_t attached_output; | |
96 | ||
cc68c81a SF |
97 | /* |
98 | * Hotplug activation bits for this device | |
99 | */ | |
5fa7ac9c | 100 | uint16_t hotplug_active; |
cc68c81a | 101 | |
e953fd7b CW |
102 | /** |
103 | * This is used to select the color range of RBG outputs in HDMI mode. | |
104 | * It is only valid when using TMDS encoding and 8 bit per color mode. | |
105 | */ | |
106 | uint32_t color_range; | |
55bc60db | 107 | bool color_range_auto; |
e953fd7b | 108 | |
7949dd47 VS |
109 | /** |
110 | * HDMI user specified aspect ratio | |
111 | */ | |
112 | enum hdmi_picture_aspect aspect_ratio; | |
113 | ||
e2f0ba97 JB |
114 | /** |
115 | * This is set if we're going to treat the device as TV-out. | |
116 | * | |
117 | * While we have these nice friendly flags for output types that ought | |
118 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
119 | * shows up as RGB1 (VGA). | |
120 | */ | |
121 | bool is_tv; | |
122 | ||
eef4eacb DV |
123 | /* On different gens SDVOB is at different places. */ |
124 | bool is_sdvob; | |
125 | ||
ce6feabd | 126 | /* This is for current tv format name */ |
40039750 | 127 | int tv_format_index; |
ce6feabd | 128 | |
e2f0ba97 JB |
129 | /** |
130 | * This is set if we treat the device as HDMI, instead of DVI. | |
131 | */ | |
132 | bool is_hdmi; | |
da79de97 CW |
133 | bool has_hdmi_monitor; |
134 | bool has_hdmi_audio; | |
abedc077 | 135 | bool rgb_quant_range_selectable; |
12682a97 | 136 | |
7086c87f | 137 | /** |
6c9547ff CW |
138 | * This is set if we detect output of sdvo device as LVDS and |
139 | * have a valid fixed mode to use with the panel. | |
7086c87f ML |
140 | */ |
141 | bool is_lvds; | |
e2f0ba97 | 142 | |
12682a97 | 143 | /** |
144 | * This is sdvo fixed pannel mode pointer | |
145 | */ | |
146 | struct drm_display_mode *sdvo_lvds_fixed_mode; | |
147 | ||
c751ce4f | 148 | /* DDC bus used by this SDVO encoder */ |
e2f0ba97 | 149 | uint8_t ddc_bus; |
e751823d EE |
150 | |
151 | /* | |
152 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd | |
153 | */ | |
154 | uint8_t dtd_sdvo_flags; | |
14571b4c ZW |
155 | }; |
156 | ||
157 | struct intel_sdvo_connector { | |
615fb93f CW |
158 | struct intel_connector base; |
159 | ||
14571b4c ZW |
160 | /* Mark the type of connector */ |
161 | uint16_t output_flag; | |
162 | ||
c3e5f67b | 163 | enum hdmi_force_audio force_audio; |
7f36e7ed | 164 | |
14571b4c | 165 | /* This contains all current supported TV format */ |
40039750 | 166 | u8 tv_format_supported[TV_FORMAT_NUM]; |
14571b4c | 167 | int format_supported_num; |
c5521706 | 168 | struct drm_property *tv_format; |
14571b4c | 169 | |
b9219c5e | 170 | /* add the property for the SDVO-TV */ |
c5521706 CW |
171 | struct drm_property *left; |
172 | struct drm_property *right; | |
173 | struct drm_property *top; | |
174 | struct drm_property *bottom; | |
175 | struct drm_property *hpos; | |
176 | struct drm_property *vpos; | |
177 | struct drm_property *contrast; | |
178 | struct drm_property *saturation; | |
179 | struct drm_property *hue; | |
180 | struct drm_property *sharpness; | |
181 | struct drm_property *flicker_filter; | |
182 | struct drm_property *flicker_filter_adaptive; | |
183 | struct drm_property *flicker_filter_2d; | |
184 | struct drm_property *tv_chroma_filter; | |
185 | struct drm_property *tv_luma_filter; | |
e044218a | 186 | struct drm_property *dot_crawl; |
b9219c5e ZY |
187 | |
188 | /* add the property for the SDVO-TV/LVDS */ | |
c5521706 | 189 | struct drm_property *brightness; |
b9219c5e ZY |
190 | |
191 | /* Add variable to record current setting for the above property */ | |
192 | u32 left_margin, right_margin, top_margin, bottom_margin; | |
c5521706 | 193 | |
b9219c5e ZY |
194 | /* this is to get the range of margin.*/ |
195 | u32 max_hscan, max_vscan; | |
196 | u32 max_hpos, cur_hpos; | |
197 | u32 max_vpos, cur_vpos; | |
198 | u32 cur_brightness, max_brightness; | |
199 | u32 cur_contrast, max_contrast; | |
200 | u32 cur_saturation, max_saturation; | |
201 | u32 cur_hue, max_hue; | |
c5521706 CW |
202 | u32 cur_sharpness, max_sharpness; |
203 | u32 cur_flicker_filter, max_flicker_filter; | |
204 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; | |
205 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; | |
206 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; | |
207 | u32 cur_tv_luma_filter, max_tv_luma_filter; | |
e044218a | 208 | u32 cur_dot_crawl, max_dot_crawl; |
79e53945 JB |
209 | }; |
210 | ||
8aca63aa | 211 | static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) |
ea5b213a | 212 | { |
8aca63aa | 213 | return container_of(encoder, struct intel_sdvo, base); |
ea5b213a CW |
214 | } |
215 | ||
df0e9248 CW |
216 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
217 | { | |
8aca63aa | 218 | return to_sdvo(intel_attached_encoder(connector)); |
df0e9248 CW |
219 | } |
220 | ||
615fb93f CW |
221 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
222 | { | |
223 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); | |
224 | } | |
225 | ||
fb7a46f3 | 226 | static bool |
ea5b213a | 227 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
32aad86f CW |
228 | static bool |
229 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | |
230 | struct intel_sdvo_connector *intel_sdvo_connector, | |
231 | int type); | |
232 | static bool | |
233 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, | |
234 | struct intel_sdvo_connector *intel_sdvo_connector); | |
fb7a46f3 | 235 | |
79e53945 JB |
236 | /** |
237 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
238 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
239 | * comments in the BIOS). | |
240 | */ | |
ea5b213a | 241 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
79e53945 | 242 | { |
4ef69c7a | 243 | struct drm_device *dev = intel_sdvo->base.base.dev; |
79e53945 | 244 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
245 | u32 bval = val, cval = val; |
246 | int i; | |
247 | ||
ea5b213a CW |
248 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
249 | I915_WRITE(intel_sdvo->sdvo_reg, val); | |
abab6311 | 250 | POSTING_READ(intel_sdvo->sdvo_reg); |
e8504ee2 VS |
251 | /* |
252 | * HW workaround, need to write this twice for issue | |
253 | * that may result in first write getting masked. | |
254 | */ | |
255 | if (HAS_PCH_IBX(dev)) { | |
256 | I915_WRITE(intel_sdvo->sdvo_reg, val); | |
257 | POSTING_READ(intel_sdvo->sdvo_reg); | |
258 | } | |
461ed3ca ZY |
259 | return; |
260 | } | |
261 | ||
e2debe91 PZ |
262 | if (intel_sdvo->sdvo_reg == GEN3_SDVOB) |
263 | cval = I915_READ(GEN3_SDVOC); | |
264 | else | |
265 | bval = I915_READ(GEN3_SDVOB); | |
266 | ||
79e53945 JB |
267 | /* |
268 | * Write the registers twice for luck. Sometimes, | |
269 | * writing them only once doesn't appear to 'stick'. | |
270 | * The BIOS does this too. Yay, magic | |
271 | */ | |
272 | for (i = 0; i < 2; i++) | |
273 | { | |
e2debe91 | 274 | I915_WRITE(GEN3_SDVOB, bval); |
abab6311 | 275 | POSTING_READ(GEN3_SDVOB); |
e2debe91 | 276 | I915_WRITE(GEN3_SDVOC, cval); |
abab6311 | 277 | POSTING_READ(GEN3_SDVOC); |
79e53945 JB |
278 | } |
279 | } | |
280 | ||
32aad86f | 281 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
79e53945 | 282 | { |
79e53945 JB |
283 | struct i2c_msg msgs[] = { |
284 | { | |
e957d772 | 285 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
286 | .flags = 0, |
287 | .len = 1, | |
e957d772 | 288 | .buf = &addr, |
79e53945 JB |
289 | }, |
290 | { | |
e957d772 | 291 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
292 | .flags = I2C_M_RD, |
293 | .len = 1, | |
e957d772 | 294 | .buf = ch, |
79e53945 JB |
295 | } |
296 | }; | |
32aad86f | 297 | int ret; |
79e53945 | 298 | |
f899fc64 | 299 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
79e53945 | 300 | return true; |
79e53945 | 301 | |
8a4c47f3 | 302 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
79e53945 JB |
303 | return false; |
304 | } | |
305 | ||
79e53945 JB |
306 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
307 | /** Mapping of command numbers to names, for debug output */ | |
005568be | 308 | static const struct _sdvo_cmd_name { |
e2f0ba97 | 309 | u8 cmd; |
2e88e40b | 310 | const char *name; |
79e53945 | 311 | } sdvo_cmd_names[] = { |
0206e353 AJ |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), | |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), | |
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), | |
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
355 | ||
356 | /* Add the op code for SDVO enhancements */ | |
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), | |
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), | |
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), | |
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), | |
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), | |
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), | |
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), | |
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), | |
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), | |
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), | |
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), | |
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), | |
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), | |
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), | |
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), | |
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), | |
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), | |
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), | |
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), | |
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), | |
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), | |
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), | |
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), | |
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), | |
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), | |
382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), | |
383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), | |
384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), | |
385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), | |
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), | |
387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), | |
388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), | |
389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), | |
390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), | |
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), | |
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), | |
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), | |
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), | |
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), | |
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), | |
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), | |
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), | |
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), | |
400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), | |
401 | ||
402 | /* HDMI op code */ | |
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
409 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
410 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
411 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
412 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
413 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
414 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
415 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
416 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
417 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
418 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
419 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
420 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
421 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
422 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
79e53945 JB |
423 | }; |
424 | ||
eef4eacb | 425 | #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") |
79e53945 | 426 | |
ea5b213a | 427 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
32aad86f | 428 | const void *args, int args_len) |
79e53945 | 429 | { |
84fcb469 DV |
430 | int i, pos = 0; |
431 | #define BUF_LEN 256 | |
432 | char buffer[BUF_LEN]; | |
433 | ||
434 | #define BUF_PRINT(args...) \ | |
435 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) | |
436 | ||
79e53945 | 437 | |
84fcb469 DV |
438 | for (i = 0; i < args_len; i++) { |
439 | BUF_PRINT("%02X ", ((u8 *)args)[i]); | |
440 | } | |
441 | for (; i < 8; i++) { | |
442 | BUF_PRINT(" "); | |
443 | } | |
04ad327f | 444 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
79e53945 | 445 | if (cmd == sdvo_cmd_names[i].cmd) { |
84fcb469 | 446 | BUF_PRINT("(%s)", sdvo_cmd_names[i].name); |
79e53945 JB |
447 | break; |
448 | } | |
449 | } | |
84fcb469 DV |
450 | if (i == ARRAY_SIZE(sdvo_cmd_names)) { |
451 | BUF_PRINT("(%02X)", cmd); | |
452 | } | |
453 | BUG_ON(pos >= BUF_LEN - 1); | |
454 | #undef BUF_PRINT | |
455 | #undef BUF_LEN | |
456 | ||
457 | DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); | |
79e53945 | 458 | } |
79e53945 | 459 | |
4d9194de | 460 | static const char * const cmd_status_names[] = { |
e957d772 CW |
461 | "Power on", |
462 | "Success", | |
463 | "Not supported", | |
464 | "Invalid arg", | |
465 | "Pending", | |
466 | "Target not specified", | |
467 | "Scaling not supported" | |
468 | }; | |
469 | ||
32aad86f CW |
470 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
471 | const void *args, int args_len) | |
79e53945 | 472 | { |
3bf3f452 BW |
473 | u8 *buf, status; |
474 | struct i2c_msg *msgs; | |
475 | int i, ret = true; | |
476 | ||
0274df3e | 477 | /* Would be simpler to allocate both in one go ? */ |
5c67eeb6 | 478 | buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); |
3bf3f452 BW |
479 | if (!buf) |
480 | return false; | |
481 | ||
482 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); | |
0274df3e AC |
483 | if (!msgs) { |
484 | kfree(buf); | |
3bf3f452 | 485 | return false; |
0274df3e | 486 | } |
79e53945 | 487 | |
ea5b213a | 488 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
79e53945 JB |
489 | |
490 | for (i = 0; i < args_len; i++) { | |
e957d772 CW |
491 | msgs[i].addr = intel_sdvo->slave_addr; |
492 | msgs[i].flags = 0; | |
493 | msgs[i].len = 2; | |
494 | msgs[i].buf = buf + 2 *i; | |
495 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; | |
496 | buf[2*i + 1] = ((u8*)args)[i]; | |
497 | } | |
498 | msgs[i].addr = intel_sdvo->slave_addr; | |
499 | msgs[i].flags = 0; | |
500 | msgs[i].len = 2; | |
501 | msgs[i].buf = buf + 2*i; | |
502 | buf[2*i + 0] = SDVO_I2C_OPCODE; | |
503 | buf[2*i + 1] = cmd; | |
504 | ||
505 | /* the following two are to read the response */ | |
506 | status = SDVO_I2C_CMD_STATUS; | |
507 | msgs[i+1].addr = intel_sdvo->slave_addr; | |
508 | msgs[i+1].flags = 0; | |
509 | msgs[i+1].len = 1; | |
510 | msgs[i+1].buf = &status; | |
511 | ||
512 | msgs[i+2].addr = intel_sdvo->slave_addr; | |
513 | msgs[i+2].flags = I2C_M_RD; | |
514 | msgs[i+2].len = 1; | |
515 | msgs[i+2].buf = &status; | |
516 | ||
517 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); | |
518 | if (ret < 0) { | |
519 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); | |
3bf3f452 BW |
520 | ret = false; |
521 | goto out; | |
e957d772 CW |
522 | } |
523 | if (ret != i+3) { | |
524 | /* failure in I2C transfer */ | |
525 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); | |
3bf3f452 | 526 | ret = false; |
e957d772 CW |
527 | } |
528 | ||
3bf3f452 BW |
529 | out: |
530 | kfree(msgs); | |
531 | kfree(buf); | |
532 | return ret; | |
79e53945 JB |
533 | } |
534 | ||
b5c616a7 CW |
535 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
536 | void *response, int response_len) | |
79e53945 | 537 | { |
fc37381c | 538 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
b5c616a7 | 539 | u8 status; |
84fcb469 DV |
540 | int i, pos = 0; |
541 | #define BUF_LEN 256 | |
542 | char buffer[BUF_LEN]; | |
79e53945 | 543 | |
d121a5d2 | 544 | |
b5c616a7 CW |
545 | /* |
546 | * The documentation states that all commands will be | |
547 | * processed within 15µs, and that we need only poll | |
548 | * the status byte a maximum of 3 times in order for the | |
549 | * command to be complete. | |
550 | * | |
551 | * Check 5 times in case the hardware failed to read the docs. | |
fc37381c CW |
552 | * |
553 | * Also beware that the first response by many devices is to | |
554 | * reply PENDING and stall for time. TVs are notorious for | |
555 | * requiring longer than specified to complete their replies. | |
556 | * Originally (in the DDX long ago), the delay was only ever 15ms | |
557 | * with an additional delay of 30ms applied for TVs added later after | |
558 | * many experiments. To accommodate both sets of delays, we do a | |
559 | * sequence of slow checks if the device is falling behind and fails | |
560 | * to reply within 5*15µs. | |
b5c616a7 | 561 | */ |
d121a5d2 CW |
562 | if (!intel_sdvo_read_byte(intel_sdvo, |
563 | SDVO_I2C_CMD_STATUS, | |
564 | &status)) | |
565 | goto log_fail; | |
566 | ||
1ad87e72 | 567 | while ((status == SDVO_CMD_STATUS_PENDING || |
46a3f4a3 | 568 | status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { |
fc37381c CW |
569 | if (retry < 10) |
570 | msleep(15); | |
571 | else | |
572 | udelay(15); | |
573 | ||
b5c616a7 CW |
574 | if (!intel_sdvo_read_byte(intel_sdvo, |
575 | SDVO_I2C_CMD_STATUS, | |
576 | &status)) | |
d121a5d2 CW |
577 | goto log_fail; |
578 | } | |
b5c616a7 | 579 | |
84fcb469 DV |
580 | #define BUF_PRINT(args...) \ |
581 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) | |
582 | ||
79e53945 | 583 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
84fcb469 | 584 | BUF_PRINT("(%s)", cmd_status_names[status]); |
79e53945 | 585 | else |
84fcb469 | 586 | BUF_PRINT("(??? %d)", status); |
79e53945 | 587 | |
b5c616a7 CW |
588 | if (status != SDVO_CMD_STATUS_SUCCESS) |
589 | goto log_fail; | |
79e53945 | 590 | |
b5c616a7 CW |
591 | /* Read the command response */ |
592 | for (i = 0; i < response_len; i++) { | |
593 | if (!intel_sdvo_read_byte(intel_sdvo, | |
594 | SDVO_I2C_RETURN_0 + i, | |
595 | &((u8 *)response)[i])) | |
596 | goto log_fail; | |
84fcb469 | 597 | BUF_PRINT(" %02X", ((u8 *)response)[i]); |
b5c616a7 | 598 | } |
84fcb469 DV |
599 | BUG_ON(pos >= BUF_LEN - 1); |
600 | #undef BUF_PRINT | |
601 | #undef BUF_LEN | |
602 | ||
603 | DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); | |
b5c616a7 | 604 | return true; |
79e53945 | 605 | |
b5c616a7 | 606 | log_fail: |
84fcb469 | 607 | DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); |
b5c616a7 | 608 | return false; |
79e53945 JB |
609 | } |
610 | ||
5e7234c9 | 611 | static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) |
79e53945 | 612 | { |
aad941d5 | 613 | if (adjusted_mode->crtc_clock >= 100000) |
79e53945 | 614 | return 1; |
aad941d5 | 615 | else if (adjusted_mode->crtc_clock >= 50000) |
79e53945 JB |
616 | return 2; |
617 | else | |
618 | return 4; | |
619 | } | |
620 | ||
e957d772 CW |
621 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
622 | u8 ddc_bus) | |
79e53945 | 623 | { |
d121a5d2 | 624 | /* This must be the immediately preceding write before the i2c xfer */ |
e957d772 CW |
625 | return intel_sdvo_write_cmd(intel_sdvo, |
626 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, | |
627 | &ddc_bus, 1); | |
79e53945 JB |
628 | } |
629 | ||
32aad86f | 630 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
79e53945 | 631 | { |
d121a5d2 CW |
632 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
633 | return false; | |
634 | ||
635 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); | |
32aad86f | 636 | } |
79e53945 | 637 | |
32aad86f CW |
638 | static bool |
639 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) | |
640 | { | |
641 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) | |
642 | return false; | |
79e53945 | 643 | |
32aad86f CW |
644 | return intel_sdvo_read_response(intel_sdvo, value, len); |
645 | } | |
79e53945 | 646 | |
32aad86f CW |
647 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
648 | { | |
649 | struct intel_sdvo_set_target_input_args targets = {0}; | |
650 | return intel_sdvo_set_value(intel_sdvo, | |
651 | SDVO_CMD_SET_TARGET_INPUT, | |
652 | &targets, sizeof(targets)); | |
79e53945 JB |
653 | } |
654 | ||
655 | /** | |
656 | * Return whether each input is trained. | |
657 | * | |
658 | * This function is making an assumption about the layout of the response, | |
659 | * which should be checked against the docs. | |
660 | */ | |
ea5b213a | 661 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
79e53945 JB |
662 | { |
663 | struct intel_sdvo_get_trained_inputs_response response; | |
79e53945 | 664 | |
1a3665c8 | 665 | BUILD_BUG_ON(sizeof(response) != 1); |
32aad86f CW |
666 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
667 | &response, sizeof(response))) | |
79e53945 JB |
668 | return false; |
669 | ||
670 | *input_1 = response.input0_trained; | |
671 | *input_2 = response.input1_trained; | |
672 | return true; | |
673 | } | |
674 | ||
ea5b213a | 675 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
676 | u16 outputs) |
677 | { | |
32aad86f CW |
678 | return intel_sdvo_set_value(intel_sdvo, |
679 | SDVO_CMD_SET_ACTIVE_OUTPUTS, | |
680 | &outputs, sizeof(outputs)); | |
79e53945 JB |
681 | } |
682 | ||
4ac41f47 DV |
683 | static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
684 | u16 *outputs) | |
685 | { | |
686 | return intel_sdvo_get_value(intel_sdvo, | |
687 | SDVO_CMD_GET_ACTIVE_OUTPUTS, | |
688 | outputs, sizeof(*outputs)); | |
689 | } | |
690 | ||
ea5b213a | 691 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
692 | int mode) |
693 | { | |
32aad86f | 694 | u8 state = SDVO_ENCODER_STATE_ON; |
79e53945 JB |
695 | |
696 | switch (mode) { | |
697 | case DRM_MODE_DPMS_ON: | |
698 | state = SDVO_ENCODER_STATE_ON; | |
699 | break; | |
700 | case DRM_MODE_DPMS_STANDBY: | |
701 | state = SDVO_ENCODER_STATE_STANDBY; | |
702 | break; | |
703 | case DRM_MODE_DPMS_SUSPEND: | |
704 | state = SDVO_ENCODER_STATE_SUSPEND; | |
705 | break; | |
706 | case DRM_MODE_DPMS_OFF: | |
707 | state = SDVO_ENCODER_STATE_OFF; | |
708 | break; | |
709 | } | |
710 | ||
32aad86f CW |
711 | return intel_sdvo_set_value(intel_sdvo, |
712 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); | |
79e53945 JB |
713 | } |
714 | ||
ea5b213a | 715 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
716 | int *clock_min, |
717 | int *clock_max) | |
718 | { | |
719 | struct intel_sdvo_pixel_clock_range clocks; | |
79e53945 | 720 | |
1a3665c8 | 721 | BUILD_BUG_ON(sizeof(clocks) != 4); |
32aad86f CW |
722 | if (!intel_sdvo_get_value(intel_sdvo, |
723 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
724 | &clocks, sizeof(clocks))) | |
79e53945 JB |
725 | return false; |
726 | ||
727 | /* Convert the values from units of 10 kHz to kHz. */ | |
728 | *clock_min = clocks.min * 10; | |
729 | *clock_max = clocks.max * 10; | |
79e53945 JB |
730 | return true; |
731 | } | |
732 | ||
ea5b213a | 733 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
734 | u16 outputs) |
735 | { | |
32aad86f CW |
736 | return intel_sdvo_set_value(intel_sdvo, |
737 | SDVO_CMD_SET_TARGET_OUTPUT, | |
738 | &outputs, sizeof(outputs)); | |
79e53945 JB |
739 | } |
740 | ||
ea5b213a | 741 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
79e53945 JB |
742 | struct intel_sdvo_dtd *dtd) |
743 | { | |
32aad86f CW |
744 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
745 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
79e53945 JB |
746 | } |
747 | ||
045ac3b5 JB |
748 | static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
749 | struct intel_sdvo_dtd *dtd) | |
750 | { | |
751 | return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && | |
752 | intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
753 | } | |
754 | ||
ea5b213a | 755 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
756 | struct intel_sdvo_dtd *dtd) |
757 | { | |
ea5b213a | 758 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
759 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
760 | } | |
761 | ||
ea5b213a | 762 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
763 | struct intel_sdvo_dtd *dtd) |
764 | { | |
ea5b213a | 765 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
766 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
767 | } | |
768 | ||
045ac3b5 JB |
769 | static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, |
770 | struct intel_sdvo_dtd *dtd) | |
771 | { | |
772 | return intel_sdvo_get_timing(intel_sdvo, | |
773 | SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); | |
774 | } | |
775 | ||
e2f0ba97 | 776 | static bool |
ea5b213a | 777 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
778 | uint16_t clock, |
779 | uint16_t width, | |
780 | uint16_t height) | |
781 | { | |
782 | struct intel_sdvo_preferred_input_timing_args args; | |
e2f0ba97 | 783 | |
e642c6f1 | 784 | memset(&args, 0, sizeof(args)); |
e2f0ba97 JB |
785 | args.clock = clock; |
786 | args.width = width; | |
787 | args.height = height; | |
e642c6f1 | 788 | args.interlace = 0; |
12682a97 | 789 | |
ea5b213a CW |
790 | if (intel_sdvo->is_lvds && |
791 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || | |
792 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) | |
12682a97 | 793 | args.scaled = 1; |
794 | ||
32aad86f CW |
795 | return intel_sdvo_set_value(intel_sdvo, |
796 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, | |
797 | &args, sizeof(args)); | |
e2f0ba97 JB |
798 | } |
799 | ||
ea5b213a | 800 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
801 | struct intel_sdvo_dtd *dtd) |
802 | { | |
1a3665c8 CW |
803 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
804 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); | |
32aad86f CW |
805 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
806 | &dtd->part1, sizeof(dtd->part1)) && | |
807 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
808 | &dtd->part2, sizeof(dtd->part2)); | |
e2f0ba97 | 809 | } |
79e53945 | 810 | |
ea5b213a | 811 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
79e53945 | 812 | { |
32aad86f | 813 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
79e53945 JB |
814 | } |
815 | ||
e2f0ba97 | 816 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
32aad86f | 817 | const struct drm_display_mode *mode) |
79e53945 | 818 | { |
e2f0ba97 JB |
819 | uint16_t width, height; |
820 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
821 | uint16_t h_sync_offset, v_sync_offset; | |
6651819b | 822 | int mode_clock; |
79e53945 | 823 | |
1c4a814e DV |
824 | memset(dtd, 0, sizeof(*dtd)); |
825 | ||
c6ebd4c0 DV |
826 | width = mode->hdisplay; |
827 | height = mode->vdisplay; | |
79e53945 JB |
828 | |
829 | /* do some mode translations */ | |
c6ebd4c0 DV |
830 | h_blank_len = mode->htotal - mode->hdisplay; |
831 | h_sync_len = mode->hsync_end - mode->hsync_start; | |
79e53945 | 832 | |
c6ebd4c0 DV |
833 | v_blank_len = mode->vtotal - mode->vdisplay; |
834 | v_sync_len = mode->vsync_end - mode->vsync_start; | |
79e53945 | 835 | |
c6ebd4c0 DV |
836 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
837 | v_sync_offset = mode->vsync_start - mode->vdisplay; | |
79e53945 | 838 | |
6651819b | 839 | mode_clock = mode->clock; |
6651819b DV |
840 | mode_clock /= 10; |
841 | dtd->part1.clock = mode_clock; | |
842 | ||
e2f0ba97 JB |
843 | dtd->part1.h_active = width & 0xff; |
844 | dtd->part1.h_blank = h_blank_len & 0xff; | |
845 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
79e53945 | 846 | ((h_blank_len >> 8) & 0xf); |
e2f0ba97 JB |
847 | dtd->part1.v_active = height & 0xff; |
848 | dtd->part1.v_blank = v_blank_len & 0xff; | |
849 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
79e53945 JB |
850 | ((v_blank_len >> 8) & 0xf); |
851 | ||
171a9e96 | 852 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
e2f0ba97 JB |
853 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
854 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
79e53945 | 855 | (v_sync_len & 0xf); |
e2f0ba97 | 856 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
79e53945 JB |
857 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
858 | ((v_sync_len & 0x30) >> 4); | |
859 | ||
e2f0ba97 | 860 | dtd->part2.dtd_flags = 0x18; |
59d92bfa DV |
861 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
862 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; | |
79e53945 | 863 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
59d92bfa | 864 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
79e53945 | 865 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
59d92bfa | 866 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
e2f0ba97 | 867 | |
e2f0ba97 | 868 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
e2f0ba97 JB |
869 | } |
870 | ||
1c4a814e | 871 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, |
32aad86f | 872 | const struct intel_sdvo_dtd *dtd) |
e2f0ba97 | 873 | { |
1c4a814e DV |
874 | struct drm_display_mode mode = {}; |
875 | ||
876 | mode.hdisplay = dtd->part1.h_active; | |
877 | mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
878 | mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; | |
879 | mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; | |
880 | mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; | |
881 | mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
882 | mode.htotal = mode.hdisplay + dtd->part1.h_blank; | |
883 | mode.htotal += (dtd->part1.h_high & 0xf) << 8; | |
884 | ||
885 | mode.vdisplay = dtd->part1.v_active; | |
886 | mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
887 | mode.vsync_start = mode.vdisplay; | |
888 | mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
889 | mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; | |
890 | mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; | |
891 | mode.vsync_end = mode.vsync_start + | |
e2f0ba97 | 892 | (dtd->part2.v_sync_off_width & 0xf); |
1c4a814e DV |
893 | mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
894 | mode.vtotal = mode.vdisplay + dtd->part1.v_blank; | |
895 | mode.vtotal += (dtd->part1.v_high & 0xf) << 8; | |
e2f0ba97 | 896 | |
1c4a814e | 897 | mode.clock = dtd->part1.clock * 10; |
e2f0ba97 | 898 | |
59d92bfa | 899 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
1c4a814e | 900 | mode.flags |= DRM_MODE_FLAG_INTERLACE; |
59d92bfa | 901 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
1c4a814e | 902 | mode.flags |= DRM_MODE_FLAG_PHSYNC; |
3cea210f | 903 | else |
1c4a814e | 904 | mode.flags |= DRM_MODE_FLAG_NHSYNC; |
59d92bfa | 905 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
1c4a814e | 906 | mode.flags |= DRM_MODE_FLAG_PVSYNC; |
3cea210f | 907 | else |
1c4a814e DV |
908 | mode.flags |= DRM_MODE_FLAG_NVSYNC; |
909 | ||
910 | drm_mode_set_crtcinfo(&mode, 0); | |
911 | ||
912 | drm_mode_copy(pmode, &mode); | |
e2f0ba97 JB |
913 | } |
914 | ||
e27d8538 | 915 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
e2f0ba97 | 916 | { |
e27d8538 | 917 | struct intel_sdvo_encode encode; |
e2f0ba97 | 918 | |
1a3665c8 | 919 | BUILD_BUG_ON(sizeof(encode) != 2); |
e27d8538 CW |
920 | return intel_sdvo_get_value(intel_sdvo, |
921 | SDVO_CMD_GET_SUPP_ENCODE, | |
922 | &encode, sizeof(encode)); | |
e2f0ba97 JB |
923 | } |
924 | ||
ea5b213a | 925 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
c751ce4f | 926 | uint8_t mode) |
e2f0ba97 | 927 | { |
32aad86f | 928 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
e2f0ba97 JB |
929 | } |
930 | ||
ea5b213a | 931 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
932 | uint8_t mode) |
933 | { | |
32aad86f | 934 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
e2f0ba97 JB |
935 | } |
936 | ||
937 | #if 0 | |
ea5b213a | 938 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
e2f0ba97 JB |
939 | { |
940 | int i, j; | |
941 | uint8_t set_buf_index[2]; | |
942 | uint8_t av_split; | |
943 | uint8_t buf_size; | |
944 | uint8_t buf[48]; | |
945 | uint8_t *pos; | |
946 | ||
32aad86f | 947 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
e2f0ba97 JB |
948 | |
949 | for (i = 0; i <= av_split; i++) { | |
950 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
c751ce4f | 951 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
e2f0ba97 | 952 | set_buf_index, 2); |
c751ce4f EA |
953 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
954 | intel_sdvo_read_response(encoder, &buf_size, 1); | |
e2f0ba97 JB |
955 | |
956 | pos = buf; | |
957 | for (j = 0; j <= buf_size; j += 8) { | |
c751ce4f | 958 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
e2f0ba97 | 959 | NULL, 0); |
c751ce4f | 960 | intel_sdvo_read_response(encoder, pos, 8); |
e2f0ba97 JB |
961 | pos += 8; |
962 | } | |
963 | } | |
964 | } | |
965 | #endif | |
966 | ||
b6e0e543 DV |
967 | static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
968 | unsigned if_index, uint8_t tx_rate, | |
fff63867 | 969 | const uint8_t *data, unsigned length) |
b6e0e543 DV |
970 | { |
971 | uint8_t set_buf_index[2] = { if_index, 0 }; | |
972 | uint8_t hbuf_size, tmp[8]; | |
973 | int i; | |
974 | ||
975 | if (!intel_sdvo_set_value(intel_sdvo, | |
976 | SDVO_CMD_SET_HBUF_INDEX, | |
977 | set_buf_index, 2)) | |
978 | return false; | |
979 | ||
980 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, | |
981 | &hbuf_size, 1)) | |
982 | return false; | |
983 | ||
984 | /* Buffer size is 0 based, hooray! */ | |
985 | hbuf_size++; | |
986 | ||
987 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", | |
988 | if_index, length, hbuf_size); | |
989 | ||
990 | for (i = 0; i < hbuf_size; i += 8) { | |
991 | memset(tmp, 0, 8); | |
992 | if (i < length) | |
993 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); | |
994 | ||
995 | if (!intel_sdvo_set_value(intel_sdvo, | |
996 | SDVO_CMD_SET_HBUF_DATA, | |
997 | tmp, 8)) | |
998 | return false; | |
999 | } | |
1000 | ||
1001 | return intel_sdvo_set_value(intel_sdvo, | |
1002 | SDVO_CMD_SET_HBUF_TXRATE, | |
1003 | &tx_rate, 1); | |
1004 | } | |
1005 | ||
abedc077 VS |
1006 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
1007 | const struct drm_display_mode *adjusted_mode) | |
e2f0ba97 | 1008 | { |
15dcd350 DL |
1009 | uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; |
1010 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; | |
1011 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1012 | union hdmi_infoframe frame; | |
1013 | int ret; | |
1014 | ssize_t len; | |
1015 | ||
1016 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, | |
1017 | adjusted_mode); | |
1018 | if (ret < 0) { | |
1019 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
1020 | return false; | |
1021 | } | |
3c17fe4b | 1022 | |
abedc077 | 1023 | if (intel_sdvo->rgb_quant_range_selectable) { |
6e3c9717 | 1024 | if (intel_crtc->config->limited_color_range) |
15dcd350 DL |
1025 | frame.avi.quantization_range = |
1026 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 1027 | else |
15dcd350 DL |
1028 | frame.avi.quantization_range = |
1029 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
1030 | } |
1031 | ||
15dcd350 DL |
1032 | len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); |
1033 | if (len < 0) | |
1034 | return false; | |
81014b9d | 1035 | |
b6e0e543 DV |
1036 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, |
1037 | SDVO_HBUF_TX_VSYNC, | |
1038 | sdvo_data, sizeof(sdvo_data)); | |
e2f0ba97 JB |
1039 | } |
1040 | ||
32aad86f | 1041 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
7026d4ac | 1042 | { |
ce6feabd | 1043 | struct intel_sdvo_tv_format format; |
40039750 | 1044 | uint32_t format_map; |
ce6feabd | 1045 | |
40039750 | 1046 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1047 | memset(&format, 0, sizeof(format)); |
32aad86f | 1048 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
ce6feabd | 1049 | |
32aad86f CW |
1050 | BUILD_BUG_ON(sizeof(format) != 6); |
1051 | return intel_sdvo_set_value(intel_sdvo, | |
1052 | SDVO_CMD_SET_TV_FORMAT, | |
1053 | &format, sizeof(format)); | |
7026d4ac ZW |
1054 | } |
1055 | ||
32aad86f CW |
1056 | static bool |
1057 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, | |
e811f5ae | 1058 | const struct drm_display_mode *mode) |
e2f0ba97 | 1059 | { |
32aad86f | 1060 | struct intel_sdvo_dtd output_dtd; |
79e53945 | 1061 | |
32aad86f CW |
1062 | if (!intel_sdvo_set_target_output(intel_sdvo, |
1063 | intel_sdvo->attached_output)) | |
1064 | return false; | |
e2f0ba97 | 1065 | |
32aad86f CW |
1066 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
1067 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) | |
1068 | return false; | |
e2f0ba97 | 1069 | |
32aad86f CW |
1070 | return true; |
1071 | } | |
1072 | ||
c9a29698 DV |
1073 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
1074 | * Unfortunately we have to set up the full output mode to do that. */ | |
32aad86f | 1075 | static bool |
c9a29698 | 1076 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
e811f5ae | 1077 | const struct drm_display_mode *mode, |
c9a29698 | 1078 | struct drm_display_mode *adjusted_mode) |
32aad86f | 1079 | { |
c9a29698 DV |
1080 | struct intel_sdvo_dtd input_dtd; |
1081 | ||
32aad86f CW |
1082 | /* Reset the input timing to the screen. Assume always input 0. */ |
1083 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
1084 | return false; | |
e2f0ba97 | 1085 | |
32aad86f CW |
1086 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
1087 | mode->clock / 10, | |
1088 | mode->hdisplay, | |
1089 | mode->vdisplay)) | |
1090 | return false; | |
e2f0ba97 | 1091 | |
32aad86f | 1092 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
c9a29698 | 1093 | &input_dtd)) |
32aad86f | 1094 | return false; |
e2f0ba97 | 1095 | |
c9a29698 | 1096 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
e751823d | 1097 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
79e53945 | 1098 | |
32aad86f CW |
1099 | return true; |
1100 | } | |
12682a97 | 1101 | |
5cec258b | 1102 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) |
70484559 | 1103 | { |
3c52f4eb | 1104 | unsigned dotclock = pipe_config->port_clock; |
70484559 DV |
1105 | struct dpll *clock = &pipe_config->dpll; |
1106 | ||
1107 | /* SDVO TV has fixed PLL values depend on its clock range, | |
1108 | this mirrors vbios setting. */ | |
1109 | if (dotclock >= 100000 && dotclock < 140500) { | |
1110 | clock->p1 = 2; | |
1111 | clock->p2 = 10; | |
1112 | clock->n = 3; | |
1113 | clock->m1 = 16; | |
1114 | clock->m2 = 8; | |
1115 | } else if (dotclock >= 140500 && dotclock <= 200000) { | |
1116 | clock->p1 = 1; | |
1117 | clock->p2 = 10; | |
1118 | clock->n = 6; | |
1119 | clock->m1 = 12; | |
1120 | clock->m2 = 8; | |
1121 | } else { | |
1122 | WARN(1, "SDVO TV clock out of range: %i\n", dotclock); | |
1123 | } | |
1124 | ||
1125 | pipe_config->clock_set = true; | |
1126 | } | |
1127 | ||
6cc5f341 | 1128 | static bool intel_sdvo_compute_config(struct intel_encoder *encoder, |
5cec258b | 1129 | struct intel_crtc_state *pipe_config) |
32aad86f | 1130 | { |
8aca63aa | 1131 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
2d112de7 ACO |
1132 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1133 | struct drm_display_mode *mode = &pipe_config->base.mode; | |
12682a97 | 1134 | |
5d2d38dd DV |
1135 | DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); |
1136 | pipe_config->pipe_bpp = 8*3; | |
1137 | ||
5bfe2ac0 DV |
1138 | if (HAS_PCH_SPLIT(encoder->base.dev)) |
1139 | pipe_config->has_pch_encoder = true; | |
1140 | ||
32aad86f CW |
1141 | /* We need to construct preferred input timings based on our |
1142 | * output timings. To do that, we have to set the output | |
1143 | * timings, even though this isn't really the right place in | |
1144 | * the sequence to do it. Oh well. | |
1145 | */ | |
1146 | if (intel_sdvo->is_tv) { | |
1147 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) | |
1148 | return false; | |
12682a97 | 1149 | |
c9a29698 DV |
1150 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1151 | mode, | |
1152 | adjusted_mode); | |
09ede541 | 1153 | pipe_config->sdvo_tv_clock = true; |
ea5b213a | 1154 | } else if (intel_sdvo->is_lvds) { |
32aad86f | 1155 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
6c9547ff | 1156 | intel_sdvo->sdvo_lvds_fixed_mode)) |
e2f0ba97 | 1157 | return false; |
12682a97 | 1158 | |
c9a29698 DV |
1159 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1160 | mode, | |
1161 | adjusted_mode); | |
e2f0ba97 | 1162 | } |
32aad86f CW |
1163 | |
1164 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
6c9547ff | 1165 | * SDVO device will factor out the multiplier during mode_set. |
32aad86f | 1166 | */ |
6cc5f341 DV |
1167 | pipe_config->pixel_multiplier = |
1168 | intel_sdvo_get_pixel_multiplier(adjusted_mode); | |
32aad86f | 1169 | |
9f04003e DV |
1170 | pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; |
1171 | ||
55bc60db VS |
1172 | if (intel_sdvo->color_range_auto) { |
1173 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
4f3a8bc7 PZ |
1174 | /* FIXME: This bit is only valid when using TMDS encoding and 8 |
1175 | * bit per color mode. */ | |
9f04003e | 1176 | if (pipe_config->has_hdmi_sink && |
18316c8c | 1177 | drm_match_cea_mode(adjusted_mode) > 1) |
69f5acc8 DV |
1178 | pipe_config->limited_color_range = true; |
1179 | } else { | |
9f04003e | 1180 | if (pipe_config->has_hdmi_sink && |
69f5acc8 DV |
1181 | intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) |
1182 | pipe_config->limited_color_range = true; | |
55bc60db VS |
1183 | } |
1184 | ||
70484559 DV |
1185 | /* Clock computation needs to happen after pixel multiplier. */ |
1186 | if (intel_sdvo->is_tv) | |
1187 | i9xx_adjust_sdvo_tv_clock(pipe_config); | |
1188 | ||
7949dd47 VS |
1189 | /* Set user selected PAR to incoming mode's member */ |
1190 | if (intel_sdvo->is_hdmi) | |
1191 | adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio; | |
1192 | ||
e2f0ba97 JB |
1193 | return true; |
1194 | } | |
1195 | ||
192d47a6 | 1196 | static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) |
e2f0ba97 | 1197 | { |
6cc5f341 | 1198 | struct drm_device *dev = intel_encoder->base.dev; |
e2f0ba97 | 1199 | struct drm_i915_private *dev_priv = dev->dev_private; |
eeb47937 | 1200 | struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); |
7c5f93b0 | 1201 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
6e3c9717 | 1202 | struct drm_display_mode *mode = &crtc->config->base.mode; |
8aca63aa | 1203 | struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); |
6c9547ff | 1204 | u32 sdvox; |
e2f0ba97 | 1205 | struct intel_sdvo_in_out_map in_out; |
6651819b | 1206 | struct intel_sdvo_dtd input_dtd, output_dtd; |
6c9547ff | 1207 | int rate; |
e2f0ba97 JB |
1208 | |
1209 | if (!mode) | |
1210 | return; | |
1211 | ||
1212 | /* First, set the input mapping for the first input to our controlled | |
1213 | * output. This is only correct if we're a single-input device, in | |
1214 | * which case the first input is the output from the appropriate SDVO | |
1215 | * channel on the motherboard. In a two-input device, the first input | |
1216 | * will be SDVOB and the second SDVOC. | |
1217 | */ | |
ea5b213a | 1218 | in_out.in0 = intel_sdvo->attached_output; |
e2f0ba97 JB |
1219 | in_out.in1 = 0; |
1220 | ||
c74696b9 PR |
1221 | intel_sdvo_set_value(intel_sdvo, |
1222 | SDVO_CMD_SET_IN_OUT_MAP, | |
1223 | &in_out, sizeof(in_out)); | |
e2f0ba97 | 1224 | |
6c9547ff CW |
1225 | /* Set the output timings to the screen */ |
1226 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1227 | intel_sdvo->attached_output)) | |
1228 | return; | |
e2f0ba97 | 1229 | |
6651819b DV |
1230 | /* lvds has a special fixed output timing. */ |
1231 | if (intel_sdvo->is_lvds) | |
1232 | intel_sdvo_get_dtd_from_mode(&output_dtd, | |
1233 | intel_sdvo->sdvo_lvds_fixed_mode); | |
1234 | else | |
1235 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); | |
c8d4bb54 DV |
1236 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
1237 | DRM_INFO("Setting output timings on %s failed\n", | |
1238 | SDVO_NAME(intel_sdvo)); | |
79e53945 JB |
1239 | |
1240 | /* Set the input timing to the screen. Assume always input 0. */ | |
32aad86f CW |
1241 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
1242 | return; | |
79e53945 | 1243 | |
6e3c9717 | 1244 | if (crtc->config->has_hdmi_sink) { |
97aaf910 CW |
1245 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
1246 | intel_sdvo_set_colorimetry(intel_sdvo, | |
1247 | SDVO_COLORIMETRY_RGB256); | |
abedc077 | 1248 | intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); |
97aaf910 CW |
1249 | } else |
1250 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); | |
7026d4ac | 1251 | |
6c9547ff CW |
1252 | if (intel_sdvo->is_tv && |
1253 | !intel_sdvo_set_tv_format(intel_sdvo)) | |
1254 | return; | |
e2f0ba97 | 1255 | |
6651819b | 1256 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
eeb47937 | 1257 | |
e751823d EE |
1258 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) |
1259 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; | |
c8d4bb54 DV |
1260 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
1261 | DRM_INFO("Setting input timings on %s failed\n", | |
1262 | SDVO_NAME(intel_sdvo)); | |
79e53945 | 1263 | |
6e3c9717 | 1264 | switch (crtc->config->pixel_multiplier) { |
6c9547ff | 1265 | default: |
fd0753cf | 1266 | WARN(1, "unknown pixel multiplier specified\n"); |
32aad86f CW |
1267 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
1268 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; | |
1269 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; | |
79e53945 | 1270 | } |
32aad86f CW |
1271 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
1272 | return; | |
79e53945 JB |
1273 | |
1274 | /* Set the SDVO control regs. */ | |
a6c45cf0 | 1275 | if (INTEL_INFO(dev)->gen >= 4) { |
ba68e086 PZ |
1276 | /* The real mode polarity is set by the SDVO commands, using |
1277 | * struct intel_sdvo_dtd. */ | |
1278 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; | |
6e3c9717 | 1279 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
69f5acc8 | 1280 | sdvox |= HDMI_COLOR_RANGE_16_235; |
6714afb1 CW |
1281 | if (INTEL_INFO(dev)->gen < 5) |
1282 | sdvox |= SDVO_BORDER_ENABLE; | |
e2f0ba97 | 1283 | } else { |
6c9547ff | 1284 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
ea5b213a | 1285 | switch (intel_sdvo->sdvo_reg) { |
e2debe91 | 1286 | case GEN3_SDVOB: |
e2f0ba97 JB |
1287 | sdvox &= SDVOB_PRESERVE_MASK; |
1288 | break; | |
e2debe91 | 1289 | case GEN3_SDVOC: |
e2f0ba97 JB |
1290 | sdvox &= SDVOC_PRESERVE_MASK; |
1291 | break; | |
1292 | } | |
1293 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | |
1294 | } | |
3573c410 PZ |
1295 | |
1296 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) | |
eeb47937 | 1297 | sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
3573c410 | 1298 | else |
eeb47937 | 1299 | sdvox |= SDVO_PIPE_SEL(crtc->pipe); |
3573c410 | 1300 | |
da79de97 | 1301 | if (intel_sdvo->has_hdmi_audio) |
6c9547ff | 1302 | sdvox |= SDVO_AUDIO_ENABLE; |
79e53945 | 1303 | |
a6c45cf0 | 1304 | if (INTEL_INFO(dev)->gen >= 4) { |
e2f0ba97 JB |
1305 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1306 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1307 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
79e53945 | 1308 | } else { |
6e3c9717 | 1309 | sdvox |= (crtc->config->pixel_multiplier - 1) |
6cc5f341 | 1310 | << SDVO_PORT_MULTIPLY_SHIFT; |
79e53945 JB |
1311 | } |
1312 | ||
6714afb1 CW |
1313 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
1314 | INTEL_INFO(dev)->gen < 5) | |
12682a97 | 1315 | sdvox |= SDVO_STALL_SELECT; |
ea5b213a | 1316 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
79e53945 JB |
1317 | } |
1318 | ||
4ac41f47 | 1319 | static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
79e53945 | 1320 | { |
4ac41f47 DV |
1321 | struct intel_sdvo_connector *intel_sdvo_connector = |
1322 | to_intel_sdvo_connector(&connector->base); | |
1323 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); | |
2f28c50b | 1324 | u16 active_outputs = 0; |
4ac41f47 DV |
1325 | |
1326 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); | |
1327 | ||
1328 | if (active_outputs & intel_sdvo_connector->output_flag) | |
1329 | return true; | |
1330 | else | |
1331 | return false; | |
1332 | } | |
1333 | ||
1334 | static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, | |
1335 | enum pipe *pipe) | |
1336 | { | |
1337 | struct drm_device *dev = encoder->base.dev; | |
79e53945 | 1338 | struct drm_i915_private *dev_priv = dev->dev_private; |
8aca63aa | 1339 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
2f28c50b | 1340 | u16 active_outputs = 0; |
4ac41f47 DV |
1341 | u32 tmp; |
1342 | ||
1343 | tmp = I915_READ(intel_sdvo->sdvo_reg); | |
7a7d1fb7 | 1344 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
4ac41f47 | 1345 | |
7a7d1fb7 | 1346 | if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) |
4ac41f47 DV |
1347 | return false; |
1348 | ||
1349 | if (HAS_PCH_CPT(dev)) | |
1350 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
1351 | else | |
1352 | *pipe = PORT_TO_PIPE(tmp); | |
1353 | ||
1354 | return true; | |
1355 | } | |
1356 | ||
045ac3b5 | 1357 | static void intel_sdvo_get_config(struct intel_encoder *encoder, |
5cec258b | 1358 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 1359 | { |
6c49f241 DV |
1360 | struct drm_device *dev = encoder->base.dev; |
1361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8aca63aa | 1362 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
045ac3b5 | 1363 | struct intel_sdvo_dtd dtd; |
6c49f241 | 1364 | int encoder_pixel_multiplier = 0; |
18442d08 | 1365 | int dotclock; |
6c49f241 DV |
1366 | u32 flags = 0, sdvox; |
1367 | u8 val; | |
045ac3b5 JB |
1368 | bool ret; |
1369 | ||
b5a9fa09 DV |
1370 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
1371 | ||
045ac3b5 JB |
1372 | ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); |
1373 | if (!ret) { | |
bb760063 DV |
1374 | /* Some sdvo encoders are not spec compliant and don't |
1375 | * implement the mandatory get_timings function. */ | |
045ac3b5 | 1376 | DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); |
bb760063 DV |
1377 | pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; |
1378 | } else { | |
1379 | if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) | |
1380 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1381 | else | |
1382 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1383 | |
bb760063 DV |
1384 | if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
1385 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1386 | else | |
1387 | flags |= DRM_MODE_FLAG_NVSYNC; | |
045ac3b5 JB |
1388 | } |
1389 | ||
2d112de7 | 1390 | pipe_config->base.adjusted_mode.flags |= flags; |
045ac3b5 | 1391 | |
fdafa9e2 DV |
1392 | /* |
1393 | * pixel multiplier readout is tricky: Only on i915g/gm it is stored in | |
1394 | * the sdvo port register, on all other platforms it is part of the dpll | |
1395 | * state. Since the general pipe state readout happens before the | |
1396 | * encoder->get_config we so already have a valid pixel multplier on all | |
1397 | * other platfroms. | |
1398 | */ | |
6c49f241 | 1399 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
6c49f241 DV |
1400 | pipe_config->pixel_multiplier = |
1401 | ((sdvox & SDVO_PORT_MULTIPLY_MASK) | |
1402 | >> SDVO_PORT_MULTIPLY_SHIFT) + 1; | |
1403 | } | |
045ac3b5 | 1404 | |
2b85886a VS |
1405 | dotclock = pipe_config->port_clock; |
1406 | if (pipe_config->pixel_multiplier) | |
1407 | dotclock /= pipe_config->pixel_multiplier; | |
18442d08 VS |
1408 | |
1409 | if (HAS_PCH_SPLIT(dev)) | |
1410 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
1411 | ||
2d112de7 | 1412 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
18442d08 | 1413 | |
6c49f241 | 1414 | /* Cross check the port pixel multiplier with the sdvo encoder state. */ |
53b91408 DL |
1415 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, |
1416 | &val, 1)) { | |
1417 | switch (val) { | |
1418 | case SDVO_CLOCK_RATE_MULT_1X: | |
1419 | encoder_pixel_multiplier = 1; | |
1420 | break; | |
1421 | case SDVO_CLOCK_RATE_MULT_2X: | |
1422 | encoder_pixel_multiplier = 2; | |
1423 | break; | |
1424 | case SDVO_CLOCK_RATE_MULT_4X: | |
1425 | encoder_pixel_multiplier = 4; | |
1426 | break; | |
1427 | } | |
6c49f241 | 1428 | } |
fdafa9e2 | 1429 | |
b5a9fa09 DV |
1430 | if (sdvox & HDMI_COLOR_RANGE_16_235) |
1431 | pipe_config->limited_color_range = true; | |
1432 | ||
9f04003e DV |
1433 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, |
1434 | &val, 1)) { | |
1435 | if (val == SDVO_ENCODE_HDMI) | |
1436 | pipe_config->has_hdmi_sink = true; | |
1437 | } | |
1438 | ||
6c49f241 DV |
1439 | WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, |
1440 | "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", | |
1441 | pipe_config->pixel_multiplier, encoder_pixel_multiplier); | |
045ac3b5 JB |
1442 | } |
1443 | ||
ce22c320 DV |
1444 | static void intel_disable_sdvo(struct intel_encoder *encoder) |
1445 | { | |
1446 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
8aca63aa | 1447 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
1612c8bd | 1448 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
ce22c320 DV |
1449 | u32 temp; |
1450 | ||
1451 | intel_sdvo_set_active_outputs(intel_sdvo, 0); | |
1452 | if (0) | |
1453 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1454 | DRM_MODE_DPMS_OFF); | |
1455 | ||
1456 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
776ca7cf | 1457 | |
1612c8bd VS |
1458 | temp &= ~SDVO_ENABLE; |
1459 | intel_sdvo_write_sdvox(intel_sdvo, temp); | |
1460 | ||
1461 | /* | |
1462 | * HW workaround for IBX, we need to move the port | |
1463 | * to transcoder A after disabling it to allow the | |
1464 | * matching DP port to be enabled on transcoder A. | |
1465 | */ | |
1466 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { | |
0c241d5b VS |
1467 | /* |
1468 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1469 | * doing the workaround. Sweep them under the rug. | |
1470 | */ | |
1471 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1472 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1473 | ||
1612c8bd VS |
1474 | temp &= ~SDVO_PIPE_B_SELECT; |
1475 | temp |= SDVO_ENABLE; | |
1476 | intel_sdvo_write_sdvox(intel_sdvo, temp); | |
1477 | ||
1478 | temp &= ~SDVO_ENABLE; | |
1479 | intel_sdvo_write_sdvox(intel_sdvo, temp); | |
0c241d5b VS |
1480 | |
1481 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); | |
1482 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1483 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
ce22c320 DV |
1484 | } |
1485 | } | |
1486 | ||
3c65d1d1 VS |
1487 | static void pch_disable_sdvo(struct intel_encoder *encoder) |
1488 | { | |
1489 | } | |
1490 | ||
1491 | static void pch_post_disable_sdvo(struct intel_encoder *encoder) | |
1492 | { | |
1493 | intel_disable_sdvo(encoder); | |
1494 | } | |
1495 | ||
ce22c320 DV |
1496 | static void intel_enable_sdvo(struct intel_encoder *encoder) |
1497 | { | |
1498 | struct drm_device *dev = encoder->base.dev; | |
1499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8aca63aa | 1500 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
ce22c320 | 1501 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 1502 | u32 temp; |
ce22c320 DV |
1503 | bool input1, input2; |
1504 | int i; | |
d0a7b6de | 1505 | bool success; |
ce22c320 DV |
1506 | |
1507 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
3c65d1d1 VS |
1508 | temp |= SDVO_ENABLE; |
1509 | intel_sdvo_write_sdvox(intel_sdvo, temp); | |
776ca7cf | 1510 | |
ce22c320 DV |
1511 | for (i = 0; i < 2; i++) |
1512 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1513 | ||
d0a7b6de | 1514 | success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
ce22c320 DV |
1515 | /* Warn if the device reported failure to sync. |
1516 | * A lot of SDVO devices fail to notify of sync, but it's | |
1517 | * a given it the status is a success, we succeeded. | |
1518 | */ | |
d0a7b6de | 1519 | if (success && !input1) { |
ce22c320 DV |
1520 | DRM_DEBUG_KMS("First %s output reported failure to " |
1521 | "sync\n", SDVO_NAME(intel_sdvo)); | |
1522 | } | |
1523 | ||
1524 | if (0) | |
1525 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1526 | DRM_MODE_DPMS_ON); | |
1527 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
1528 | } | |
1529 | ||
c19de8eb DL |
1530 | static enum drm_mode_status |
1531 | intel_sdvo_mode_valid(struct drm_connector *connector, | |
1532 | struct drm_display_mode *mode) | |
79e53945 | 1533 | { |
df0e9248 | 1534 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
79e53945 JB |
1535 | |
1536 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1537 | return MODE_NO_DBLESCAN; | |
1538 | ||
ea5b213a | 1539 | if (intel_sdvo->pixel_clock_min > mode->clock) |
79e53945 JB |
1540 | return MODE_CLOCK_LOW; |
1541 | ||
ea5b213a | 1542 | if (intel_sdvo->pixel_clock_max < mode->clock) |
79e53945 JB |
1543 | return MODE_CLOCK_HIGH; |
1544 | ||
8545423a | 1545 | if (intel_sdvo->is_lvds) { |
ea5b213a | 1546 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
12682a97 | 1547 | return MODE_PANEL; |
1548 | ||
ea5b213a | 1549 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
12682a97 | 1550 | return MODE_PANEL; |
1551 | } | |
1552 | ||
79e53945 JB |
1553 | return MODE_OK; |
1554 | } | |
1555 | ||
ea5b213a | 1556 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
79e53945 | 1557 | { |
1a3665c8 | 1558 | BUILD_BUG_ON(sizeof(*caps) != 8); |
e957d772 CW |
1559 | if (!intel_sdvo_get_value(intel_sdvo, |
1560 | SDVO_CMD_GET_DEVICE_CAPS, | |
1561 | caps, sizeof(*caps))) | |
1562 | return false; | |
1563 | ||
1564 | DRM_DEBUG_KMS("SDVO capabilities:\n" | |
1565 | " vendor_id: %d\n" | |
1566 | " device_id: %d\n" | |
1567 | " device_rev_id: %d\n" | |
1568 | " sdvo_version_major: %d\n" | |
1569 | " sdvo_version_minor: %d\n" | |
1570 | " sdvo_inputs_mask: %d\n" | |
1571 | " smooth_scaling: %d\n" | |
1572 | " sharp_scaling: %d\n" | |
1573 | " up_scaling: %d\n" | |
1574 | " down_scaling: %d\n" | |
1575 | " stall_support: %d\n" | |
1576 | " output_flags: %d\n", | |
1577 | caps->vendor_id, | |
1578 | caps->device_id, | |
1579 | caps->device_rev_id, | |
1580 | caps->sdvo_version_major, | |
1581 | caps->sdvo_version_minor, | |
1582 | caps->sdvo_inputs_mask, | |
1583 | caps->smooth_scaling, | |
1584 | caps->sharp_scaling, | |
1585 | caps->up_scaling, | |
1586 | caps->down_scaling, | |
1587 | caps->stall_support, | |
1588 | caps->output_flags); | |
1589 | ||
1590 | return true; | |
79e53945 JB |
1591 | } |
1592 | ||
5fa7ac9c | 1593 | static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
79e53945 | 1594 | { |
768b107e | 1595 | struct drm_device *dev = intel_sdvo->base.base.dev; |
5fa7ac9c | 1596 | uint16_t hotplug; |
79e53945 | 1597 | |
1d83d957 VS |
1598 | if (!I915_HAS_HOTPLUG(dev)) |
1599 | return 0; | |
1600 | ||
768b107e DV |
1601 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
1602 | * on the line. */ | |
1603 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
5fa7ac9c | 1604 | return 0; |
768b107e | 1605 | |
5fa7ac9c JN |
1606 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
1607 | &hotplug, sizeof(hotplug))) | |
1608 | return 0; | |
768b107e | 1609 | |
5fa7ac9c | 1610 | return hotplug; |
79e53945 JB |
1611 | } |
1612 | ||
cc68c81a | 1613 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
79e53945 | 1614 | { |
8aca63aa | 1615 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
79e53945 | 1616 | |
5fa7ac9c JN |
1617 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, |
1618 | &intel_sdvo->hotplug_active, 2); | |
79e53945 JB |
1619 | } |
1620 | ||
fb7a46f3 | 1621 | static bool |
ea5b213a | 1622 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
fb7a46f3 | 1623 | { |
bc65212c | 1624 | /* Is there more than one type of output? */ |
2294488d | 1625 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
fb7a46f3 | 1626 | } |
1627 | ||
f899fc64 | 1628 | static struct edid * |
e957d772 | 1629 | intel_sdvo_get_edid(struct drm_connector *connector) |
f899fc64 | 1630 | { |
e957d772 CW |
1631 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
1632 | return drm_get_edid(connector, &sdvo->ddc); | |
f899fc64 CW |
1633 | } |
1634 | ||
ff482d83 CW |
1635 | /* Mac mini hack -- use the same DDC as the analog connector */ |
1636 | static struct edid * | |
1637 | intel_sdvo_get_analog_edid(struct drm_connector *connector) | |
1638 | { | |
f899fc64 | 1639 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ff482d83 | 1640 | |
0c1dab89 | 1641 | return drm_get_edid(connector, |
3bd7d909 | 1642 | intel_gmbus_get_adapter(dev_priv, |
41aa3448 | 1643 | dev_priv->vbt.crt_ddc_pin)); |
ff482d83 CW |
1644 | } |
1645 | ||
c43b5634 | 1646 | static enum drm_connector_status |
8bf38485 | 1647 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
9dff6af8 | 1648 | { |
df0e9248 | 1649 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
9d1a903d CW |
1650 | enum drm_connector_status status; |
1651 | struct edid *edid; | |
9dff6af8 | 1652 | |
e957d772 | 1653 | edid = intel_sdvo_get_edid(connector); |
57cdaf90 | 1654 | |
ea5b213a | 1655 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
e957d772 | 1656 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
9d1a903d | 1657 | |
7c3f0a27 ZY |
1658 | /* |
1659 | * Don't use the 1 as the argument of DDC bus switch to get | |
1660 | * the EDID. It is used for SDVO SPD ROM. | |
1661 | */ | |
9d1a903d | 1662 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
e957d772 CW |
1663 | intel_sdvo->ddc_bus = ddc; |
1664 | edid = intel_sdvo_get_edid(connector); | |
1665 | if (edid) | |
7c3f0a27 | 1666 | break; |
7c3f0a27 | 1667 | } |
e957d772 CW |
1668 | /* |
1669 | * If we found the EDID on the other bus, | |
1670 | * assume that is the correct DDC bus. | |
1671 | */ | |
1672 | if (edid == NULL) | |
1673 | intel_sdvo->ddc_bus = saved_ddc; | |
7c3f0a27 | 1674 | } |
9d1a903d CW |
1675 | |
1676 | /* | |
1677 | * When there is no edid and no monitor is connected with VGA | |
1678 | * port, try to use the CRT ddc to read the EDID for DVI-connector. | |
57cdaf90 | 1679 | */ |
ff482d83 CW |
1680 | if (edid == NULL) |
1681 | edid = intel_sdvo_get_analog_edid(connector); | |
149c36a3 | 1682 | |
2f551c84 | 1683 | status = connector_status_unknown; |
9dff6af8 | 1684 | if (edid != NULL) { |
149c36a3 | 1685 | /* DDC bus is shared, match EDID to connector type */ |
9d1a903d CW |
1686 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
1687 | status = connector_status_connected; | |
da79de97 CW |
1688 | if (intel_sdvo->is_hdmi) { |
1689 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); | |
1690 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); | |
abedc077 VS |
1691 | intel_sdvo->rgb_quant_range_selectable = |
1692 | drm_rgb_quant_range_selectable(edid); | |
da79de97 | 1693 | } |
13946743 CW |
1694 | } else |
1695 | status = connector_status_disconnected; | |
9d1a903d CW |
1696 | kfree(edid); |
1697 | } | |
7f36e7ed CW |
1698 | |
1699 | if (status == connector_status_connected) { | |
1700 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
c3e5f67b DV |
1701 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
1702 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); | |
7f36e7ed CW |
1703 | } |
1704 | ||
2b8d33f7 | 1705 | return status; |
9dff6af8 ML |
1706 | } |
1707 | ||
52220085 CW |
1708 | static bool |
1709 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, | |
1710 | struct edid *edid) | |
1711 | { | |
1712 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); | |
1713 | bool connector_is_digital = !!IS_DIGITAL(sdvo); | |
1714 | ||
1715 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", | |
1716 | connector_is_digital, monitor_is_digital); | |
1717 | return connector_is_digital == monitor_is_digital; | |
1718 | } | |
1719 | ||
7b334fcb | 1720 | static enum drm_connector_status |
930a9e28 | 1721 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 1722 | { |
fb7a46f3 | 1723 | uint16_t response; |
df0e9248 | 1724 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1725 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
14571b4c | 1726 | enum drm_connector_status ret; |
79e53945 | 1727 | |
164c8598 | 1728 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1729 | connector->base.id, connector->name); |
164c8598 | 1730 | |
fc37381c CW |
1731 | if (!intel_sdvo_get_value(intel_sdvo, |
1732 | SDVO_CMD_GET_ATTACHED_DISPLAYS, | |
1733 | &response, 2)) | |
32aad86f | 1734 | return connector_status_unknown; |
79e53945 | 1735 | |
e957d772 CW |
1736 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
1737 | response & 0xff, response >> 8, | |
1738 | intel_sdvo_connector->output_flag); | |
e2f0ba97 | 1739 | |
fb7a46f3 | 1740 | if (response == 0) |
79e53945 | 1741 | return connector_status_disconnected; |
fb7a46f3 | 1742 | |
ea5b213a | 1743 | intel_sdvo->attached_output = response; |
14571b4c | 1744 | |
97aaf910 CW |
1745 | intel_sdvo->has_hdmi_monitor = false; |
1746 | intel_sdvo->has_hdmi_audio = false; | |
abedc077 | 1747 | intel_sdvo->rgb_quant_range_selectable = false; |
97aaf910 | 1748 | |
615fb93f | 1749 | if ((intel_sdvo_connector->output_flag & response) == 0) |
14571b4c | 1750 | ret = connector_status_disconnected; |
13946743 | 1751 | else if (IS_TMDS(intel_sdvo_connector)) |
8bf38485 | 1752 | ret = intel_sdvo_tmds_sink_detect(connector); |
13946743 CW |
1753 | else { |
1754 | struct edid *edid; | |
1755 | ||
1756 | /* if we have an edid check it matches the connection */ | |
1757 | edid = intel_sdvo_get_edid(connector); | |
1758 | if (edid == NULL) | |
1759 | edid = intel_sdvo_get_analog_edid(connector); | |
1760 | if (edid != NULL) { | |
52220085 CW |
1761 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
1762 | edid)) | |
13946743 | 1763 | ret = connector_status_connected; |
52220085 CW |
1764 | else |
1765 | ret = connector_status_disconnected; | |
1766 | ||
13946743 CW |
1767 | kfree(edid); |
1768 | } else | |
1769 | ret = connector_status_connected; | |
1770 | } | |
14571b4c ZW |
1771 | |
1772 | /* May update encoder flag for like clock for SDVO TV, etc.*/ | |
1773 | if (ret == connector_status_connected) { | |
ea5b213a CW |
1774 | intel_sdvo->is_tv = false; |
1775 | intel_sdvo->is_lvds = false; | |
14571b4c | 1776 | |
09ede541 | 1777 | if (response & SDVO_TV_MASK) |
ea5b213a | 1778 | intel_sdvo->is_tv = true; |
14571b4c | 1779 | if (response & SDVO_LVDS_MASK) |
8545423a | 1780 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
fb7a46f3 | 1781 | } |
14571b4c ZW |
1782 | |
1783 | return ret; | |
79e53945 JB |
1784 | } |
1785 | ||
e2f0ba97 | 1786 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
79e53945 | 1787 | { |
ff482d83 | 1788 | struct edid *edid; |
79e53945 | 1789 | |
46a3f4a3 | 1790 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1791 | connector->base.id, connector->name); |
46a3f4a3 | 1792 | |
79e53945 | 1793 | /* set the bus switch and get the modes */ |
e957d772 | 1794 | edid = intel_sdvo_get_edid(connector); |
79e53945 | 1795 | |
57cdaf90 KP |
1796 | /* |
1797 | * Mac mini hack. On this device, the DVI-I connector shares one DDC | |
1798 | * link between analog and digital outputs. So, if the regular SDVO | |
1799 | * DDC fails, check to see if the analog output is disconnected, in | |
1800 | * which case we'll look there for the digital DDC data. | |
e2f0ba97 | 1801 | */ |
f899fc64 CW |
1802 | if (edid == NULL) |
1803 | edid = intel_sdvo_get_analog_edid(connector); | |
1804 | ||
ff482d83 | 1805 | if (edid != NULL) { |
52220085 CW |
1806 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
1807 | edid)) { | |
0c1dab89 CW |
1808 | drm_mode_connector_update_edid_property(connector, edid); |
1809 | drm_add_edid_modes(connector, edid); | |
1810 | } | |
13946743 | 1811 | |
ff482d83 | 1812 | kfree(edid); |
e2f0ba97 | 1813 | } |
e2f0ba97 JB |
1814 | } |
1815 | ||
1816 | /* | |
1817 | * Set of SDVO TV modes. | |
1818 | * Note! This is in reply order (see loop in get_tv_modes). | |
1819 | * XXX: all 60Hz refresh? | |
1820 | */ | |
b1f559ec | 1821 | static const struct drm_display_mode sdvo_tv_modes[] = { |
7026d4ac ZW |
1822 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1823 | 416, 0, 200, 201, 232, 233, 0, | |
e2f0ba97 | 1824 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1825 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1826 | 416, 0, 240, 241, 272, 273, 0, | |
e2f0ba97 | 1827 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1828 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1829 | 496, 0, 300, 301, 332, 333, 0, | |
e2f0ba97 | 1830 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1831 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1832 | 736, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1833 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1834 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1835 | 736, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1836 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1837 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1838 | 736, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1839 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1840 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1841 | 800, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1842 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1843 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1844 | 800, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1845 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1846 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1847 | 816, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1848 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1849 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1850 | 816, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1851 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1852 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1853 | 816, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1854 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1855 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1856 | 816, 0, 540, 541, 572, 573, 0, | |
e2f0ba97 | 1857 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1858 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1859 | 816, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1860 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1861 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1862 | 864, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1863 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1864 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1865 | 896, 0, 600, 601, 632, 633, 0, | |
e2f0ba97 | 1866 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1867 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1868 | 928, 0, 624, 625, 656, 657, 0, | |
e2f0ba97 | 1869 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1870 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1871 | 1016, 0, 766, 767, 798, 799, 0, | |
e2f0ba97 | 1872 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1873 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1874 | 1120, 0, 768, 769, 800, 801, 0, | |
e2f0ba97 | 1875 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1876 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1877 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
e2f0ba97 JB |
1878 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1879 | }; | |
1880 | ||
1881 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1882 | { | |
df0e9248 | 1883 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7026d4ac | 1884 | struct intel_sdvo_sdtv_resolution_request tv_res; |
ce6feabd ZY |
1885 | uint32_t reply = 0, format_map = 0; |
1886 | int i; | |
e2f0ba97 | 1887 | |
46a3f4a3 | 1888 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1889 | connector->base.id, connector->name); |
46a3f4a3 | 1890 | |
e2f0ba97 JB |
1891 | /* Read the list of supported input resolutions for the selected TV |
1892 | * format. | |
1893 | */ | |
40039750 | 1894 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1895 | memcpy(&tv_res, &format_map, |
32aad86f | 1896 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
ce6feabd | 1897 | |
32aad86f CW |
1898 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
1899 | return; | |
ce6feabd | 1900 | |
32aad86f | 1901 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
e957d772 CW |
1902 | if (!intel_sdvo_write_cmd(intel_sdvo, |
1903 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, | |
32aad86f CW |
1904 | &tv_res, sizeof(tv_res))) |
1905 | return; | |
1906 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) | |
e2f0ba97 JB |
1907 | return; |
1908 | ||
1909 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
7026d4ac ZW |
1910 | if (reply & (1 << i)) { |
1911 | struct drm_display_mode *nmode; | |
1912 | nmode = drm_mode_duplicate(connector->dev, | |
32aad86f | 1913 | &sdvo_tv_modes[i]); |
7026d4ac ZW |
1914 | if (nmode) |
1915 | drm_mode_probed_add(connector, nmode); | |
1916 | } | |
e2f0ba97 JB |
1917 | } |
1918 | ||
7086c87f ML |
1919 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1920 | { | |
df0e9248 | 1921 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7086c87f | 1922 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
12682a97 | 1923 | struct drm_display_mode *newmode; |
7086c87f | 1924 | |
46a3f4a3 | 1925 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1926 | connector->base.id, connector->name); |
46a3f4a3 | 1927 | |
7086c87f | 1928 | /* |
c3456fb3 | 1929 | * Fetch modes from VBT. For SDVO prefer the VBT mode since some |
4300a0f8 | 1930 | * SDVO->LVDS transcoders can't cope with the EDID mode. |
7086c87f | 1931 | */ |
41aa3448 | 1932 | if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { |
7086c87f | 1933 | newmode = drm_mode_duplicate(connector->dev, |
41aa3448 | 1934 | dev_priv->vbt.sdvo_lvds_vbt_mode); |
7086c87f ML |
1935 | if (newmode != NULL) { |
1936 | /* Guarantee the mode is preferred */ | |
1937 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1938 | DRM_MODE_TYPE_DRIVER); | |
1939 | drm_mode_probed_add(connector, newmode); | |
1940 | } | |
1941 | } | |
12682a97 | 1942 | |
4300a0f8 DA |
1943 | /* |
1944 | * Attempt to get the mode list from DDC. | |
1945 | * Assume that the preferred modes are | |
1946 | * arranged in priority order. | |
1947 | */ | |
1948 | intel_ddc_get_modes(connector, &intel_sdvo->ddc); | |
1949 | ||
12682a97 | 1950 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
1951 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
ea5b213a | 1952 | intel_sdvo->sdvo_lvds_fixed_mode = |
12682a97 | 1953 | drm_mode_duplicate(connector->dev, newmode); |
6c9547ff | 1954 | |
8545423a | 1955 | intel_sdvo->is_lvds = true; |
12682a97 | 1956 | break; |
1957 | } | |
1958 | } | |
7086c87f ML |
1959 | } |
1960 | ||
e2f0ba97 JB |
1961 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1962 | { | |
615fb93f | 1963 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e2f0ba97 | 1964 | |
615fb93f | 1965 | if (IS_TV(intel_sdvo_connector)) |
e2f0ba97 | 1966 | intel_sdvo_get_tv_modes(connector); |
615fb93f | 1967 | else if (IS_LVDS(intel_sdvo_connector)) |
7086c87f | 1968 | intel_sdvo_get_lvds_modes(connector); |
e2f0ba97 JB |
1969 | else |
1970 | intel_sdvo_get_ddc_modes(connector); | |
1971 | ||
32aad86f | 1972 | return !list_empty(&connector->probed_modes); |
79e53945 JB |
1973 | } |
1974 | ||
1975 | static void intel_sdvo_destroy(struct drm_connector *connector) | |
1976 | { | |
615fb93f | 1977 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
79e53945 | 1978 | |
79e53945 | 1979 | drm_connector_cleanup(connector); |
4b745b1e | 1980 | kfree(intel_sdvo_connector); |
79e53945 JB |
1981 | } |
1982 | ||
1aad7ac0 CW |
1983 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
1984 | { | |
1985 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
1986 | struct edid *edid; | |
1987 | bool has_audio = false; | |
1988 | ||
1989 | if (!intel_sdvo->is_hdmi) | |
1990 | return false; | |
1991 | ||
1992 | edid = intel_sdvo_get_edid(connector); | |
1993 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1994 | has_audio = drm_detect_monitor_audio(edid); | |
38ab8a20 | 1995 | kfree(edid); |
1aad7ac0 CW |
1996 | |
1997 | return has_audio; | |
1998 | } | |
1999 | ||
ce6feabd ZY |
2000 | static int |
2001 | intel_sdvo_set_property(struct drm_connector *connector, | |
2002 | struct drm_property *property, | |
2003 | uint64_t val) | |
2004 | { | |
df0e9248 | 2005 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 2006 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e953fd7b | 2007 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
b9219c5e | 2008 | uint16_t temp_value; |
32aad86f CW |
2009 | uint8_t cmd; |
2010 | int ret; | |
ce6feabd | 2011 | |
662595df | 2012 | ret = drm_object_property_set_value(&connector->base, property, val); |
32aad86f CW |
2013 | if (ret) |
2014 | return ret; | |
ce6feabd | 2015 | |
3f43c48d | 2016 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2017 | int i = val; |
2018 | bool has_audio; | |
2019 | ||
2020 | if (i == intel_sdvo_connector->force_audio) | |
7f36e7ed CW |
2021 | return 0; |
2022 | ||
1aad7ac0 | 2023 | intel_sdvo_connector->force_audio = i; |
7f36e7ed | 2024 | |
c3e5f67b | 2025 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
2026 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
2027 | else | |
c3e5f67b | 2028 | has_audio = (i == HDMI_AUDIO_ON); |
7f36e7ed | 2029 | |
1aad7ac0 | 2030 | if (has_audio == intel_sdvo->has_hdmi_audio) |
7f36e7ed | 2031 | return 0; |
7f36e7ed | 2032 | |
1aad7ac0 | 2033 | intel_sdvo->has_hdmi_audio = has_audio; |
7f36e7ed CW |
2034 | goto done; |
2035 | } | |
2036 | ||
e953fd7b | 2037 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
2038 | bool old_auto = intel_sdvo->color_range_auto; |
2039 | uint32_t old_range = intel_sdvo->color_range; | |
2040 | ||
55bc60db VS |
2041 | switch (val) { |
2042 | case INTEL_BROADCAST_RGB_AUTO: | |
2043 | intel_sdvo->color_range_auto = true; | |
2044 | break; | |
2045 | case INTEL_BROADCAST_RGB_FULL: | |
2046 | intel_sdvo->color_range_auto = false; | |
2047 | intel_sdvo->color_range = 0; | |
2048 | break; | |
2049 | case INTEL_BROADCAST_RGB_LIMITED: | |
2050 | intel_sdvo->color_range_auto = false; | |
4f3a8bc7 PZ |
2051 | /* FIXME: this bit is only valid when using TMDS |
2052 | * encoding and 8 bit per color mode. */ | |
2053 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; | |
55bc60db VS |
2054 | break; |
2055 | default: | |
2056 | return -EINVAL; | |
2057 | } | |
ae4edb80 DV |
2058 | |
2059 | if (old_auto == intel_sdvo->color_range_auto && | |
2060 | old_range == intel_sdvo->color_range) | |
2061 | return 0; | |
2062 | ||
7f36e7ed CW |
2063 | goto done; |
2064 | } | |
2065 | ||
7949dd47 VS |
2066 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
2067 | switch (val) { | |
2068 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
2069 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
2070 | break; | |
2071 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
2072 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
2073 | break; | |
2074 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
2075 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
2076 | break; | |
2077 | default: | |
2078 | return -EINVAL; | |
2079 | } | |
2080 | goto done; | |
2081 | } | |
2082 | ||
c5521706 CW |
2083 | #define CHECK_PROPERTY(name, NAME) \ |
2084 | if (intel_sdvo_connector->name == property) { \ | |
2085 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ | |
2086 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ | |
2087 | cmd = SDVO_CMD_SET_##NAME; \ | |
2088 | intel_sdvo_connector->cur_##name = temp_value; \ | |
2089 | goto set_value; \ | |
2090 | } | |
2091 | ||
2092 | if (property == intel_sdvo_connector->tv_format) { | |
32aad86f CW |
2093 | if (val >= TV_FORMAT_NUM) |
2094 | return -EINVAL; | |
2095 | ||
40039750 | 2096 | if (intel_sdvo->tv_format_index == |
615fb93f | 2097 | intel_sdvo_connector->tv_format_supported[val]) |
32aad86f | 2098 | return 0; |
ce6feabd | 2099 | |
40039750 | 2100 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
c5521706 | 2101 | goto done; |
32aad86f | 2102 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
b9219c5e | 2103 | temp_value = val; |
c5521706 | 2104 | if (intel_sdvo_connector->left == property) { |
662595df | 2105 | drm_object_property_set_value(&connector->base, |
c5521706 | 2106 | intel_sdvo_connector->right, val); |
615fb93f | 2107 | if (intel_sdvo_connector->left_margin == temp_value) |
32aad86f | 2108 | return 0; |
b9219c5e | 2109 | |
615fb93f CW |
2110 | intel_sdvo_connector->left_margin = temp_value; |
2111 | intel_sdvo_connector->right_margin = temp_value; | |
2112 | temp_value = intel_sdvo_connector->max_hscan - | |
c5521706 | 2113 | intel_sdvo_connector->left_margin; |
b9219c5e | 2114 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2115 | goto set_value; |
2116 | } else if (intel_sdvo_connector->right == property) { | |
662595df | 2117 | drm_object_property_set_value(&connector->base, |
c5521706 | 2118 | intel_sdvo_connector->left, val); |
615fb93f | 2119 | if (intel_sdvo_connector->right_margin == temp_value) |
32aad86f | 2120 | return 0; |
b9219c5e | 2121 | |
615fb93f CW |
2122 | intel_sdvo_connector->left_margin = temp_value; |
2123 | intel_sdvo_connector->right_margin = temp_value; | |
2124 | temp_value = intel_sdvo_connector->max_hscan - | |
2125 | intel_sdvo_connector->left_margin; | |
b9219c5e | 2126 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2127 | goto set_value; |
2128 | } else if (intel_sdvo_connector->top == property) { | |
662595df | 2129 | drm_object_property_set_value(&connector->base, |
c5521706 | 2130 | intel_sdvo_connector->bottom, val); |
615fb93f | 2131 | if (intel_sdvo_connector->top_margin == temp_value) |
32aad86f | 2132 | return 0; |
b9219c5e | 2133 | |
615fb93f CW |
2134 | intel_sdvo_connector->top_margin = temp_value; |
2135 | intel_sdvo_connector->bottom_margin = temp_value; | |
2136 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2137 | intel_sdvo_connector->top_margin; |
b9219c5e | 2138 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2139 | goto set_value; |
2140 | } else if (intel_sdvo_connector->bottom == property) { | |
662595df | 2141 | drm_object_property_set_value(&connector->base, |
c5521706 | 2142 | intel_sdvo_connector->top, val); |
615fb93f | 2143 | if (intel_sdvo_connector->bottom_margin == temp_value) |
32aad86f CW |
2144 | return 0; |
2145 | ||
615fb93f CW |
2146 | intel_sdvo_connector->top_margin = temp_value; |
2147 | intel_sdvo_connector->bottom_margin = temp_value; | |
2148 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2149 | intel_sdvo_connector->top_margin; |
b9219c5e | 2150 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2151 | goto set_value; |
2152 | } | |
2153 | CHECK_PROPERTY(hpos, HPOS) | |
2154 | CHECK_PROPERTY(vpos, VPOS) | |
2155 | CHECK_PROPERTY(saturation, SATURATION) | |
2156 | CHECK_PROPERTY(contrast, CONTRAST) | |
2157 | CHECK_PROPERTY(hue, HUE) | |
2158 | CHECK_PROPERTY(brightness, BRIGHTNESS) | |
2159 | CHECK_PROPERTY(sharpness, SHARPNESS) | |
2160 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) | |
2161 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) | |
2162 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) | |
2163 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) | |
2164 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) | |
e044218a | 2165 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
c5521706 | 2166 | } |
b9219c5e | 2167 | |
c5521706 | 2168 | return -EINVAL; /* unknown property */ |
b9219c5e | 2169 | |
c5521706 CW |
2170 | set_value: |
2171 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) | |
2172 | return -EIO; | |
b9219c5e | 2173 | |
b9219c5e | 2174 | |
c5521706 | 2175 | done: |
c0c36b94 CW |
2176 | if (intel_sdvo->base.base.crtc) |
2177 | intel_crtc_restore_mode(intel_sdvo->base.base.crtc); | |
c5521706 | 2178 | |
32aad86f | 2179 | return 0; |
c5521706 | 2180 | #undef CHECK_PROPERTY |
ce6feabd ZY |
2181 | } |
2182 | ||
79e53945 | 2183 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
4d688a2a | 2184 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 JB |
2185 | .detect = intel_sdvo_detect, |
2186 | .fill_modes = drm_helper_probe_single_connector_modes, | |
ce6feabd | 2187 | .set_property = intel_sdvo_set_property, |
2545e4a6 | 2188 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 | 2189 | .destroy = intel_sdvo_destroy, |
c6f95f27 | 2190 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 2191 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
2192 | }; |
2193 | ||
2194 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
2195 | .get_modes = intel_sdvo_get_modes, | |
2196 | .mode_valid = intel_sdvo_mode_valid, | |
df0e9248 | 2197 | .best_encoder = intel_best_encoder, |
79e53945 JB |
2198 | }; |
2199 | ||
b358d0a6 | 2200 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 2201 | { |
8aca63aa | 2202 | struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); |
d2a82a6f | 2203 | |
ea5b213a | 2204 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
d2a82a6f | 2205 | drm_mode_destroy(encoder->dev, |
ea5b213a | 2206 | intel_sdvo->sdvo_lvds_fixed_mode); |
d2a82a6f | 2207 | |
e957d772 | 2208 | i2c_del_adapter(&intel_sdvo->ddc); |
ea5b213a | 2209 | intel_encoder_destroy(encoder); |
79e53945 JB |
2210 | } |
2211 | ||
2212 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
2213 | .destroy = intel_sdvo_enc_destroy, | |
2214 | }; | |
2215 | ||
b66d8424 CW |
2216 | static void |
2217 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) | |
2218 | { | |
2219 | uint16_t mask = 0; | |
2220 | unsigned int num_bits; | |
2221 | ||
2222 | /* Make a mask of outputs less than or equal to our own priority in the | |
2223 | * list. | |
2224 | */ | |
2225 | switch (sdvo->controlled_output) { | |
2226 | case SDVO_OUTPUT_LVDS1: | |
2227 | mask |= SDVO_OUTPUT_LVDS1; | |
2228 | case SDVO_OUTPUT_LVDS0: | |
2229 | mask |= SDVO_OUTPUT_LVDS0; | |
2230 | case SDVO_OUTPUT_TMDS1: | |
2231 | mask |= SDVO_OUTPUT_TMDS1; | |
2232 | case SDVO_OUTPUT_TMDS0: | |
2233 | mask |= SDVO_OUTPUT_TMDS0; | |
2234 | case SDVO_OUTPUT_RGB1: | |
2235 | mask |= SDVO_OUTPUT_RGB1; | |
2236 | case SDVO_OUTPUT_RGB0: | |
2237 | mask |= SDVO_OUTPUT_RGB0; | |
2238 | break; | |
2239 | } | |
2240 | ||
2241 | /* Count bits to find what number we are in the priority list. */ | |
2242 | mask &= sdvo->caps.output_flags; | |
2243 | num_bits = hweight16(mask); | |
2244 | /* If more than 3 outputs, default to DDC bus 3 for now. */ | |
2245 | if (num_bits > 3) | |
2246 | num_bits = 3; | |
2247 | ||
2248 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
2249 | sdvo->ddc_bus = 1 << num_bits; | |
2250 | } | |
79e53945 | 2251 | |
e2f0ba97 JB |
2252 | /** |
2253 | * Choose the appropriate DDC bus for control bus switch command for this | |
2254 | * SDVO output based on the controlled output. | |
2255 | * | |
2256 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
2257 | * outputs, then LVDS outputs. | |
2258 | */ | |
2259 | static void | |
b1083333 | 2260 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
8bd864b8 | 2261 | struct intel_sdvo *sdvo) |
e2f0ba97 | 2262 | { |
b1083333 | 2263 | struct sdvo_device_mapping *mapping; |
e2f0ba97 | 2264 | |
eef4eacb | 2265 | if (sdvo->is_sdvob) |
b1083333 AJ |
2266 | mapping = &(dev_priv->sdvo_mappings[0]); |
2267 | else | |
2268 | mapping = &(dev_priv->sdvo_mappings[1]); | |
e2f0ba97 | 2269 | |
b66d8424 CW |
2270 | if (mapping->initialized) |
2271 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); | |
2272 | else | |
2273 | intel_sdvo_guess_ddc_bus(sdvo); | |
e2f0ba97 JB |
2274 | } |
2275 | ||
e957d772 CW |
2276 | static void |
2277 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, | |
8bd864b8 | 2278 | struct intel_sdvo *sdvo) |
e957d772 CW |
2279 | { |
2280 | struct sdvo_device_mapping *mapping; | |
46eb3036 | 2281 | u8 pin; |
e957d772 | 2282 | |
eef4eacb | 2283 | if (sdvo->is_sdvob) |
e957d772 CW |
2284 | mapping = &dev_priv->sdvo_mappings[0]; |
2285 | else | |
2286 | mapping = &dev_priv->sdvo_mappings[1]; | |
2287 | ||
88ac7939 JN |
2288 | if (mapping->initialized && |
2289 | intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) | |
e957d772 | 2290 | pin = mapping->i2c_pin; |
6cb1612a | 2291 | else |
988c7015 | 2292 | pin = GMBUS_PIN_DPB; |
e957d772 | 2293 | |
6cb1612a JN |
2294 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
2295 | ||
2296 | /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow | |
2297 | * our code totally fails once we start using gmbus. Hence fall back to | |
2298 | * bit banging for now. */ | |
2299 | intel_gmbus_force_bit(sdvo->i2c, true); | |
e957d772 CW |
2300 | } |
2301 | ||
fbfcc4f3 JN |
2302 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
2303 | static void | |
2304 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) | |
2305 | { | |
2306 | intel_gmbus_force_bit(sdvo->i2c, false); | |
e957d772 CW |
2307 | } |
2308 | ||
e2f0ba97 | 2309 | static bool |
e27d8538 | 2310 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
e2f0ba97 | 2311 | { |
97aaf910 | 2312 | return intel_sdvo_check_supp_encode(intel_sdvo); |
e2f0ba97 JB |
2313 | } |
2314 | ||
714605e4 | 2315 | static u8 |
eef4eacb | 2316 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
714605e4 | 2317 | { |
2318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2319 | struct sdvo_device_mapping *my_mapping, *other_mapping; | |
2320 | ||
eef4eacb | 2321 | if (sdvo->is_sdvob) { |
714605e4 | 2322 | my_mapping = &dev_priv->sdvo_mappings[0]; |
2323 | other_mapping = &dev_priv->sdvo_mappings[1]; | |
2324 | } else { | |
2325 | my_mapping = &dev_priv->sdvo_mappings[1]; | |
2326 | other_mapping = &dev_priv->sdvo_mappings[0]; | |
2327 | } | |
2328 | ||
2329 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
2330 | if (my_mapping->slave_addr) | |
2331 | return my_mapping->slave_addr; | |
2332 | ||
2333 | /* If the BIOS only described a different SDVO device, use the | |
2334 | * address that it isn't using. | |
2335 | */ | |
2336 | if (other_mapping->slave_addr) { | |
2337 | if (other_mapping->slave_addr == 0x70) | |
2338 | return 0x72; | |
2339 | else | |
2340 | return 0x70; | |
2341 | } | |
2342 | ||
2343 | /* No SDVO device info is found for another DVO port, | |
2344 | * so use mapping assumption we had before BIOS parsing. | |
2345 | */ | |
eef4eacb | 2346 | if (sdvo->is_sdvob) |
714605e4 | 2347 | return 0x70; |
2348 | else | |
2349 | return 0x72; | |
2350 | } | |
2351 | ||
931c1c26 ID |
2352 | static void |
2353 | intel_sdvo_connector_unregister(struct intel_connector *intel_connector) | |
2354 | { | |
2355 | struct drm_connector *drm_connector; | |
2356 | struct intel_sdvo *sdvo_encoder; | |
2357 | ||
2358 | drm_connector = &intel_connector->base; | |
2359 | sdvo_encoder = intel_attached_sdvo(&intel_connector->base); | |
2360 | ||
2361 | sysfs_remove_link(&drm_connector->kdev->kobj, | |
2362 | sdvo_encoder->ddc.dev.kobj.name); | |
2363 | intel_connector_unregister(intel_connector); | |
2364 | } | |
2365 | ||
c393454d | 2366 | static int |
df0e9248 CW |
2367 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
2368 | struct intel_sdvo *encoder) | |
14571b4c | 2369 | { |
c393454d ID |
2370 | struct drm_connector *drm_connector; |
2371 | int ret; | |
2372 | ||
2373 | drm_connector = &connector->base.base; | |
2374 | ret = drm_connector_init(encoder->base.base.dev, | |
2375 | drm_connector, | |
df0e9248 CW |
2376 | &intel_sdvo_connector_funcs, |
2377 | connector->base.base.connector_type); | |
c393454d ID |
2378 | if (ret < 0) |
2379 | return ret; | |
6070a4a9 | 2380 | |
c393454d | 2381 | drm_connector_helper_add(drm_connector, |
df0e9248 | 2382 | &intel_sdvo_connector_helper_funcs); |
14571b4c | 2383 | |
8f4839e2 | 2384 | connector->base.base.interlace_allowed = 1; |
df0e9248 CW |
2385 | connector->base.base.doublescan_allowed = 0; |
2386 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; | |
4ac41f47 | 2387 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
931c1c26 | 2388 | connector->base.unregister = intel_sdvo_connector_unregister; |
14571b4c | 2389 | |
df0e9248 | 2390 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
34ea3d38 | 2391 | ret = drm_connector_register(drm_connector); |
c393454d ID |
2392 | if (ret < 0) |
2393 | goto err1; | |
2394 | ||
4d43e9bd EE |
2395 | ret = sysfs_create_link(&drm_connector->kdev->kobj, |
2396 | &encoder->ddc.dev.kobj, | |
931c1c26 ID |
2397 | encoder->ddc.dev.kobj.name); |
2398 | if (ret < 0) | |
2399 | goto err2; | |
2400 | ||
c393454d ID |
2401 | return 0; |
2402 | ||
931c1c26 | 2403 | err2: |
34ea3d38 | 2404 | drm_connector_unregister(drm_connector); |
c393454d ID |
2405 | err1: |
2406 | drm_connector_cleanup(drm_connector); | |
2407 | ||
2408 | return ret; | |
14571b4c | 2409 | } |
6070a4a9 | 2410 | |
7f36e7ed | 2411 | static void |
55bc60db VS |
2412 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
2413 | struct intel_sdvo_connector *connector) | |
7f36e7ed CW |
2414 | { |
2415 | struct drm_device *dev = connector->base.base.dev; | |
2416 | ||
3f43c48d | 2417 | intel_attach_force_audio_property(&connector->base.base); |
55bc60db | 2418 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { |
e953fd7b | 2419 | intel_attach_broadcast_rgb_property(&connector->base.base); |
55bc60db VS |
2420 | intel_sdvo->color_range_auto = true; |
2421 | } | |
7949dd47 VS |
2422 | intel_attach_aspect_ratio_property(&connector->base.base); |
2423 | intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
7f36e7ed CW |
2424 | } |
2425 | ||
08d9bc92 ACO |
2426 | static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) |
2427 | { | |
2428 | struct intel_sdvo_connector *sdvo_connector; | |
2429 | ||
2430 | sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); | |
2431 | if (!sdvo_connector) | |
2432 | return NULL; | |
2433 | ||
2434 | if (intel_connector_init(&sdvo_connector->base) < 0) { | |
2435 | kfree(sdvo_connector); | |
2436 | return NULL; | |
2437 | } | |
2438 | ||
2439 | return sdvo_connector; | |
2440 | } | |
2441 | ||
fb7a46f3 | 2442 | static bool |
ea5b213a | 2443 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
fb7a46f3 | 2444 | { |
4ef69c7a | 2445 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
14571b4c | 2446 | struct drm_connector *connector; |
cc68c81a | 2447 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
14571b4c | 2448 | struct intel_connector *intel_connector; |
615fb93f | 2449 | struct intel_sdvo_connector *intel_sdvo_connector; |
14571b4c | 2450 | |
46a3f4a3 CW |
2451 | DRM_DEBUG_KMS("initialising DVI device %d\n", device); |
2452 | ||
08d9bc92 | 2453 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f | 2454 | if (!intel_sdvo_connector) |
14571b4c ZW |
2455 | return false; |
2456 | ||
14571b4c | 2457 | if (device == 0) { |
ea5b213a | 2458 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
615fb93f | 2459 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
14571b4c | 2460 | } else if (device == 1) { |
ea5b213a | 2461 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
615fb93f | 2462 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
14571b4c ZW |
2463 | } |
2464 | ||
615fb93f | 2465 | intel_connector = &intel_sdvo_connector->base; |
14571b4c | 2466 | connector = &intel_connector->base; |
5fa7ac9c JN |
2467 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
2468 | intel_sdvo_connector->output_flag) { | |
5fa7ac9c | 2469 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
cc68c81a SF |
2470 | /* Some SDVO devices have one-shot hotplug interrupts. |
2471 | * Ensure that they get re-enabled when an interrupt happens. | |
2472 | */ | |
2473 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; | |
3a2fb2c3 | 2474 | intel_sdvo_enable_hotplug(intel_encoder); |
5fa7ac9c | 2475 | } else { |
821450c6 | 2476 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
5fa7ac9c | 2477 | } |
14571b4c ZW |
2478 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
2479 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; | |
2480 | ||
e27d8538 | 2481 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
14571b4c | 2482 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
e27d8538 | 2483 | intel_sdvo->is_hdmi = true; |
14571b4c | 2484 | } |
14571b4c | 2485 | |
c393454d ID |
2486 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2487 | kfree(intel_sdvo_connector); | |
2488 | return false; | |
2489 | } | |
2490 | ||
f797d221 | 2491 | if (intel_sdvo->is_hdmi) |
55bc60db | 2492 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
14571b4c ZW |
2493 | |
2494 | return true; | |
2495 | } | |
2496 | ||
2497 | static bool | |
ea5b213a | 2498 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
14571b4c | 2499 | { |
4ef69c7a CW |
2500 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2501 | struct drm_connector *connector; | |
2502 | struct intel_connector *intel_connector; | |
2503 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2504 | |
46a3f4a3 CW |
2505 | DRM_DEBUG_KMS("initialising TV type %d\n", type); |
2506 | ||
08d9bc92 | 2507 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f CW |
2508 | if (!intel_sdvo_connector) |
2509 | return false; | |
14571b4c | 2510 | |
615fb93f | 2511 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a CW |
2512 | connector = &intel_connector->base; |
2513 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | |
2514 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
14571b4c | 2515 | |
4ef69c7a CW |
2516 | intel_sdvo->controlled_output |= type; |
2517 | intel_sdvo_connector->output_flag = type; | |
14571b4c | 2518 | |
4ef69c7a | 2519 | intel_sdvo->is_tv = true; |
14571b4c | 2520 | |
c393454d ID |
2521 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2522 | kfree(intel_sdvo_connector); | |
2523 | return false; | |
2524 | } | |
14571b4c | 2525 | |
4ef69c7a | 2526 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
32aad86f | 2527 | goto err; |
14571b4c | 2528 | |
4ef69c7a | 2529 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f | 2530 | goto err; |
14571b4c | 2531 | |
4ef69c7a | 2532 | return true; |
32aad86f CW |
2533 | |
2534 | err: | |
34ea3d38 | 2535 | drm_connector_unregister(connector); |
123d5c01 | 2536 | intel_sdvo_destroy(connector); |
32aad86f | 2537 | return false; |
14571b4c ZW |
2538 | } |
2539 | ||
2540 | static bool | |
ea5b213a | 2541 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2542 | { |
4ef69c7a CW |
2543 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2544 | struct drm_connector *connector; | |
2545 | struct intel_connector *intel_connector; | |
2546 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2547 | |
46a3f4a3 CW |
2548 | DRM_DEBUG_KMS("initialising analog device %d\n", device); |
2549 | ||
8ce7da47 | 2550 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f CW |
2551 | if (!intel_sdvo_connector) |
2552 | return false; | |
14571b4c | 2553 | |
615fb93f | 2554 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a | 2555 | connector = &intel_connector->base; |
821450c6 | 2556 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
4ef69c7a CW |
2557 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
2558 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
2559 | ||
2560 | if (device == 0) { | |
2561 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; | |
2562 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; | |
2563 | } else if (device == 1) { | |
2564 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; | |
2565 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; | |
2566 | } | |
2567 | ||
c393454d ID |
2568 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2569 | kfree(intel_sdvo_connector); | |
2570 | return false; | |
2571 | } | |
2572 | ||
4ef69c7a | 2573 | return true; |
14571b4c ZW |
2574 | } |
2575 | ||
2576 | static bool | |
ea5b213a | 2577 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2578 | { |
4ef69c7a CW |
2579 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2580 | struct drm_connector *connector; | |
2581 | struct intel_connector *intel_connector; | |
2582 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2583 | |
46a3f4a3 CW |
2584 | DRM_DEBUG_KMS("initialising LVDS device %d\n", device); |
2585 | ||
08d9bc92 | 2586 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f CW |
2587 | if (!intel_sdvo_connector) |
2588 | return false; | |
14571b4c | 2589 | |
615fb93f CW |
2590 | intel_connector = &intel_sdvo_connector->base; |
2591 | connector = &intel_connector->base; | |
4ef69c7a CW |
2592 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
2593 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2594 | ||
2595 | if (device == 0) { | |
2596 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; | |
2597 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; | |
2598 | } else if (device == 1) { | |
2599 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; | |
2600 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; | |
2601 | } | |
2602 | ||
c393454d ID |
2603 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2604 | kfree(intel_sdvo_connector); | |
2605 | return false; | |
2606 | } | |
2607 | ||
4ef69c7a | 2608 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f CW |
2609 | goto err; |
2610 | ||
2611 | return true; | |
2612 | ||
2613 | err: | |
34ea3d38 | 2614 | drm_connector_unregister(connector); |
123d5c01 | 2615 | intel_sdvo_destroy(connector); |
32aad86f | 2616 | return false; |
14571b4c ZW |
2617 | } |
2618 | ||
2619 | static bool | |
ea5b213a | 2620 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
14571b4c | 2621 | { |
ea5b213a | 2622 | intel_sdvo->is_tv = false; |
ea5b213a | 2623 | intel_sdvo->is_lvds = false; |
fb7a46f3 | 2624 | |
14571b4c | 2625 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
fb7a46f3 | 2626 | |
14571b4c | 2627 | if (flags & SDVO_OUTPUT_TMDS0) |
ea5b213a | 2628 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
14571b4c ZW |
2629 | return false; |
2630 | ||
2631 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) | |
ea5b213a | 2632 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
14571b4c ZW |
2633 | return false; |
2634 | ||
2635 | /* TV has no XXX1 function block */ | |
a1f4b7ff | 2636 | if (flags & SDVO_OUTPUT_SVID0) |
ea5b213a | 2637 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
14571b4c ZW |
2638 | return false; |
2639 | ||
2640 | if (flags & SDVO_OUTPUT_CVBS0) | |
ea5b213a | 2641 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
14571b4c | 2642 | return false; |
fb7a46f3 | 2643 | |
a0b1c7a5 CW |
2644 | if (flags & SDVO_OUTPUT_YPRPB0) |
2645 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) | |
2646 | return false; | |
2647 | ||
14571b4c | 2648 | if (flags & SDVO_OUTPUT_RGB0) |
ea5b213a | 2649 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
14571b4c ZW |
2650 | return false; |
2651 | ||
2652 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) | |
ea5b213a | 2653 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
14571b4c ZW |
2654 | return false; |
2655 | ||
2656 | if (flags & SDVO_OUTPUT_LVDS0) | |
ea5b213a | 2657 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
14571b4c ZW |
2658 | return false; |
2659 | ||
2660 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) | |
ea5b213a | 2661 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
14571b4c | 2662 | return false; |
fb7a46f3 | 2663 | |
14571b4c | 2664 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
fb7a46f3 | 2665 | unsigned char bytes[2]; |
2666 | ||
ea5b213a CW |
2667 | intel_sdvo->controlled_output = 0; |
2668 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); | |
51c8b407 | 2669 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
ea5b213a | 2670 | SDVO_NAME(intel_sdvo), |
51c8b407 | 2671 | bytes[0], bytes[1]); |
14571b4c | 2672 | return false; |
fb7a46f3 | 2673 | } |
27f8227b | 2674 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
fb7a46f3 | 2675 | |
14571b4c | 2676 | return true; |
fb7a46f3 | 2677 | } |
2678 | ||
d0ddfbd3 JN |
2679 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
2680 | { | |
2681 | struct drm_device *dev = intel_sdvo->base.base.dev; | |
2682 | struct drm_connector *connector, *tmp; | |
2683 | ||
2684 | list_for_each_entry_safe(connector, tmp, | |
2685 | &dev->mode_config.connector_list, head) { | |
d9255d57 | 2686 | if (intel_attached_encoder(connector) == &intel_sdvo->base) { |
34ea3d38 | 2687 | drm_connector_unregister(connector); |
d0ddfbd3 | 2688 | intel_sdvo_destroy(connector); |
d9255d57 | 2689 | } |
d0ddfbd3 JN |
2690 | } |
2691 | } | |
2692 | ||
32aad86f CW |
2693 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2694 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2695 | int type) | |
ce6feabd | 2696 | { |
4ef69c7a | 2697 | struct drm_device *dev = intel_sdvo->base.base.dev; |
ce6feabd ZY |
2698 | struct intel_sdvo_tv_format format; |
2699 | uint32_t format_map, i; | |
ce6feabd | 2700 | |
32aad86f CW |
2701 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
2702 | return false; | |
ce6feabd | 2703 | |
1a3665c8 | 2704 | BUILD_BUG_ON(sizeof(format) != 6); |
32aad86f CW |
2705 | if (!intel_sdvo_get_value(intel_sdvo, |
2706 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, | |
2707 | &format, sizeof(format))) | |
2708 | return false; | |
ce6feabd | 2709 | |
32aad86f | 2710 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
ce6feabd ZY |
2711 | |
2712 | if (format_map == 0) | |
32aad86f | 2713 | return false; |
ce6feabd | 2714 | |
615fb93f | 2715 | intel_sdvo_connector->format_supported_num = 0; |
ce6feabd | 2716 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
40039750 CW |
2717 | if (format_map & (1 << i)) |
2718 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; | |
ce6feabd ZY |
2719 | |
2720 | ||
c5521706 | 2721 | intel_sdvo_connector->tv_format = |
32aad86f CW |
2722 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
2723 | "mode", intel_sdvo_connector->format_supported_num); | |
c5521706 | 2724 | if (!intel_sdvo_connector->tv_format) |
fcc8d672 | 2725 | return false; |
ce6feabd | 2726 | |
615fb93f | 2727 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
ce6feabd | 2728 | drm_property_add_enum( |
c5521706 | 2729 | intel_sdvo_connector->tv_format, i, |
40039750 | 2730 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
ce6feabd | 2731 | |
40039750 | 2732 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
662595df | 2733 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
c5521706 | 2734 | intel_sdvo_connector->tv_format, 0); |
32aad86f | 2735 | return true; |
ce6feabd ZY |
2736 | |
2737 | } | |
2738 | ||
c5521706 CW |
2739 | #define ENHANCEMENT(name, NAME) do { \ |
2740 | if (enhancements.name) { \ | |
2741 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ | |
2742 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ | |
2743 | return false; \ | |
2744 | intel_sdvo_connector->max_##name = data_value[0]; \ | |
2745 | intel_sdvo_connector->cur_##name = response; \ | |
2746 | intel_sdvo_connector->name = \ | |
d9bc3c02 | 2747 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
c5521706 | 2748 | if (!intel_sdvo_connector->name) return false; \ |
662595df | 2749 | drm_object_attach_property(&connector->base, \ |
c5521706 CW |
2750 | intel_sdvo_connector->name, \ |
2751 | intel_sdvo_connector->cur_##name); \ | |
2752 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ | |
2753 | data_value[0], data_value[1], response); \ | |
2754 | } \ | |
0206e353 | 2755 | } while (0) |
c5521706 CW |
2756 | |
2757 | static bool | |
2758 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, | |
2759 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2760 | struct intel_sdvo_enhancements_reply enhancements) | |
b9219c5e | 2761 | { |
4ef69c7a | 2762 | struct drm_device *dev = intel_sdvo->base.base.dev; |
32aad86f | 2763 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
b9219c5e ZY |
2764 | uint16_t response, data_value[2]; |
2765 | ||
c5521706 CW |
2766 | /* when horizontal overscan is supported, Add the left/right property */ |
2767 | if (enhancements.overscan_h) { | |
2768 | if (!intel_sdvo_get_value(intel_sdvo, | |
2769 | SDVO_CMD_GET_MAX_OVERSCAN_H, | |
2770 | &data_value, 4)) | |
2771 | return false; | |
32aad86f | 2772 | |
c5521706 CW |
2773 | if (!intel_sdvo_get_value(intel_sdvo, |
2774 | SDVO_CMD_GET_OVERSCAN_H, | |
2775 | &response, 2)) | |
2776 | return false; | |
fcc8d672 | 2777 | |
c5521706 CW |
2778 | intel_sdvo_connector->max_hscan = data_value[0]; |
2779 | intel_sdvo_connector->left_margin = data_value[0] - response; | |
2780 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; | |
2781 | intel_sdvo_connector->left = | |
d9bc3c02 | 2782 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
c5521706 CW |
2783 | if (!intel_sdvo_connector->left) |
2784 | return false; | |
fcc8d672 | 2785 | |
662595df | 2786 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2787 | intel_sdvo_connector->left, |
2788 | intel_sdvo_connector->left_margin); | |
fcc8d672 | 2789 | |
c5521706 | 2790 | intel_sdvo_connector->right = |
d9bc3c02 | 2791 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
c5521706 CW |
2792 | if (!intel_sdvo_connector->right) |
2793 | return false; | |
32aad86f | 2794 | |
662595df | 2795 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2796 | intel_sdvo_connector->right, |
2797 | intel_sdvo_connector->right_margin); | |
2798 | DRM_DEBUG_KMS("h_overscan: max %d, " | |
2799 | "default %d, current %d\n", | |
2800 | data_value[0], data_value[1], response); | |
2801 | } | |
32aad86f | 2802 | |
c5521706 CW |
2803 | if (enhancements.overscan_v) { |
2804 | if (!intel_sdvo_get_value(intel_sdvo, | |
2805 | SDVO_CMD_GET_MAX_OVERSCAN_V, | |
2806 | &data_value, 4)) | |
2807 | return false; | |
fcc8d672 | 2808 | |
c5521706 CW |
2809 | if (!intel_sdvo_get_value(intel_sdvo, |
2810 | SDVO_CMD_GET_OVERSCAN_V, | |
2811 | &response, 2)) | |
2812 | return false; | |
32aad86f | 2813 | |
c5521706 CW |
2814 | intel_sdvo_connector->max_vscan = data_value[0]; |
2815 | intel_sdvo_connector->top_margin = data_value[0] - response; | |
2816 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; | |
2817 | intel_sdvo_connector->top = | |
d9bc3c02 SH |
2818 | drm_property_create_range(dev, 0, |
2819 | "top_margin", 0, data_value[0]); | |
c5521706 CW |
2820 | if (!intel_sdvo_connector->top) |
2821 | return false; | |
32aad86f | 2822 | |
662595df | 2823 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2824 | intel_sdvo_connector->top, |
2825 | intel_sdvo_connector->top_margin); | |
fcc8d672 | 2826 | |
c5521706 | 2827 | intel_sdvo_connector->bottom = |
d9bc3c02 SH |
2828 | drm_property_create_range(dev, 0, |
2829 | "bottom_margin", 0, data_value[0]); | |
c5521706 CW |
2830 | if (!intel_sdvo_connector->bottom) |
2831 | return false; | |
32aad86f | 2832 | |
662595df | 2833 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2834 | intel_sdvo_connector->bottom, |
2835 | intel_sdvo_connector->bottom_margin); | |
2836 | DRM_DEBUG_KMS("v_overscan: max %d, " | |
2837 | "default %d, current %d\n", | |
2838 | data_value[0], data_value[1], response); | |
2839 | } | |
32aad86f | 2840 | |
c5521706 CW |
2841 | ENHANCEMENT(hpos, HPOS); |
2842 | ENHANCEMENT(vpos, VPOS); | |
2843 | ENHANCEMENT(saturation, SATURATION); | |
2844 | ENHANCEMENT(contrast, CONTRAST); | |
2845 | ENHANCEMENT(hue, HUE); | |
2846 | ENHANCEMENT(sharpness, SHARPNESS); | |
2847 | ENHANCEMENT(brightness, BRIGHTNESS); | |
2848 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); | |
2849 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); | |
2850 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); | |
2851 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); | |
2852 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); | |
fcc8d672 | 2853 | |
e044218a CW |
2854 | if (enhancements.dot_crawl) { |
2855 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) | |
2856 | return false; | |
2857 | ||
2858 | intel_sdvo_connector->max_dot_crawl = 1; | |
2859 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; | |
2860 | intel_sdvo_connector->dot_crawl = | |
d9bc3c02 | 2861 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
e044218a CW |
2862 | if (!intel_sdvo_connector->dot_crawl) |
2863 | return false; | |
2864 | ||
662595df | 2865 | drm_object_attach_property(&connector->base, |
e044218a CW |
2866 | intel_sdvo_connector->dot_crawl, |
2867 | intel_sdvo_connector->cur_dot_crawl); | |
2868 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); | |
2869 | } | |
2870 | ||
c5521706 CW |
2871 | return true; |
2872 | } | |
32aad86f | 2873 | |
c5521706 CW |
2874 | static bool |
2875 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, | |
2876 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2877 | struct intel_sdvo_enhancements_reply enhancements) | |
2878 | { | |
4ef69c7a | 2879 | struct drm_device *dev = intel_sdvo->base.base.dev; |
c5521706 CW |
2880 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
2881 | uint16_t response, data_value[2]; | |
32aad86f | 2882 | |
c5521706 | 2883 | ENHANCEMENT(brightness, BRIGHTNESS); |
fcc8d672 | 2884 | |
c5521706 CW |
2885 | return true; |
2886 | } | |
2887 | #undef ENHANCEMENT | |
32aad86f | 2888 | |
c5521706 CW |
2889 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
2890 | struct intel_sdvo_connector *intel_sdvo_connector) | |
2891 | { | |
2892 | union { | |
2893 | struct intel_sdvo_enhancements_reply reply; | |
2894 | uint16_t response; | |
2895 | } enhancements; | |
32aad86f | 2896 | |
1a3665c8 CW |
2897 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
2898 | ||
cf9a2f3a CW |
2899 | enhancements.response = 0; |
2900 | intel_sdvo_get_value(intel_sdvo, | |
2901 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, | |
2902 | &enhancements, sizeof(enhancements)); | |
c5521706 CW |
2903 | if (enhancements.response == 0) { |
2904 | DRM_DEBUG_KMS("No enhancement is supported\n"); | |
2905 | return true; | |
b9219c5e | 2906 | } |
32aad86f | 2907 | |
c5521706 CW |
2908 | if (IS_TV(intel_sdvo_connector)) |
2909 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); | |
0206e353 | 2910 | else if (IS_LVDS(intel_sdvo_connector)) |
c5521706 CW |
2911 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2912 | else | |
2913 | return true; | |
e957d772 CW |
2914 | } |
2915 | ||
2916 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, | |
2917 | struct i2c_msg *msgs, | |
2918 | int num) | |
2919 | { | |
2920 | struct intel_sdvo *sdvo = adapter->algo_data; | |
fcc8d672 | 2921 | |
e957d772 CW |
2922 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
2923 | return -EIO; | |
2924 | ||
2925 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); | |
2926 | } | |
2927 | ||
2928 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) | |
2929 | { | |
2930 | struct intel_sdvo *sdvo = adapter->algo_data; | |
2931 | return sdvo->i2c->algo->functionality(sdvo->i2c); | |
2932 | } | |
2933 | ||
2934 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { | |
2935 | .master_xfer = intel_sdvo_ddc_proxy_xfer, | |
2936 | .functionality = intel_sdvo_ddc_proxy_func | |
2937 | }; | |
2938 | ||
2939 | static bool | |
2940 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, | |
2941 | struct drm_device *dev) | |
2942 | { | |
2943 | sdvo->ddc.owner = THIS_MODULE; | |
2944 | sdvo->ddc.class = I2C_CLASS_DDC; | |
2945 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); | |
2946 | sdvo->ddc.dev.parent = &dev->pdev->dev; | |
2947 | sdvo->ddc.algo_data = sdvo; | |
2948 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; | |
2949 | ||
2950 | return i2c_add_adapter(&sdvo->ddc) == 0; | |
b9219c5e ZY |
2951 | } |
2952 | ||
eef4eacb | 2953 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) |
79e53945 | 2954 | { |
b01f2c3a | 2955 | struct drm_i915_private *dev_priv = dev->dev_private; |
21d40d37 | 2956 | struct intel_encoder *intel_encoder; |
ea5b213a | 2957 | struct intel_sdvo *intel_sdvo; |
79e53945 | 2958 | int i; |
b14c5679 | 2959 | intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); |
ea5b213a | 2960 | if (!intel_sdvo) |
7d57382e | 2961 | return false; |
79e53945 | 2962 | |
56184e3d | 2963 | intel_sdvo->sdvo_reg = sdvo_reg; |
eef4eacb DV |
2964 | intel_sdvo->is_sdvob = is_sdvob; |
2965 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; | |
8bd864b8 | 2966 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); |
fbfcc4f3 JN |
2967 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) |
2968 | goto err_i2c_bus; | |
e957d772 | 2969 | |
56184e3d | 2970 | /* encoder type will be decided later */ |
ea5b213a | 2971 | intel_encoder = &intel_sdvo->base; |
21d40d37 | 2972 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
373a3cf7 | 2973 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
79e53945 | 2974 | |
79e53945 JB |
2975 | /* Read the regs to test if we can talk to the device */ |
2976 | for (i = 0; i < 0x40; i++) { | |
f899fc64 CW |
2977 | u8 byte; |
2978 | ||
2979 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { | |
eef4eacb DV |
2980 | DRM_DEBUG_KMS("No SDVO device found on %s\n", |
2981 | SDVO_NAME(intel_sdvo)); | |
f899fc64 | 2982 | goto err; |
79e53945 JB |
2983 | } |
2984 | } | |
2985 | ||
6cc5f341 | 2986 | intel_encoder->compute_config = intel_sdvo_compute_config; |
3c65d1d1 VS |
2987 | if (HAS_PCH_SPLIT(dev)) { |
2988 | intel_encoder->disable = pch_disable_sdvo; | |
2989 | intel_encoder->post_disable = pch_post_disable_sdvo; | |
2990 | } else { | |
2991 | intel_encoder->disable = intel_disable_sdvo; | |
2992 | } | |
192d47a6 | 2993 | intel_encoder->pre_enable = intel_sdvo_pre_enable; |
ce22c320 | 2994 | intel_encoder->enable = intel_enable_sdvo; |
4ac41f47 | 2995 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
045ac3b5 | 2996 | intel_encoder->get_config = intel_sdvo_get_config; |
ce22c320 | 2997 | |
af901ca1 | 2998 | /* In default case sdvo lvds is false */ |
32aad86f | 2999 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
f899fc64 | 3000 | goto err; |
79e53945 | 3001 | |
ea5b213a CW |
3002 | if (intel_sdvo_output_setup(intel_sdvo, |
3003 | intel_sdvo->caps.output_flags) != true) { | |
eef4eacb DV |
3004 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
3005 | SDVO_NAME(intel_sdvo)); | |
d0ddfbd3 JN |
3006 | /* Output_setup can leave behind connectors! */ |
3007 | goto err_output; | |
79e53945 JB |
3008 | } |
3009 | ||
7ba220ce CW |
3010 | /* Only enable the hotplug irq if we need it, to work around noisy |
3011 | * hotplug lines. | |
3012 | */ | |
3013 | if (intel_sdvo->hotplug_active) { | |
3014 | intel_encoder->hpd_pin = | |
3015 | intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; | |
3016 | } | |
3017 | ||
e506d6fd DV |
3018 | /* |
3019 | * Cloning SDVO with anything is often impossible, since the SDVO | |
3020 | * encoder can request a special input timing mode. And even if that's | |
3021 | * not the case we have evidence that cloning a plain unscaled mode with | |
3022 | * VGA doesn't really work. Furthermore the cloning flags are way too | |
3023 | * simplistic anyway to express such constraints, so just give up on | |
3024 | * cloning for SDVO encoders. | |
3025 | */ | |
bc079e8b | 3026 | intel_sdvo->base.cloneable = 0; |
e506d6fd | 3027 | |
8bd864b8 | 3028 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); |
e2f0ba97 | 3029 | |
79e53945 | 3030 | /* Set the input timing to the screen. Assume always input 0. */ |
32aad86f | 3031 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
d0ddfbd3 | 3032 | goto err_output; |
79e53945 | 3033 | |
32aad86f CW |
3034 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
3035 | &intel_sdvo->pixel_clock_min, | |
3036 | &intel_sdvo->pixel_clock_max)) | |
d0ddfbd3 | 3037 | goto err_output; |
79e53945 | 3038 | |
8a4c47f3 | 3039 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
342dc382 | 3040 | "clock range %dMHz - %dMHz, " |
3041 | "input 1: %c, input 2: %c, " | |
3042 | "output 1: %c, output 2: %c\n", | |
ea5b213a CW |
3043 | SDVO_NAME(intel_sdvo), |
3044 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, | |
3045 | intel_sdvo->caps.device_rev_id, | |
3046 | intel_sdvo->pixel_clock_min / 1000, | |
3047 | intel_sdvo->pixel_clock_max / 1000, | |
3048 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
3049 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
342dc382 | 3050 | /* check currently supported outputs */ |
ea5b213a | 3051 | intel_sdvo->caps.output_flags & |
79e53945 | 3052 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
ea5b213a | 3053 | intel_sdvo->caps.output_flags & |
79e53945 | 3054 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
7d57382e | 3055 | return true; |
79e53945 | 3056 | |
d0ddfbd3 JN |
3057 | err_output: |
3058 | intel_sdvo_output_cleanup(intel_sdvo); | |
3059 | ||
f899fc64 | 3060 | err: |
373a3cf7 | 3061 | drm_encoder_cleanup(&intel_encoder->base); |
e957d772 | 3062 | i2c_del_adapter(&intel_sdvo->ddc); |
fbfcc4f3 JN |
3063 | err_i2c_bus: |
3064 | intel_sdvo_unselect_i2c_bus(intel_sdvo); | |
ea5b213a | 3065 | kfree(intel_sdvo); |
79e53945 | 3066 | |
7d57382e | 3067 | return false; |
79e53945 | 3068 | } |