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drm/i915: remove disabled memset of framebuffer from intel_fb
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
83 * i830_sdvo_get_capabilities()
84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
890f3359 205static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 206{
4ef69c7a 207 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
212 return container_of(intel_attached_encoder(connector),
213 struct intel_sdvo, base);
214}
215
615fb93f
CW		 216static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
217{
218 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
219}
220
fb7a46f3 221static bool
ea5b213a 222intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 223static bool
224intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
225 struct intel_sdvo_connector *intel_sdvo_connector,
226 int type);
227static bool
228intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
229 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 230
79e53945
JB		 231/**
232 * Writes the SDVOB or SDVOC with the given value, but always writes both
233 * SDVOB and SDVOC to work around apparent hardware issues (according to
234 * comments in the BIOS).
235 */
ea5b213a 236static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 237{
4ef69c7a 238 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 239 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 240 u32 bval = val, cval = val;
241 int i;
242
ea5b213a
CW		 243 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
244 I915_WRITE(intel_sdvo->sdvo_reg, val);
245 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 246 return;
247 }
248
ea5b213a 249 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 250 cval = I915_READ(SDVOC);
251 } else {
252 bval = I915_READ(SDVOB);
253 }
254 /*
255 * Write the registers twice for luck. Sometimes,
256 * writing them only once doesn't appear to 'stick'.
257 * The BIOS does this too. Yay, magic
258 */
259 for (i = 0; i < 2; i++)
260 {
261 I915_WRITE(SDVOB, bval);
262 I915_READ(SDVOB);
263 I915_WRITE(SDVOC, cval);
264 I915_READ(SDVOC);
265 }
266}
267
32aad86f 268static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 269{
79e53945
JB		 270 struct i2c_msg msgs[] = {
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = 0,
274 .len = 1,
e957d772 275 .buf = &addr,
79e53945
JB		 276 },
277 {
e957d772 278 .addr = intel_sdvo->slave_addr,
79e53945
JB		 279 .flags = I2C_M_RD,
280 .len = 1,
e957d772 281 .buf = ch,
79e53945
JB		 282 }
283 };
32aad86f 284 int ret;
79e53945 285
f899fc64 286 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 287 return true;
79e53945 288
8a4c47f3 289 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 290 return false;
291}
292
79e53945
JB		 293#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
294/** Mapping of command numbers to names, for debug output */
005568be 295static const struct _sdvo_cmd_name {
e2f0ba97 296 u8 cmd;
2e88e40b 297 const char *name;
79e53945 298} sdvo_cmd_names[] = {
0206e353
AJ		 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
342
343 /* Add the op code for SDVO enhancements */
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
388
389 /* HDMI op code */
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 410};
411
eef4eacb 412#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 413
ea5b213a 414static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 415 const void *args, int args_len)
79e53945 416{
79e53945
JB		 417 int i;
418
8a4c47f3 419 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 420 SDVO_NAME(intel_sdvo), cmd);
79e53945 421 for (i = 0; i < args_len; i++)
342dc382 422 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 423 for (; i < 8; i++)
342dc382 424 DRM_LOG_KMS(" ");
04ad327f 425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 426 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 427 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 428 break;
429 }
430 }
04ad327f 431 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 432 DRM_LOG_KMS("(%02X)", cmd);
433 DRM_LOG_KMS("\n");
79e53945 434}
79e53945 435
e957d772
CW		 436static const char *cmd_status_names[] = {
437 "Power on",
438 "Success",
439 "Not supported",
440 "Invalid arg",
441 "Pending",
442 "Target not specified",
443 "Scaling not supported"
444};
445
32aad86f
CW		 446static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
447 const void *args, int args_len)
79e53945 448{
3bf3f452
BW		 449 u8 *buf, status;
450 struct i2c_msg *msgs;
451 int i, ret = true;
452
0274df3e 453 /* Would be simpler to allocate both in one go ? */
3bf3f452
BW		 454 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
455 if (!buf)
456 return false;
457
458 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 459 if (!msgs) {
460 kfree(buf);
3bf3f452 461 return false;
0274df3e 462 }
79e53945 463
ea5b213a 464 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 465
466 for (i = 0; i < args_len; i++) {
e957d772
CW		 467 msgs[i].addr = intel_sdvo->slave_addr;
468 msgs[i].flags = 0;
469 msgs[i].len = 2;
470 msgs[i].buf = buf + 2 *i;
471 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
472 buf[2*i + 1] = ((u8*)args)[i];
473 }
474 msgs[i].addr = intel_sdvo->slave_addr;
475 msgs[i].flags = 0;
476 msgs[i].len = 2;
477 msgs[i].buf = buf + 2*i;
478 buf[2*i + 0] = SDVO_I2C_OPCODE;
479 buf[2*i + 1] = cmd;
480
481 /* the following two are to read the response */
482 status = SDVO_I2C_CMD_STATUS;
483 msgs[i+1].addr = intel_sdvo->slave_addr;
484 msgs[i+1].flags = 0;
485 msgs[i+1].len = 1;
486 msgs[i+1].buf = &status;
487
488 msgs[i+2].addr = intel_sdvo->slave_addr;
489 msgs[i+2].flags = I2C_M_RD;
490 msgs[i+2].len = 1;
491 msgs[i+2].buf = &status;
492
493 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
494 if (ret < 0) {
495 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 496 ret = false;
497 goto out;
e957d772
CW		 498 }
499 if (ret != i+3) {
500 /* failure in I2C transfer */
501 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 502 ret = false;
e957d772
CW		 503 }
504
3bf3f452
BW		 505out:
506 kfree(msgs);
507 kfree(buf);
508 return ret;
79e53945
JB		 509}
510
b5c616a7
CW		 511static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
512 void *response, int response_len)
79e53945 513{
fc37381c 514 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 515 u8 status;
33b52961 516 int i;
79e53945 517
d121a5d2
CW		 518 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
519
b5c616a7
CW		 520 /*
521 * The documentation states that all commands will be
522 * processed within 15µs, and that we need only poll
523 * the status byte a maximum of 3 times in order for the
524 * command to be complete.
525 *
526 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 527 *
528 * Also beware that the first response by many devices is to
529 * reply PENDING and stall for time. TVs are notorious for
530 * requiring longer than specified to complete their replies.
531 * Originally (in the DDX long ago), the delay was only ever 15ms
532 * with an additional delay of 30ms applied for TVs added later after
533 * many experiments. To accommodate both sets of delays, we do a
534 * sequence of slow checks if the device is falling behind and fails
535 * to reply within 5*15µs.
b5c616a7 536 */
d121a5d2
CW		 537 if (!intel_sdvo_read_byte(intel_sdvo,
538 SDVO_I2C_CMD_STATUS,
539 &status))
540 goto log_fail;
541
fc37381c
CW		 542 while (status == SDVO_CMD_STATUS_PENDING && --retry) {
543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
b5c616a7
CW		 548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
d121a5d2
CW		 551 goto log_fail;
552 }
b5c616a7 553
79e53945 554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 556 else
342dc382 557 DRM_LOG_KMS("(??? %d)", status);
79e53945 558
b5c616a7
CW		 559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
79e53945 561
b5c616a7
CW		 562 /* Read the command response */
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
e957d772 568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 569 }
b5c616a7 570 DRM_LOG_KMS("\n");
b5c616a7 571 return true;
79e53945 572
b5c616a7 573log_fail:
d121a5d2 574 DRM_LOG_KMS("... failed\n");
b5c616a7 575 return false;
79e53945
JB		 576}
577
b358d0a6 578static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 579{
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586}
587
e957d772
CW		 588static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
79e53945 590{
d121a5d2 591 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
79e53945
JB		 595}
596
32aad86f 597static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 598{
d121a5d2
CW		 599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 603}
79e53945 604
32aad86f
CW		 605static bool
606intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607{
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
79e53945 610
32aad86f
CW		 611 return intel_sdvo_read_response(intel_sdvo, value, len);
612}
79e53945 613
32aad86f
CW		 614static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615{
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
79e53945
JB		 620}
621
622/**
623 * Return whether each input is trained.
624 *
625 * This function is making an assumption about the layout of the response,
626 * which should be checked against the docs.
627 */
ea5b213a 628static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 629{
630 struct intel_sdvo_get_trained_inputs_response response;
79e53945 631
1a3665c8 632 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
79e53945
JB		 635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640}
641
ea5b213a 642static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 643 u16 outputs)
644{
32aad86f
CW		 645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
79e53945
JB		 648}
649
4ac41f47
DV		 650static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652{
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656}
657
ea5b213a 658static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 659 int mode)
660{
32aad86f 661 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
32aad86f
CW		 678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 680}
681
ea5b213a 682static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int *clock_min,
684 int *clock_max)
685{
686 struct intel_sdvo_pixel_clock_range clocks;
79e53945 687
1a3665c8 688 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
79e53945
JB		 692 return false;
693
694 /* Convert the values from units of 10 kHz to kHz. */
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
79e53945
JB		 697 return true;
698}
699
ea5b213a 700static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 701 u16 outputs)
702{
32aad86f
CW		 703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
79e53945
JB		 706}
707
ea5b213a 708static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 709 struct intel_sdvo_dtd *dtd)
710{
32aad86f
CW		 711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 713}
714
ea5b213a 715static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 716 struct intel_sdvo_dtd *dtd)
717{
ea5b213a 718 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 719 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
720}
721
ea5b213a 722static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 723 struct intel_sdvo_dtd *dtd)
724{
ea5b213a 725 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 726 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
727}
728
e2f0ba97 729static bool
ea5b213a 730intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 731 uint16_t clock,
732 uint16_t width,
733 uint16_t height)
734{
735 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 736
e642c6f1 737 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 738 args.clock = clock;
739 args.width = width;
740 args.height = height;
e642c6f1 741 args.interlace = 0;
12682a97 742
ea5b213a
CW		 743 if (intel_sdvo->is_lvds &&
744 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
745 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 746 args.scaled = 1;
747
32aad86f
CW		 748 return intel_sdvo_set_value(intel_sdvo,
749 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
750 &args, sizeof(args));
e2f0ba97
JB		 751}
752
ea5b213a 753static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 754 struct intel_sdvo_dtd *dtd)
755{
1a3665c8
CW		 756 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
757 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 758 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
759 &dtd->part1, sizeof(dtd->part1)) &&
760 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
761 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 762}
79e53945 763
ea5b213a 764static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 765{
32aad86f 766 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 767}
768
e2f0ba97 769static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 770 const struct drm_display_mode *mode)
79e53945 771{
e2f0ba97
JB		 772 uint16_t width, height;
773 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
774 uint16_t h_sync_offset, v_sync_offset;
6651819b 775 int mode_clock;
79e53945 776
c6ebd4c0
DV		 777 width = mode->hdisplay;
778 height = mode->vdisplay;
79e53945
JB		 779
780 /* do some mode translations */
c6ebd4c0
DV		 781 h_blank_len = mode->htotal - mode->hdisplay;
782 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 783
c6ebd4c0
DV		 784 v_blank_len = mode->vtotal - mode->vdisplay;
785 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 786
c6ebd4c0
DV		 787 h_sync_offset = mode->hsync_start - mode->hdisplay;
788 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 789
6651819b
DV		 790 mode_clock = mode->clock;
791 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
792 mode_clock /= 10;
793 dtd->part1.clock = mode_clock;
794
e2f0ba97
JB		 795 dtd->part1.h_active = width & 0xff;
796 dtd->part1.h_blank = h_blank_len & 0xff;
797 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 798 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 799 dtd->part1.v_active = height & 0xff;
800 dtd->part1.v_blank = v_blank_len & 0xff;
801 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 802 ((v_blank_len >> 8) & 0xf);
803
171a9e96 804 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 805 dtd->part2.h_sync_width = h_sync_len & 0xff;
806 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 807 (v_sync_len & 0xf);
e2f0ba97 808 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 809 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
810 ((v_sync_len & 0x30) >> 4);
811
e2f0ba97 812 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 813 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
814 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 815 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 816 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 817 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 818 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 819
820 dtd->part2.sdvo_flags = 0;
821 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
822 dtd->part2.reserved = 0;
823}
824
825static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 826 const struct intel_sdvo_dtd *dtd)
e2f0ba97 827{
e2f0ba97
JB		 828 mode->hdisplay = dtd->part1.h_active;
829 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
830 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 831 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 832 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
833 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
834 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
835 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
836
837 mode->vdisplay = dtd->part1.v_active;
838 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
839 mode->vsync_start = mode->vdisplay;
840 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 841 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 842 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
843 mode->vsync_end = mode->vsync_start +
844 (dtd->part2.v_sync_off_width & 0xf);
845 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
846 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
847 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
848
849 mode->clock = dtd->part1.clock * 10;
850
171a9e96 851 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 852 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
853 mode->flags |= DRM_MODE_FLAG_INTERLACE;
854 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 855 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 856 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 857 mode->flags |= DRM_MODE_FLAG_PVSYNC;
858}
859
e27d8538 860static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 861{
e27d8538 862 struct intel_sdvo_encode encode;
e2f0ba97 863
1a3665c8 864 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 865 return intel_sdvo_get_value(intel_sdvo,
866 SDVO_CMD_GET_SUPP_ENCODE,
867 &encode, sizeof(encode));
e2f0ba97
JB		 868}
869
ea5b213a 870static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 871 uint8_t mode)
e2f0ba97 872{
32aad86f 873 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 874}
875
ea5b213a 876static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 877 uint8_t mode)
878{
32aad86f 879 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 880}
881
882#if 0
ea5b213a 883static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 884{
885 int i, j;
886 uint8_t set_buf_index[2];
887 uint8_t av_split;
888 uint8_t buf_size;
889 uint8_t buf[48];
890 uint8_t *pos;
891
32aad86f 892 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 893
894 for (i = 0; i <= av_split; i++) {
895 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 896 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 897 set_buf_index, 2);
c751ce4f
EA		 898 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
899 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 900
901 pos = buf;
902 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 903 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 904 NULL, 0);
c751ce4f 905 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 906 pos += 8;
907 }
908 }
909}
910#endif
911
b6e0e543
DV		 912static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
913 unsigned if_index, uint8_t tx_rate,
914 uint8_t *data, unsigned length)
915{
916 uint8_t set_buf_index[2] = { if_index, 0 };
917 uint8_t hbuf_size, tmp[8];
918 int i;
919
920 if (!intel_sdvo_set_value(intel_sdvo,
921 SDVO_CMD_SET_HBUF_INDEX,
922 set_buf_index, 2))
923 return false;
924
925 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
926 &hbuf_size, 1))
927 return false;
928
929 /* Buffer size is 0 based, hooray! */
930 hbuf_size++;
931
932 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
933 if_index, length, hbuf_size);
934
935 for (i = 0; i < hbuf_size; i += 8) {
936 memset(tmp, 0, 8);
937 if (i < length)
938 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
939
940 if (!intel_sdvo_set_value(intel_sdvo,
941 SDVO_CMD_SET_HBUF_DATA,
942 tmp, 8))
943 return false;
944 }
945
946 return intel_sdvo_set_value(intel_sdvo,
947 SDVO_CMD_SET_HBUF_TXRATE,
948 &tx_rate, 1);
949}
950
abedc077
VS		 951static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
952 const struct drm_display_mode *adjusted_mode)
e2f0ba97
JB		 953{
954 struct dip_infoframe avi_if = {
955 .type = DIP_TYPE_AVI,
3c17fe4b 956 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 957 .len = DIP_LEN_AVI,
958 };
81014b9d 959 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
3c17fe4b 960
abedc077
VS		 961 if (intel_sdvo->rgb_quant_range_selectable) {
962 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
963 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
964 else
965 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
966 }
967
3c17fe4b
DH		 968 intel_dip_infoframe_csum(&avi_if);
969
81014b9d
DV		 970 /* sdvo spec says that the ecc is handled by the hw, and it looks like
971 * we must not send the ecc field, either. */
972 memcpy(sdvo_data, &avi_if, 3);
973 sdvo_data[3] = avi_if.checksum;
974 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
975
b6e0e543
DV		 976 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
977 SDVO_HBUF_TX_VSYNC,
978 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 979}
980
32aad86f 981static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 982{
ce6feabd 983 struct intel_sdvo_tv_format format;
40039750 984 uint32_t format_map;
ce6feabd 985
40039750 986 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 987 memset(&format, 0, sizeof(format));
32aad86f 988 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 989
32aad86f
CW		 990 BUILD_BUG_ON(sizeof(format) != 6);
991 return intel_sdvo_set_value(intel_sdvo,
992 SDVO_CMD_SET_TV_FORMAT,
993 &format, sizeof(format));
7026d4ac
ZW		 994}
995
32aad86f
CW		 996static bool
997intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 998 const struct drm_display_mode *mode)
e2f0ba97 999{
32aad86f 1000 struct intel_sdvo_dtd output_dtd;
79e53945 1001
32aad86f
CW		 1002 if (!intel_sdvo_set_target_output(intel_sdvo,
1003 intel_sdvo->attached_output))
1004 return false;
e2f0ba97 1005
32aad86f
CW		 1006 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1007 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1008 return false;
e2f0ba97 1009
32aad86f
CW		 1010 return true;
1011}
1012
c9a29698
DV		 1013/* Asks the sdvo controller for the preferred input mode given the output mode.
1014 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1015static bool
c9a29698 1016intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1017 const struct drm_display_mode *mode,
c9a29698 1018 struct drm_display_mode *adjusted_mode)
32aad86f 1019{
c9a29698
DV		 1020 struct intel_sdvo_dtd input_dtd;
1021
32aad86f
CW		 1022 /* Reset the input timing to the screen. Assume always input 0. */
1023 if (!intel_sdvo_set_target_input(intel_sdvo))
1024 return false;
e2f0ba97 1025
32aad86f
CW		 1026 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1027 mode->clock / 10,
1028 mode->hdisplay,
1029 mode->vdisplay))
1030 return false;
e2f0ba97 1031
32aad86f 1032 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1033 &input_dtd))
32aad86f 1034 return false;
e2f0ba97 1035
c9a29698 1036 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1037 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1038
32aad86f
CW		 1039 return true;
1040}
12682a97 1041
32aad86f 1042static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1043 const struct drm_display_mode *mode,
32aad86f
CW		 1044 struct drm_display_mode *adjusted_mode)
1045{
890f3359 1046 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1047 int multiplier;
12682a97 1048
32aad86f
CW		 1049 /* We need to construct preferred input timings based on our
1050 * output timings. To do that, we have to set the output
1051 * timings, even though this isn't really the right place in
1052 * the sequence to do it. Oh well.
1053 */
1054 if (intel_sdvo->is_tv) {
1055 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1056 return false;
12682a97 1057
c9a29698
DV		 1058 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1059 mode,
1060 adjusted_mode);
ea5b213a 1061 } else if (intel_sdvo->is_lvds) {
32aad86f 1062 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1063 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1064 return false;
12682a97 1065
c9a29698
DV		 1066 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1067 mode,
1068 adjusted_mode);
e2f0ba97 1069 }
32aad86f
CW		 1070
1071 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1072 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1073 */
6c9547ff
CW		 1074 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1075 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1076
55bc60db
VS		 1077 if (intel_sdvo->color_range_auto) {
1078 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1079 if (intel_sdvo->has_hdmi_monitor &&
1080 drm_mode_cea_vic(adjusted_mode) > 1)
1081 intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
1082 else
1083 intel_sdvo->color_range = 0;
1084 }
1085
3685a8f3
VS		 1086 if (intel_sdvo->color_range)
1087 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
1088
e2f0ba97
JB		 1089 return true;
1090}
1091
1092static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1093 struct drm_display_mode *mode,
1094 struct drm_display_mode *adjusted_mode)
1095{
1096 struct drm_device *dev = encoder->dev;
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 struct drm_crtc *crtc = encoder->crtc;
1099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1100 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1101 u32 sdvox;
e2f0ba97 1102 struct intel_sdvo_in_out_map in_out;
6651819b 1103 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1104 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1105 int rate;
e2f0ba97
JB		 1106
1107 if (!mode)
1108 return;
1109
1110 /* First, set the input mapping for the first input to our controlled
1111 * output. This is only correct if we're a single-input device, in
1112 * which case the first input is the output from the appropriate SDVO
1113 * channel on the motherboard. In a two-input device, the first input
1114 * will be SDVOB and the second SDVOC.
1115 */
ea5b213a 1116 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1117 in_out.in1 = 0;
1118
c74696b9
PR		 1119 intel_sdvo_set_value(intel_sdvo,
1120 SDVO_CMD_SET_IN_OUT_MAP,
1121 &in_out, sizeof(in_out));
e2f0ba97 1122
6c9547ff
CW		 1123 /* Set the output timings to the screen */
1124 if (!intel_sdvo_set_target_output(intel_sdvo,
1125 intel_sdvo->attached_output))
1126 return;
e2f0ba97 1127
6651819b
DV		 1128 /* lvds has a special fixed output timing. */
1129 if (intel_sdvo->is_lvds)
1130 intel_sdvo_get_dtd_from_mode(&output_dtd,
1131 intel_sdvo->sdvo_lvds_fixed_mode);
1132 else
1133 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1134 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1135 DRM_INFO("Setting output timings on %s failed\n",
1136 SDVO_NAME(intel_sdvo));
79e53945
JB		 1137
1138 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1139 if (!intel_sdvo_set_target_input(intel_sdvo))
1140 return;
79e53945 1141
97aaf910
CW		 1142 if (intel_sdvo->has_hdmi_monitor) {
1143 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1144 intel_sdvo_set_colorimetry(intel_sdvo,
1145 SDVO_COLORIMETRY_RGB256);
abedc077 1146 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1147 } else
1148 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1149
6c9547ff
CW		 1150 if (intel_sdvo->is_tv &&
1151 !intel_sdvo_set_tv_format(intel_sdvo))
1152 return;
e2f0ba97 1153
6651819b
DV		 1154 /* We have tried to get input timing in mode_fixup, and filled into
1155 * adjusted_mode.
1156 */
1157 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
e751823d
EE		 1158 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1159 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1160 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1161 DRM_INFO("Setting input timings on %s failed\n",
1162 SDVO_NAME(intel_sdvo));
79e53945 1163
6c9547ff
CW		 1164 switch (pixel_multiplier) {
1165 default:
32aad86f
CW		 1166 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1167 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1168 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1169 }
32aad86f
CW		 1170 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1171 return;
79e53945
JB		 1172
1173 /* Set the SDVO control regs. */
a6c45cf0 1174 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1175 /* The real mode polarity is set by the SDVO commands, using
1176 * struct intel_sdvo_dtd. */
1177 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1178 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1179 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1180 if (INTEL_INFO(dev)->gen < 5)
1181 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1182 } else {
6c9547ff 1183 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1184 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1185 case SDVOB:
1186 sdvox &= SDVOB_PRESERVE_MASK;
1187 break;
1188 case SDVOC:
1189 sdvox &= SDVOC_PRESERVE_MASK;
1190 break;
1191 }
1192 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1193 }
3573c410
PZ		 1194
1195 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1196 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1197 else
1198 sdvox |= TRANSCODER(intel_crtc->pipe);
1199
da79de97 1200 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1201 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1202
a6c45cf0 1203 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1204 /* done in crtc_mode_set as the dpll_md reg must be written early */
1205 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1206 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1207 } else {
6c9547ff 1208 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1209 }
1210
6714afb1
CW		 1211 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1212 INTEL_INFO(dev)->gen < 5)
12682a97 1213 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1214 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1215}
1216
4ac41f47 1217static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1218{
4ac41f47
DV		 1219 struct intel_sdvo_connector *intel_sdvo_connector =
1220 to_intel_sdvo_connector(&connector->base);
1221 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1222 u16 active_outputs;
1223
1224 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1225
1226 if (active_outputs & intel_sdvo_connector->output_flag)
1227 return true;
1228 else
1229 return false;
1230}
1231
1232static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1233 enum pipe *pipe)
1234{
1235 struct drm_device *dev = encoder->base.dev;
79e53945 1236 struct drm_i915_private *dev_priv = dev->dev_private;
4ac41f47
DV		 1237 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1238 u32 tmp;
1239
1240 tmp = I915_READ(intel_sdvo->sdvo_reg);
1241
1242 if (!(tmp & SDVO_ENABLE))
1243 return false;
1244
1245 if (HAS_PCH_CPT(dev))
1246 *pipe = PORT_TO_PIPE_CPT(tmp);
1247 else
1248 *pipe = PORT_TO_PIPE(tmp);
1249
1250 return true;
1251}
1252
ce22c320
DV		 1253static void intel_disable_sdvo(struct intel_encoder *encoder)
1254{
1255 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1256 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1257 u32 temp;
1258
1259 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1260 if (0)
1261 intel_sdvo_set_encoder_power_state(intel_sdvo,
1262 DRM_MODE_DPMS_OFF);
1263
1264 temp = I915_READ(intel_sdvo->sdvo_reg);
1265 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1266 /* HW workaround for IBX, we need to move the port to
1267 * transcoder A before disabling it. */
1268 if (HAS_PCH_IBX(encoder->base.dev)) {
1269 struct drm_crtc *crtc = encoder->base.crtc;
1270 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1271
1272 if (temp & SDVO_PIPE_B_SELECT) {
1273 temp &= ~SDVO_PIPE_B_SELECT;
1274 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1275 POSTING_READ(intel_sdvo->sdvo_reg);
1276
1277 /* Again we need to write this twice. */
1278 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1279 POSTING_READ(intel_sdvo->sdvo_reg);
1280
1281 /* Transcoder selection bits only update
1282 * effectively on vblank. */
1283 if (crtc)
1284 intel_wait_for_vblank(encoder->base.dev, pipe);
1285 else
1286 msleep(50);
1287 }
1288 }
1289
ce22c320
DV		 1290 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1291 }
1292}
1293
1294static void intel_enable_sdvo(struct intel_encoder *encoder)
1295{
1296 struct drm_device *dev = encoder->base.dev;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1299 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1300 u32 temp;
ce22c320
DV		 1301 bool input1, input2;
1302 int i;
1303 u8 status;
1304
1305 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1306 if ((temp & SDVO_ENABLE) == 0) {
1307 /* HW workaround for IBX, we need to move the port
1308 * to transcoder A before disabling it. */
1309 if (HAS_PCH_IBX(dev)) {
1310 struct drm_crtc *crtc = encoder->base.crtc;
1311 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1312
1313 /* Restore the transcoder select bit. */
1314 if (pipe == PIPE_B)
1315 temp |= SDVO_PIPE_B_SELECT;
1316 }
1317
ce22c320 1318 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1319 }
ce22c320
DV		 1320 for (i = 0; i < 2; i++)
1321 intel_wait_for_vblank(dev, intel_crtc->pipe);
1322
1323 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1324 /* Warn if the device reported failure to sync.
1325 * A lot of SDVO devices fail to notify of sync, but it's
1326 * a given it the status is a success, we succeeded.
1327 */
1328 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1329 DRM_DEBUG_KMS("First %s output reported failure to "
1330 "sync\n", SDVO_NAME(intel_sdvo));
1331 }
1332
1333 if (0)
1334 intel_sdvo_set_encoder_power_state(intel_sdvo,
1335 DRM_MODE_DPMS_ON);
1336 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1337}
1338
b2cabb0e 1339static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1340{
b2cabb0e
DV		 1341 struct drm_crtc *crtc;
1342 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1343
1344 /* dvo supports only 2 dpms states. */
1345 if (mode != DRM_MODE_DPMS_ON)
1346 mode = DRM_MODE_DPMS_OFF;
1347
1348 if (mode == connector->dpms)
1349 return;
1350
1351 connector->dpms = mode;
1352
1353 /* Only need to change hw state when actually enabled */
1354 crtc = intel_sdvo->base.base.crtc;
1355 if (!crtc) {
1356 intel_sdvo->base.connectors_active = false;
1357 return;
1358 }
79e53945
JB		 1359
1360 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1361 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1362 if (0)
ea5b213a 1363 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1364
b2cabb0e
DV		 1365 intel_sdvo->base.connectors_active = false;
1366
1367 intel_crtc_update_dpms(crtc);
79e53945 1368 } else {
b2cabb0e
DV		 1369 intel_sdvo->base.connectors_active = true;
1370
1371 intel_crtc_update_dpms(crtc);
79e53945
JB		 1372
1373 if (0)
ea5b213a
CW		 1374 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1375 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1376 }
0a91ca29 1377
b980514c 1378 intel_modeset_check_state(connector->dev);
79e53945
JB		 1379}
1380
79e53945
JB		 1381static int intel_sdvo_mode_valid(struct drm_connector *connector,
1382 struct drm_display_mode *mode)
1383{
df0e9248 1384 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1385
1386 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1387 return MODE_NO_DBLESCAN;
1388
ea5b213a 1389 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1390 return MODE_CLOCK_LOW;
1391
ea5b213a 1392 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1393 return MODE_CLOCK_HIGH;
1394
8545423a 1395 if (intel_sdvo->is_lvds) {
ea5b213a 1396 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1397 return MODE_PANEL;
1398
ea5b213a 1399 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1400 return MODE_PANEL;
1401 }
1402
79e53945
JB		 1403 return MODE_OK;
1404}
1405
ea5b213a 1406static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1407{
1a3665c8 1408 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1409 if (!intel_sdvo_get_value(intel_sdvo,
1410 SDVO_CMD_GET_DEVICE_CAPS,
1411 caps, sizeof(*caps)))
1412 return false;
1413
1414 DRM_DEBUG_KMS("SDVO capabilities:\n"
1415 " vendor_id: %d\n"
1416 " device_id: %d\n"
1417 " device_rev_id: %d\n"
1418 " sdvo_version_major: %d\n"
1419 " sdvo_version_minor: %d\n"
1420 " sdvo_inputs_mask: %d\n"
1421 " smooth_scaling: %d\n"
1422 " sharp_scaling: %d\n"
1423 " up_scaling: %d\n"
1424 " down_scaling: %d\n"
1425 " stall_support: %d\n"
1426 " output_flags: %d\n",
1427 caps->vendor_id,
1428 caps->device_id,
1429 caps->device_rev_id,
1430 caps->sdvo_version_major,
1431 caps->sdvo_version_minor,
1432 caps->sdvo_inputs_mask,
1433 caps->smooth_scaling,
1434 caps->sharp_scaling,
1435 caps->up_scaling,
1436 caps->down_scaling,
1437 caps->stall_support,
1438 caps->output_flags);
1439
1440 return true;
79e53945
JB		 1441}
1442
5fa7ac9c 1443static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1444{
768b107e 1445 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1446 uint16_t hotplug;
79e53945 1447
768b107e
DV		 1448 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1449 * on the line. */
1450 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1451 return 0;
768b107e 1452
5fa7ac9c
JN		 1453 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1454 &hotplug, sizeof(hotplug)))
1455 return 0;
768b107e 1456
5fa7ac9c 1457 return hotplug;
79e53945
JB		 1458}
1459
cc68c81a 1460static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1461{
cc68c81a 1462 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1463
5fa7ac9c
JN		 1464 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1465 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1466}
1467
fb7a46f3 1468static bool
ea5b213a 1469intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1470{
bc65212c 1471 /* Is there more than one type of output? */
2294488d 1472 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1473}
1474
f899fc64 1475static struct edid *
e957d772 1476intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1477{
e957d772
CW		 1478 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1479 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1480}
1481
ff482d83
CW		 1482/* Mac mini hack -- use the same DDC as the analog connector */
1483static struct edid *
1484intel_sdvo_get_analog_edid(struct drm_connector *connector)
1485{
f899fc64 1486 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1487
0c1dab89 1488 return drm_get_edid(connector,
3bd7d909
DK		 1489 intel_gmbus_get_adapter(dev_priv,
1490 dev_priv->crt_ddc_pin));
ff482d83
CW		 1491}
1492
c43b5634 1493static enum drm_connector_status
8bf38485 1494intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1495{
df0e9248 1496 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1497 enum drm_connector_status status;
1498 struct edid *edid;
9dff6af8 1499
e957d772 1500 edid = intel_sdvo_get_edid(connector);
57cdaf90 1501
ea5b213a 1502 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1503 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1504
7c3f0a27
ZY		 1505 /*
1506 * Don't use the 1 as the argument of DDC bus switch to get
1507 * the EDID. It is used for SDVO SPD ROM.
1508 */
9d1a903d 1509 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1510 intel_sdvo->ddc_bus = ddc;
1511 edid = intel_sdvo_get_edid(connector);
1512 if (edid)
7c3f0a27 1513 break;
7c3f0a27 1514 }
e957d772
CW		 1515 /*
1516 * If we found the EDID on the other bus,
1517 * assume that is the correct DDC bus.
1518 */
1519 if (edid == NULL)
1520 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1521 }
9d1a903d
CW		 1522
1523 /*
1524 * When there is no edid and no monitor is connected with VGA
1525 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1526 */
ff482d83
CW		 1527 if (edid == NULL)
1528 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1529
2f551c84 1530 status = connector_status_unknown;
9dff6af8 1531 if (edid != NULL) {
149c36a3 1532 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1533 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1534 status = connector_status_connected;
da79de97
CW		 1535 if (intel_sdvo->is_hdmi) {
1536 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1537 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1538 intel_sdvo->rgb_quant_range_selectable =
1539 drm_rgb_quant_range_selectable(edid);
da79de97 1540 }
13946743
CW		 1541 } else
1542 status = connector_status_disconnected;
9d1a903d
CW		 1543 kfree(edid);
1544 }
7f36e7ed
CW		 1545
1546 if (status == connector_status_connected) {
1547 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1548 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1549 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1550 }
1551
2b8d33f7 1552 return status;
9dff6af8
ML		 1553}
1554
52220085
CW		 1555static bool
1556intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1557 struct edid *edid)
1558{
1559 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1560 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1561
1562 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1563 connector_is_digital, monitor_is_digital);
1564 return connector_is_digital == monitor_is_digital;
1565}
1566
7b334fcb 1567static enum drm_connector_status
930a9e28 1568intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1569{
fb7a46f3 1570 uint16_t response;
df0e9248 1571 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1572 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1573 enum drm_connector_status ret;
79e53945 1574
fc37381c
CW		 1575 if (!intel_sdvo_get_value(intel_sdvo,
1576 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1577 &response, 2))
32aad86f 1578 return connector_status_unknown;
79e53945 1579
e957d772
CW		 1580 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1581 response & 0xff, response >> 8,
1582 intel_sdvo_connector->output_flag);
e2f0ba97 1583
fb7a46f3 1584 if (response == 0)
79e53945 1585 return connector_status_disconnected;
fb7a46f3 1586
ea5b213a 1587 intel_sdvo->attached_output = response;
14571b4c 1588
97aaf910
CW		 1589 intel_sdvo->has_hdmi_monitor = false;
1590 intel_sdvo->has_hdmi_audio = false;
abedc077 1591 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1592
615fb93f 1593 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1594 ret = connector_status_disconnected;
13946743 1595 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1596 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1597 else {
1598 struct edid *edid;
1599
1600 /* if we have an edid check it matches the connection */
1601 edid = intel_sdvo_get_edid(connector);
1602 if (edid == NULL)
1603 edid = intel_sdvo_get_analog_edid(connector);
1604 if (edid != NULL) {
52220085
CW		 1605 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1606 edid))
13946743 1607 ret = connector_status_connected;
52220085
CW		 1608 else
1609 ret = connector_status_disconnected;
1610
13946743
CW		 1611 kfree(edid);
1612 } else
1613 ret = connector_status_connected;
1614 }
14571b4c
ZW		 1615
1616 /* May update encoder flag for like clock for SDVO TV, etc.*/
1617 if (ret == connector_status_connected) {
ea5b213a
CW		 1618 intel_sdvo->is_tv = false;
1619 intel_sdvo->is_lvds = false;
1620 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1621
1622 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1623 intel_sdvo->is_tv = true;
1624 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1625 }
1626 if (response & SDVO_LVDS_MASK)
8545423a 1627 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1628 }
14571b4c
ZW		 1629
1630 return ret;
79e53945
JB		 1631}
1632
e2f0ba97 1633static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1634{
ff482d83 1635 struct edid *edid;
79e53945
JB		 1636
1637 /* set the bus switch and get the modes */
e957d772 1638 edid = intel_sdvo_get_edid(connector);
79e53945 1639
57cdaf90
KP		 1640 /*
1641 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1642 * link between analog and digital outputs. So, if the regular SDVO
1643 * DDC fails, check to see if the analog output is disconnected, in
1644 * which case we'll look there for the digital DDC data.
e2f0ba97 1645 */
f899fc64
CW		 1646 if (edid == NULL)
1647 edid = intel_sdvo_get_analog_edid(connector);
1648
ff482d83 1649 if (edid != NULL) {
52220085
CW		 1650 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1651 edid)) {
0c1dab89
CW		 1652 drm_mode_connector_update_edid_property(connector, edid);
1653 drm_add_edid_modes(connector, edid);
1654 }
13946743 1655
ff482d83 1656 kfree(edid);
e2f0ba97 1657 }
e2f0ba97
JB		 1658}
1659
1660/*
1661 * Set of SDVO TV modes.
1662 * Note! This is in reply order (see loop in get_tv_modes).
1663 * XXX: all 60Hz refresh?
1664 */
b1f559ec 1665static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1666 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1667 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1669 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1670 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1672 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1673 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1674 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1675 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1676 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1678 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1679 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1680 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1681 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1682 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1683 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1684 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1685 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1686 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1687 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1688 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1690 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1691 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1693 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1694 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1696 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1697 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1698 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1699 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1700 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1701 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1702 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1703 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1705 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1706 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1708 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1709 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1710 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1711 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1712 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1713 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1714 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1715 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1716 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1717 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1718 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1720 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1721 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1722 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1723};
1724
1725static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1726{
df0e9248 1727 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1728 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1729 uint32_t reply = 0, format_map = 0;
1730 int i;
e2f0ba97
JB		 1731
1732 /* Read the list of supported input resolutions for the selected TV
1733 * format.
1734 */
40039750 1735 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1736 memcpy(&tv_res, &format_map,
32aad86f 1737 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1738
32aad86f
CW		 1739 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1740 return;
ce6feabd 1741
32aad86f 1742 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1743 if (!intel_sdvo_write_cmd(intel_sdvo,
1744 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1745 &tv_res, sizeof(tv_res)))
1746 return;
1747 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1748 return;
1749
1750 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1751 if (reply & (1 << i)) {
1752 struct drm_display_mode *nmode;
1753 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1754 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1755 if (nmode)
1756 drm_mode_probed_add(connector, nmode);
1757 }
e2f0ba97
JB		 1758}
1759
7086c87f
ML		 1760static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1761{
df0e9248 1762 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1763 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1764 struct drm_display_mode *newmode;
7086c87f
ML		 1765
1766 /*
1767 * Attempt to get the mode list from DDC.
1768 * Assume that the preferred modes are
1769 * arranged in priority order.
1770 */
f899fc64 1771 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1772 if (list_empty(&connector->probed_modes) == false)
12682a97 1773 goto end;
7086c87f
ML		 1774
1775 /* Fetch modes from VBT */
1776 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1777 newmode = drm_mode_duplicate(connector->dev,
1778 dev_priv->sdvo_lvds_vbt_mode);
1779 if (newmode != NULL) {
1780 /* Guarantee the mode is preferred */
1781 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1782 DRM_MODE_TYPE_DRIVER);
1783 drm_mode_probed_add(connector, newmode);
1784 }
1785 }
12682a97 1786
1787end:
1788 list_for_each_entry(newmode, &connector->probed_modes, head) {
1789 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1790 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1791 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1792
8545423a 1793 intel_sdvo->is_lvds = true;
12682a97 1794 break;
1795 }
1796 }
1797
7086c87f
ML		 1798}
1799
e2f0ba97
JB		 1800static int intel_sdvo_get_modes(struct drm_connector *connector)
1801{
615fb93f 1802 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1803
615fb93f 1804 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1805 intel_sdvo_get_tv_modes(connector);
615fb93f 1806 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1807 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1808 else
1809 intel_sdvo_get_ddc_modes(connector);
1810
32aad86f 1811 return !list_empty(&connector->probed_modes);
79e53945
JB		 1812}
1813
fcc8d672
CW		 1814static void
1815intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1816{
615fb93f 1817 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1818 struct drm_device *dev = connector->dev;
1819
c5521706
CW		 1820 if (intel_sdvo_connector->left)
1821 drm_property_destroy(dev, intel_sdvo_connector->left);
1822 if (intel_sdvo_connector->right)
1823 drm_property_destroy(dev, intel_sdvo_connector->right);
1824 if (intel_sdvo_connector->top)
1825 drm_property_destroy(dev, intel_sdvo_connector->top);
1826 if (intel_sdvo_connector->bottom)
1827 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1828 if (intel_sdvo_connector->hpos)
1829 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1830 if (intel_sdvo_connector->vpos)
1831 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1832 if (intel_sdvo_connector->saturation)
1833 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1834 if (intel_sdvo_connector->contrast)
1835 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1836 if (intel_sdvo_connector->hue)
1837 drm_property_destroy(dev, intel_sdvo_connector->hue);
1838 if (intel_sdvo_connector->sharpness)
1839 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1840 if (intel_sdvo_connector->flicker_filter)
1841 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1842 if (intel_sdvo_connector->flicker_filter_2d)
1843 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1844 if (intel_sdvo_connector->flicker_filter_adaptive)
1845 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1846 if (intel_sdvo_connector->tv_luma_filter)
1847 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1848 if (intel_sdvo_connector->tv_chroma_filter)
1849 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1850 if (intel_sdvo_connector->dot_crawl)
1851 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1852 if (intel_sdvo_connector->brightness)
1853 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1854}
1855
79e53945
JB		 1856static void intel_sdvo_destroy(struct drm_connector *connector)
1857{
615fb93f 1858 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1859
c5521706 1860 if (intel_sdvo_connector->tv_format)
ce6feabd 1861 drm_property_destroy(connector->dev,
c5521706 1862 intel_sdvo_connector->tv_format);
b9219c5e 1863
d2a82a6f 1864 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1865 drm_sysfs_connector_remove(connector);
1866 drm_connector_cleanup(connector);
4b745b1e 1867 kfree(intel_sdvo_connector);
79e53945
JB		 1868}
1869
1aad7ac0
CW		 1870static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1871{
1872 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1873 struct edid *edid;
1874 bool has_audio = false;
1875
1876 if (!intel_sdvo->is_hdmi)
1877 return false;
1878
1879 edid = intel_sdvo_get_edid(connector);
1880 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1881 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 1882 kfree(edid);
1aad7ac0
CW		 1883
1884 return has_audio;
1885}
1886
ce6feabd
ZY		 1887static int
1888intel_sdvo_set_property(struct drm_connector *connector,
1889 struct drm_property *property,
1890 uint64_t val)
1891{
df0e9248 1892 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1893 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1894 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1895 uint16_t temp_value;
32aad86f
CW		 1896 uint8_t cmd;
1897 int ret;
ce6feabd 1898
662595df 1899 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 1900 if (ret)
1901 return ret;
ce6feabd 1902
3f43c48d 1903 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1904 int i = val;
1905 bool has_audio;
1906
1907 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1908 return 0;
1909
1aad7ac0 1910 intel_sdvo_connector->force_audio = i;
7f36e7ed 1911
c3e5f67b 1912 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1913 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1914 else
c3e5f67b 1915 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1916
1aad7ac0 1917 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1918 return 0;
7f36e7ed 1919
1aad7ac0 1920 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1921 goto done;
1922 }
1923
e953fd7b 1924 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 1925 switch (val) {
1926 case INTEL_BROADCAST_RGB_AUTO:
1927 intel_sdvo->color_range_auto = true;
1928 break;
1929 case INTEL_BROADCAST_RGB_FULL:
1930 intel_sdvo->color_range_auto = false;
1931 intel_sdvo->color_range = 0;
1932 break;
1933 case INTEL_BROADCAST_RGB_LIMITED:
1934 intel_sdvo->color_range_auto = false;
1935 intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
1936 break;
1937 default:
1938 return -EINVAL;
1939 }
7f36e7ed
CW		 1940 goto done;
1941 }
1942
c5521706
CW		 1943#define CHECK_PROPERTY(name, NAME) \
1944 if (intel_sdvo_connector->name == property) { \
1945 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1946 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1947 cmd = SDVO_CMD_SET_##NAME; \
1948 intel_sdvo_connector->cur_##name = temp_value; \
1949 goto set_value; \
1950 }
1951
1952 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1953 if (val >= TV_FORMAT_NUM)
1954 return -EINVAL;
1955
40039750 1956 if (intel_sdvo->tv_format_index ==
615fb93f 1957 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1958 return 0;
ce6feabd 1959
40039750 1960 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1961 goto done;
32aad86f 1962 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1963 temp_value = val;
c5521706 1964 if (intel_sdvo_connector->left == property) {
662595df 1965 drm_object_property_set_value(&connector->base,
c5521706 1966 intel_sdvo_connector->right, val);
615fb93f 1967 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1968 return 0;
b9219c5e 1969
615fb93f
CW		 1970 intel_sdvo_connector->left_margin = temp_value;
1971 intel_sdvo_connector->right_margin = temp_value;
1972 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1973 intel_sdvo_connector->left_margin;
b9219c5e 1974 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1975 goto set_value;
1976 } else if (intel_sdvo_connector->right == property) {
662595df 1977 drm_object_property_set_value(&connector->base,
c5521706 1978 intel_sdvo_connector->left, val);
615fb93f 1979 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1980 return 0;
b9219c5e 1981
615fb93f
CW		 1982 intel_sdvo_connector->left_margin = temp_value;
1983 intel_sdvo_connector->right_margin = temp_value;
1984 temp_value = intel_sdvo_connector->max_hscan -
1985 intel_sdvo_connector->left_margin;
b9219c5e 1986 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1987 goto set_value;
1988 } else if (intel_sdvo_connector->top == property) {
662595df 1989 drm_object_property_set_value(&connector->base,
c5521706 1990 intel_sdvo_connector->bottom, val);
615fb93f 1991 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1992 return 0;
b9219c5e 1993
615fb93f
CW		 1994 intel_sdvo_connector->top_margin = temp_value;
1995 intel_sdvo_connector->bottom_margin = temp_value;
1996 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1997 intel_sdvo_connector->top_margin;
b9219c5e 1998 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1999 goto set_value;
2000 } else if (intel_sdvo_connector->bottom == property) {
662595df 2001 drm_object_property_set_value(&connector->base,
c5521706 2002 intel_sdvo_connector->top, val);
615fb93f 2003 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2004 return 0;
2005
615fb93f
CW		 2006 intel_sdvo_connector->top_margin = temp_value;
2007 intel_sdvo_connector->bottom_margin = temp_value;
2008 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2009 intel_sdvo_connector->top_margin;
b9219c5e 2010 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2011 goto set_value;
2012 }
2013 CHECK_PROPERTY(hpos, HPOS)
2014 CHECK_PROPERTY(vpos, VPOS)
2015 CHECK_PROPERTY(saturation, SATURATION)
2016 CHECK_PROPERTY(contrast, CONTRAST)
2017 CHECK_PROPERTY(hue, HUE)
2018 CHECK_PROPERTY(brightness, BRIGHTNESS)
2019 CHECK_PROPERTY(sharpness, SHARPNESS)
2020 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2021 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2022 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2023 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2024 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2025 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2026 }
b9219c5e 2027
c5521706 2028 return -EINVAL; /* unknown property */
b9219c5e 2029
c5521706
CW		 2030set_value:
2031 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2032 return -EIO;
b9219c5e 2033
b9219c5e 2034
c5521706 2035done:
c0c36b94
CW		 2036 if (intel_sdvo->base.base.crtc)
2037 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2038
32aad86f 2039 return 0;
c5521706 2040#undef CHECK_PROPERTY
ce6feabd
ZY		 2041}
2042
79e53945 2043static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
79e53945 2044 .mode_fixup = intel_sdvo_mode_fixup,
79e53945 2045 .mode_set = intel_sdvo_mode_set,
1f703855 2046 .disable = intel_encoder_noop,
79e53945
JB		 2047};
2048
2049static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2050 .dpms = intel_sdvo_dpms,
79e53945
JB		 2051 .detect = intel_sdvo_detect,
2052 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2053 .set_property = intel_sdvo_set_property,
79e53945
JB		 2054 .destroy = intel_sdvo_destroy,
2055};
2056
2057static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2058 .get_modes = intel_sdvo_get_modes,
2059 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2060 .best_encoder = intel_best_encoder,
79e53945
JB		 2061};
2062
b358d0a6 2063static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2064{
890f3359 2065 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 2066
ea5b213a 2067 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2068 drm_mode_destroy(encoder->dev,
ea5b213a 2069 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2070
e957d772 2071 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2072 intel_encoder_destroy(encoder);
79e53945
JB		 2073}
2074
2075static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2076 .destroy = intel_sdvo_enc_destroy,
2077};
2078
b66d8424
CW		 2079static void
2080intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2081{
2082 uint16_t mask = 0;
2083 unsigned int num_bits;
2084
2085 /* Make a mask of outputs less than or equal to our own priority in the
2086 * list.
2087 */
2088 switch (sdvo->controlled_output) {
2089 case SDVO_OUTPUT_LVDS1:
2090 mask |= SDVO_OUTPUT_LVDS1;
2091 case SDVO_OUTPUT_LVDS0:
2092 mask |= SDVO_OUTPUT_LVDS0;
2093 case SDVO_OUTPUT_TMDS1:
2094 mask |= SDVO_OUTPUT_TMDS1;
2095 case SDVO_OUTPUT_TMDS0:
2096 mask |= SDVO_OUTPUT_TMDS0;
2097 case SDVO_OUTPUT_RGB1:
2098 mask |= SDVO_OUTPUT_RGB1;
2099 case SDVO_OUTPUT_RGB0:
2100 mask |= SDVO_OUTPUT_RGB0;
2101 break;
2102 }
2103
2104 /* Count bits to find what number we are in the priority list. */
2105 mask &= sdvo->caps.output_flags;
2106 num_bits = hweight16(mask);
2107 /* If more than 3 outputs, default to DDC bus 3 for now. */
2108 if (num_bits > 3)
2109 num_bits = 3;
2110
2111 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2112 sdvo->ddc_bus = 1 << num_bits;
2113}
79e53945 2114
e2f0ba97
JB		 2115/**
2116 * Choose the appropriate DDC bus for control bus switch command for this
2117 * SDVO output based on the controlled output.
2118 *
2119 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2120 * outputs, then LVDS outputs.
2121 */
2122static void
b1083333 2123intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2124 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2125{
b1083333 2126 struct sdvo_device_mapping *mapping;
e2f0ba97 2127
eef4eacb 2128 if (sdvo->is_sdvob)
b1083333
AJ		 2129 mapping = &(dev_priv->sdvo_mappings[0]);
2130 else
2131 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2132
b66d8424
CW		 2133 if (mapping->initialized)
2134 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2135 else
2136 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2137}
2138
e957d772
CW		 2139static void
2140intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2141 struct intel_sdvo *sdvo, u32 reg)
2142{
2143 struct sdvo_device_mapping *mapping;
46eb3036 2144 u8 pin;
e957d772 2145
eef4eacb 2146 if (sdvo->is_sdvob)
e957d772
CW		 2147 mapping = &dev_priv->sdvo_mappings[0];
2148 else
2149 mapping = &dev_priv->sdvo_mappings[1];
2150
6cb1612a 2151 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2152 pin = mapping->i2c_pin;
6cb1612a
JN		 2153 else
2154 pin = GMBUS_PORT_DPB;
e957d772 2155
6cb1612a
JN		 2156 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2157
2158 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2159 * our code totally fails once we start using gmbus. Hence fall back to
2160 * bit banging for now. */
2161 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2162}
2163
fbfcc4f3
JN		 2164/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2165static void
2166intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2167{
2168 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2169}
2170
e2f0ba97 2171static bool
e27d8538 2172intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2173{
97aaf910 2174 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2175}
2176
714605e4 2177static u8
eef4eacb 2178intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2179{
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct sdvo_device_mapping *my_mapping, *other_mapping;
2182
eef4eacb 2183 if (sdvo->is_sdvob) {
714605e4 2184 my_mapping = &dev_priv->sdvo_mappings[0];
2185 other_mapping = &dev_priv->sdvo_mappings[1];
2186 } else {
2187 my_mapping = &dev_priv->sdvo_mappings[1];
2188 other_mapping = &dev_priv->sdvo_mappings[0];
2189 }
2190
2191 /* If the BIOS described our SDVO device, take advantage of it. */
2192 if (my_mapping->slave_addr)
2193 return my_mapping->slave_addr;
2194
2195 /* If the BIOS only described a different SDVO device, use the
2196 * address that it isn't using.
2197 */
2198 if (other_mapping->slave_addr) {
2199 if (other_mapping->slave_addr == 0x70)
2200 return 0x72;
2201 else
2202 return 0x70;
2203 }
2204
2205 /* No SDVO device info is found for another DVO port,
2206 * so use mapping assumption we had before BIOS parsing.
2207 */
eef4eacb 2208 if (sdvo->is_sdvob)
714605e4 2209 return 0x70;
2210 else
2211 return 0x72;
2212}
2213
14571b4c 2214static void
df0e9248
CW		 2215intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2216 struct intel_sdvo *encoder)
14571b4c 2217{
df0e9248
CW		 2218 drm_connector_init(encoder->base.base.dev,
2219 &connector->base.base,
2220 &intel_sdvo_connector_funcs,
2221 connector->base.base.connector_type);
6070a4a9 2222
df0e9248
CW		 2223 drm_connector_helper_add(&connector->base.base,
2224 &intel_sdvo_connector_helper_funcs);
14571b4c 2225
8f4839e2 2226 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2227 connector->base.base.doublescan_allowed = 0;
2228 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2229 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2230
df0e9248
CW		 2231 intel_connector_attach_encoder(&connector->base, &encoder->base);
2232 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2233}
6070a4a9 2234
7f36e7ed 2235static void
55bc60db
VS		 2236intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2237 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2238{
2239 struct drm_device *dev = connector->base.base.dev;
2240
3f43c48d 2241 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2242 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2243 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2244 intel_sdvo->color_range_auto = true;
2245 }
7f36e7ed
CW		 2246}
2247
fb7a46f3 2248static bool
ea5b213a 2249intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2250{
4ef69c7a 2251 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2252 struct drm_connector *connector;
cc68c81a 2253 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2254 struct intel_connector *intel_connector;
615fb93f 2255 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2256
615fb93f
CW		 2257 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2258 if (!intel_sdvo_connector)
14571b4c
ZW		 2259 return false;
2260
14571b4c 2261 if (device == 0) {
ea5b213a 2262 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2263 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2264 } else if (device == 1) {
ea5b213a 2265 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2266 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2267 }
2268
615fb93f 2269 intel_connector = &intel_sdvo_connector->base;
14571b4c 2270 connector = &intel_connector->base;
5fa7ac9c
JN		 2271 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2272 intel_sdvo_connector->output_flag) {
cc68c81a 2273 connector->polled = DRM_CONNECTOR_POLL_HPD;
5fa7ac9c 2274 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2275 /* Some SDVO devices have one-shot hotplug interrupts.
2276 * Ensure that they get re-enabled when an interrupt happens.
2277 */
2278 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2279 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2280 } else {
cc68c81a 2281 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2282 }
14571b4c
ZW		 2283 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2284 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2285
e27d8538 2286 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2287 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2288 intel_sdvo->is_hdmi = true;
14571b4c 2289 }
14571b4c 2290
df0e9248 2291 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221 2292 if (intel_sdvo->is_hdmi)
55bc60db 2293 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2294
2295 return true;
2296}
2297
2298static bool
ea5b213a 2299intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2300{
4ef69c7a
CW		 2301 struct drm_encoder *encoder = &intel_sdvo->base.base;
2302 struct drm_connector *connector;
2303 struct intel_connector *intel_connector;
2304 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2305
615fb93f
CW		 2306 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2307 if (!intel_sdvo_connector)
2308 return false;
14571b4c 2309
615fb93f 2310 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2311 connector = &intel_connector->base;
2312 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2313 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2314
4ef69c7a
CW		 2315 intel_sdvo->controlled_output |= type;
2316 intel_sdvo_connector->output_flag = type;
14571b4c 2317
4ef69c7a
CW		 2318 intel_sdvo->is_tv = true;
2319 intel_sdvo->base.needs_tv_clock = true;
14571b4c 2320
df0e9248 2321 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2322
4ef69c7a 2323 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2324 goto err;
14571b4c 2325
4ef69c7a 2326 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2327 goto err;
14571b4c 2328
4ef69c7a 2329 return true;
32aad86f
CW		 2330
2331err:
123d5c01 2332 intel_sdvo_destroy(connector);
32aad86f 2333 return false;
14571b4c
ZW		 2334}
2335
2336static bool
ea5b213a 2337intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2338{
4ef69c7a
CW		 2339 struct drm_encoder *encoder = &intel_sdvo->base.base;
2340 struct drm_connector *connector;
2341 struct intel_connector *intel_connector;
2342 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2343
615fb93f
CW		 2344 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2345 if (!intel_sdvo_connector)
2346 return false;
14571b4c 2347
615fb93f 2348 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2349 connector = &intel_connector->base;
eb1f8e4f 2350 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2351 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2352 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2353
2354 if (device == 0) {
2355 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2356 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2357 } else if (device == 1) {
2358 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2359 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2360 }
2361
df0e9248
CW		 2362 intel_sdvo_connector_init(intel_sdvo_connector,
2363 intel_sdvo);
4ef69c7a 2364 return true;
14571b4c
ZW		 2365}
2366
2367static bool
ea5b213a 2368intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2369{
4ef69c7a
CW		 2370 struct drm_encoder *encoder = &intel_sdvo->base.base;
2371 struct drm_connector *connector;
2372 struct intel_connector *intel_connector;
2373 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2374
615fb93f
CW		 2375 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2376 if (!intel_sdvo_connector)
2377 return false;
14571b4c 2378
615fb93f
CW		 2379 intel_connector = &intel_sdvo_connector->base;
2380 connector = &intel_connector->base;
4ef69c7a
CW		 2381 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2382 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2383
2384 if (device == 0) {
2385 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2386 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2387 } else if (device == 1) {
2388 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2389 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2390 }
2391
df0e9248 2392 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2393 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2394 goto err;
2395
2396 return true;
2397
2398err:
123d5c01 2399 intel_sdvo_destroy(connector);
32aad86f 2400 return false;
14571b4c
ZW		 2401}
2402
2403static bool
ea5b213a 2404intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2405{
ea5b213a
CW		 2406 intel_sdvo->is_tv = false;
2407 intel_sdvo->base.needs_tv_clock = false;
2408 intel_sdvo->is_lvds = false;
fb7a46f3 2409
14571b4c 2410 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2411
14571b4c 2412 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2413 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2414 return false;
2415
2416 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2417 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2418 return false;
2419
2420 /* TV has no XXX1 function block */
a1f4b7ff 2421 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2422 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2423 return false;
2424
2425 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2426 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2427 return false;
fb7a46f3 2428
a0b1c7a5
CW		 2429 if (flags & SDVO_OUTPUT_YPRPB0)
2430 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2431 return false;
2432
14571b4c 2433 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2434 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2435 return false;
2436
2437 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2438 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2439 return false;
2440
2441 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2442 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2443 return false;
2444
2445 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2446 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2447 return false;
fb7a46f3 2448
14571b4c 2449 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2450 unsigned char bytes[2];
2451
ea5b213a
CW		 2452 intel_sdvo->controlled_output = 0;
2453 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2454 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2455 SDVO_NAME(intel_sdvo),
51c8b407 2456 bytes[0], bytes[1]);
14571b4c 2457 return false;
fb7a46f3 2458 }
27f8227b 2459 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2460
14571b4c 2461 return true;
fb7a46f3 2462}
2463
d0ddfbd3
JN		 2464static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2465{
2466 struct drm_device *dev = intel_sdvo->base.base.dev;
2467 struct drm_connector *connector, *tmp;
2468
2469 list_for_each_entry_safe(connector, tmp,
2470 &dev->mode_config.connector_list, head) {
2471 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2472 intel_sdvo_destroy(connector);
2473 }
2474}
2475
32aad86f
CW		 2476static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2477 struct intel_sdvo_connector *intel_sdvo_connector,
2478 int type)
ce6feabd 2479{
4ef69c7a 2480 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2481 struct intel_sdvo_tv_format format;
2482 uint32_t format_map, i;
ce6feabd 2483
32aad86f
CW		 2484 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2485 return false;
ce6feabd 2486
1a3665c8 2487 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2488 if (!intel_sdvo_get_value(intel_sdvo,
2489 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2490 &format, sizeof(format)))
2491 return false;
ce6feabd 2492
32aad86f 2493 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2494
2495 if (format_map == 0)
32aad86f 2496 return false;
ce6feabd 2497
615fb93f 2498 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2499 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2500 if (format_map & (1 << i))
2501 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2502
2503
c5521706 2504 intel_sdvo_connector->tv_format =
32aad86f
CW		 2505 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2506 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2507 if (!intel_sdvo_connector->tv_format)
fcc8d672 2508 return false;
ce6feabd 2509
615fb93f 2510 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2511 drm_property_add_enum(
c5521706 2512 intel_sdvo_connector->tv_format, i,
40039750 2513 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2514
40039750 2515 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2516 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2517 intel_sdvo_connector->tv_format, 0);
32aad86f 2518 return true;
ce6feabd
ZY		 2519
2520}
2521
c5521706
CW		 2522#define ENHANCEMENT(name, NAME) do { \
2523 if (enhancements.name) { \
2524 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2525 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2526 return false; \
2527 intel_sdvo_connector->max_##name = data_value[0]; \
2528 intel_sdvo_connector->cur_##name = response; \
2529 intel_sdvo_connector->name = \
d9bc3c02 2530 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2531 if (!intel_sdvo_connector->name) return false; \
662595df 2532 drm_object_attach_property(&connector->base, \
c5521706
CW		 2533 intel_sdvo_connector->name, \
2534 intel_sdvo_connector->cur_##name); \
2535 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2536 data_value[0], data_value[1], response); \
2537 } \
0206e353 2538} while (0)
c5521706
CW		 2539
2540static bool
2541intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2542 struct intel_sdvo_connector *intel_sdvo_connector,
2543 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2544{
4ef69c7a 2545 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2546 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2547 uint16_t response, data_value[2];
2548
c5521706
CW		 2549 /* when horizontal overscan is supported, Add the left/right property */
2550 if (enhancements.overscan_h) {
2551 if (!intel_sdvo_get_value(intel_sdvo,
2552 SDVO_CMD_GET_MAX_OVERSCAN_H,
2553 &data_value, 4))
2554 return false;
32aad86f 2555
c5521706
CW		 2556 if (!intel_sdvo_get_value(intel_sdvo,
2557 SDVO_CMD_GET_OVERSCAN_H,
2558 &response, 2))
2559 return false;
fcc8d672 2560
c5521706
CW		 2561 intel_sdvo_connector->max_hscan = data_value[0];
2562 intel_sdvo_connector->left_margin = data_value[0] - response;
2563 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2564 intel_sdvo_connector->left =
d9bc3c02 2565 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2566 if (!intel_sdvo_connector->left)
2567 return false;
fcc8d672 2568
662595df 2569 drm_object_attach_property(&connector->base,
c5521706
CW		 2570 intel_sdvo_connector->left,
2571 intel_sdvo_connector->left_margin);
fcc8d672 2572
c5521706 2573 intel_sdvo_connector->right =
d9bc3c02 2574 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2575 if (!intel_sdvo_connector->right)
2576 return false;
32aad86f 2577
662595df 2578 drm_object_attach_property(&connector->base,
c5521706
CW		 2579 intel_sdvo_connector->right,
2580 intel_sdvo_connector->right_margin);
2581 DRM_DEBUG_KMS("h_overscan: max %d, "
2582 "default %d, current %d\n",
2583 data_value[0], data_value[1], response);
2584 }
32aad86f 2585
c5521706
CW		 2586 if (enhancements.overscan_v) {
2587 if (!intel_sdvo_get_value(intel_sdvo,
2588 SDVO_CMD_GET_MAX_OVERSCAN_V,
2589 &data_value, 4))
2590 return false;
fcc8d672 2591
c5521706
CW		 2592 if (!intel_sdvo_get_value(intel_sdvo,
2593 SDVO_CMD_GET_OVERSCAN_V,
2594 &response, 2))
2595 return false;
32aad86f 2596
c5521706
CW		 2597 intel_sdvo_connector->max_vscan = data_value[0];
2598 intel_sdvo_connector->top_margin = data_value[0] - response;
2599 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2600 intel_sdvo_connector->top =
d9bc3c02
SH		 2601 drm_property_create_range(dev, 0,
2602 "top_margin", 0, data_value[0]);
c5521706
CW		 2603 if (!intel_sdvo_connector->top)
2604 return false;
32aad86f 2605
662595df 2606 drm_object_attach_property(&connector->base,
c5521706
CW		 2607 intel_sdvo_connector->top,
2608 intel_sdvo_connector->top_margin);
fcc8d672 2609
c5521706 2610 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2611 drm_property_create_range(dev, 0,
2612 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2613 if (!intel_sdvo_connector->bottom)
2614 return false;
32aad86f 2615
662595df 2616 drm_object_attach_property(&connector->base,
c5521706
CW		 2617 intel_sdvo_connector->bottom,
2618 intel_sdvo_connector->bottom_margin);
2619 DRM_DEBUG_KMS("v_overscan: max %d, "
2620 "default %d, current %d\n",
2621 data_value[0], data_value[1], response);
2622 }
32aad86f 2623
c5521706
CW		 2624 ENHANCEMENT(hpos, HPOS);
2625 ENHANCEMENT(vpos, VPOS);
2626 ENHANCEMENT(saturation, SATURATION);
2627 ENHANCEMENT(contrast, CONTRAST);
2628 ENHANCEMENT(hue, HUE);
2629 ENHANCEMENT(sharpness, SHARPNESS);
2630 ENHANCEMENT(brightness, BRIGHTNESS);
2631 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2632 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2633 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2634 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2635 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2636
e044218a
CW		 2637 if (enhancements.dot_crawl) {
2638 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2639 return false;
2640
2641 intel_sdvo_connector->max_dot_crawl = 1;
2642 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2643 intel_sdvo_connector->dot_crawl =
d9bc3c02 2644 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2645 if (!intel_sdvo_connector->dot_crawl)
2646 return false;
2647
662595df 2648 drm_object_attach_property(&connector->base,
e044218a
CW		 2649 intel_sdvo_connector->dot_crawl,
2650 intel_sdvo_connector->cur_dot_crawl);
2651 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2652 }
2653
c5521706
CW		 2654 return true;
2655}
32aad86f 2656
c5521706
CW		 2657static bool
2658intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2659 struct intel_sdvo_connector *intel_sdvo_connector,
2660 struct intel_sdvo_enhancements_reply enhancements)
2661{
4ef69c7a 2662 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2663 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2664 uint16_t response, data_value[2];
32aad86f 2665
c5521706 2666 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2667
c5521706
CW		 2668 return true;
2669}
2670#undef ENHANCEMENT
32aad86f 2671
c5521706
CW		 2672static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2673 struct intel_sdvo_connector *intel_sdvo_connector)
2674{
2675 union {
2676 struct intel_sdvo_enhancements_reply reply;
2677 uint16_t response;
2678 } enhancements;
32aad86f 2679
1a3665c8
CW		 2680 BUILD_BUG_ON(sizeof(enhancements) != 2);
2681
cf9a2f3a
CW		 2682 enhancements.response = 0;
2683 intel_sdvo_get_value(intel_sdvo,
2684 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2685 &enhancements, sizeof(enhancements));
c5521706
CW		 2686 if (enhancements.response == 0) {
2687 DRM_DEBUG_KMS("No enhancement is supported\n");
2688 return true;
b9219c5e 2689 }
32aad86f 2690
c5521706
CW		 2691 if (IS_TV(intel_sdvo_connector))
2692 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2693 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2694 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2695 else
2696 return true;
e957d772
CW		 2697}
2698
2699static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2700 struct i2c_msg *msgs,
2701 int num)
2702{
2703 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2704
e957d772
CW		 2705 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2706 return -EIO;
2707
2708 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2709}
2710
2711static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2712{
2713 struct intel_sdvo *sdvo = adapter->algo_data;
2714 return sdvo->i2c->algo->functionality(sdvo->i2c);
2715}
2716
2717static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2718 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2719 .functionality = intel_sdvo_ddc_proxy_func
2720};
2721
2722static bool
2723intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2724 struct drm_device *dev)
2725{
2726 sdvo->ddc.owner = THIS_MODULE;
2727 sdvo->ddc.class = I2C_CLASS_DDC;
2728 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2729 sdvo->ddc.dev.parent = &dev->pdev->dev;
2730 sdvo->ddc.algo_data = sdvo;
2731 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2732
2733 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2734}
2735
eef4eacb 2736bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2737{
b01f2c3a 2738 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2739 struct intel_encoder *intel_encoder;
ea5b213a 2740 struct intel_sdvo *intel_sdvo;
084b612e 2741 u32 hotplug_mask;
79e53945 2742 int i;
79e53945 2743
ea5b213a
CW		 2744 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2745 if (!intel_sdvo)
7d57382e 2746 return false;
79e53945 2747
56184e3d 2748 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2749 intel_sdvo->is_sdvob = is_sdvob;
2750 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2751 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2752 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2753 goto err_i2c_bus;
e957d772 2754
56184e3d 2755 /* encoder type will be decided later */
ea5b213a 2756 intel_encoder = &intel_sdvo->base;
21d40d37 2757 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2758 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2759
79e53945
JB		 2760 /* Read the regs to test if we can talk to the device */
2761 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2762 u8 byte;
2763
2764 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2765 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2766 SDVO_NAME(intel_sdvo));
f899fc64 2767 goto err;
79e53945
JB		 2768 }
2769 }
2770
084b612e
CW		 2771 hotplug_mask = 0;
2772 if (IS_G4X(dev)) {
2773 hotplug_mask = intel_sdvo->is_sdvob ?
2774 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2775 } else if (IS_GEN4(dev)) {
2776 hotplug_mask = intel_sdvo->is_sdvob ?
2777 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2778 } else {
2779 hotplug_mask = intel_sdvo->is_sdvob ?
2780 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2781 }
619ac3b7 2782
4ef69c7a 2783 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2784
ce22c320
DV		 2785 intel_encoder->disable = intel_disable_sdvo;
2786 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2787 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
ce22c320 2788
af901ca1 2789 /* In default case sdvo lvds is false */
32aad86f 2790 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2791 goto err;
79e53945 2792
ea5b213a
CW		 2793 if (intel_sdvo_output_setup(intel_sdvo,
2794 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2795 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2796 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 2797 /* Output_setup can leave behind connectors! */
2798 goto err_output;
79e53945
JB		 2799 }
2800
e506d6fd
DV		 2801 /*
2802 * Cloning SDVO with anything is often impossible, since the SDVO
2803 * encoder can request a special input timing mode. And even if that's
2804 * not the case we have evidence that cloning a plain unscaled mode with
2805 * VGA doesn't really work. Furthermore the cloning flags are way too
2806 * simplistic anyway to express such constraints, so just give up on
2807 * cloning for SDVO encoders.
2808 */
2809 intel_sdvo->base.cloneable = false;
2810
fcbc50da
JN		 2811 /* Only enable the hotplug irq if we need it, to work around noisy
2812 * hotplug lines.
2813 */
5fa7ac9c 2814 if (intel_sdvo->hotplug_active)
fcbc50da
JN		 2815 dev_priv->hotplug_supported_mask |= hotplug_mask;
2816
ea5b213a 2817 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2818
79e53945 2819 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2820 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 2821 goto err_output;
79e53945 2822
32aad86f
CW		 2823 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2824 &intel_sdvo->pixel_clock_min,
2825 &intel_sdvo->pixel_clock_max))
d0ddfbd3 2826 goto err_output;
79e53945 2827
8a4c47f3 2828 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2829 "clock range %dMHz - %dMHz, "
2830 "input 1: %c, input 2: %c, "
2831 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2832 SDVO_NAME(intel_sdvo),
2833 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2834 intel_sdvo->caps.device_rev_id,
2835 intel_sdvo->pixel_clock_min / 1000,
2836 intel_sdvo->pixel_clock_max / 1000,
2837 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2838 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2839 /* check currently supported outputs */
ea5b213a 2840 intel_sdvo->caps.output_flags &
79e53945 2841 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2842 intel_sdvo->caps.output_flags &
79e53945 2843 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2844 return true;
79e53945 2845
d0ddfbd3
JN		 2846err_output:
2847 intel_sdvo_output_cleanup(intel_sdvo);
2848
f899fc64 2849err:
373a3cf7 2850 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2851 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2852err_i2c_bus:
2853 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2854 kfree(intel_sdvo);
79e53945 2855
7d57382e 2856 return false;
79e53945 2857}
Linux kernel - Deliverables
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