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drm/i915: group ADPA #defines together
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
2e88e40b 56static const char *tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 77 uint32_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
100 uint8_t hotplug_active[2];
101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
12682a97 129
7086c87f 130 /**
6c9547ff
CW		 131 * This is set if we detect output of sdvo device as LVDS and
132 * have a valid fixed mode to use with the panel.
7086c87f
ML		 133 */
134 bool is_lvds;
e2f0ba97 135
12682a97 136 /**
137 * This is sdvo fixed pannel mode pointer
138 */
139 struct drm_display_mode *sdvo_lvds_fixed_mode;
140
c751ce4f 141 /* DDC bus used by this SDVO encoder */
e2f0ba97 142 uint8_t ddc_bus;
14571b4c
ZW		 143};
144
145struct intel_sdvo_connector {
615fb93f
CW		 146 struct intel_connector base;
147
14571b4c
ZW		 148 /* Mark the type of connector */
149 uint16_t output_flag;
150
c3e5f67b 151 enum hdmi_force_audio force_audio;
7f36e7ed 152
14571b4c 153 /* This contains all current supported TV format */
40039750 154 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 155 int format_supported_num;
c5521706 156 struct drm_property *tv_format;
14571b4c 157
b9219c5e 158 /* add the property for the SDVO-TV */
c5521706
CW		 159 struct drm_property *left;
160 struct drm_property *right;
161 struct drm_property *top;
162 struct drm_property *bottom;
163 struct drm_property *hpos;
164 struct drm_property *vpos;
165 struct drm_property *contrast;
166 struct drm_property *saturation;
167 struct drm_property *hue;
168 struct drm_property *sharpness;
169 struct drm_property *flicker_filter;
170 struct drm_property *flicker_filter_adaptive;
171 struct drm_property *flicker_filter_2d;
172 struct drm_property *tv_chroma_filter;
173 struct drm_property *tv_luma_filter;
e044218a 174 struct drm_property *dot_crawl;
b9219c5e
ZY		 175
176 /* add the property for the SDVO-TV/LVDS */
c5521706 177 struct drm_property *brightness;
b9219c5e
ZY		 178
179 /* Add variable to record current setting for the above property */
180 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 181
b9219c5e
ZY		 182 /* this is to get the range of margin.*/
183 u32 max_hscan, max_vscan;
184 u32 max_hpos, cur_hpos;
185 u32 max_vpos, cur_vpos;
186 u32 cur_brightness, max_brightness;
187 u32 cur_contrast, max_contrast;
188 u32 cur_saturation, max_saturation;
189 u32 cur_hue, max_hue;
c5521706
CW		 190 u32 cur_sharpness, max_sharpness;
191 u32 cur_flicker_filter, max_flicker_filter;
192 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
193 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
194 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
195 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 196 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 197};
198
890f3359 199static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 200{
4ef69c7a 201 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 202}
203
df0e9248
CW		 204static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
205{
206 return container_of(intel_attached_encoder(connector),
207 struct intel_sdvo, base);
208}
209
615fb93f
CW		 210static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
211{
212 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
213}
214
fb7a46f3 215static bool
ea5b213a 216intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 217static bool
218intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
219 struct intel_sdvo_connector *intel_sdvo_connector,
220 int type);
221static bool
222intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
223 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 224
79e53945
JB		 225/**
226 * Writes the SDVOB or SDVOC with the given value, but always writes both
227 * SDVOB and SDVOC to work around apparent hardware issues (according to
228 * comments in the BIOS).
229 */
ea5b213a 230static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 231{
4ef69c7a 232 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 233 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 234 u32 bval = val, cval = val;
235 int i;
236
ea5b213a
CW		 237 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
238 I915_WRITE(intel_sdvo->sdvo_reg, val);
239 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 240 return;
241 }
242
ea5b213a 243 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 244 cval = I915_READ(SDVOC);
245 } else {
246 bval = I915_READ(SDVOB);
247 }
248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
253 for (i = 0; i < 2; i++)
254 {
255 I915_WRITE(SDVOB, bval);
256 I915_READ(SDVOB);
257 I915_WRITE(SDVOC, cval);
258 I915_READ(SDVOC);
259 }
260}
261
32aad86f 262static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 263{
79e53945
JB		 264 struct i2c_msg msgs[] = {
265 {
e957d772 266 .addr = intel_sdvo->slave_addr,
79e53945
JB		 267 .flags = 0,
268 .len = 1,
e957d772 269 .buf = &addr,
79e53945
JB		 270 },
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = I2C_M_RD,
274 .len = 1,
e957d772 275 .buf = ch,
79e53945
JB		 276 }
277 };
32aad86f 278 int ret;
79e53945 279
f899fc64 280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 281 return true;
79e53945 282
8a4c47f3 283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 284 return false;
285}
286
79e53945
JB		 287#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288/** Mapping of command numbers to names, for debug output */
005568be 289static const struct _sdvo_cmd_name {
e2f0ba97 290 u8 cmd;
2e88e40b 291 const char *name;
79e53945 292} sdvo_cmd_names[] = {
0206e353
AJ		 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 404};
405
eef4eacb 406#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 407
ea5b213a 408static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 409 const void *args, int args_len)
79e53945 410{
79e53945
JB		 411 int i;
412
8a4c47f3 413 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 414 SDVO_NAME(intel_sdvo), cmd);
79e53945 415 for (i = 0; i < args_len; i++)
342dc382 416 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 417 for (; i < 8; i++)
342dc382 418 DRM_LOG_KMS(" ");
04ad327f 419 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 420 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 421 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 422 break;
423 }
424 }
04ad327f 425 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 426 DRM_LOG_KMS("(%02X)", cmd);
427 DRM_LOG_KMS("\n");
79e53945 428}
79e53945 429
e957d772
CW		 430static const char *cmd_status_names[] = {
431 "Power on",
432 "Success",
433 "Not supported",
434 "Invalid arg",
435 "Pending",
436 "Target not specified",
437 "Scaling not supported"
438};
439
32aad86f
CW		 440static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
441 const void *args, int args_len)
79e53945 442{
3bf3f452
BW		 443 u8 *buf, status;
444 struct i2c_msg *msgs;
445 int i, ret = true;
446
447 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
448 if (!buf)
449 return false;
450
451 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
452 if (!msgs)
453 return false;
79e53945 454
ea5b213a 455 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 456
457 for (i = 0; i < args_len; i++) {
e957d772
CW		 458 msgs[i].addr = intel_sdvo->slave_addr;
459 msgs[i].flags = 0;
460 msgs[i].len = 2;
461 msgs[i].buf = buf + 2 *i;
462 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
463 buf[2*i + 1] = ((u8*)args)[i];
464 }
465 msgs[i].addr = intel_sdvo->slave_addr;
466 msgs[i].flags = 0;
467 msgs[i].len = 2;
468 msgs[i].buf = buf + 2*i;
469 buf[2*i + 0] = SDVO_I2C_OPCODE;
470 buf[2*i + 1] = cmd;
471
472 /* the following two are to read the response */
473 status = SDVO_I2C_CMD_STATUS;
474 msgs[i+1].addr = intel_sdvo->slave_addr;
475 msgs[i+1].flags = 0;
476 msgs[i+1].len = 1;
477 msgs[i+1].buf = &status;
478
479 msgs[i+2].addr = intel_sdvo->slave_addr;
480 msgs[i+2].flags = I2C_M_RD;
481 msgs[i+2].len = 1;
482 msgs[i+2].buf = &status;
483
484 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
485 if (ret < 0) {
486 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 487 ret = false;
488 goto out;
e957d772
CW		 489 }
490 if (ret != i+3) {
491 /* failure in I2C transfer */
492 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 493 ret = false;
e957d772
CW		 494 }
495
3bf3f452
BW		 496out:
497 kfree(msgs);
498 kfree(buf);
499 return ret;
79e53945
JB		 500}
501
b5c616a7
CW		 502static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
503 void *response, int response_len)
79e53945 504{
b5c616a7
CW		 505 u8 retry = 5;
506 u8 status;
33b52961 507 int i;
79e53945 508
d121a5d2
CW		 509 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
510
b5c616a7
CW		 511 /*
512 * The documentation states that all commands will be
513 * processed within 15µs, and that we need only poll
514 * the status byte a maximum of 3 times in order for the
515 * command to be complete.
516 *
517 * Check 5 times in case the hardware failed to read the docs.
518 */
d121a5d2
CW		 519 if (!intel_sdvo_read_byte(intel_sdvo,
520 SDVO_I2C_CMD_STATUS,
521 &status))
522 goto log_fail;
523
524 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
525 udelay(15);
b5c616a7
CW		 526 if (!intel_sdvo_read_byte(intel_sdvo,
527 SDVO_I2C_CMD_STATUS,
528 &status))
d121a5d2
CW		 529 goto log_fail;
530 }
b5c616a7 531
79e53945 532 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 533 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 534 else
342dc382 535 DRM_LOG_KMS("(??? %d)", status);
79e53945 536
b5c616a7
CW		 537 if (status != SDVO_CMD_STATUS_SUCCESS)
538 goto log_fail;
79e53945 539
b5c616a7
CW		 540 /* Read the command response */
541 for (i = 0; i < response_len; i++) {
542 if (!intel_sdvo_read_byte(intel_sdvo,
543 SDVO_I2C_RETURN_0 + i,
544 &((u8 *)response)[i]))
545 goto log_fail;
e957d772 546 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 547 }
b5c616a7 548 DRM_LOG_KMS("\n");
b5c616a7 549 return true;
79e53945 550
b5c616a7 551log_fail:
d121a5d2 552 DRM_LOG_KMS("... failed\n");
b5c616a7 553 return false;
79e53945
JB		 554}
555
b358d0a6 556static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 557{
558 if (mode->clock >= 100000)
559 return 1;
560 else if (mode->clock >= 50000)
561 return 2;
562 else
563 return 4;
564}
565
e957d772
CW		 566static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
567 u8 ddc_bus)
79e53945 568{
d121a5d2 569 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 570 return intel_sdvo_write_cmd(intel_sdvo,
571 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
572 &ddc_bus, 1);
79e53945
JB		 573}
574
32aad86f 575static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 576{
d121a5d2
CW		 577 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
578 return false;
579
580 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 581}
79e53945 582
32aad86f
CW		 583static bool
584intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
585{
586 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
587 return false;
79e53945 588
32aad86f
CW		 589 return intel_sdvo_read_response(intel_sdvo, value, len);
590}
79e53945 591
32aad86f
CW		 592static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
593{
594 struct intel_sdvo_set_target_input_args targets = {0};
595 return intel_sdvo_set_value(intel_sdvo,
596 SDVO_CMD_SET_TARGET_INPUT,
597 &targets, sizeof(targets));
79e53945
JB		 598}
599
600/**
601 * Return whether each input is trained.
602 *
603 * This function is making an assumption about the layout of the response,
604 * which should be checked against the docs.
605 */
ea5b213a 606static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 607{
608 struct intel_sdvo_get_trained_inputs_response response;
79e53945 609
1a3665c8 610 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 611 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
612 &response, sizeof(response)))
79e53945
JB		 613 return false;
614
615 *input_1 = response.input0_trained;
616 *input_2 = response.input1_trained;
617 return true;
618}
619
ea5b213a 620static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 621 u16 outputs)
622{
32aad86f
CW		 623 return intel_sdvo_set_value(intel_sdvo,
624 SDVO_CMD_SET_ACTIVE_OUTPUTS,
625 &outputs, sizeof(outputs));
79e53945
JB		 626}
627
ea5b213a 628static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 629 int mode)
630{
32aad86f 631 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 632
633 switch (mode) {
634 case DRM_MODE_DPMS_ON:
635 state = SDVO_ENCODER_STATE_ON;
636 break;
637 case DRM_MODE_DPMS_STANDBY:
638 state = SDVO_ENCODER_STATE_STANDBY;
639 break;
640 case DRM_MODE_DPMS_SUSPEND:
641 state = SDVO_ENCODER_STATE_SUSPEND;
642 break;
643 case DRM_MODE_DPMS_OFF:
644 state = SDVO_ENCODER_STATE_OFF;
645 break;
646 }
647
32aad86f
CW		 648 return intel_sdvo_set_value(intel_sdvo,
649 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 650}
651
ea5b213a 652static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 653 int *clock_min,
654 int *clock_max)
655{
656 struct intel_sdvo_pixel_clock_range clocks;
79e53945 657
1a3665c8 658 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 659 if (!intel_sdvo_get_value(intel_sdvo,
660 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
661 &clocks, sizeof(clocks)))
79e53945
JB		 662 return false;
663
664 /* Convert the values from units of 10 kHz to kHz. */
665 *clock_min = clocks.min * 10;
666 *clock_max = clocks.max * 10;
79e53945
JB		 667 return true;
668}
669
ea5b213a 670static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 671 u16 outputs)
672{
32aad86f
CW		 673 return intel_sdvo_set_value(intel_sdvo,
674 SDVO_CMD_SET_TARGET_OUTPUT,
675 &outputs, sizeof(outputs));
79e53945
JB		 676}
677
ea5b213a 678static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 679 struct intel_sdvo_dtd *dtd)
680{
32aad86f
CW		 681 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
682 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 683}
684
ea5b213a 685static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 686 struct intel_sdvo_dtd *dtd)
687{
ea5b213a 688 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 689 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
690}
691
ea5b213a 692static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 693 struct intel_sdvo_dtd *dtd)
694{
ea5b213a 695 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 696 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
697}
698
e2f0ba97 699static bool
ea5b213a 700intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 701 uint16_t clock,
702 uint16_t width,
703 uint16_t height)
704{
705 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 706
e642c6f1 707 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 708 args.clock = clock;
709 args.width = width;
710 args.height = height;
e642c6f1 711 args.interlace = 0;
12682a97 712
ea5b213a
CW		 713 if (intel_sdvo->is_lvds &&
714 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
715 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 716 args.scaled = 1;
717
32aad86f
CW		 718 return intel_sdvo_set_value(intel_sdvo,
719 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
720 &args, sizeof(args));
e2f0ba97
JB		 721}
722
ea5b213a 723static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 724 struct intel_sdvo_dtd *dtd)
725{
1a3665c8
CW		 726 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
727 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 728 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
729 &dtd->part1, sizeof(dtd->part1)) &&
730 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
731 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 732}
79e53945 733
ea5b213a 734static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 735{
32aad86f 736 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 737}
738
e2f0ba97 739static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 740 const struct drm_display_mode *mode)
79e53945 741{
e2f0ba97
JB		 742 uint16_t width, height;
743 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
744 uint16_t h_sync_offset, v_sync_offset;
6651819b 745 int mode_clock;
79e53945 746
c6ebd4c0
DV		 747 width = mode->hdisplay;
748 height = mode->vdisplay;
79e53945
JB		 749
750 /* do some mode translations */
c6ebd4c0
DV		 751 h_blank_len = mode->htotal - mode->hdisplay;
752 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 753
c6ebd4c0
DV		 754 v_blank_len = mode->vtotal - mode->vdisplay;
755 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 756
c6ebd4c0
DV		 757 h_sync_offset = mode->hsync_start - mode->hdisplay;
758 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 759
6651819b
DV		 760 mode_clock = mode->clock;
761 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
762 mode_clock /= 10;
763 dtd->part1.clock = mode_clock;
764
e2f0ba97
JB		 765 dtd->part1.h_active = width & 0xff;
766 dtd->part1.h_blank = h_blank_len & 0xff;
767 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 768 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 769 dtd->part1.v_active = height & 0xff;
770 dtd->part1.v_blank = v_blank_len & 0xff;
771 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 772 ((v_blank_len >> 8) & 0xf);
773
171a9e96 774 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 775 dtd->part2.h_sync_width = h_sync_len & 0xff;
776 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 777 (v_sync_len & 0xf);
e2f0ba97 778 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 779 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
780 ((v_sync_len & 0x30) >> 4);
781
e2f0ba97 782 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 783 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
784 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 785 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 786 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 787 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 788 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 789
790 dtd->part2.sdvo_flags = 0;
791 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
792 dtd->part2.reserved = 0;
793}
794
795static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 796 const struct intel_sdvo_dtd *dtd)
e2f0ba97 797{
e2f0ba97
JB		 798 mode->hdisplay = dtd->part1.h_active;
799 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
800 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 801 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 802 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
803 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
804 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
805 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
806
807 mode->vdisplay = dtd->part1.v_active;
808 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
809 mode->vsync_start = mode->vdisplay;
810 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 811 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 812 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
813 mode->vsync_end = mode->vsync_start +
814 (dtd->part2.v_sync_off_width & 0xf);
815 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
816 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
817 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
818
819 mode->clock = dtd->part1.clock * 10;
820
171a9e96 821 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 822 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
823 mode->flags |= DRM_MODE_FLAG_INTERLACE;
824 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 825 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 826 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 827 mode->flags |= DRM_MODE_FLAG_PVSYNC;
828}
829
e27d8538 830static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 831{
e27d8538 832 struct intel_sdvo_encode encode;
e2f0ba97 833
1a3665c8 834 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 835 return intel_sdvo_get_value(intel_sdvo,
836 SDVO_CMD_GET_SUPP_ENCODE,
837 &encode, sizeof(encode));
e2f0ba97
JB		 838}
839
ea5b213a 840static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 841 uint8_t mode)
e2f0ba97 842{
32aad86f 843 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 844}
845
ea5b213a 846static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 847 uint8_t mode)
848{
32aad86f 849 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 850}
851
852#if 0
ea5b213a 853static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 854{
855 int i, j;
856 uint8_t set_buf_index[2];
857 uint8_t av_split;
858 uint8_t buf_size;
859 uint8_t buf[48];
860 uint8_t *pos;
861
32aad86f 862 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 863
864 for (i = 0; i <= av_split; i++) {
865 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 866 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 867 set_buf_index, 2);
c751ce4f
EA		 868 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
869 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 870
871 pos = buf;
872 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 873 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 874 NULL, 0);
c751ce4f 875 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 876 pos += 8;
877 }
878 }
879}
880#endif
881
3c17fe4b 882static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 883{
884 struct dip_infoframe avi_if = {
885 .type = DIP_TYPE_AVI,
3c17fe4b 886 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 887 .len = DIP_LEN_AVI,
888 };
3c17fe4b
DH		 889 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
890 uint8_t set_buf_index[2] = { 1, 0 };
81014b9d
DV		 891 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
892 uint64_t *data = (uint64_t *)sdvo_data;
3c17fe4b
DH		 893 unsigned i;
894
895 intel_dip_infoframe_csum(&avi_if);
896
81014b9d
DV		 897 /* sdvo spec says that the ecc is handled by the hw, and it looks like
898 * we must not send the ecc field, either. */
899 memcpy(sdvo_data, &avi_if, 3);
900 sdvo_data[3] = avi_if.checksum;
901 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
902
d121a5d2
CW		 903 if (!intel_sdvo_set_value(intel_sdvo,
904 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 905 set_buf_index, 2))
906 return false;
907
81014b9d 908 for (i = 0; i < sizeof(sdvo_data); i += 8) {
d121a5d2
CW		 909 if (!intel_sdvo_set_value(intel_sdvo,
910 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 911 data, 8))
912 return false;
913 data++;
914 }
e2f0ba97 915
d121a5d2
CW		 916 return intel_sdvo_set_value(intel_sdvo,
917 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 918 &tx_rate, 1);
e2f0ba97
JB		 919}
920
32aad86f 921static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 922{
ce6feabd 923 struct intel_sdvo_tv_format format;
40039750 924 uint32_t format_map;
ce6feabd 925
40039750 926 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 927 memset(&format, 0, sizeof(format));
32aad86f 928 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 929
32aad86f
CW		 930 BUILD_BUG_ON(sizeof(format) != 6);
931 return intel_sdvo_set_value(intel_sdvo,
932 SDVO_CMD_SET_TV_FORMAT,
933 &format, sizeof(format));
7026d4ac
ZW		 934}
935
32aad86f
CW		 936static bool
937intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 938 const struct drm_display_mode *mode)
e2f0ba97 939{
32aad86f 940 struct intel_sdvo_dtd output_dtd;
79e53945 941
32aad86f
CW		 942 if (!intel_sdvo_set_target_output(intel_sdvo,
943 intel_sdvo->attached_output))
944 return false;
e2f0ba97 945
32aad86f
CW		 946 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
947 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
948 return false;
e2f0ba97 949
32aad86f
CW		 950 return true;
951}
952
c9a29698
DV		 953/* Asks the sdvo controller for the preferred input mode given the output mode.
954 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 955static bool
c9a29698 956intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 957 const struct drm_display_mode *mode,
c9a29698 958 struct drm_display_mode *adjusted_mode)
32aad86f 959{
c9a29698
DV		 960 struct intel_sdvo_dtd input_dtd;
961
32aad86f
CW		 962 /* Reset the input timing to the screen. Assume always input 0. */
963 if (!intel_sdvo_set_target_input(intel_sdvo))
964 return false;
e2f0ba97 965
32aad86f
CW		 966 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
967 mode->clock / 10,
968 mode->hdisplay,
969 mode->vdisplay))
970 return false;
e2f0ba97 971
32aad86f 972 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 973 &input_dtd))
32aad86f 974 return false;
e2f0ba97 975
c9a29698 976 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
79e53945 977
32aad86f
CW		 978 return true;
979}
12682a97 980
32aad86f 981static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
e811f5ae 982 const struct drm_display_mode *mode,
32aad86f
CW		 983 struct drm_display_mode *adjusted_mode)
984{
890f3359 985 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 986 int multiplier;
12682a97 987
32aad86f
CW		 988 /* We need to construct preferred input timings based on our
989 * output timings. To do that, we have to set the output
990 * timings, even though this isn't really the right place in
991 * the sequence to do it. Oh well.
992 */
993 if (intel_sdvo->is_tv) {
994 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
995 return false;
12682a97 996
c9a29698
DV		 997 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
998 mode,
999 adjusted_mode);
ea5b213a 1000 } else if (intel_sdvo->is_lvds) {
32aad86f 1001 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1002 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1003 return false;
12682a97 1004
c9a29698
DV		 1005 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1006 mode,
1007 adjusted_mode);
e2f0ba97 1008 }
32aad86f
CW		 1009
1010 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1011 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1012 */
6c9547ff
CW		 1013 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1014 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1015
e2f0ba97
JB		 1016 return true;
1017}
1018
1019static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1020 struct drm_display_mode *mode,
1021 struct drm_display_mode *adjusted_mode)
1022{
1023 struct drm_device *dev = encoder->dev;
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 struct drm_crtc *crtc = encoder->crtc;
1026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1027 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1028 u32 sdvox;
e2f0ba97 1029 struct intel_sdvo_in_out_map in_out;
6651819b 1030 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1031 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1032 int rate;
e2f0ba97
JB		 1033
1034 if (!mode)
1035 return;
1036
1037 /* First, set the input mapping for the first input to our controlled
1038 * output. This is only correct if we're a single-input device, in
1039 * which case the first input is the output from the appropriate SDVO
1040 * channel on the motherboard. In a two-input device, the first input
1041 * will be SDVOB and the second SDVOC.
1042 */
ea5b213a 1043 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1044 in_out.in1 = 0;
1045
c74696b9
PR		 1046 intel_sdvo_set_value(intel_sdvo,
1047 SDVO_CMD_SET_IN_OUT_MAP,
1048 &in_out, sizeof(in_out));
e2f0ba97 1049
6c9547ff
CW		 1050 /* Set the output timings to the screen */
1051 if (!intel_sdvo_set_target_output(intel_sdvo,
1052 intel_sdvo->attached_output))
1053 return;
e2f0ba97 1054
6651819b
DV		 1055 /* lvds has a special fixed output timing. */
1056 if (intel_sdvo->is_lvds)
1057 intel_sdvo_get_dtd_from_mode(&output_dtd,
1058 intel_sdvo->sdvo_lvds_fixed_mode);
1059 else
1060 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1061 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1062 DRM_INFO("Setting output timings on %s failed\n",
1063 SDVO_NAME(intel_sdvo));
79e53945
JB		 1064
1065 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1066 if (!intel_sdvo_set_target_input(intel_sdvo))
1067 return;
79e53945 1068
97aaf910
CW		 1069 if (intel_sdvo->has_hdmi_monitor) {
1070 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1071 intel_sdvo_set_colorimetry(intel_sdvo,
1072 SDVO_COLORIMETRY_RGB256);
1073 intel_sdvo_set_avi_infoframe(intel_sdvo);
1074 } else
1075 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1076
6c9547ff
CW		 1077 if (intel_sdvo->is_tv &&
1078 !intel_sdvo_set_tv_format(intel_sdvo))
1079 return;
e2f0ba97 1080
6651819b
DV		 1081 /* We have tried to get input timing in mode_fixup, and filled into
1082 * adjusted_mode.
1083 */
1084 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c8d4bb54
DV		 1085 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1086 DRM_INFO("Setting input timings on %s failed\n",
1087 SDVO_NAME(intel_sdvo));
79e53945 1088
6c9547ff
CW		 1089 switch (pixel_multiplier) {
1090 default:
32aad86f
CW		 1091 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1092 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1093 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1094 }
32aad86f
CW		 1095 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1096 return;
79e53945
JB		 1097
1098 /* Set the SDVO control regs. */
a6c45cf0 1099 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1100 /* The real mode polarity is set by the SDVO commands, using
1101 * struct intel_sdvo_dtd. */
1102 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1103 if (intel_sdvo->is_hdmi)
1104 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1105 if (INTEL_INFO(dev)->gen < 5)
1106 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1107 } else {
6c9547ff 1108 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1109 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1110 case SDVOB:
1111 sdvox &= SDVOB_PRESERVE_MASK;
1112 break;
1113 case SDVOC:
1114 sdvox &= SDVOC_PRESERVE_MASK;
1115 break;
1116 }
1117 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1118 }
3573c410
PZ		 1119
1120 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1121 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1122 else
1123 sdvox |= TRANSCODER(intel_crtc->pipe);
1124
da79de97 1125 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1126 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1127
a6c45cf0 1128 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1129 /* done in crtc_mode_set as the dpll_md reg must be written early */
1130 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1131 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1132 } else {
6c9547ff 1133 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1134 }
1135
6714afb1
CW		 1136 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1137 INTEL_INFO(dev)->gen < 5)
12682a97 1138 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1139 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1140}
1141
1142static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1143{
1144 struct drm_device *dev = encoder->dev;
1145 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1146 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1147 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1148 u32 temp;
1149
1150 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1151 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1152 if (0)
ea5b213a 1153 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1154
1155 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1156 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1157 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1158 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1159 }
1160 }
1161 } else {
1162 bool input1, input2;
1163 int i;
1164 u8 status;
1165
ea5b213a 1166 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1167 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1168 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1169 for (i = 0; i < 2; i++)
9d0498a2 1170 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1171
32aad86f 1172 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1173 /* Warn if the device reported failure to sync.
1174 * A lot of SDVO devices fail to notify of sync, but it's
1175 * a given it the status is a success, we succeeded.
1176 */
1177 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1178 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1179 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1180 }
1181
1182 if (0)
ea5b213a
CW		 1183 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1184 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1185 }
1186 return;
1187}
1188
79e53945
JB		 1189static int intel_sdvo_mode_valid(struct drm_connector *connector,
1190 struct drm_display_mode *mode)
1191{
df0e9248 1192 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1193
1194 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1195 return MODE_NO_DBLESCAN;
1196
ea5b213a 1197 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1198 return MODE_CLOCK_LOW;
1199
ea5b213a 1200 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1201 return MODE_CLOCK_HIGH;
1202
8545423a 1203 if (intel_sdvo->is_lvds) {
ea5b213a 1204 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1205 return MODE_PANEL;
1206
ea5b213a 1207 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1208 return MODE_PANEL;
1209 }
1210
79e53945
JB		 1211 return MODE_OK;
1212}
1213
ea5b213a 1214static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1215{
1a3665c8 1216 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1217 if (!intel_sdvo_get_value(intel_sdvo,
1218 SDVO_CMD_GET_DEVICE_CAPS,
1219 caps, sizeof(*caps)))
1220 return false;
1221
1222 DRM_DEBUG_KMS("SDVO capabilities:\n"
1223 " vendor_id: %d\n"
1224 " device_id: %d\n"
1225 " device_rev_id: %d\n"
1226 " sdvo_version_major: %d\n"
1227 " sdvo_version_minor: %d\n"
1228 " sdvo_inputs_mask: %d\n"
1229 " smooth_scaling: %d\n"
1230 " sharp_scaling: %d\n"
1231 " up_scaling: %d\n"
1232 " down_scaling: %d\n"
1233 " stall_support: %d\n"
1234 " output_flags: %d\n",
1235 caps->vendor_id,
1236 caps->device_id,
1237 caps->device_rev_id,
1238 caps->sdvo_version_major,
1239 caps->sdvo_version_minor,
1240 caps->sdvo_inputs_mask,
1241 caps->smooth_scaling,
1242 caps->sharp_scaling,
1243 caps->up_scaling,
1244 caps->down_scaling,
1245 caps->stall_support,
1246 caps->output_flags);
1247
1248 return true;
79e53945
JB		 1249}
1250
cc68c81a 1251static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945 1252{
768b107e 1253 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 1254 u8 response[2];
79e53945 1255
768b107e
DV		 1256 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1257 * on the line. */
1258 if (IS_I945G(dev) || IS_I945GM(dev))
1259 return false;
1260
32aad86f
CW		 1261 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1262 &response, 2) && response[0];
79e53945
JB		 1263}
1264
cc68c81a 1265static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1266{
cc68c81a 1267 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1268
cc68c81a 1269 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1270}
1271
fb7a46f3 1272static bool
ea5b213a 1273intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1274{
bc65212c 1275 /* Is there more than one type of output? */
2294488d 1276 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1277}
1278
f899fc64 1279static struct edid *
e957d772 1280intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1281{
e957d772
CW		 1282 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1283 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1284}
1285
ff482d83
CW		 1286/* Mac mini hack -- use the same DDC as the analog connector */
1287static struct edid *
1288intel_sdvo_get_analog_edid(struct drm_connector *connector)
1289{
f899fc64 1290 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1291
0c1dab89 1292 return drm_get_edid(connector,
3bd7d909
DK		 1293 intel_gmbus_get_adapter(dev_priv,
1294 dev_priv->crt_ddc_pin));
ff482d83
CW		 1295}
1296
c43b5634 1297static enum drm_connector_status
8bf38485 1298intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1299{
df0e9248 1300 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1301 enum drm_connector_status status;
1302 struct edid *edid;
9dff6af8 1303
e957d772 1304 edid = intel_sdvo_get_edid(connector);
57cdaf90 1305
ea5b213a 1306 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1307 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1308
7c3f0a27
ZY		 1309 /*
1310 * Don't use the 1 as the argument of DDC bus switch to get
1311 * the EDID. It is used for SDVO SPD ROM.
1312 */
9d1a903d 1313 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1314 intel_sdvo->ddc_bus = ddc;
1315 edid = intel_sdvo_get_edid(connector);
1316 if (edid)
7c3f0a27 1317 break;
7c3f0a27 1318 }
e957d772
CW		 1319 /*
1320 * If we found the EDID on the other bus,
1321 * assume that is the correct DDC bus.
1322 */
1323 if (edid == NULL)
1324 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1325 }
9d1a903d
CW		 1326
1327 /*
1328 * When there is no edid and no monitor is connected with VGA
1329 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1330 */
ff482d83
CW		 1331 if (edid == NULL)
1332 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1333
2f551c84 1334 status = connector_status_unknown;
9dff6af8 1335 if (edid != NULL) {
149c36a3 1336 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1337 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1338 status = connector_status_connected;
da79de97
CW		 1339 if (intel_sdvo->is_hdmi) {
1340 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1341 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1342 }
13946743
CW		 1343 } else
1344 status = connector_status_disconnected;
149c36a3 1345 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1346 kfree(edid);
1347 }
7f36e7ed
CW		 1348
1349 if (status == connector_status_connected) {
1350 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1351 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1352 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1353 }
1354
2b8d33f7 1355 return status;
9dff6af8
ML		 1356}
1357
52220085
CW		 1358static bool
1359intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1360 struct edid *edid)
1361{
1362 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1363 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1364
1365 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1366 connector_is_digital, monitor_is_digital);
1367 return connector_is_digital == monitor_is_digital;
1368}
1369
7b334fcb 1370static enum drm_connector_status
930a9e28 1371intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1372{
fb7a46f3 1373 uint16_t response;
df0e9248 1374 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1375 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1376 enum drm_connector_status ret;
79e53945 1377
32aad86f 1378 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1379 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1380 return connector_status_unknown;
ba84cd1f
CW		 1381
1382 /* add 30ms delay when the output type might be TV */
a0b1c7a5 1383 if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
6c982376 1384 msleep(30);
ba84cd1f 1385
32aad86f
CW		 1386 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1387 return connector_status_unknown;
79e53945 1388
e957d772
CW		 1389 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1390 response & 0xff, response >> 8,
1391 intel_sdvo_connector->output_flag);
e2f0ba97 1392
fb7a46f3 1393 if (response == 0)
79e53945 1394 return connector_status_disconnected;
fb7a46f3 1395
ea5b213a 1396 intel_sdvo->attached_output = response;
14571b4c 1397
97aaf910
CW		 1398 intel_sdvo->has_hdmi_monitor = false;
1399 intel_sdvo->has_hdmi_audio = false;
1400
615fb93f 1401 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1402 ret = connector_status_disconnected;
13946743 1403 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1404 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1405 else {
1406 struct edid *edid;
1407
1408 /* if we have an edid check it matches the connection */
1409 edid = intel_sdvo_get_edid(connector);
1410 if (edid == NULL)
1411 edid = intel_sdvo_get_analog_edid(connector);
1412 if (edid != NULL) {
52220085
CW		 1413 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1414 edid))
13946743 1415 ret = connector_status_connected;
52220085
CW		 1416 else
1417 ret = connector_status_disconnected;
1418
13946743
CW		 1419 connector->display_info.raw_edid = NULL;
1420 kfree(edid);
1421 } else
1422 ret = connector_status_connected;
1423 }
14571b4c
ZW		 1424
1425 /* May update encoder flag for like clock for SDVO TV, etc.*/
1426 if (ret == connector_status_connected) {
ea5b213a
CW		 1427 intel_sdvo->is_tv = false;
1428 intel_sdvo->is_lvds = false;
1429 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1430
1431 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1432 intel_sdvo->is_tv = true;
1433 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1434 }
1435 if (response & SDVO_LVDS_MASK)
8545423a 1436 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1437 }
14571b4c
ZW		 1438
1439 return ret;
79e53945
JB		 1440}
1441
e2f0ba97 1442static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1443{
ff482d83 1444 struct edid *edid;
79e53945
JB		 1445
1446 /* set the bus switch and get the modes */
e957d772 1447 edid = intel_sdvo_get_edid(connector);
79e53945 1448
57cdaf90
KP		 1449 /*
1450 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1451 * link between analog and digital outputs. So, if the regular SDVO
1452 * DDC fails, check to see if the analog output is disconnected, in
1453 * which case we'll look there for the digital DDC data.
e2f0ba97 1454 */
f899fc64
CW		 1455 if (edid == NULL)
1456 edid = intel_sdvo_get_analog_edid(connector);
1457
ff482d83 1458 if (edid != NULL) {
52220085
CW		 1459 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1460 edid)) {
0c1dab89
CW		 1461 drm_mode_connector_update_edid_property(connector, edid);
1462 drm_add_edid_modes(connector, edid);
1463 }
13946743 1464
ff482d83
CW		 1465 connector->display_info.raw_edid = NULL;
1466 kfree(edid);
e2f0ba97 1467 }
e2f0ba97
JB		 1468}
1469
1470/*
1471 * Set of SDVO TV modes.
1472 * Note! This is in reply order (see loop in get_tv_modes).
1473 * XXX: all 60Hz refresh?
1474 */
b1f559ec 1475static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1476 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1477 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1479 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1480 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1482 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1483 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1485 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1486 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1488 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1489 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1491 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1492 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1494 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1495 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1497 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1498 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1500 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1501 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1503 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1504 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1506 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1507 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1509 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1510 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1512 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1513 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1515 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1516 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1518 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1519 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1521 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1522 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1524 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1525 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1527 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1528 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1530 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1531 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1533};
1534
1535static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1536{
df0e9248 1537 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1538 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1539 uint32_t reply = 0, format_map = 0;
1540 int i;
e2f0ba97
JB		 1541
1542 /* Read the list of supported input resolutions for the selected TV
1543 * format.
1544 */
40039750 1545 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1546 memcpy(&tv_res, &format_map,
32aad86f 1547 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1548
32aad86f
CW		 1549 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1550 return;
ce6feabd 1551
32aad86f 1552 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1553 if (!intel_sdvo_write_cmd(intel_sdvo,
1554 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1555 &tv_res, sizeof(tv_res)))
1556 return;
1557 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1558 return;
1559
1560 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1561 if (reply & (1 << i)) {
1562 struct drm_display_mode *nmode;
1563 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1564 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1565 if (nmode)
1566 drm_mode_probed_add(connector, nmode);
1567 }
e2f0ba97
JB		 1568}
1569
7086c87f
ML		 1570static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1571{
df0e9248 1572 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1573 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1574 struct drm_display_mode *newmode;
7086c87f
ML		 1575
1576 /*
1577 * Attempt to get the mode list from DDC.
1578 * Assume that the preferred modes are
1579 * arranged in priority order.
1580 */
f899fc64 1581 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1582 if (list_empty(&connector->probed_modes) == false)
12682a97 1583 goto end;
7086c87f
ML		 1584
1585 /* Fetch modes from VBT */
1586 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1587 newmode = drm_mode_duplicate(connector->dev,
1588 dev_priv->sdvo_lvds_vbt_mode);
1589 if (newmode != NULL) {
1590 /* Guarantee the mode is preferred */
1591 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1592 DRM_MODE_TYPE_DRIVER);
1593 drm_mode_probed_add(connector, newmode);
1594 }
1595 }
12682a97 1596
1597end:
1598 list_for_each_entry(newmode, &connector->probed_modes, head) {
1599 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1600 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1601 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1602
8545423a 1603 intel_sdvo->is_lvds = true;
12682a97 1604 break;
1605 }
1606 }
1607
7086c87f
ML		 1608}
1609
e2f0ba97
JB		 1610static int intel_sdvo_get_modes(struct drm_connector *connector)
1611{
615fb93f 1612 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1613
615fb93f 1614 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1615 intel_sdvo_get_tv_modes(connector);
615fb93f 1616 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1617 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1618 else
1619 intel_sdvo_get_ddc_modes(connector);
1620
32aad86f 1621 return !list_empty(&connector->probed_modes);
79e53945
JB		 1622}
1623
fcc8d672
CW		 1624static void
1625intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1626{
615fb93f 1627 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1628 struct drm_device *dev = connector->dev;
1629
c5521706
CW		 1630 if (intel_sdvo_connector->left)
1631 drm_property_destroy(dev, intel_sdvo_connector->left);
1632 if (intel_sdvo_connector->right)
1633 drm_property_destroy(dev, intel_sdvo_connector->right);
1634 if (intel_sdvo_connector->top)
1635 drm_property_destroy(dev, intel_sdvo_connector->top);
1636 if (intel_sdvo_connector->bottom)
1637 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1638 if (intel_sdvo_connector->hpos)
1639 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1640 if (intel_sdvo_connector->vpos)
1641 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1642 if (intel_sdvo_connector->saturation)
1643 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1644 if (intel_sdvo_connector->contrast)
1645 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1646 if (intel_sdvo_connector->hue)
1647 drm_property_destroy(dev, intel_sdvo_connector->hue);
1648 if (intel_sdvo_connector->sharpness)
1649 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1650 if (intel_sdvo_connector->flicker_filter)
1651 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1652 if (intel_sdvo_connector->flicker_filter_2d)
1653 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1654 if (intel_sdvo_connector->flicker_filter_adaptive)
1655 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1656 if (intel_sdvo_connector->tv_luma_filter)
1657 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1658 if (intel_sdvo_connector->tv_chroma_filter)
1659 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1660 if (intel_sdvo_connector->dot_crawl)
1661 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1662 if (intel_sdvo_connector->brightness)
1663 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1664}
1665
79e53945
JB		 1666static void intel_sdvo_destroy(struct drm_connector *connector)
1667{
615fb93f 1668 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1669
c5521706 1670 if (intel_sdvo_connector->tv_format)
ce6feabd 1671 drm_property_destroy(connector->dev,
c5521706 1672 intel_sdvo_connector->tv_format);
b9219c5e 1673
d2a82a6f 1674 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1675 drm_sysfs_connector_remove(connector);
1676 drm_connector_cleanup(connector);
d2a82a6f 1677 kfree(connector);
79e53945
JB		 1678}
1679
1aad7ac0
CW		 1680static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1681{
1682 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1683 struct edid *edid;
1684 bool has_audio = false;
1685
1686 if (!intel_sdvo->is_hdmi)
1687 return false;
1688
1689 edid = intel_sdvo_get_edid(connector);
1690 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1691 has_audio = drm_detect_monitor_audio(edid);
1692
1693 return has_audio;
1694}
1695
ce6feabd
ZY		 1696static int
1697intel_sdvo_set_property(struct drm_connector *connector,
1698 struct drm_property *property,
1699 uint64_t val)
1700{
df0e9248 1701 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1702 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1703 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1704 uint16_t temp_value;
32aad86f
CW		 1705 uint8_t cmd;
1706 int ret;
ce6feabd
ZY		 1707
1708 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1709 if (ret)
1710 return ret;
ce6feabd 1711
3f43c48d 1712 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1713 int i = val;
1714 bool has_audio;
1715
1716 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1717 return 0;
1718
1aad7ac0 1719 intel_sdvo_connector->force_audio = i;
7f36e7ed 1720
c3e5f67b 1721 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1722 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1723 else
c3e5f67b 1724 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1725
1aad7ac0 1726 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1727 return 0;
7f36e7ed 1728
1aad7ac0 1729 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1730 goto done;
1731 }
1732
e953fd7b
CW		 1733 if (property == dev_priv->broadcast_rgb_property) {
1734 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1735 return 0;
1736
e953fd7b 1737 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1738 goto done;
1739 }
1740
c5521706
CW		 1741#define CHECK_PROPERTY(name, NAME) \
1742 if (intel_sdvo_connector->name == property) { \
1743 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1744 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1745 cmd = SDVO_CMD_SET_##NAME; \
1746 intel_sdvo_connector->cur_##name = temp_value; \
1747 goto set_value; \
1748 }
1749
1750 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1751 if (val >= TV_FORMAT_NUM)
1752 return -EINVAL;
1753
40039750 1754 if (intel_sdvo->tv_format_index ==
615fb93f 1755 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1756 return 0;
ce6feabd 1757
40039750 1758 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1759 goto done;
32aad86f 1760 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1761 temp_value = val;
c5521706 1762 if (intel_sdvo_connector->left == property) {
b9219c5e 1763 drm_connector_property_set_value(connector,
c5521706 1764 intel_sdvo_connector->right, val);
615fb93f 1765 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1766 return 0;
b9219c5e 1767
615fb93f
CW		 1768 intel_sdvo_connector->left_margin = temp_value;
1769 intel_sdvo_connector->right_margin = temp_value;
1770 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1771 intel_sdvo_connector->left_margin;
b9219c5e 1772 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1773 goto set_value;
1774 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1775 drm_connector_property_set_value(connector,
c5521706 1776 intel_sdvo_connector->left, val);
615fb93f 1777 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1778 return 0;
b9219c5e 1779
615fb93f
CW		 1780 intel_sdvo_connector->left_margin = temp_value;
1781 intel_sdvo_connector->right_margin = temp_value;
1782 temp_value = intel_sdvo_connector->max_hscan -
1783 intel_sdvo_connector->left_margin;
b9219c5e 1784 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1785 goto set_value;
1786 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1787 drm_connector_property_set_value(connector,
c5521706 1788 intel_sdvo_connector->bottom, val);
615fb93f 1789 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1790 return 0;
b9219c5e 1791
615fb93f
CW		 1792 intel_sdvo_connector->top_margin = temp_value;
1793 intel_sdvo_connector->bottom_margin = temp_value;
1794 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1795 intel_sdvo_connector->top_margin;
b9219c5e 1796 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1797 goto set_value;
1798 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1799 drm_connector_property_set_value(connector,
c5521706 1800 intel_sdvo_connector->top, val);
615fb93f 1801 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1802 return 0;
1803
615fb93f
CW		 1804 intel_sdvo_connector->top_margin = temp_value;
1805 intel_sdvo_connector->bottom_margin = temp_value;
1806 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1807 intel_sdvo_connector->top_margin;
b9219c5e 1808 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1809 goto set_value;
1810 }
1811 CHECK_PROPERTY(hpos, HPOS)
1812 CHECK_PROPERTY(vpos, VPOS)
1813 CHECK_PROPERTY(saturation, SATURATION)
1814 CHECK_PROPERTY(contrast, CONTRAST)
1815 CHECK_PROPERTY(hue, HUE)
1816 CHECK_PROPERTY(brightness, BRIGHTNESS)
1817 CHECK_PROPERTY(sharpness, SHARPNESS)
1818 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1819 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1820 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1821 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1822 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1823 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1824 }
b9219c5e 1825
c5521706 1826 return -EINVAL; /* unknown property */
b9219c5e 1827
c5521706
CW		 1828set_value:
1829 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1830 return -EIO;
b9219c5e 1831
b9219c5e 1832
c5521706 1833done:
df0e9248
CW		 1834 if (intel_sdvo->base.base.crtc) {
1835 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1836 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1837 crtc->y, crtc->fb);
1838 }
1839
32aad86f 1840 return 0;
c5521706 1841#undef CHECK_PROPERTY
ce6feabd
ZY		 1842}
1843
79e53945
JB		 1844static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1845 .dpms = intel_sdvo_dpms,
1846 .mode_fixup = intel_sdvo_mode_fixup,
1847 .prepare = intel_encoder_prepare,
1848 .mode_set = intel_sdvo_mode_set,
1849 .commit = intel_encoder_commit,
1850};
1851
1852static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1853 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1854 .detect = intel_sdvo_detect,
1855 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1856 .set_property = intel_sdvo_set_property,
79e53945
JB		 1857 .destroy = intel_sdvo_destroy,
1858};
1859
1860static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1861 .get_modes = intel_sdvo_get_modes,
1862 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1863 .best_encoder = intel_best_encoder,
79e53945
JB		 1864};
1865
b358d0a6 1866static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1867{
890f3359 1868 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1869
ea5b213a 1870 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1871 drm_mode_destroy(encoder->dev,
ea5b213a 1872 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1873
e957d772 1874 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1875 intel_encoder_destroy(encoder);
79e53945
JB		 1876}
1877
1878static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1879 .destroy = intel_sdvo_enc_destroy,
1880};
1881
b66d8424
CW		 1882static void
1883intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1884{
1885 uint16_t mask = 0;
1886 unsigned int num_bits;
1887
1888 /* Make a mask of outputs less than or equal to our own priority in the
1889 * list.
1890 */
1891 switch (sdvo->controlled_output) {
1892 case SDVO_OUTPUT_LVDS1:
1893 mask |= SDVO_OUTPUT_LVDS1;
1894 case SDVO_OUTPUT_LVDS0:
1895 mask |= SDVO_OUTPUT_LVDS0;
1896 case SDVO_OUTPUT_TMDS1:
1897 mask |= SDVO_OUTPUT_TMDS1;
1898 case SDVO_OUTPUT_TMDS0:
1899 mask |= SDVO_OUTPUT_TMDS0;
1900 case SDVO_OUTPUT_RGB1:
1901 mask |= SDVO_OUTPUT_RGB1;
1902 case SDVO_OUTPUT_RGB0:
1903 mask |= SDVO_OUTPUT_RGB0;
1904 break;
1905 }
1906
1907 /* Count bits to find what number we are in the priority list. */
1908 mask &= sdvo->caps.output_flags;
1909 num_bits = hweight16(mask);
1910 /* If more than 3 outputs, default to DDC bus 3 for now. */
1911 if (num_bits > 3)
1912 num_bits = 3;
1913
1914 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1915 sdvo->ddc_bus = 1 << num_bits;
1916}
79e53945 1917
e2f0ba97
JB		 1918/**
1919 * Choose the appropriate DDC bus for control bus switch command for this
1920 * SDVO output based on the controlled output.
1921 *
1922 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1923 * outputs, then LVDS outputs.
1924 */
1925static void
b1083333 1926intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1927 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1928{
b1083333 1929 struct sdvo_device_mapping *mapping;
e2f0ba97 1930
eef4eacb 1931 if (sdvo->is_sdvob)
b1083333
AJ		 1932 mapping = &(dev_priv->sdvo_mappings[0]);
1933 else
1934 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1935
b66d8424
CW		 1936 if (mapping->initialized)
1937 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1938 else
1939 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1940}
1941
e957d772
CW		 1942static void
1943intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1944 struct intel_sdvo *sdvo, u32 reg)
1945{
1946 struct sdvo_device_mapping *mapping;
46eb3036 1947 u8 pin;
e957d772 1948
eef4eacb 1949 if (sdvo->is_sdvob)
e957d772
CW		 1950 mapping = &dev_priv->sdvo_mappings[0];
1951 else
1952 mapping = &dev_priv->sdvo_mappings[1];
1953
1954 pin = GMBUS_PORT_DPB;
46eb3036 1955 if (mapping->initialized)
e957d772 1956 pin = mapping->i2c_pin;
e957d772 1957
3bd7d909
DK		 1958 if (intel_gmbus_is_port_valid(pin)) {
1959 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
d5090b96 1960 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1961 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1962 } else {
3bd7d909 1963 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
46eb3036 1964 }
e957d772
CW		 1965}
1966
e2f0ba97 1967static bool
e27d8538 1968intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1969{
97aaf910 1970 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1971}
1972
714605e4 1973static u8
eef4eacb 1974intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 1975{
1976 struct drm_i915_private *dev_priv = dev->dev_private;
1977 struct sdvo_device_mapping *my_mapping, *other_mapping;
1978
eef4eacb 1979 if (sdvo->is_sdvob) {
714605e4 1980 my_mapping = &dev_priv->sdvo_mappings[0];
1981 other_mapping = &dev_priv->sdvo_mappings[1];
1982 } else {
1983 my_mapping = &dev_priv->sdvo_mappings[1];
1984 other_mapping = &dev_priv->sdvo_mappings[0];
1985 }
1986
1987 /* If the BIOS described our SDVO device, take advantage of it. */
1988 if (my_mapping->slave_addr)
1989 return my_mapping->slave_addr;
1990
1991 /* If the BIOS only described a different SDVO device, use the
1992 * address that it isn't using.
1993 */
1994 if (other_mapping->slave_addr) {
1995 if (other_mapping->slave_addr == 0x70)
1996 return 0x72;
1997 else
1998 return 0x70;
1999 }
2000
2001 /* No SDVO device info is found for another DVO port,
2002 * so use mapping assumption we had before BIOS parsing.
2003 */
eef4eacb 2004 if (sdvo->is_sdvob)
714605e4 2005 return 0x70;
2006 else
2007 return 0x72;
2008}
2009
14571b4c 2010static void
df0e9248
CW		 2011intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2012 struct intel_sdvo *encoder)
14571b4c 2013{
df0e9248
CW		 2014 drm_connector_init(encoder->base.base.dev,
2015 &connector->base.base,
2016 &intel_sdvo_connector_funcs,
2017 connector->base.base.connector_type);
6070a4a9 2018
df0e9248
CW		 2019 drm_connector_helper_add(&connector->base.base,
2020 &intel_sdvo_connector_helper_funcs);
14571b4c 2021
8f4839e2 2022 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2023 connector->base.base.doublescan_allowed = 0;
2024 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2025
df0e9248
CW		 2026 intel_connector_attach_encoder(&connector->base, &encoder->base);
2027 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2028}
6070a4a9 2029
7f36e7ed
CW		 2030static void
2031intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2032{
2033 struct drm_device *dev = connector->base.base.dev;
2034
3f43c48d 2035 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2036 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2037 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2038}
2039
fb7a46f3 2040static bool
ea5b213a 2041intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2042{
4ef69c7a 2043 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2044 struct drm_connector *connector;
cc68c81a 2045 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2046 struct intel_connector *intel_connector;
615fb93f 2047 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2048
615fb93f
CW		 2049 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2050 if (!intel_sdvo_connector)
14571b4c
ZW		 2051 return false;
2052
14571b4c 2053 if (device == 0) {
ea5b213a 2054 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2055 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2056 } else if (device == 1) {
ea5b213a 2057 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2058 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2059 }
2060
615fb93f 2061 intel_connector = &intel_sdvo_connector->base;
14571b4c 2062 connector = &intel_connector->base;
cc68c81a
SF		 2063 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2064 connector->polled = DRM_CONNECTOR_POLL_HPD;
2065 intel_sdvo->hotplug_active[0] |= 1 << device;
2066 /* Some SDVO devices have one-shot hotplug interrupts.
2067 * Ensure that they get re-enabled when an interrupt happens.
2068 */
2069 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2070 intel_sdvo_enable_hotplug(intel_encoder);
2071 }
2072 else
2073 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2074 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2075 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2076
e27d8538 2077 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2078 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2079 intel_sdvo->is_hdmi = true;
14571b4c 2080 }
ea5b213a
CW		 2081 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2082 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2083
df0e9248 2084 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2085 if (intel_sdvo->is_hdmi)
2086 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2087
2088 return true;
2089}
2090
2091static bool
ea5b213a 2092intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2093{
4ef69c7a
CW		 2094 struct drm_encoder *encoder = &intel_sdvo->base.base;
2095 struct drm_connector *connector;
2096 struct intel_connector *intel_connector;
2097 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2098
615fb93f
CW		 2099 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2100 if (!intel_sdvo_connector)
2101 return false;
14571b4c 2102
615fb93f 2103 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2104 connector = &intel_connector->base;
2105 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2106 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2107
4ef69c7a
CW		 2108 intel_sdvo->controlled_output |= type;
2109 intel_sdvo_connector->output_flag = type;
14571b4c 2110
4ef69c7a
CW		 2111 intel_sdvo->is_tv = true;
2112 intel_sdvo->base.needs_tv_clock = true;
2113 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2114
df0e9248 2115 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2116
4ef69c7a 2117 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2118 goto err;
14571b4c 2119
4ef69c7a 2120 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2121 goto err;
14571b4c 2122
4ef69c7a 2123 return true;
32aad86f
CW		 2124
2125err:
123d5c01 2126 intel_sdvo_destroy(connector);
32aad86f 2127 return false;
14571b4c
ZW		 2128}
2129
2130static bool
ea5b213a 2131intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2132{
4ef69c7a
CW		 2133 struct drm_encoder *encoder = &intel_sdvo->base.base;
2134 struct drm_connector *connector;
2135 struct intel_connector *intel_connector;
2136 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2137
615fb93f
CW		 2138 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2139 if (!intel_sdvo_connector)
2140 return false;
14571b4c 2141
615fb93f 2142 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2143 connector = &intel_connector->base;
eb1f8e4f 2144 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2145 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2146 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2147
2148 if (device == 0) {
2149 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2150 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2151 } else if (device == 1) {
2152 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2153 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2154 }
2155
2156 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2157 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2158
df0e9248
CW		 2159 intel_sdvo_connector_init(intel_sdvo_connector,
2160 intel_sdvo);
4ef69c7a 2161 return true;
14571b4c
ZW		 2162}
2163
2164static bool
ea5b213a 2165intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2166{
4ef69c7a
CW		 2167 struct drm_encoder *encoder = &intel_sdvo->base.base;
2168 struct drm_connector *connector;
2169 struct intel_connector *intel_connector;
2170 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2171
615fb93f
CW		 2172 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2173 if (!intel_sdvo_connector)
2174 return false;
14571b4c 2175
615fb93f
CW		 2176 intel_connector = &intel_sdvo_connector->base;
2177 connector = &intel_connector->base;
4ef69c7a
CW		 2178 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2179 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2180
2181 if (device == 0) {
2182 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2183 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2184 } else if (device == 1) {
2185 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2186 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2187 }
2188
2189 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2190 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2191
df0e9248 2192 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2193 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2194 goto err;
2195
2196 return true;
2197
2198err:
123d5c01 2199 intel_sdvo_destroy(connector);
32aad86f 2200 return false;
14571b4c
ZW		 2201}
2202
2203static bool
ea5b213a 2204intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2205{
ea5b213a
CW		 2206 intel_sdvo->is_tv = false;
2207 intel_sdvo->base.needs_tv_clock = false;
2208 intel_sdvo->is_lvds = false;
fb7a46f3 2209
14571b4c 2210 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2211
14571b4c 2212 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2213 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2214 return false;
2215
2216 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2217 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2218 return false;
2219
2220 /* TV has no XXX1 function block */
a1f4b7ff 2221 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2222 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2223 return false;
2224
2225 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2226 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2227 return false;
fb7a46f3 2228
a0b1c7a5
CW		 2229 if (flags & SDVO_OUTPUT_YPRPB0)
2230 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2231 return false;
2232
14571b4c 2233 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2234 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2235 return false;
2236
2237 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2238 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2239 return false;
2240
2241 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2242 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2243 return false;
2244
2245 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2246 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2247 return false;
fb7a46f3 2248
14571b4c 2249 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2250 unsigned char bytes[2];
2251
ea5b213a
CW		 2252 intel_sdvo->controlled_output = 0;
2253 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2254 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2255 SDVO_NAME(intel_sdvo),
51c8b407 2256 bytes[0], bytes[1]);
14571b4c 2257 return false;
fb7a46f3 2258 }
27f8227b 2259 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2260
14571b4c 2261 return true;
fb7a46f3 2262}
2263
32aad86f
CW		 2264static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2265 struct intel_sdvo_connector *intel_sdvo_connector,
2266 int type)
ce6feabd 2267{
4ef69c7a 2268 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2269 struct intel_sdvo_tv_format format;
2270 uint32_t format_map, i;
ce6feabd 2271
32aad86f
CW		 2272 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2273 return false;
ce6feabd 2274
1a3665c8 2275 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2276 if (!intel_sdvo_get_value(intel_sdvo,
2277 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2278 &format, sizeof(format)))
2279 return false;
ce6feabd 2280
32aad86f 2281 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2282
2283 if (format_map == 0)
32aad86f 2284 return false;
ce6feabd 2285
615fb93f 2286 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2287 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2288 if (format_map & (1 << i))
2289 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2290
2291
c5521706 2292 intel_sdvo_connector->tv_format =
32aad86f
CW		 2293 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2294 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2295 if (!intel_sdvo_connector->tv_format)
fcc8d672 2296 return false;
ce6feabd 2297
615fb93f 2298 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2299 drm_property_add_enum(
c5521706 2300 intel_sdvo_connector->tv_format, i,
40039750 2301 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2302
40039750 2303 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2304 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2305 intel_sdvo_connector->tv_format, 0);
32aad86f 2306 return true;
ce6feabd
ZY		 2307
2308}
2309
c5521706
CW		 2310#define ENHANCEMENT(name, NAME) do { \
2311 if (enhancements.name) { \
2312 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2313 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2314 return false; \
2315 intel_sdvo_connector->max_##name = data_value[0]; \
2316 intel_sdvo_connector->cur_##name = response; \
2317 intel_sdvo_connector->name = \
d9bc3c02 2318 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2319 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2320 drm_connector_attach_property(connector, \
2321 intel_sdvo_connector->name, \
2322 intel_sdvo_connector->cur_##name); \
2323 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2324 data_value[0], data_value[1], response); \
2325 } \
0206e353 2326} while (0)
c5521706
CW		 2327
2328static bool
2329intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2330 struct intel_sdvo_connector *intel_sdvo_connector,
2331 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2332{
4ef69c7a 2333 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2334 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2335 uint16_t response, data_value[2];
2336
c5521706
CW		 2337 /* when horizontal overscan is supported, Add the left/right property */
2338 if (enhancements.overscan_h) {
2339 if (!intel_sdvo_get_value(intel_sdvo,
2340 SDVO_CMD_GET_MAX_OVERSCAN_H,
2341 &data_value, 4))
2342 return false;
32aad86f 2343
c5521706
CW		 2344 if (!intel_sdvo_get_value(intel_sdvo,
2345 SDVO_CMD_GET_OVERSCAN_H,
2346 &response, 2))
2347 return false;
fcc8d672 2348
c5521706
CW		 2349 intel_sdvo_connector->max_hscan = data_value[0];
2350 intel_sdvo_connector->left_margin = data_value[0] - response;
2351 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2352 intel_sdvo_connector->left =
d9bc3c02 2353 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2354 if (!intel_sdvo_connector->left)
2355 return false;
fcc8d672 2356
c5521706
CW		 2357 drm_connector_attach_property(connector,
2358 intel_sdvo_connector->left,
2359 intel_sdvo_connector->left_margin);
fcc8d672 2360
c5521706 2361 intel_sdvo_connector->right =
d9bc3c02 2362 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2363 if (!intel_sdvo_connector->right)
2364 return false;
32aad86f 2365
c5521706
CW		 2366 drm_connector_attach_property(connector,
2367 intel_sdvo_connector->right,
2368 intel_sdvo_connector->right_margin);
2369 DRM_DEBUG_KMS("h_overscan: max %d, "
2370 "default %d, current %d\n",
2371 data_value[0], data_value[1], response);
2372 }
32aad86f 2373
c5521706
CW		 2374 if (enhancements.overscan_v) {
2375 if (!intel_sdvo_get_value(intel_sdvo,
2376 SDVO_CMD_GET_MAX_OVERSCAN_V,
2377 &data_value, 4))
2378 return false;
fcc8d672 2379
c5521706
CW		 2380 if (!intel_sdvo_get_value(intel_sdvo,
2381 SDVO_CMD_GET_OVERSCAN_V,
2382 &response, 2))
2383 return false;
32aad86f 2384
c5521706
CW		 2385 intel_sdvo_connector->max_vscan = data_value[0];
2386 intel_sdvo_connector->top_margin = data_value[0] - response;
2387 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2388 intel_sdvo_connector->top =
d9bc3c02
SH		 2389 drm_property_create_range(dev, 0,
2390 "top_margin", 0, data_value[0]);
c5521706
CW		 2391 if (!intel_sdvo_connector->top)
2392 return false;
32aad86f 2393
c5521706
CW		 2394 drm_connector_attach_property(connector,
2395 intel_sdvo_connector->top,
2396 intel_sdvo_connector->top_margin);
fcc8d672 2397
c5521706 2398 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2399 drm_property_create_range(dev, 0,
2400 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2401 if (!intel_sdvo_connector->bottom)
2402 return false;
32aad86f 2403
c5521706
CW		 2404 drm_connector_attach_property(connector,
2405 intel_sdvo_connector->bottom,
2406 intel_sdvo_connector->bottom_margin);
2407 DRM_DEBUG_KMS("v_overscan: max %d, "
2408 "default %d, current %d\n",
2409 data_value[0], data_value[1], response);
2410 }
32aad86f 2411
c5521706
CW		 2412 ENHANCEMENT(hpos, HPOS);
2413 ENHANCEMENT(vpos, VPOS);
2414 ENHANCEMENT(saturation, SATURATION);
2415 ENHANCEMENT(contrast, CONTRAST);
2416 ENHANCEMENT(hue, HUE);
2417 ENHANCEMENT(sharpness, SHARPNESS);
2418 ENHANCEMENT(brightness, BRIGHTNESS);
2419 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2420 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2421 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2422 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2423 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2424
e044218a
CW		 2425 if (enhancements.dot_crawl) {
2426 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2427 return false;
2428
2429 intel_sdvo_connector->max_dot_crawl = 1;
2430 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2431 intel_sdvo_connector->dot_crawl =
d9bc3c02 2432 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2433 if (!intel_sdvo_connector->dot_crawl)
2434 return false;
2435
e044218a
CW		 2436 drm_connector_attach_property(connector,
2437 intel_sdvo_connector->dot_crawl,
2438 intel_sdvo_connector->cur_dot_crawl);
2439 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2440 }
2441
c5521706
CW		 2442 return true;
2443}
32aad86f 2444
c5521706
CW		 2445static bool
2446intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2447 struct intel_sdvo_connector *intel_sdvo_connector,
2448 struct intel_sdvo_enhancements_reply enhancements)
2449{
4ef69c7a 2450 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2451 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2452 uint16_t response, data_value[2];
32aad86f 2453
c5521706 2454 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2455
c5521706
CW		 2456 return true;
2457}
2458#undef ENHANCEMENT
32aad86f 2459
c5521706
CW		 2460static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2461 struct intel_sdvo_connector *intel_sdvo_connector)
2462{
2463 union {
2464 struct intel_sdvo_enhancements_reply reply;
2465 uint16_t response;
2466 } enhancements;
32aad86f 2467
1a3665c8
CW		 2468 BUILD_BUG_ON(sizeof(enhancements) != 2);
2469
cf9a2f3a
CW		 2470 enhancements.response = 0;
2471 intel_sdvo_get_value(intel_sdvo,
2472 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2473 &enhancements, sizeof(enhancements));
c5521706
CW		 2474 if (enhancements.response == 0) {
2475 DRM_DEBUG_KMS("No enhancement is supported\n");
2476 return true;
b9219c5e 2477 }
32aad86f 2478
c5521706
CW		 2479 if (IS_TV(intel_sdvo_connector))
2480 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2481 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2482 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2483 else
2484 return true;
e957d772
CW		 2485}
2486
2487static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2488 struct i2c_msg *msgs,
2489 int num)
2490{
2491 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2492
e957d772
CW		 2493 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2494 return -EIO;
2495
2496 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2497}
2498
2499static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2500{
2501 struct intel_sdvo *sdvo = adapter->algo_data;
2502 return sdvo->i2c->algo->functionality(sdvo->i2c);
2503}
2504
2505static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2506 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2507 .functionality = intel_sdvo_ddc_proxy_func
2508};
2509
2510static bool
2511intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2512 struct drm_device *dev)
2513{
2514 sdvo->ddc.owner = THIS_MODULE;
2515 sdvo->ddc.class = I2C_CLASS_DDC;
2516 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2517 sdvo->ddc.dev.parent = &dev->pdev->dev;
2518 sdvo->ddc.algo_data = sdvo;
2519 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2520
2521 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2522}
2523
eef4eacb 2524bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2525{
b01f2c3a 2526 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2527 struct intel_encoder *intel_encoder;
ea5b213a 2528 struct intel_sdvo *intel_sdvo;
084b612e 2529 u32 hotplug_mask;
79e53945 2530 int i;
79e53945 2531
ea5b213a
CW		 2532 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2533 if (!intel_sdvo)
7d57382e 2534 return false;
79e53945 2535
56184e3d 2536 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2537 intel_sdvo->is_sdvob = is_sdvob;
2538 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2539 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2540 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2541 kfree(intel_sdvo);
2542 return false;
2543 }
2544
56184e3d 2545 /* encoder type will be decided later */
ea5b213a 2546 intel_encoder = &intel_sdvo->base;
21d40d37 2547 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2548 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2549
79e53945
JB		 2550 /* Read the regs to test if we can talk to the device */
2551 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2552 u8 byte;
2553
2554 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2555 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2556 SDVO_NAME(intel_sdvo));
f899fc64 2557 goto err;
79e53945
JB		 2558 }
2559 }
2560
084b612e
CW		 2561 hotplug_mask = 0;
2562 if (IS_G4X(dev)) {
2563 hotplug_mask = intel_sdvo->is_sdvob ?
2564 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2565 } else if (IS_GEN4(dev)) {
2566 hotplug_mask = intel_sdvo->is_sdvob ?
2567 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2568 } else {
2569 hotplug_mask = intel_sdvo->is_sdvob ?
2570 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2571 }
2572 dev_priv->hotplug_supported_mask |= hotplug_mask;
619ac3b7 2573
4ef69c7a 2574 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2575
af901ca1 2576 /* In default case sdvo lvds is false */
32aad86f 2577 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2578 goto err;
79e53945 2579
cc68c81a
SF		 2580 /* Set up hotplug command - note paranoia about contents of reply.
2581 * We assume that the hardware is in a sane state, and only touch
2582 * the bits we think we understand.
2583 */
2584 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2585 &intel_sdvo->hotplug_active, 2);
2586 intel_sdvo->hotplug_active[0] &= ~0x3;
2587
ea5b213a
CW		 2588 if (intel_sdvo_output_setup(intel_sdvo,
2589 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2590 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2591 SDVO_NAME(intel_sdvo));
f899fc64 2592 goto err;
79e53945
JB		 2593 }
2594
ea5b213a 2595 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2596
79e53945 2597 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2598 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2599 goto err;
79e53945 2600
32aad86f
CW		 2601 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2602 &intel_sdvo->pixel_clock_min,
2603 &intel_sdvo->pixel_clock_max))
f899fc64 2604 goto err;
79e53945 2605
8a4c47f3 2606 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2607 "clock range %dMHz - %dMHz, "
2608 "input 1: %c, input 2: %c, "
2609 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2610 SDVO_NAME(intel_sdvo),
2611 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2612 intel_sdvo->caps.device_rev_id,
2613 intel_sdvo->pixel_clock_min / 1000,
2614 intel_sdvo->pixel_clock_max / 1000,
2615 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2616 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2617 /* check currently supported outputs */
ea5b213a 2618 intel_sdvo->caps.output_flags &
79e53945 2619 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2620 intel_sdvo->caps.output_flags &
79e53945 2621 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2622 return true;
79e53945 2623
f899fc64 2624err:
373a3cf7 2625 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2626 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2627 kfree(intel_sdvo);
79e53945 2628
7d57382e 2629 return false;
79e53945 2630}
Linux kernel - Deliverables
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