projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: only enable sdvo hotplug irq if needed
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
2e88e40b 56static const char *tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 77 uint32_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
100 uint8_t hotplug_active[2];
101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
12682a97 129
7086c87f 130 /**
6c9547ff
CW		 131 * This is set if we detect output of sdvo device as LVDS and
132 * have a valid fixed mode to use with the panel.
7086c87f
ML		 133 */
134 bool is_lvds;
e2f0ba97 135
12682a97 136 /**
137 * This is sdvo fixed pannel mode pointer
138 */
139 struct drm_display_mode *sdvo_lvds_fixed_mode;
140
c751ce4f 141 /* DDC bus used by this SDVO encoder */
e2f0ba97 142 uint8_t ddc_bus;
14571b4c
ZW		 143};
144
145struct intel_sdvo_connector {
615fb93f
CW		 146 struct intel_connector base;
147
14571b4c
ZW		 148 /* Mark the type of connector */
149 uint16_t output_flag;
150
c3e5f67b 151 enum hdmi_force_audio force_audio;
7f36e7ed 152
14571b4c 153 /* This contains all current supported TV format */
40039750 154 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 155 int format_supported_num;
c5521706 156 struct drm_property *tv_format;
14571b4c 157
b9219c5e 158 /* add the property for the SDVO-TV */
c5521706
CW		 159 struct drm_property *left;
160 struct drm_property *right;
161 struct drm_property *top;
162 struct drm_property *bottom;
163 struct drm_property *hpos;
164 struct drm_property *vpos;
165 struct drm_property *contrast;
166 struct drm_property *saturation;
167 struct drm_property *hue;
168 struct drm_property *sharpness;
169 struct drm_property *flicker_filter;
170 struct drm_property *flicker_filter_adaptive;
171 struct drm_property *flicker_filter_2d;
172 struct drm_property *tv_chroma_filter;
173 struct drm_property *tv_luma_filter;
e044218a 174 struct drm_property *dot_crawl;
b9219c5e
ZY		 175
176 /* add the property for the SDVO-TV/LVDS */
c5521706 177 struct drm_property *brightness;
b9219c5e
ZY		 178
179 /* Add variable to record current setting for the above property */
180 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 181
b9219c5e
ZY		 182 /* this is to get the range of margin.*/
183 u32 max_hscan, max_vscan;
184 u32 max_hpos, cur_hpos;
185 u32 max_vpos, cur_vpos;
186 u32 cur_brightness, max_brightness;
187 u32 cur_contrast, max_contrast;
188 u32 cur_saturation, max_saturation;
189 u32 cur_hue, max_hue;
c5521706
CW		 190 u32 cur_sharpness, max_sharpness;
191 u32 cur_flicker_filter, max_flicker_filter;
192 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
193 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
194 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
195 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 196 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 197};
198
890f3359 199static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 200{
4ef69c7a 201 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 202}
203
df0e9248
CW		 204static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
205{
206 return container_of(intel_attached_encoder(connector),
207 struct intel_sdvo, base);
208}
209
615fb93f
CW		 210static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
211{
212 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
213}
214
fb7a46f3 215static bool
ea5b213a 216intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 217static bool
218intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
219 struct intel_sdvo_connector *intel_sdvo_connector,
220 int type);
221static bool
222intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
223 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 224
79e53945
JB		 225/**
226 * Writes the SDVOB or SDVOC with the given value, but always writes both
227 * SDVOB and SDVOC to work around apparent hardware issues (according to
228 * comments in the BIOS).
229 */
ea5b213a 230static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 231{
4ef69c7a 232 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 233 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 234 u32 bval = val, cval = val;
235 int i;
236
ea5b213a
CW		 237 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
238 I915_WRITE(intel_sdvo->sdvo_reg, val);
239 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 240 return;
241 }
242
ea5b213a 243 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 244 cval = I915_READ(SDVOC);
245 } else {
246 bval = I915_READ(SDVOB);
247 }
248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
253 for (i = 0; i < 2; i++)
254 {
255 I915_WRITE(SDVOB, bval);
256 I915_READ(SDVOB);
257 I915_WRITE(SDVOC, cval);
258 I915_READ(SDVOC);
259 }
260}
261
32aad86f 262static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 263{
79e53945
JB		 264 struct i2c_msg msgs[] = {
265 {
e957d772 266 .addr = intel_sdvo->slave_addr,
79e53945
JB		 267 .flags = 0,
268 .len = 1,
e957d772 269 .buf = &addr,
79e53945
JB		 270 },
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = I2C_M_RD,
274 .len = 1,
e957d772 275 .buf = ch,
79e53945
JB		 276 }
277 };
32aad86f 278 int ret;
79e53945 279
f899fc64 280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 281 return true;
79e53945 282
8a4c47f3 283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 284 return false;
285}
286
79e53945
JB		 287#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288/** Mapping of command numbers to names, for debug output */
005568be 289static const struct _sdvo_cmd_name {
e2f0ba97 290 u8 cmd;
2e88e40b 291 const char *name;
79e53945 292} sdvo_cmd_names[] = {
0206e353
AJ		 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 404};
405
eef4eacb 406#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 407
ea5b213a 408static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 409 const void *args, int args_len)
79e53945 410{
79e53945
JB		 411 int i;
412
8a4c47f3 413 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 414 SDVO_NAME(intel_sdvo), cmd);
79e53945 415 for (i = 0; i < args_len; i++)
342dc382 416 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 417 for (; i < 8; i++)
342dc382 418 DRM_LOG_KMS(" ");
04ad327f 419 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 420 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 421 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 422 break;
423 }
424 }
04ad327f 425 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 426 DRM_LOG_KMS("(%02X)", cmd);
427 DRM_LOG_KMS("\n");
79e53945 428}
79e53945 429
e957d772
CW		 430static const char *cmd_status_names[] = {
431 "Power on",
432 "Success",
433 "Not supported",
434 "Invalid arg",
435 "Pending",
436 "Target not specified",
437 "Scaling not supported"
438};
439
32aad86f
CW		 440static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
441 const void *args, int args_len)
79e53945 442{
3bf3f452
BW		 443 u8 *buf, status;
444 struct i2c_msg *msgs;
445 int i, ret = true;
446
0274df3e 447 /* Would be simpler to allocate both in one go ? */
3bf3f452
BW		 448 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
449 if (!buf)
450 return false;
451
452 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 453 if (!msgs) {
454 kfree(buf);
3bf3f452 455 return false;
0274df3e 456 }
79e53945 457
ea5b213a 458 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 459
460 for (i = 0; i < args_len; i++) {
e957d772
CW		 461 msgs[i].addr = intel_sdvo->slave_addr;
462 msgs[i].flags = 0;
463 msgs[i].len = 2;
464 msgs[i].buf = buf + 2 *i;
465 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
466 buf[2*i + 1] = ((u8*)args)[i];
467 }
468 msgs[i].addr = intel_sdvo->slave_addr;
469 msgs[i].flags = 0;
470 msgs[i].len = 2;
471 msgs[i].buf = buf + 2*i;
472 buf[2*i + 0] = SDVO_I2C_OPCODE;
473 buf[2*i + 1] = cmd;
474
475 /* the following two are to read the response */
476 status = SDVO_I2C_CMD_STATUS;
477 msgs[i+1].addr = intel_sdvo->slave_addr;
478 msgs[i+1].flags = 0;
479 msgs[i+1].len = 1;
480 msgs[i+1].buf = &status;
481
482 msgs[i+2].addr = intel_sdvo->slave_addr;
483 msgs[i+2].flags = I2C_M_RD;
484 msgs[i+2].len = 1;
485 msgs[i+2].buf = &status;
486
487 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
488 if (ret < 0) {
489 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 490 ret = false;
491 goto out;
e957d772
CW		 492 }
493 if (ret != i+3) {
494 /* failure in I2C transfer */
495 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 496 ret = false;
e957d772
CW		 497 }
498
3bf3f452
BW		 499out:
500 kfree(msgs);
501 kfree(buf);
502 return ret;
79e53945
JB		 503}
504
b5c616a7
CW		 505static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
506 void *response, int response_len)
79e53945 507{
b5c616a7
CW		 508 u8 retry = 5;
509 u8 status;
33b52961 510 int i;
79e53945 511
d121a5d2
CW		 512 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
513
b5c616a7
CW		 514 /*
515 * The documentation states that all commands will be
516 * processed within 15µs, and that we need only poll
517 * the status byte a maximum of 3 times in order for the
518 * command to be complete.
519 *
520 * Check 5 times in case the hardware failed to read the docs.
521 */
d121a5d2
CW		 522 if (!intel_sdvo_read_byte(intel_sdvo,
523 SDVO_I2C_CMD_STATUS,
524 &status))
525 goto log_fail;
526
527 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
528 udelay(15);
b5c616a7
CW		 529 if (!intel_sdvo_read_byte(intel_sdvo,
530 SDVO_I2C_CMD_STATUS,
531 &status))
d121a5d2
CW		 532 goto log_fail;
533 }
b5c616a7 534
79e53945 535 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 536 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 537 else
342dc382 538 DRM_LOG_KMS("(??? %d)", status);
79e53945 539
b5c616a7
CW		 540 if (status != SDVO_CMD_STATUS_SUCCESS)
541 goto log_fail;
79e53945 542
b5c616a7
CW		 543 /* Read the command response */
544 for (i = 0; i < response_len; i++) {
545 if (!intel_sdvo_read_byte(intel_sdvo,
546 SDVO_I2C_RETURN_0 + i,
547 &((u8 *)response)[i]))
548 goto log_fail;
e957d772 549 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 550 }
b5c616a7 551 DRM_LOG_KMS("\n");
b5c616a7 552 return true;
79e53945 553
b5c616a7 554log_fail:
d121a5d2 555 DRM_LOG_KMS("... failed\n");
b5c616a7 556 return false;
79e53945
JB		 557}
558
b358d0a6 559static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 560{
561 if (mode->clock >= 100000)
562 return 1;
563 else if (mode->clock >= 50000)
564 return 2;
565 else
566 return 4;
567}
568
e957d772
CW		 569static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
570 u8 ddc_bus)
79e53945 571{
d121a5d2 572 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 573 return intel_sdvo_write_cmd(intel_sdvo,
574 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
575 &ddc_bus, 1);
79e53945
JB		 576}
577
32aad86f 578static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 579{
d121a5d2
CW		 580 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
581 return false;
582
583 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 584}
79e53945 585
32aad86f
CW		 586static bool
587intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
588{
589 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
590 return false;
79e53945 591
32aad86f
CW		 592 return intel_sdvo_read_response(intel_sdvo, value, len);
593}
79e53945 594
32aad86f
CW		 595static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
596{
597 struct intel_sdvo_set_target_input_args targets = {0};
598 return intel_sdvo_set_value(intel_sdvo,
599 SDVO_CMD_SET_TARGET_INPUT,
600 &targets, sizeof(targets));
79e53945
JB		 601}
602
603/**
604 * Return whether each input is trained.
605 *
606 * This function is making an assumption about the layout of the response,
607 * which should be checked against the docs.
608 */
ea5b213a 609static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 610{
611 struct intel_sdvo_get_trained_inputs_response response;
79e53945 612
1a3665c8 613 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 614 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
615 &response, sizeof(response)))
79e53945
JB		 616 return false;
617
618 *input_1 = response.input0_trained;
619 *input_2 = response.input1_trained;
620 return true;
621}
622
ea5b213a 623static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 624 u16 outputs)
625{
32aad86f
CW		 626 return intel_sdvo_set_value(intel_sdvo,
627 SDVO_CMD_SET_ACTIVE_OUTPUTS,
628 &outputs, sizeof(outputs));
79e53945
JB		 629}
630
ea5b213a 631static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 632 int mode)
633{
32aad86f 634 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 635
636 switch (mode) {
637 case DRM_MODE_DPMS_ON:
638 state = SDVO_ENCODER_STATE_ON;
639 break;
640 case DRM_MODE_DPMS_STANDBY:
641 state = SDVO_ENCODER_STATE_STANDBY;
642 break;
643 case DRM_MODE_DPMS_SUSPEND:
644 state = SDVO_ENCODER_STATE_SUSPEND;
645 break;
646 case DRM_MODE_DPMS_OFF:
647 state = SDVO_ENCODER_STATE_OFF;
648 break;
649 }
650
32aad86f
CW		 651 return intel_sdvo_set_value(intel_sdvo,
652 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 653}
654
ea5b213a 655static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 656 int *clock_min,
657 int *clock_max)
658{
659 struct intel_sdvo_pixel_clock_range clocks;
79e53945 660
1a3665c8 661 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 662 if (!intel_sdvo_get_value(intel_sdvo,
663 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
664 &clocks, sizeof(clocks)))
79e53945
JB		 665 return false;
666
667 /* Convert the values from units of 10 kHz to kHz. */
668 *clock_min = clocks.min * 10;
669 *clock_max = clocks.max * 10;
79e53945
JB		 670 return true;
671}
672
ea5b213a 673static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 674 u16 outputs)
675{
32aad86f
CW		 676 return intel_sdvo_set_value(intel_sdvo,
677 SDVO_CMD_SET_TARGET_OUTPUT,
678 &outputs, sizeof(outputs));
79e53945
JB		 679}
680
ea5b213a 681static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 682 struct intel_sdvo_dtd *dtd)
683{
32aad86f
CW		 684 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
685 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 686}
687
ea5b213a 688static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 689 struct intel_sdvo_dtd *dtd)
690{
ea5b213a 691 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 692 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
693}
694
ea5b213a 695static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 696 struct intel_sdvo_dtd *dtd)
697{
ea5b213a 698 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 699 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
700}
701
e2f0ba97 702static bool
ea5b213a 703intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 704 uint16_t clock,
705 uint16_t width,
706 uint16_t height)
707{
708 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 709
e642c6f1 710 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 711 args.clock = clock;
712 args.width = width;
713 args.height = height;
e642c6f1 714 args.interlace = 0;
12682a97 715
ea5b213a
CW		 716 if (intel_sdvo->is_lvds &&
717 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
718 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 719 args.scaled = 1;
720
32aad86f
CW		 721 return intel_sdvo_set_value(intel_sdvo,
722 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
723 &args, sizeof(args));
e2f0ba97
JB		 724}
725
ea5b213a 726static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 727 struct intel_sdvo_dtd *dtd)
728{
1a3665c8
CW		 729 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
730 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 731 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
732 &dtd->part1, sizeof(dtd->part1)) &&
733 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
734 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 735}
79e53945 736
ea5b213a 737static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 738{
32aad86f 739 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 740}
741
e2f0ba97 742static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 743 const struct drm_display_mode *mode)
79e53945 744{
e2f0ba97
JB		 745 uint16_t width, height;
746 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
747 uint16_t h_sync_offset, v_sync_offset;
6651819b 748 int mode_clock;
79e53945 749
c6ebd4c0
DV		 750 width = mode->hdisplay;
751 height = mode->vdisplay;
79e53945
JB		 752
753 /* do some mode translations */
c6ebd4c0
DV		 754 h_blank_len = mode->htotal - mode->hdisplay;
755 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 756
c6ebd4c0
DV		 757 v_blank_len = mode->vtotal - mode->vdisplay;
758 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 759
c6ebd4c0
DV		 760 h_sync_offset = mode->hsync_start - mode->hdisplay;
761 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 762
6651819b
DV		 763 mode_clock = mode->clock;
764 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
765 mode_clock /= 10;
766 dtd->part1.clock = mode_clock;
767
e2f0ba97
JB		 768 dtd->part1.h_active = width & 0xff;
769 dtd->part1.h_blank = h_blank_len & 0xff;
770 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 771 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 772 dtd->part1.v_active = height & 0xff;
773 dtd->part1.v_blank = v_blank_len & 0xff;
774 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 775 ((v_blank_len >> 8) & 0xf);
776
171a9e96 777 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 778 dtd->part2.h_sync_width = h_sync_len & 0xff;
779 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 780 (v_sync_len & 0xf);
e2f0ba97 781 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 782 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
783 ((v_sync_len & 0x30) >> 4);
784
e2f0ba97 785 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 786 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
787 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 788 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 789 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 790 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 791 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 792
793 dtd->part2.sdvo_flags = 0;
794 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
795 dtd->part2.reserved = 0;
796}
797
798static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 799 const struct intel_sdvo_dtd *dtd)
e2f0ba97 800{
e2f0ba97
JB		 801 mode->hdisplay = dtd->part1.h_active;
802 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
803 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 804 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 805 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
806 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
807 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
808 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
809
810 mode->vdisplay = dtd->part1.v_active;
811 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
812 mode->vsync_start = mode->vdisplay;
813 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 814 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 815 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
816 mode->vsync_end = mode->vsync_start +
817 (dtd->part2.v_sync_off_width & 0xf);
818 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
819 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
820 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
821
822 mode->clock = dtd->part1.clock * 10;
823
171a9e96 824 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 825 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
826 mode->flags |= DRM_MODE_FLAG_INTERLACE;
827 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 828 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 829 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 830 mode->flags |= DRM_MODE_FLAG_PVSYNC;
831}
832
e27d8538 833static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 834{
e27d8538 835 struct intel_sdvo_encode encode;
e2f0ba97 836
1a3665c8 837 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 838 return intel_sdvo_get_value(intel_sdvo,
839 SDVO_CMD_GET_SUPP_ENCODE,
840 &encode, sizeof(encode));
e2f0ba97
JB		 841}
842
ea5b213a 843static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 844 uint8_t mode)
e2f0ba97 845{
32aad86f 846 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 847}
848
ea5b213a 849static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 850 uint8_t mode)
851{
32aad86f 852 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 853}
854
855#if 0
ea5b213a 856static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 857{
858 int i, j;
859 uint8_t set_buf_index[2];
860 uint8_t av_split;
861 uint8_t buf_size;
862 uint8_t buf[48];
863 uint8_t *pos;
864
32aad86f 865 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 866
867 for (i = 0; i <= av_split; i++) {
868 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 869 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 870 set_buf_index, 2);
c751ce4f
EA		 871 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
872 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 873
874 pos = buf;
875 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 876 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 877 NULL, 0);
c751ce4f 878 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 879 pos += 8;
880 }
881 }
882}
883#endif
884
3c17fe4b 885static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 886{
887 struct dip_infoframe avi_if = {
888 .type = DIP_TYPE_AVI,
3c17fe4b 889 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 890 .len = DIP_LEN_AVI,
891 };
3c17fe4b
DH		 892 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
893 uint8_t set_buf_index[2] = { 1, 0 };
81014b9d
DV		 894 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
895 uint64_t *data = (uint64_t *)sdvo_data;
3c17fe4b
DH		 896 unsigned i;
897
898 intel_dip_infoframe_csum(&avi_if);
899
81014b9d
DV		 900 /* sdvo spec says that the ecc is handled by the hw, and it looks like
901 * we must not send the ecc field, either. */
902 memcpy(sdvo_data, &avi_if, 3);
903 sdvo_data[3] = avi_if.checksum;
904 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
905
d121a5d2
CW		 906 if (!intel_sdvo_set_value(intel_sdvo,
907 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 908 set_buf_index, 2))
909 return false;
910
81014b9d 911 for (i = 0; i < sizeof(sdvo_data); i += 8) {
d121a5d2
CW		 912 if (!intel_sdvo_set_value(intel_sdvo,
913 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 914 data, 8))
915 return false;
916 data++;
917 }
e2f0ba97 918
d121a5d2
CW		 919 return intel_sdvo_set_value(intel_sdvo,
920 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 921 &tx_rate, 1);
e2f0ba97
JB		 922}
923
32aad86f 924static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 925{
ce6feabd 926 struct intel_sdvo_tv_format format;
40039750 927 uint32_t format_map;
ce6feabd 928
40039750 929 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 930 memset(&format, 0, sizeof(format));
32aad86f 931 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 932
32aad86f
CW		 933 BUILD_BUG_ON(sizeof(format) != 6);
934 return intel_sdvo_set_value(intel_sdvo,
935 SDVO_CMD_SET_TV_FORMAT,
936 &format, sizeof(format));
7026d4ac
ZW		 937}
938
32aad86f
CW		 939static bool
940intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 941 const struct drm_display_mode *mode)
e2f0ba97 942{
32aad86f 943 struct intel_sdvo_dtd output_dtd;
79e53945 944
32aad86f
CW		 945 if (!intel_sdvo_set_target_output(intel_sdvo,
946 intel_sdvo->attached_output))
947 return false;
e2f0ba97 948
32aad86f
CW		 949 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
950 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
951 return false;
e2f0ba97 952
32aad86f
CW		 953 return true;
954}
955
c9a29698
DV		 956/* Asks the sdvo controller for the preferred input mode given the output mode.
957 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 958static bool
c9a29698 959intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 960 const struct drm_display_mode *mode,
c9a29698 961 struct drm_display_mode *adjusted_mode)
32aad86f 962{
c9a29698
DV		 963 struct intel_sdvo_dtd input_dtd;
964
32aad86f
CW		 965 /* Reset the input timing to the screen. Assume always input 0. */
966 if (!intel_sdvo_set_target_input(intel_sdvo))
967 return false;
e2f0ba97 968
32aad86f
CW		 969 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
970 mode->clock / 10,
971 mode->hdisplay,
972 mode->vdisplay))
973 return false;
e2f0ba97 974
32aad86f 975 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 976 &input_dtd))
32aad86f 977 return false;
e2f0ba97 978
c9a29698 979 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
79e53945 980
32aad86f
CW		 981 return true;
982}
12682a97 983
32aad86f 984static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
e811f5ae 985 const struct drm_display_mode *mode,
32aad86f
CW		 986 struct drm_display_mode *adjusted_mode)
987{
890f3359 988 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 989 int multiplier;
12682a97 990
32aad86f
CW		 991 /* We need to construct preferred input timings based on our
992 * output timings. To do that, we have to set the output
993 * timings, even though this isn't really the right place in
994 * the sequence to do it. Oh well.
995 */
996 if (intel_sdvo->is_tv) {
997 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
998 return false;
12682a97 999
c9a29698
DV		 1000 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1001 mode,
1002 adjusted_mode);
ea5b213a 1003 } else if (intel_sdvo->is_lvds) {
32aad86f 1004 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1005 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1006 return false;
12682a97 1007
c9a29698
DV		 1008 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1009 mode,
1010 adjusted_mode);
e2f0ba97 1011 }
32aad86f
CW		 1012
1013 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1014 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1015 */
6c9547ff
CW		 1016 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1017 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1018
e2f0ba97
JB		 1019 return true;
1020}
1021
1022static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1023 struct drm_display_mode *mode,
1024 struct drm_display_mode *adjusted_mode)
1025{
1026 struct drm_device *dev = encoder->dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_crtc *crtc = encoder->crtc;
1029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1030 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1031 u32 sdvox;
e2f0ba97 1032 struct intel_sdvo_in_out_map in_out;
6651819b 1033 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1034 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1035 int rate;
e2f0ba97
JB		 1036
1037 if (!mode)
1038 return;
1039
1040 /* First, set the input mapping for the first input to our controlled
1041 * output. This is only correct if we're a single-input device, in
1042 * which case the first input is the output from the appropriate SDVO
1043 * channel on the motherboard. In a two-input device, the first input
1044 * will be SDVOB and the second SDVOC.
1045 */
ea5b213a 1046 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1047 in_out.in1 = 0;
1048
c74696b9
PR		 1049 intel_sdvo_set_value(intel_sdvo,
1050 SDVO_CMD_SET_IN_OUT_MAP,
1051 &in_out, sizeof(in_out));
e2f0ba97 1052
6c9547ff
CW		 1053 /* Set the output timings to the screen */
1054 if (!intel_sdvo_set_target_output(intel_sdvo,
1055 intel_sdvo->attached_output))
1056 return;
e2f0ba97 1057
6651819b
DV		 1058 /* lvds has a special fixed output timing. */
1059 if (intel_sdvo->is_lvds)
1060 intel_sdvo_get_dtd_from_mode(&output_dtd,
1061 intel_sdvo->sdvo_lvds_fixed_mode);
1062 else
1063 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1064 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1065 DRM_INFO("Setting output timings on %s failed\n",
1066 SDVO_NAME(intel_sdvo));
79e53945
JB		 1067
1068 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1069 if (!intel_sdvo_set_target_input(intel_sdvo))
1070 return;
79e53945 1071
97aaf910
CW		 1072 if (intel_sdvo->has_hdmi_monitor) {
1073 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1074 intel_sdvo_set_colorimetry(intel_sdvo,
1075 SDVO_COLORIMETRY_RGB256);
1076 intel_sdvo_set_avi_infoframe(intel_sdvo);
1077 } else
1078 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1079
6c9547ff
CW		 1080 if (intel_sdvo->is_tv &&
1081 !intel_sdvo_set_tv_format(intel_sdvo))
1082 return;
e2f0ba97 1083
6651819b
DV		 1084 /* We have tried to get input timing in mode_fixup, and filled into
1085 * adjusted_mode.
1086 */
1087 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c8d4bb54
DV		 1088 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1089 DRM_INFO("Setting input timings on %s failed\n",
1090 SDVO_NAME(intel_sdvo));
79e53945 1091
6c9547ff
CW		 1092 switch (pixel_multiplier) {
1093 default:
32aad86f
CW		 1094 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1095 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1096 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1097 }
32aad86f
CW		 1098 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1099 return;
79e53945
JB		 1100
1101 /* Set the SDVO control regs. */
a6c45cf0 1102 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1103 /* The real mode polarity is set by the SDVO commands, using
1104 * struct intel_sdvo_dtd. */
1105 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1106 if (intel_sdvo->is_hdmi)
1107 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1108 if (INTEL_INFO(dev)->gen < 5)
1109 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1110 } else {
6c9547ff 1111 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1112 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1113 case SDVOB:
1114 sdvox &= SDVOB_PRESERVE_MASK;
1115 break;
1116 case SDVOC:
1117 sdvox &= SDVOC_PRESERVE_MASK;
1118 break;
1119 }
1120 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1121 }
3573c410
PZ		 1122
1123 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1124 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1125 else
1126 sdvox |= TRANSCODER(intel_crtc->pipe);
1127
da79de97 1128 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1129 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1130
a6c45cf0 1131 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1132 /* done in crtc_mode_set as the dpll_md reg must be written early */
1133 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1134 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1135 } else {
6c9547ff 1136 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1137 }
1138
6714afb1
CW		 1139 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1140 INTEL_INFO(dev)->gen < 5)
12682a97 1141 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1142 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1143}
1144
1145static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1146{
1147 struct drm_device *dev = encoder->dev;
1148 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1149 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1150 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1151 u32 temp;
1152
1153 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1154 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1155 if (0)
ea5b213a 1156 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1157
1158 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1159 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1160 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1161 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1162 }
1163 }
1164 } else {
1165 bool input1, input2;
1166 int i;
1167 u8 status;
1168
ea5b213a 1169 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1170 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1171 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1172 for (i = 0; i < 2; i++)
9d0498a2 1173 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1174
32aad86f 1175 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1176 /* Warn if the device reported failure to sync.
1177 * A lot of SDVO devices fail to notify of sync, but it's
1178 * a given it the status is a success, we succeeded.
1179 */
1180 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1181 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1182 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1183 }
1184
1185 if (0)
ea5b213a
CW		 1186 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1187 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1188 }
1189 return;
1190}
1191
79e53945
JB		 1192static int intel_sdvo_mode_valid(struct drm_connector *connector,
1193 struct drm_display_mode *mode)
1194{
df0e9248 1195 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1196
1197 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1198 return MODE_NO_DBLESCAN;
1199
ea5b213a 1200 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1201 return MODE_CLOCK_LOW;
1202
ea5b213a 1203 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1204 return MODE_CLOCK_HIGH;
1205
8545423a 1206 if (intel_sdvo->is_lvds) {
ea5b213a 1207 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1208 return MODE_PANEL;
1209
ea5b213a 1210 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1211 return MODE_PANEL;
1212 }
1213
79e53945
JB		 1214 return MODE_OK;
1215}
1216
ea5b213a 1217static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1218{
1a3665c8 1219 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1220 if (!intel_sdvo_get_value(intel_sdvo,
1221 SDVO_CMD_GET_DEVICE_CAPS,
1222 caps, sizeof(*caps)))
1223 return false;
1224
1225 DRM_DEBUG_KMS("SDVO capabilities:\n"
1226 " vendor_id: %d\n"
1227 " device_id: %d\n"
1228 " device_rev_id: %d\n"
1229 " sdvo_version_major: %d\n"
1230 " sdvo_version_minor: %d\n"
1231 " sdvo_inputs_mask: %d\n"
1232 " smooth_scaling: %d\n"
1233 " sharp_scaling: %d\n"
1234 " up_scaling: %d\n"
1235 " down_scaling: %d\n"
1236 " stall_support: %d\n"
1237 " output_flags: %d\n",
1238 caps->vendor_id,
1239 caps->device_id,
1240 caps->device_rev_id,
1241 caps->sdvo_version_major,
1242 caps->sdvo_version_minor,
1243 caps->sdvo_inputs_mask,
1244 caps->smooth_scaling,
1245 caps->sharp_scaling,
1246 caps->up_scaling,
1247 caps->down_scaling,
1248 caps->stall_support,
1249 caps->output_flags);
1250
1251 return true;
79e53945
JB		 1252}
1253
cc68c81a 1254static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945 1255{
768b107e 1256 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 1257 u8 response[2];
79e53945 1258
768b107e
DV		 1259 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1260 * on the line. */
1261 if (IS_I945G(dev) || IS_I945GM(dev))
1262 return false;
1263
32aad86f
CW		 1264 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1265 &response, 2) && response[0];
79e53945
JB		 1266}
1267
cc68c81a 1268static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1269{
cc68c81a 1270 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1271
cc68c81a 1272 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1273}
1274
fb7a46f3 1275static bool
ea5b213a 1276intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1277{
bc65212c 1278 /* Is there more than one type of output? */
2294488d 1279 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1280}
1281
f899fc64 1282static struct edid *
e957d772 1283intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1284{
e957d772
CW		 1285 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1286 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1287}
1288
ff482d83
CW		 1289/* Mac mini hack -- use the same DDC as the analog connector */
1290static struct edid *
1291intel_sdvo_get_analog_edid(struct drm_connector *connector)
1292{
f899fc64 1293 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1294
0c1dab89 1295 return drm_get_edid(connector,
3bd7d909
DK		 1296 intel_gmbus_get_adapter(dev_priv,
1297 dev_priv->crt_ddc_pin));
ff482d83
CW		 1298}
1299
c43b5634 1300static enum drm_connector_status
8bf38485 1301intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1302{
df0e9248 1303 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1304 enum drm_connector_status status;
1305 struct edid *edid;
9dff6af8 1306
e957d772 1307 edid = intel_sdvo_get_edid(connector);
57cdaf90 1308
ea5b213a 1309 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1310 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1311
7c3f0a27
ZY		 1312 /*
1313 * Don't use the 1 as the argument of DDC bus switch to get
1314 * the EDID. It is used for SDVO SPD ROM.
1315 */
9d1a903d 1316 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1317 intel_sdvo->ddc_bus = ddc;
1318 edid = intel_sdvo_get_edid(connector);
1319 if (edid)
7c3f0a27 1320 break;
7c3f0a27 1321 }
e957d772
CW		 1322 /*
1323 * If we found the EDID on the other bus,
1324 * assume that is the correct DDC bus.
1325 */
1326 if (edid == NULL)
1327 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1328 }
9d1a903d
CW		 1329
1330 /*
1331 * When there is no edid and no monitor is connected with VGA
1332 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1333 */
ff482d83
CW		 1334 if (edid == NULL)
1335 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1336
2f551c84 1337 status = connector_status_unknown;
9dff6af8 1338 if (edid != NULL) {
149c36a3 1339 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1340 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1341 status = connector_status_connected;
da79de97
CW		 1342 if (intel_sdvo->is_hdmi) {
1343 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1344 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1345 }
13946743
CW		 1346 } else
1347 status = connector_status_disconnected;
9d1a903d
CW		 1348 kfree(edid);
1349 }
7f36e7ed
CW		 1350
1351 if (status == connector_status_connected) {
1352 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1353 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1354 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1355 }
1356
2b8d33f7 1357 return status;
9dff6af8
ML		 1358}
1359
52220085
CW		 1360static bool
1361intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1362 struct edid *edid)
1363{
1364 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1365 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1366
1367 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1368 connector_is_digital, monitor_is_digital);
1369 return connector_is_digital == monitor_is_digital;
1370}
1371
7b334fcb 1372static enum drm_connector_status
930a9e28 1373intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1374{
fb7a46f3 1375 uint16_t response;
df0e9248 1376 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1377 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1378 enum drm_connector_status ret;
79e53945 1379
32aad86f 1380 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1381 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1382 return connector_status_unknown;
ba84cd1f
CW		 1383
1384 /* add 30ms delay when the output type might be TV */
a0b1c7a5 1385 if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
6c982376 1386 msleep(30);
ba84cd1f 1387
32aad86f
CW		 1388 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1389 return connector_status_unknown;
79e53945 1390
e957d772
CW		 1391 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1392 response & 0xff, response >> 8,
1393 intel_sdvo_connector->output_flag);
e2f0ba97 1394
fb7a46f3 1395 if (response == 0)
79e53945 1396 return connector_status_disconnected;
fb7a46f3 1397
ea5b213a 1398 intel_sdvo->attached_output = response;
14571b4c 1399
97aaf910
CW		 1400 intel_sdvo->has_hdmi_monitor = false;
1401 intel_sdvo->has_hdmi_audio = false;
1402
615fb93f 1403 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1404 ret = connector_status_disconnected;
13946743 1405 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1406 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1407 else {
1408 struct edid *edid;
1409
1410 /* if we have an edid check it matches the connection */
1411 edid = intel_sdvo_get_edid(connector);
1412 if (edid == NULL)
1413 edid = intel_sdvo_get_analog_edid(connector);
1414 if (edid != NULL) {
52220085
CW		 1415 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1416 edid))
13946743 1417 ret = connector_status_connected;
52220085
CW		 1418 else
1419 ret = connector_status_disconnected;
1420
13946743
CW		 1421 kfree(edid);
1422 } else
1423 ret = connector_status_connected;
1424 }
14571b4c
ZW		 1425
1426 /* May update encoder flag for like clock for SDVO TV, etc.*/
1427 if (ret == connector_status_connected) {
ea5b213a
CW		 1428 intel_sdvo->is_tv = false;
1429 intel_sdvo->is_lvds = false;
1430 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1431
1432 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1433 intel_sdvo->is_tv = true;
1434 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1435 }
1436 if (response & SDVO_LVDS_MASK)
8545423a 1437 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1438 }
14571b4c
ZW		 1439
1440 return ret;
79e53945
JB		 1441}
1442
e2f0ba97 1443static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1444{
ff482d83 1445 struct edid *edid;
79e53945
JB		 1446
1447 /* set the bus switch and get the modes */
e957d772 1448 edid = intel_sdvo_get_edid(connector);
79e53945 1449
57cdaf90
KP		 1450 /*
1451 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1452 * link between analog and digital outputs. So, if the regular SDVO
1453 * DDC fails, check to see if the analog output is disconnected, in
1454 * which case we'll look there for the digital DDC data.
e2f0ba97 1455 */
f899fc64
CW		 1456 if (edid == NULL)
1457 edid = intel_sdvo_get_analog_edid(connector);
1458
ff482d83 1459 if (edid != NULL) {
52220085
CW		 1460 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1461 edid)) {
0c1dab89
CW		 1462 drm_mode_connector_update_edid_property(connector, edid);
1463 drm_add_edid_modes(connector, edid);
1464 }
13946743 1465
ff482d83 1466 kfree(edid);
e2f0ba97 1467 }
e2f0ba97
JB		 1468}
1469
1470/*
1471 * Set of SDVO TV modes.
1472 * Note! This is in reply order (see loop in get_tv_modes).
1473 * XXX: all 60Hz refresh?
1474 */
b1f559ec 1475static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1476 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1477 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1479 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1480 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1482 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1483 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1485 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1486 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1488 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1489 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1491 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1492 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1494 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1495 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1497 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1498 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1500 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1501 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1503 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1504 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1506 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1507 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1509 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1510 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1512 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1513 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1515 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1516 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1518 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1519 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1521 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1522 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1524 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1525 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1527 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1528 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1530 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1531 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1533};
1534
1535static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1536{
df0e9248 1537 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1538 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1539 uint32_t reply = 0, format_map = 0;
1540 int i;
e2f0ba97
JB		 1541
1542 /* Read the list of supported input resolutions for the selected TV
1543 * format.
1544 */
40039750 1545 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1546 memcpy(&tv_res, &format_map,
32aad86f 1547 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1548
32aad86f
CW		 1549 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1550 return;
ce6feabd 1551
32aad86f 1552 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1553 if (!intel_sdvo_write_cmd(intel_sdvo,
1554 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1555 &tv_res, sizeof(tv_res)))
1556 return;
1557 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1558 return;
1559
1560 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1561 if (reply & (1 << i)) {
1562 struct drm_display_mode *nmode;
1563 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1564 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1565 if (nmode)
1566 drm_mode_probed_add(connector, nmode);
1567 }
e2f0ba97
JB		 1568}
1569
7086c87f
ML		 1570static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1571{
df0e9248 1572 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1573 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1574 struct drm_display_mode *newmode;
7086c87f
ML		 1575
1576 /*
1577 * Attempt to get the mode list from DDC.
1578 * Assume that the preferred modes are
1579 * arranged in priority order.
1580 */
f899fc64 1581 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1582 if (list_empty(&connector->probed_modes) == false)
12682a97 1583 goto end;
7086c87f
ML		 1584
1585 /* Fetch modes from VBT */
1586 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1587 newmode = drm_mode_duplicate(connector->dev,
1588 dev_priv->sdvo_lvds_vbt_mode);
1589 if (newmode != NULL) {
1590 /* Guarantee the mode is preferred */
1591 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1592 DRM_MODE_TYPE_DRIVER);
1593 drm_mode_probed_add(connector, newmode);
1594 }
1595 }
12682a97 1596
1597end:
1598 list_for_each_entry(newmode, &connector->probed_modes, head) {
1599 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1600 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1601 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1602
8545423a 1603 intel_sdvo->is_lvds = true;
12682a97 1604 break;
1605 }
1606 }
1607
7086c87f
ML		 1608}
1609
e2f0ba97
JB		 1610static int intel_sdvo_get_modes(struct drm_connector *connector)
1611{
615fb93f 1612 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1613
615fb93f 1614 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1615 intel_sdvo_get_tv_modes(connector);
615fb93f 1616 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1617 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1618 else
1619 intel_sdvo_get_ddc_modes(connector);
1620
32aad86f 1621 return !list_empty(&connector->probed_modes);
79e53945
JB		 1622}
1623
fcc8d672
CW		 1624static void
1625intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1626{
615fb93f 1627 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1628 struct drm_device *dev = connector->dev;
1629
c5521706
CW		 1630 if (intel_sdvo_connector->left)
1631 drm_property_destroy(dev, intel_sdvo_connector->left);
1632 if (intel_sdvo_connector->right)
1633 drm_property_destroy(dev, intel_sdvo_connector->right);
1634 if (intel_sdvo_connector->top)
1635 drm_property_destroy(dev, intel_sdvo_connector->top);
1636 if (intel_sdvo_connector->bottom)
1637 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1638 if (intel_sdvo_connector->hpos)
1639 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1640 if (intel_sdvo_connector->vpos)
1641 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1642 if (intel_sdvo_connector->saturation)
1643 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1644 if (intel_sdvo_connector->contrast)
1645 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1646 if (intel_sdvo_connector->hue)
1647 drm_property_destroy(dev, intel_sdvo_connector->hue);
1648 if (intel_sdvo_connector->sharpness)
1649 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1650 if (intel_sdvo_connector->flicker_filter)
1651 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1652 if (intel_sdvo_connector->flicker_filter_2d)
1653 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1654 if (intel_sdvo_connector->flicker_filter_adaptive)
1655 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1656 if (intel_sdvo_connector->tv_luma_filter)
1657 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1658 if (intel_sdvo_connector->tv_chroma_filter)
1659 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1660 if (intel_sdvo_connector->dot_crawl)
1661 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1662 if (intel_sdvo_connector->brightness)
1663 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1664}
1665
79e53945
JB		 1666static void intel_sdvo_destroy(struct drm_connector *connector)
1667{
615fb93f 1668 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1669
c5521706 1670 if (intel_sdvo_connector->tv_format)
ce6feabd 1671 drm_property_destroy(connector->dev,
c5521706 1672 intel_sdvo_connector->tv_format);
b9219c5e 1673
d2a82a6f 1674 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1675 drm_sysfs_connector_remove(connector);
1676 drm_connector_cleanup(connector);
d2a82a6f 1677 kfree(connector);
79e53945
JB		 1678}
1679
1aad7ac0
CW		 1680static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1681{
1682 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1683 struct edid *edid;
1684 bool has_audio = false;
1685
1686 if (!intel_sdvo->is_hdmi)
1687 return false;
1688
1689 edid = intel_sdvo_get_edid(connector);
1690 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1691 has_audio = drm_detect_monitor_audio(edid);
bcd7235c 1692 kfree(edid);
1aad7ac0
CW		 1693
1694 return has_audio;
1695}
1696
ce6feabd
ZY		 1697static int
1698intel_sdvo_set_property(struct drm_connector *connector,
1699 struct drm_property *property,
1700 uint64_t val)
1701{
df0e9248 1702 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1703 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1704 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1705 uint16_t temp_value;
32aad86f
CW		 1706 uint8_t cmd;
1707 int ret;
ce6feabd
ZY		 1708
1709 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1710 if (ret)
1711 return ret;
ce6feabd 1712
3f43c48d 1713 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1714 int i = val;
1715 bool has_audio;
1716
1717 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1718 return 0;
1719
1aad7ac0 1720 intel_sdvo_connector->force_audio = i;
7f36e7ed 1721
c3e5f67b 1722 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1723 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1724 else
c3e5f67b 1725 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1726
1aad7ac0 1727 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1728 return 0;
7f36e7ed 1729
1aad7ac0 1730 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1731 goto done;
1732 }
1733
e953fd7b
CW		 1734 if (property == dev_priv->broadcast_rgb_property) {
1735 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1736 return 0;
1737
e953fd7b 1738 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1739 goto done;
1740 }
1741
c5521706
CW		 1742#define CHECK_PROPERTY(name, NAME) \
1743 if (intel_sdvo_connector->name == property) { \
1744 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1745 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1746 cmd = SDVO_CMD_SET_##NAME; \
1747 intel_sdvo_connector->cur_##name = temp_value; \
1748 goto set_value; \
1749 }
1750
1751 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1752 if (val >= TV_FORMAT_NUM)
1753 return -EINVAL;
1754
40039750 1755 if (intel_sdvo->tv_format_index ==
615fb93f 1756 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1757 return 0;
ce6feabd 1758
40039750 1759 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1760 goto done;
32aad86f 1761 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1762 temp_value = val;
c5521706 1763 if (intel_sdvo_connector->left == property) {
b9219c5e 1764 drm_connector_property_set_value(connector,
c5521706 1765 intel_sdvo_connector->right, val);
615fb93f 1766 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1767 return 0;
b9219c5e 1768
615fb93f
CW		 1769 intel_sdvo_connector->left_margin = temp_value;
1770 intel_sdvo_connector->right_margin = temp_value;
1771 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1772 intel_sdvo_connector->left_margin;
b9219c5e 1773 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1774 goto set_value;
1775 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1776 drm_connector_property_set_value(connector,
c5521706 1777 intel_sdvo_connector->left, val);
615fb93f 1778 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1779 return 0;
b9219c5e 1780
615fb93f
CW		 1781 intel_sdvo_connector->left_margin = temp_value;
1782 intel_sdvo_connector->right_margin = temp_value;
1783 temp_value = intel_sdvo_connector->max_hscan -
1784 intel_sdvo_connector->left_margin;
b9219c5e 1785 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1786 goto set_value;
1787 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1788 drm_connector_property_set_value(connector,
c5521706 1789 intel_sdvo_connector->bottom, val);
615fb93f 1790 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1791 return 0;
b9219c5e 1792
615fb93f
CW		 1793 intel_sdvo_connector->top_margin = temp_value;
1794 intel_sdvo_connector->bottom_margin = temp_value;
1795 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1796 intel_sdvo_connector->top_margin;
b9219c5e 1797 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1798 goto set_value;
1799 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1800 drm_connector_property_set_value(connector,
c5521706 1801 intel_sdvo_connector->top, val);
615fb93f 1802 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1803 return 0;
1804
615fb93f
CW		 1805 intel_sdvo_connector->top_margin = temp_value;
1806 intel_sdvo_connector->bottom_margin = temp_value;
1807 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1808 intel_sdvo_connector->top_margin;
b9219c5e 1809 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1810 goto set_value;
1811 }
1812 CHECK_PROPERTY(hpos, HPOS)
1813 CHECK_PROPERTY(vpos, VPOS)
1814 CHECK_PROPERTY(saturation, SATURATION)
1815 CHECK_PROPERTY(contrast, CONTRAST)
1816 CHECK_PROPERTY(hue, HUE)
1817 CHECK_PROPERTY(brightness, BRIGHTNESS)
1818 CHECK_PROPERTY(sharpness, SHARPNESS)
1819 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1820 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1821 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1822 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1823 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1824 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1825 }
b9219c5e 1826
c5521706 1827 return -EINVAL; /* unknown property */
b9219c5e 1828
c5521706
CW		 1829set_value:
1830 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1831 return -EIO;
b9219c5e 1832
b9219c5e 1833
c5521706 1834done:
df0e9248
CW		 1835 if (intel_sdvo->base.base.crtc) {
1836 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1837 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1838 crtc->y, crtc->fb);
1839 }
1840
32aad86f 1841 return 0;
c5521706 1842#undef CHECK_PROPERTY
ce6feabd
ZY		 1843}
1844
79e53945
JB		 1845static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1846 .dpms = intel_sdvo_dpms,
1847 .mode_fixup = intel_sdvo_mode_fixup,
1848 .prepare = intel_encoder_prepare,
1849 .mode_set = intel_sdvo_mode_set,
1850 .commit = intel_encoder_commit,
1851};
1852
1853static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1854 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1855 .detect = intel_sdvo_detect,
1856 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1857 .set_property = intel_sdvo_set_property,
79e53945
JB		 1858 .destroy = intel_sdvo_destroy,
1859};
1860
1861static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1862 .get_modes = intel_sdvo_get_modes,
1863 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1864 .best_encoder = intel_best_encoder,
79e53945
JB		 1865};
1866
b358d0a6 1867static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1868{
890f3359 1869 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1870
ea5b213a 1871 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1872 drm_mode_destroy(encoder->dev,
ea5b213a 1873 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1874
e957d772 1875 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1876 intel_encoder_destroy(encoder);
79e53945
JB		 1877}
1878
1879static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1880 .destroy = intel_sdvo_enc_destroy,
1881};
1882
b66d8424
CW		 1883static void
1884intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1885{
1886 uint16_t mask = 0;
1887 unsigned int num_bits;
1888
1889 /* Make a mask of outputs less than or equal to our own priority in the
1890 * list.
1891 */
1892 switch (sdvo->controlled_output) {
1893 case SDVO_OUTPUT_LVDS1:
1894 mask |= SDVO_OUTPUT_LVDS1;
1895 case SDVO_OUTPUT_LVDS0:
1896 mask |= SDVO_OUTPUT_LVDS0;
1897 case SDVO_OUTPUT_TMDS1:
1898 mask |= SDVO_OUTPUT_TMDS1;
1899 case SDVO_OUTPUT_TMDS0:
1900 mask |= SDVO_OUTPUT_TMDS0;
1901 case SDVO_OUTPUT_RGB1:
1902 mask |= SDVO_OUTPUT_RGB1;
1903 case SDVO_OUTPUT_RGB0:
1904 mask |= SDVO_OUTPUT_RGB0;
1905 break;
1906 }
1907
1908 /* Count bits to find what number we are in the priority list. */
1909 mask &= sdvo->caps.output_flags;
1910 num_bits = hweight16(mask);
1911 /* If more than 3 outputs, default to DDC bus 3 for now. */
1912 if (num_bits > 3)
1913 num_bits = 3;
1914
1915 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1916 sdvo->ddc_bus = 1 << num_bits;
1917}
79e53945 1918
e2f0ba97
JB		 1919/**
1920 * Choose the appropriate DDC bus for control bus switch command for this
1921 * SDVO output based on the controlled output.
1922 *
1923 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1924 * outputs, then LVDS outputs.
1925 */
1926static void
b1083333 1927intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1928 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1929{
b1083333 1930 struct sdvo_device_mapping *mapping;
e2f0ba97 1931
eef4eacb 1932 if (sdvo->is_sdvob)
b1083333
AJ		 1933 mapping = &(dev_priv->sdvo_mappings[0]);
1934 else
1935 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1936
b66d8424
CW		 1937 if (mapping->initialized)
1938 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1939 else
1940 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1941}
1942
e957d772
CW		 1943static void
1944intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1945 struct intel_sdvo *sdvo, u32 reg)
1946{
1947 struct sdvo_device_mapping *mapping;
46eb3036 1948 u8 pin;
e957d772 1949
eef4eacb 1950 if (sdvo->is_sdvob)
e957d772
CW		 1951 mapping = &dev_priv->sdvo_mappings[0];
1952 else
1953 mapping = &dev_priv->sdvo_mappings[1];
1954
1955 pin = GMBUS_PORT_DPB;
46eb3036 1956 if (mapping->initialized)
e957d772 1957 pin = mapping->i2c_pin;
e957d772 1958
3bd7d909
DK		 1959 if (intel_gmbus_is_port_valid(pin)) {
1960 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
d5090b96 1961 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1962 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1963 } else {
3bd7d909 1964 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
46eb3036 1965 }
e957d772
CW		 1966}
1967
e2f0ba97 1968static bool
e27d8538 1969intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1970{
97aaf910 1971 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1972}
1973
714605e4 1974static u8
eef4eacb 1975intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 1976{
1977 struct drm_i915_private *dev_priv = dev->dev_private;
1978 struct sdvo_device_mapping *my_mapping, *other_mapping;
1979
eef4eacb 1980 if (sdvo->is_sdvob) {
714605e4 1981 my_mapping = &dev_priv->sdvo_mappings[0];
1982 other_mapping = &dev_priv->sdvo_mappings[1];
1983 } else {
1984 my_mapping = &dev_priv->sdvo_mappings[1];
1985 other_mapping = &dev_priv->sdvo_mappings[0];
1986 }
1987
1988 /* If the BIOS described our SDVO device, take advantage of it. */
1989 if (my_mapping->slave_addr)
1990 return my_mapping->slave_addr;
1991
1992 /* If the BIOS only described a different SDVO device, use the
1993 * address that it isn't using.
1994 */
1995 if (other_mapping->slave_addr) {
1996 if (other_mapping->slave_addr == 0x70)
1997 return 0x72;
1998 else
1999 return 0x70;
2000 }
2001
2002 /* No SDVO device info is found for another DVO port,
2003 * so use mapping assumption we had before BIOS parsing.
2004 */
eef4eacb 2005 if (sdvo->is_sdvob)
714605e4 2006 return 0x70;
2007 else
2008 return 0x72;
2009}
2010
14571b4c 2011static void
df0e9248
CW		 2012intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2013 struct intel_sdvo *encoder)
14571b4c 2014{
df0e9248
CW		 2015 drm_connector_init(encoder->base.base.dev,
2016 &connector->base.base,
2017 &intel_sdvo_connector_funcs,
2018 connector->base.base.connector_type);
6070a4a9 2019
df0e9248
CW		 2020 drm_connector_helper_add(&connector->base.base,
2021 &intel_sdvo_connector_helper_funcs);
14571b4c 2022
8f4839e2 2023 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2024 connector->base.base.doublescan_allowed = 0;
2025 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2026
df0e9248
CW		 2027 intel_connector_attach_encoder(&connector->base, &encoder->base);
2028 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2029}
6070a4a9 2030
7f36e7ed
CW		 2031static void
2032intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2033{
2034 struct drm_device *dev = connector->base.base.dev;
2035
3f43c48d 2036 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2037 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2038 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2039}
2040
fb7a46f3 2041static bool
ea5b213a 2042intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2043{
4ef69c7a 2044 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2045 struct drm_connector *connector;
cc68c81a 2046 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2047 struct intel_connector *intel_connector;
615fb93f 2048 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2049
615fb93f
CW		 2050 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2051 if (!intel_sdvo_connector)
14571b4c
ZW		 2052 return false;
2053
14571b4c 2054 if (device == 0) {
ea5b213a 2055 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2056 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2057 } else if (device == 1) {
ea5b213a 2058 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2059 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2060 }
2061
615fb93f 2062 intel_connector = &intel_sdvo_connector->base;
14571b4c 2063 connector = &intel_connector->base;
cc68c81a
SF		 2064 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2065 connector->polled = DRM_CONNECTOR_POLL_HPD;
2066 intel_sdvo->hotplug_active[0] |= 1 << device;
2067 /* Some SDVO devices have one-shot hotplug interrupts.
2068 * Ensure that they get re-enabled when an interrupt happens.
2069 */
2070 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2071 intel_sdvo_enable_hotplug(intel_encoder);
2072 }
2073 else
2074 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2075 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2076 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2077
e27d8538 2078 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2079 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2080 intel_sdvo->is_hdmi = true;
14571b4c 2081 }
66a9278e 2082 intel_sdvo->base.cloneable = true;
14571b4c 2083
df0e9248 2084 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2085 if (intel_sdvo->is_hdmi)
2086 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2087
2088 return true;
2089}
2090
2091static bool
ea5b213a 2092intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2093{
4ef69c7a
CW		 2094 struct drm_encoder *encoder = &intel_sdvo->base.base;
2095 struct drm_connector *connector;
2096 struct intel_connector *intel_connector;
2097 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2098
615fb93f
CW		 2099 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2100 if (!intel_sdvo_connector)
2101 return false;
14571b4c 2102
615fb93f 2103 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2104 connector = &intel_connector->base;
2105 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2106 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2107
4ef69c7a
CW		 2108 intel_sdvo->controlled_output |= type;
2109 intel_sdvo_connector->output_flag = type;
14571b4c 2110
4ef69c7a
CW		 2111 intel_sdvo->is_tv = true;
2112 intel_sdvo->base.needs_tv_clock = true;
66a9278e 2113 intel_sdvo->base.cloneable = false;
14571b4c 2114
df0e9248 2115 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2116
4ef69c7a 2117 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2118 goto err;
14571b4c 2119
4ef69c7a 2120 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2121 goto err;
14571b4c 2122
4ef69c7a 2123 return true;
32aad86f
CW		 2124
2125err:
123d5c01 2126 intel_sdvo_destroy(connector);
32aad86f 2127 return false;
14571b4c
ZW		 2128}
2129
2130static bool
ea5b213a 2131intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2132{
4ef69c7a
CW		 2133 struct drm_encoder *encoder = &intel_sdvo->base.base;
2134 struct drm_connector *connector;
2135 struct intel_connector *intel_connector;
2136 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2137
615fb93f
CW		 2138 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2139 if (!intel_sdvo_connector)
2140 return false;
14571b4c 2141
615fb93f 2142 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2143 connector = &intel_connector->base;
eb1f8e4f 2144 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2145 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2146 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2147
2148 if (device == 0) {
2149 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2150 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2151 } else if (device == 1) {
2152 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2153 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2154 }
2155
66a9278e 2156 intel_sdvo->base.cloneable = true;
14571b4c 2157
df0e9248
CW		 2158 intel_sdvo_connector_init(intel_sdvo_connector,
2159 intel_sdvo);
4ef69c7a 2160 return true;
14571b4c
ZW		 2161}
2162
2163static bool
ea5b213a 2164intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2165{
4ef69c7a
CW		 2166 struct drm_encoder *encoder = &intel_sdvo->base.base;
2167 struct drm_connector *connector;
2168 struct intel_connector *intel_connector;
2169 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2170
615fb93f
CW		 2171 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2172 if (!intel_sdvo_connector)
2173 return false;
14571b4c 2174
615fb93f
CW		 2175 intel_connector = &intel_sdvo_connector->base;
2176 connector = &intel_connector->base;
4ef69c7a
CW		 2177 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2178 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2179
2180 if (device == 0) {
2181 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2182 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2183 } else if (device == 1) {
2184 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2185 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2186 }
2187
66a9278e
DV		 2188 /* SDVO LVDS is cloneable because the SDVO encoder does the upscaling,
2189 * as opposed to native LVDS, where we upscale with the panel-fitter
2190 * (and hence only the native LVDS resolution could be cloned). */
2191 intel_sdvo->base.cloneable = true;
14571b4c 2192
df0e9248 2193 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2194 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2195 goto err;
2196
2197 return true;
2198
2199err:
123d5c01 2200 intel_sdvo_destroy(connector);
32aad86f 2201 return false;
14571b4c
ZW		 2202}
2203
2204static bool
ea5b213a 2205intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2206{
ea5b213a
CW		 2207 intel_sdvo->is_tv = false;
2208 intel_sdvo->base.needs_tv_clock = false;
2209 intel_sdvo->is_lvds = false;
fb7a46f3 2210
14571b4c 2211 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2212
14571b4c 2213 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2214 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2215 return false;
2216
2217 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2218 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2219 return false;
2220
2221 /* TV has no XXX1 function block */
a1f4b7ff 2222 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2223 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2224 return false;
2225
2226 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2227 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2228 return false;
fb7a46f3 2229
a0b1c7a5
CW		 2230 if (flags & SDVO_OUTPUT_YPRPB0)
2231 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2232 return false;
2233
14571b4c 2234 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2235 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2236 return false;
2237
2238 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2239 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2240 return false;
2241
2242 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2243 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2244 return false;
2245
2246 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2247 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2248 return false;
fb7a46f3 2249
14571b4c 2250 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2251 unsigned char bytes[2];
2252
ea5b213a
CW		 2253 intel_sdvo->controlled_output = 0;
2254 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2255 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2256 SDVO_NAME(intel_sdvo),
51c8b407 2257 bytes[0], bytes[1]);
14571b4c 2258 return false;
fb7a46f3 2259 }
27f8227b 2260 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2261
14571b4c 2262 return true;
fb7a46f3 2263}
2264
32aad86f
CW		 2265static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2266 struct intel_sdvo_connector *intel_sdvo_connector,
2267 int type)
ce6feabd 2268{
4ef69c7a 2269 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2270 struct intel_sdvo_tv_format format;
2271 uint32_t format_map, i;
ce6feabd 2272
32aad86f
CW		 2273 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2274 return false;
ce6feabd 2275
1a3665c8 2276 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2277 if (!intel_sdvo_get_value(intel_sdvo,
2278 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2279 &format, sizeof(format)))
2280 return false;
ce6feabd 2281
32aad86f 2282 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2283
2284 if (format_map == 0)
32aad86f 2285 return false;
ce6feabd 2286
615fb93f 2287 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2288 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2289 if (format_map & (1 << i))
2290 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2291
2292
c5521706 2293 intel_sdvo_connector->tv_format =
32aad86f
CW		 2294 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2295 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2296 if (!intel_sdvo_connector->tv_format)
fcc8d672 2297 return false;
ce6feabd 2298
615fb93f 2299 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2300 drm_property_add_enum(
c5521706 2301 intel_sdvo_connector->tv_format, i,
40039750 2302 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2303
40039750 2304 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2305 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2306 intel_sdvo_connector->tv_format, 0);
32aad86f 2307 return true;
ce6feabd
ZY		 2308
2309}
2310
c5521706
CW		 2311#define ENHANCEMENT(name, NAME) do { \
2312 if (enhancements.name) { \
2313 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2314 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2315 return false; \
2316 intel_sdvo_connector->max_##name = data_value[0]; \
2317 intel_sdvo_connector->cur_##name = response; \
2318 intel_sdvo_connector->name = \
d9bc3c02 2319 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2320 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2321 drm_connector_attach_property(connector, \
2322 intel_sdvo_connector->name, \
2323 intel_sdvo_connector->cur_##name); \
2324 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2325 data_value[0], data_value[1], response); \
2326 } \
0206e353 2327} while (0)
c5521706
CW		 2328
2329static bool
2330intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2331 struct intel_sdvo_connector *intel_sdvo_connector,
2332 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2333{
4ef69c7a 2334 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2335 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2336 uint16_t response, data_value[2];
2337
c5521706
CW		 2338 /* when horizontal overscan is supported, Add the left/right property */
2339 if (enhancements.overscan_h) {
2340 if (!intel_sdvo_get_value(intel_sdvo,
2341 SDVO_CMD_GET_MAX_OVERSCAN_H,
2342 &data_value, 4))
2343 return false;
32aad86f 2344
c5521706
CW		 2345 if (!intel_sdvo_get_value(intel_sdvo,
2346 SDVO_CMD_GET_OVERSCAN_H,
2347 &response, 2))
2348 return false;
fcc8d672 2349
c5521706
CW		 2350 intel_sdvo_connector->max_hscan = data_value[0];
2351 intel_sdvo_connector->left_margin = data_value[0] - response;
2352 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2353 intel_sdvo_connector->left =
d9bc3c02 2354 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2355 if (!intel_sdvo_connector->left)
2356 return false;
fcc8d672 2357
c5521706
CW		 2358 drm_connector_attach_property(connector,
2359 intel_sdvo_connector->left,
2360 intel_sdvo_connector->left_margin);
fcc8d672 2361
c5521706 2362 intel_sdvo_connector->right =
d9bc3c02 2363 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2364 if (!intel_sdvo_connector->right)
2365 return false;
32aad86f 2366
c5521706
CW		 2367 drm_connector_attach_property(connector,
2368 intel_sdvo_connector->right,
2369 intel_sdvo_connector->right_margin);
2370 DRM_DEBUG_KMS("h_overscan: max %d, "
2371 "default %d, current %d\n",
2372 data_value[0], data_value[1], response);
2373 }
32aad86f 2374
c5521706
CW		 2375 if (enhancements.overscan_v) {
2376 if (!intel_sdvo_get_value(intel_sdvo,
2377 SDVO_CMD_GET_MAX_OVERSCAN_V,
2378 &data_value, 4))
2379 return false;
fcc8d672 2380
c5521706
CW		 2381 if (!intel_sdvo_get_value(intel_sdvo,
2382 SDVO_CMD_GET_OVERSCAN_V,
2383 &response, 2))
2384 return false;
32aad86f 2385
c5521706
CW		 2386 intel_sdvo_connector->max_vscan = data_value[0];
2387 intel_sdvo_connector->top_margin = data_value[0] - response;
2388 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2389 intel_sdvo_connector->top =
d9bc3c02
SH		 2390 drm_property_create_range(dev, 0,
2391 "top_margin", 0, data_value[0]);
c5521706
CW		 2392 if (!intel_sdvo_connector->top)
2393 return false;
32aad86f 2394
c5521706
CW		 2395 drm_connector_attach_property(connector,
2396 intel_sdvo_connector->top,
2397 intel_sdvo_connector->top_margin);
fcc8d672 2398
c5521706 2399 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2400 drm_property_create_range(dev, 0,
2401 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2402 if (!intel_sdvo_connector->bottom)
2403 return false;
32aad86f 2404
c5521706
CW		 2405 drm_connector_attach_property(connector,
2406 intel_sdvo_connector->bottom,
2407 intel_sdvo_connector->bottom_margin);
2408 DRM_DEBUG_KMS("v_overscan: max %d, "
2409 "default %d, current %d\n",
2410 data_value[0], data_value[1], response);
2411 }
32aad86f 2412
c5521706
CW		 2413 ENHANCEMENT(hpos, HPOS);
2414 ENHANCEMENT(vpos, VPOS);
2415 ENHANCEMENT(saturation, SATURATION);
2416 ENHANCEMENT(contrast, CONTRAST);
2417 ENHANCEMENT(hue, HUE);
2418 ENHANCEMENT(sharpness, SHARPNESS);
2419 ENHANCEMENT(brightness, BRIGHTNESS);
2420 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2421 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2422 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2423 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2424 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2425
e044218a
CW		 2426 if (enhancements.dot_crawl) {
2427 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2428 return false;
2429
2430 intel_sdvo_connector->max_dot_crawl = 1;
2431 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2432 intel_sdvo_connector->dot_crawl =
d9bc3c02 2433 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2434 if (!intel_sdvo_connector->dot_crawl)
2435 return false;
2436
e044218a
CW		 2437 drm_connector_attach_property(connector,
2438 intel_sdvo_connector->dot_crawl,
2439 intel_sdvo_connector->cur_dot_crawl);
2440 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2441 }
2442
c5521706
CW		 2443 return true;
2444}
32aad86f 2445
c5521706
CW		 2446static bool
2447intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2448 struct intel_sdvo_connector *intel_sdvo_connector,
2449 struct intel_sdvo_enhancements_reply enhancements)
2450{
4ef69c7a 2451 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2452 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2453 uint16_t response, data_value[2];
32aad86f 2454
c5521706 2455 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2456
c5521706
CW		 2457 return true;
2458}
2459#undef ENHANCEMENT
32aad86f 2460
c5521706
CW		 2461static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2462 struct intel_sdvo_connector *intel_sdvo_connector)
2463{
2464 union {
2465 struct intel_sdvo_enhancements_reply reply;
2466 uint16_t response;
2467 } enhancements;
32aad86f 2468
1a3665c8
CW		 2469 BUILD_BUG_ON(sizeof(enhancements) != 2);
2470
cf9a2f3a
CW		 2471 enhancements.response = 0;
2472 intel_sdvo_get_value(intel_sdvo,
2473 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2474 &enhancements, sizeof(enhancements));
c5521706
CW		 2475 if (enhancements.response == 0) {
2476 DRM_DEBUG_KMS("No enhancement is supported\n");
2477 return true;
b9219c5e 2478 }
32aad86f 2479
c5521706
CW		 2480 if (IS_TV(intel_sdvo_connector))
2481 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2482 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2483 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2484 else
2485 return true;
e957d772
CW		 2486}
2487
2488static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2489 struct i2c_msg *msgs,
2490 int num)
2491{
2492 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2493
e957d772
CW		 2494 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2495 return -EIO;
2496
2497 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2498}
2499
2500static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2501{
2502 struct intel_sdvo *sdvo = adapter->algo_data;
2503 return sdvo->i2c->algo->functionality(sdvo->i2c);
2504}
2505
2506static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2507 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2508 .functionality = intel_sdvo_ddc_proxy_func
2509};
2510
2511static bool
2512intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2513 struct drm_device *dev)
2514{
2515 sdvo->ddc.owner = THIS_MODULE;
2516 sdvo->ddc.class = I2C_CLASS_DDC;
2517 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2518 sdvo->ddc.dev.parent = &dev->pdev->dev;
2519 sdvo->ddc.algo_data = sdvo;
2520 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2521
2522 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2523}
2524
eef4eacb 2525bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2526{
b01f2c3a 2527 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2528 struct intel_encoder *intel_encoder;
ea5b213a 2529 struct intel_sdvo *intel_sdvo;
084b612e 2530 u32 hotplug_mask;
79e53945 2531 int i;
79e53945 2532
ea5b213a
CW		 2533 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2534 if (!intel_sdvo)
7d57382e 2535 return false;
79e53945 2536
56184e3d 2537 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2538 intel_sdvo->is_sdvob = is_sdvob;
2539 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2540 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2541 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2542 kfree(intel_sdvo);
2543 return false;
2544 }
2545
56184e3d 2546 /* encoder type will be decided later */
ea5b213a 2547 intel_encoder = &intel_sdvo->base;
21d40d37 2548 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2549 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2550
79e53945
JB		 2551 /* Read the regs to test if we can talk to the device */
2552 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2553 u8 byte;
2554
2555 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2556 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2557 SDVO_NAME(intel_sdvo));
f899fc64 2558 goto err;
79e53945
JB		 2559 }
2560 }
2561
084b612e
CW		 2562 hotplug_mask = 0;
2563 if (IS_G4X(dev)) {
2564 hotplug_mask = intel_sdvo->is_sdvob ?
2565 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2566 } else if (IS_GEN4(dev)) {
2567 hotplug_mask = intel_sdvo->is_sdvob ?
2568 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2569 } else {
2570 hotplug_mask = intel_sdvo->is_sdvob ?
2571 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2572 }
619ac3b7 2573
4ef69c7a 2574 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2575
af901ca1 2576 /* In default case sdvo lvds is false */
32aad86f 2577 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2578 goto err;
79e53945 2579
ea5b213a
CW		 2580 if (intel_sdvo_output_setup(intel_sdvo,
2581 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2582 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2583 SDVO_NAME(intel_sdvo));
f899fc64 2584 goto err;
79e53945
JB		 2585 }
2586
ff04b35a
JN		 2587 /* Only enable the hotplug irq if we need it, to work around noisy
2588 * hotplug lines.
2589 */
2590 if (intel_sdvo->hotplug_active[0])
2591 dev_priv->hotplug_supported_mask |= hotplug_mask;
2592
ea5b213a 2593 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2594
79e53945 2595 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2596 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2597 goto err;
79e53945 2598
32aad86f
CW		 2599 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2600 &intel_sdvo->pixel_clock_min,
2601 &intel_sdvo->pixel_clock_max))
f899fc64 2602 goto err;
79e53945 2603
8a4c47f3 2604 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2605 "clock range %dMHz - %dMHz, "
2606 "input 1: %c, input 2: %c, "
2607 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2608 SDVO_NAME(intel_sdvo),
2609 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2610 intel_sdvo->caps.device_rev_id,
2611 intel_sdvo->pixel_clock_min / 1000,
2612 intel_sdvo->pixel_clock_max / 1000,
2613 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2614 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2615 /* check currently supported outputs */
ea5b213a 2616 intel_sdvo->caps.output_flags &
79e53945 2617 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2618 intel_sdvo->caps.output_flags &
79e53945 2619 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2620 return true;
79e53945 2621
f899fc64 2622err:
373a3cf7 2623 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2624 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2625 kfree(intel_sdvo);
79e53945 2626
7d57382e 2627 return false;
79e53945 2628}
Linux kernel - Deliverables
This page took 0.396752 seconds and 5 git commands to generate.