[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sideband.c

/*
 * Copyright © 2013 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include "i915_drv.h"
#include "intel_drv.h"

/* IOSF sideband */
static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
			   u32 port, u32 opcode, u32 addr, u32 *val)
{
	u32 cmd, be = 0xf, bar = 0;
	bool is_read = (opcode == PUNIT_OPCODE_REG_READ ||
			opcode == DPIO_OPCODE_REG_READ);

	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
		(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
		(bar << IOSF_BAR_SHIFT);

	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));

	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
		DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
				 is_read ? "read" : "write");
		return -EAGAIN;
	}

	I915_WRITE(VLV_IOSF_ADDR, addr);
	if (!is_read)
		I915_WRITE(VLV_IOSF_DATA, *val);
	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);

	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
		DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
				 is_read ? "read" : "write");
		return -ETIMEDOUT;
	}

	if (is_read)
		*val = I915_READ(VLV_IOSF_DATA);
	I915_WRITE(VLV_IOSF_DATA, 0);

	return 0;
}

u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
{
	u32 val = 0;

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	mutex_lock(&dev_priv->dpio_lock);
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
			PUNIT_OPCODE_REG_READ, addr, &val);
	mutex_unlock(&dev_priv->dpio_lock);

	return val;
}

void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
{
	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	mutex_lock(&dev_priv->dpio_lock);
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
			PUNIT_OPCODE_REG_WRITE, addr, &val);
	mutex_unlock(&dev_priv->dpio_lock);
}

u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
{
	u32 val = 0;

	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));

	mutex_lock(&dev_priv->dpio_lock);
	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
			PUNIT_OPCODE_REG_READ, addr, &val);
	mutex_unlock(&dev_priv->dpio_lock);

	return val;
}

u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
{
	u32 val = 0;

	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
			DPIO_OPCODE_REG_READ, reg, &val);

	return val;
}

void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
{
	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
			DPIO_OPCODE_REG_WRITE, reg, &val);
}

/* SBI access */
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination)
{
	u32 value = 0;
	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));

	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
				100)) {
		DRM_ERROR("timeout waiting for SBI to become ready\n");
		return 0;
	}

	I915_WRITE(SBI_ADDR, (reg << 16));

	if (destination == SBI_ICLK)
		value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
	else
		value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
	I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);

	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
				100)) {
		DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
		return 0;
	}

	return I915_READ(SBI_DATA);
}

void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination)
{
	u32 tmp;

	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));

	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
				100)) {
		DRM_ERROR("timeout waiting for SBI to become ready\n");
		return;
	}

	I915_WRITE(SBI_ADDR, (reg << 16));
	I915_WRITE(SBI_DATA, value);

	if (destination == SBI_ICLK)
		tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
	else
		tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
	I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);

	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
				100)) {
		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
		return;
	}
}
Commit	Line	Data
59de0813 JN	1	/*
	2	* Copyright © 2013 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#include "i915_drv.h"
	26	#include "intel_drv.h"
	27
	28	/* IOSF sideband */
5a09ae9f JN	29	static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
5a09ae9f JN	30	u32 port, u32 opcode, u32 addr, u32 *val)
59de0813	31	{
5a09ae9f JN	32	u32 cmd, be = 0xf, bar = 0;
	33	bool is_read = (opcode == PUNIT_OPCODE_REG_READ \|\|
	34	opcode == DPIO_OPCODE_REG_READ);
59de0813 JN	35
	36	cmd = (devfn << IOSF_DEVFN_SHIFT) \| (opcode << IOSF_OPCODE_SHIFT) \|
	37	(port << IOSF_PORT_SHIFT) \| (be << IOSF_BYTE_ENABLES_SHIFT) \|
	38	(bar << IOSF_BAR_SHIFT);
	39
5a09ae9f	40	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
59de0813	41
5a09ae9f JN	42	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
	43	DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
	44	is_read ? "read" : "write");
59de0813 JN	45	return -EAGAIN;
	46	}
	47
	48	I915_WRITE(VLV_IOSF_ADDR, addr);
5a09ae9f	49	if (!is_read)
59de0813 JN	50	I915_WRITE(VLV_IOSF_DATA, *val);
	51	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
	52
5a09ae9f JN	53	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
	54	DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
	55	is_read ? "read" : "write");
59de0813 JN	56	return -ETIMEDOUT;
	57	}
	58
5a09ae9f	59	if (is_read)
59de0813 JN	60	*val = I915_READ(VLV_IOSF_DATA);
	61	I915_WRITE(VLV_IOSF_DATA, 0);
	62
	63	return 0;
	64	}
	65
64936258	66	u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
59de0813	67	{
64936258	68	u32 val = 0;
5a09ae9f JN	69
	70	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
	71
	72	mutex_lock(&dev_priv->dpio_lock);
64936258 JN	73	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
64936258 JN	74	PUNIT_OPCODE_REG_READ, addr, &val);
5a09ae9f JN	75	mutex_unlock(&dev_priv->dpio_lock);
5a09ae9f JN	76
64936258	77	return val;
59de0813 JN	78	}
59de0813 JN	79
64936258	80	void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
59de0813	81	{
5a09ae9f JN	82	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
	83
	84	mutex_lock(&dev_priv->dpio_lock);
64936258 JN	85	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
64936258 JN	86	PUNIT_OPCODE_REG_WRITE, addr, &val);
5a09ae9f	87	mutex_unlock(&dev_priv->dpio_lock);
59de0813 JN	88	}
59de0813 JN	89
64936258	90	u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
59de0813	91	{
64936258	92	u32 val = 0;
5a09ae9f JN	93
	94	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
	95
	96	mutex_lock(&dev_priv->dpio_lock);
64936258 JN	97	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
64936258 JN	98	PUNIT_OPCODE_REG_READ, addr, &val);
5a09ae9f JN	99	mutex_unlock(&dev_priv->dpio_lock);
5a09ae9f JN	100
64936258	101	return val;
59de0813 JN	102	}
59de0813 JN	103
ae99258f	104	u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
59de0813	105	{
5a09ae9f	106	u32 val = 0;
59de0813	107
5a09ae9f JN	108	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
5a09ae9f JN	109	DPIO_OPCODE_REG_READ, reg, &val);
59de0813	110
5a09ae9f	111	return val;
59de0813 JN	112	}
59de0813 JN	113
ae99258f	114	void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
59de0813	115	{
5a09ae9f JN	116	vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
5a09ae9f JN	117	DPIO_OPCODE_REG_WRITE, reg, &val);
59de0813 JN	118	}
	119
	120	/* SBI access */
	121	u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
	122	enum intel_sbi_destination destination)
	123	{
	124	u32 value = 0;
	125	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
	126
	127	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
	128	100)) {
	129	DRM_ERROR("timeout waiting for SBI to become ready\n");
	130	return 0;
	131	}
	132
	133	I915_WRITE(SBI_ADDR, (reg << 16));
	134
	135	if (destination == SBI_ICLK)
	136	value = SBI_CTL_DEST_ICLK \| SBI_CTL_OP_CRRD;
	137	else
	138	value = SBI_CTL_DEST_MPHY \| SBI_CTL_OP_IORD;
	139	I915_WRITE(SBI_CTL_STAT, value \| SBI_BUSY);
	140
	141	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY \| SBI_RESPONSE_FAIL)) == 0,
	142	100)) {
	143	DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
	144	return 0;
	145	}
	146
	147	return I915_READ(SBI_DATA);
	148	}
	149
	150	void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
	151	enum intel_sbi_destination destination)
	152	{
	153	u32 tmp;
	154
	155	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
	156
	157	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
	158	100)) {
	159	DRM_ERROR("timeout waiting for SBI to become ready\n");
	160	return;
	161	}
	162
	163	I915_WRITE(SBI_ADDR, (reg << 16));
	164	I915_WRITE(SBI_DATA, value);
	165
	166	if (destination == SBI_ICLK)
	167	tmp = SBI_CTL_DEST_ICLK \| SBI_CTL_OP_CRWR;
	168	else
	169	tmp = SBI_CTL_DEST_MPHY \| SBI_CTL_OP_IOWR;
	170	I915_WRITE(SBI_CTL_STAT, SBI_BUSY \| tmp);
	171
	172	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY \| SBI_RESPONSE_FAIL)) == 0,
	173	100)) {
	174	DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
	175	return;
	176	}
	177	}