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59de0813 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include "i915_drv.h" | |
26 | #include "intel_drv.h" | |
27 | ||
28 | /* IOSF sideband */ | |
5a09ae9f JN |
29 | static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
30 | u32 port, u32 opcode, u32 addr, u32 *val) | |
59de0813 | 31 | { |
5a09ae9f JN |
32 | u32 cmd, be = 0xf, bar = 0; |
33 | bool is_read = (opcode == PUNIT_OPCODE_REG_READ || | |
34 | opcode == DPIO_OPCODE_REG_READ); | |
59de0813 JN |
35 | |
36 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | | |
37 | (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | | |
38 | (bar << IOSF_BAR_SHIFT); | |
39 | ||
5a09ae9f | 40 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
59de0813 | 41 | |
5a09ae9f JN |
42 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
43 | DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n", | |
44 | is_read ? "read" : "write"); | |
59de0813 JN |
45 | return -EAGAIN; |
46 | } | |
47 | ||
48 | I915_WRITE(VLV_IOSF_ADDR, addr); | |
5a09ae9f | 49 | if (!is_read) |
59de0813 JN |
50 | I915_WRITE(VLV_IOSF_DATA, *val); |
51 | I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); | |
52 | ||
5a09ae9f JN |
53 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
54 | DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n", | |
55 | is_read ? "read" : "write"); | |
59de0813 JN |
56 | return -ETIMEDOUT; |
57 | } | |
58 | ||
5a09ae9f | 59 | if (is_read) |
59de0813 JN |
60 | *val = I915_READ(VLV_IOSF_DATA); |
61 | I915_WRITE(VLV_IOSF_DATA, 0); | |
62 | ||
63 | return 0; | |
64 | } | |
65 | ||
64936258 | 66 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr) |
59de0813 | 67 | { |
64936258 | 68 | u32 val = 0; |
5a09ae9f JN |
69 | |
70 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
71 | ||
72 | mutex_lock(&dev_priv->dpio_lock); | |
64936258 JN |
73 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
74 | PUNIT_OPCODE_REG_READ, addr, &val); | |
5a09ae9f JN |
75 | mutex_unlock(&dev_priv->dpio_lock); |
76 | ||
64936258 | 77 | return val; |
59de0813 JN |
78 | } |
79 | ||
64936258 | 80 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) |
59de0813 | 81 | { |
5a09ae9f JN |
82 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
83 | ||
84 | mutex_lock(&dev_priv->dpio_lock); | |
64936258 JN |
85 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
86 | PUNIT_OPCODE_REG_WRITE, addr, &val); | |
5a09ae9f | 87 | mutex_unlock(&dev_priv->dpio_lock); |
59de0813 JN |
88 | } |
89 | ||
64936258 | 90 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) |
59de0813 | 91 | { |
64936258 | 92 | u32 val = 0; |
5a09ae9f JN |
93 | |
94 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
95 | ||
96 | mutex_lock(&dev_priv->dpio_lock); | |
64936258 JN |
97 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC, |
98 | PUNIT_OPCODE_REG_READ, addr, &val); | |
5a09ae9f JN |
99 | mutex_unlock(&dev_priv->dpio_lock); |
100 | ||
64936258 | 101 | return val; |
59de0813 JN |
102 | } |
103 | ||
e9f882a3 JN |
104 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) |
105 | { | |
106 | u32 val = 0; | |
107 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, | |
108 | PUNIT_OPCODE_REG_READ, reg, &val); | |
109 | return val; | |
110 | } | |
111 | ||
112 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) | |
113 | { | |
114 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, | |
115 | PUNIT_OPCODE_REG_WRITE, reg, &val); | |
116 | } | |
117 | ||
118 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) | |
119 | { | |
120 | u32 val = 0; | |
121 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, | |
122 | PUNIT_OPCODE_REG_READ, reg, &val); | |
123 | return val; | |
124 | } | |
125 | ||
126 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) | |
127 | { | |
128 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, | |
129 | PUNIT_OPCODE_REG_WRITE, reg, &val); | |
130 | } | |
131 | ||
132 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) | |
133 | { | |
134 | u32 val = 0; | |
135 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, | |
136 | PUNIT_OPCODE_REG_READ, reg, &val); | |
137 | return val; | |
138 | } | |
139 | ||
140 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) | |
141 | { | |
142 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, | |
143 | PUNIT_OPCODE_REG_WRITE, reg, &val); | |
144 | } | |
145 | ||
146 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) | |
147 | { | |
148 | u32 val = 0; | |
149 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, | |
150 | PUNIT_OPCODE_REG_READ, reg, &val); | |
151 | return val; | |
152 | } | |
153 | ||
154 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) | |
155 | { | |
156 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, | |
157 | PUNIT_OPCODE_REG_WRITE, reg, &val); | |
158 | } | |
159 | ||
5e69f97f CML |
160 | static u32 vlv_get_phy_port(enum pipe pipe) |
161 | { | |
162 | u32 port = IOSF_PORT_DPIO; | |
163 | ||
164 | WARN_ON ((pipe != PIPE_A) && (pipe != PIPE_B)); | |
165 | ||
166 | return port; | |
167 | } | |
168 | ||
169 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) | |
59de0813 | 170 | { |
5a09ae9f | 171 | u32 val = 0; |
59de0813 | 172 | |
5e69f97f | 173 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe), |
5a09ae9f | 174 | DPIO_OPCODE_REG_READ, reg, &val); |
5a09ae9f | 175 | return val; |
59de0813 JN |
176 | } |
177 | ||
5e69f97f | 178 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) |
59de0813 | 179 | { |
5e69f97f | 180 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe), |
5a09ae9f | 181 | DPIO_OPCODE_REG_WRITE, reg, &val); |
59de0813 JN |
182 | } |
183 | ||
184 | /* SBI access */ | |
185 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, | |
186 | enum intel_sbi_destination destination) | |
187 | { | |
188 | u32 value = 0; | |
189 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); | |
190 | ||
191 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, | |
192 | 100)) { | |
193 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
194 | return 0; | |
195 | } | |
196 | ||
197 | I915_WRITE(SBI_ADDR, (reg << 16)); | |
198 | ||
199 | if (destination == SBI_ICLK) | |
200 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; | |
201 | else | |
202 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; | |
203 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); | |
204 | ||
205 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, | |
206 | 100)) { | |
207 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); | |
208 | return 0; | |
209 | } | |
210 | ||
211 | return I915_READ(SBI_DATA); | |
212 | } | |
213 | ||
214 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
215 | enum intel_sbi_destination destination) | |
216 | { | |
217 | u32 tmp; | |
218 | ||
219 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); | |
220 | ||
221 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, | |
222 | 100)) { | |
223 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
224 | return; | |
225 | } | |
226 | ||
227 | I915_WRITE(SBI_ADDR, (reg << 16)); | |
228 | I915_WRITE(SBI_DATA, value); | |
229 | ||
230 | if (destination == SBI_ICLK) | |
231 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; | |
232 | else | |
233 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; | |
234 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); | |
235 | ||
236 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, | |
237 | 100)) { | |
238 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); | |
239 | return; | |
240 | } | |
241 | } |