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59de0813 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include "i915_drv.h" | |
26 | #include "intel_drv.h" | |
27 | ||
d8228d0d JB |
28 | /* |
29 | * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and | |
30 | * VLV_VLV2_PUNIT_HAS_0.8.docx | |
31 | */ | |
5a09ae9f JN |
32 | static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn, |
33 | u32 port, u32 opcode, u32 addr, u32 *val) | |
59de0813 | 34 | { |
5a09ae9f JN |
35 | u32 cmd, be = 0xf, bar = 0; |
36 | bool is_read = (opcode == PUNIT_OPCODE_REG_READ || | |
37 | opcode == DPIO_OPCODE_REG_READ); | |
59de0813 JN |
38 | |
39 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | | |
40 | (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | | |
41 | (bar << IOSF_BAR_SHIFT); | |
42 | ||
5a09ae9f | 43 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
59de0813 | 44 | |
5a09ae9f JN |
45 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
46 | DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n", | |
47 | is_read ? "read" : "write"); | |
59de0813 JN |
48 | return -EAGAIN; |
49 | } | |
50 | ||
51 | I915_WRITE(VLV_IOSF_ADDR, addr); | |
5a09ae9f | 52 | if (!is_read) |
59de0813 JN |
53 | I915_WRITE(VLV_IOSF_DATA, *val); |
54 | I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); | |
55 | ||
5a09ae9f JN |
56 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { |
57 | DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n", | |
58 | is_read ? "read" : "write"); | |
59de0813 JN |
59 | return -ETIMEDOUT; |
60 | } | |
61 | ||
5a09ae9f | 62 | if (is_read) |
59de0813 JN |
63 | *val = I915_READ(VLV_IOSF_DATA); |
64 | I915_WRITE(VLV_IOSF_DATA, 0); | |
65 | ||
66 | return 0; | |
67 | } | |
68 | ||
64936258 | 69 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr) |
59de0813 | 70 | { |
64936258 | 71 | u32 val = 0; |
5a09ae9f JN |
72 | |
73 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
74 | ||
75 | mutex_lock(&dev_priv->dpio_lock); | |
64936258 JN |
76 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
77 | PUNIT_OPCODE_REG_READ, addr, &val); | |
5a09ae9f JN |
78 | mutex_unlock(&dev_priv->dpio_lock); |
79 | ||
64936258 | 80 | return val; |
59de0813 JN |
81 | } |
82 | ||
64936258 | 83 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) |
59de0813 | 84 | { |
5a09ae9f JN |
85 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
86 | ||
87 | mutex_lock(&dev_priv->dpio_lock); | |
64936258 JN |
88 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT, |
89 | PUNIT_OPCODE_REG_WRITE, addr, &val); | |
5a09ae9f | 90 | mutex_unlock(&dev_priv->dpio_lock); |
59de0813 JN |
91 | } |
92 | ||
64936258 | 93 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) |
59de0813 | 94 | { |
64936258 | 95 | u32 val = 0; |
5a09ae9f JN |
96 | |
97 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
98 | ||
99 | mutex_lock(&dev_priv->dpio_lock); | |
64936258 JN |
100 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC, |
101 | PUNIT_OPCODE_REG_READ, addr, &val); | |
5a09ae9f JN |
102 | mutex_unlock(&dev_priv->dpio_lock); |
103 | ||
64936258 | 104 | return val; |
59de0813 JN |
105 | } |
106 | ||
e9f882a3 JN |
107 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg) |
108 | { | |
109 | u32 val = 0; | |
110 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, | |
111 | PUNIT_OPCODE_REG_READ, reg, &val); | |
112 | return val; | |
113 | } | |
114 | ||
115 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) | |
116 | { | |
117 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC, | |
118 | PUNIT_OPCODE_REG_WRITE, reg, &val); | |
119 | } | |
120 | ||
121 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) | |
122 | { | |
123 | u32 val = 0; | |
124 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, | |
125 | PUNIT_OPCODE_REG_READ, reg, &val); | |
126 | return val; | |
127 | } | |
128 | ||
129 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) | |
130 | { | |
131 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK, | |
132 | PUNIT_OPCODE_REG_WRITE, reg, &val); | |
133 | } | |
134 | ||
135 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg) | |
136 | { | |
137 | u32 val = 0; | |
138 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, | |
139 | PUNIT_OPCODE_REG_READ, reg, &val); | |
140 | return val; | |
141 | } | |
142 | ||
143 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) | |
144 | { | |
145 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU, | |
146 | PUNIT_OPCODE_REG_WRITE, reg, &val); | |
147 | } | |
148 | ||
149 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg) | |
150 | { | |
151 | u32 val = 0; | |
152 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, | |
153 | PUNIT_OPCODE_REG_READ, reg, &val); | |
154 | return val; | |
155 | } | |
156 | ||
157 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) | |
158 | { | |
159 | vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE, | |
160 | PUNIT_OPCODE_REG_WRITE, reg, &val); | |
161 | } | |
162 | ||
5e69f97f CML |
163 | static u32 vlv_get_phy_port(enum pipe pipe) |
164 | { | |
165 | u32 port = IOSF_PORT_DPIO; | |
166 | ||
167 | WARN_ON ((pipe != PIPE_A) && (pipe != PIPE_B)); | |
168 | ||
169 | return port; | |
170 | } | |
171 | ||
172 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) | |
59de0813 | 173 | { |
5a09ae9f | 174 | u32 val = 0; |
59de0813 | 175 | |
5e69f97f | 176 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe), |
5a09ae9f | 177 | DPIO_OPCODE_REG_READ, reg, &val); |
5a09ae9f | 178 | return val; |
59de0813 JN |
179 | } |
180 | ||
5e69f97f | 181 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) |
59de0813 | 182 | { |
5e69f97f | 183 | vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe), |
5a09ae9f | 184 | DPIO_OPCODE_REG_WRITE, reg, &val); |
59de0813 JN |
185 | } |
186 | ||
187 | /* SBI access */ | |
188 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, | |
189 | enum intel_sbi_destination destination) | |
190 | { | |
191 | u32 value = 0; | |
192 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); | |
193 | ||
194 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, | |
195 | 100)) { | |
196 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
197 | return 0; | |
198 | } | |
199 | ||
200 | I915_WRITE(SBI_ADDR, (reg << 16)); | |
201 | ||
202 | if (destination == SBI_ICLK) | |
203 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; | |
204 | else | |
205 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; | |
206 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); | |
207 | ||
208 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, | |
209 | 100)) { | |
210 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); | |
211 | return 0; | |
212 | } | |
213 | ||
214 | return I915_READ(SBI_DATA); | |
215 | } | |
216 | ||
217 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
218 | enum intel_sbi_destination destination) | |
219 | { | |
220 | u32 tmp; | |
221 | ||
222 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); | |
223 | ||
224 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, | |
225 | 100)) { | |
226 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
227 | return; | |
228 | } | |
229 | ||
230 | I915_WRITE(SBI_ADDR, (reg << 16)); | |
231 | I915_WRITE(SBI_DATA, value); | |
232 | ||
233 | if (destination == SBI_ICLK) | |
234 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; | |
235 | else | |
236 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; | |
237 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); | |
238 | ||
239 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, | |
240 | 100)) { | |
241 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); | |
242 | return; | |
243 | } | |
244 | } |