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drm/i915: Embed the io-mapping struct inside drm_i915_private
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sprite.c
CommitLineData
b840d907
JB		 1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_fourcc.h>
1731693a 35#include <drm/drm_rect.h>
c331879c 36#include <drm/drm_atomic.h>
ea2c67bb 37#include <drm/drm_plane_helper.h>
b840d907 38#include "intel_drv.h"
5d723d7a 39#include "intel_frontbuffer.h"
760285e7 40#include <drm/i915_drm.h>
b840d907
JB		 41#include "i915_drv.h"
42
6ca2aeb2
VS		 43static bool
44format_is_yuv(uint32_t format)
45{
46 switch (format) {
47 case DRM_FORMAT_YUYV:
48 case DRM_FORMAT_UYVY:
49 case DRM_FORMAT_VYUY:
50 case DRM_FORMAT_YVYU:
51 return true;
52 default:
53 return false;
54 }
55}
56
dfd2e9ab
VS		 57int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
58 int usecs)
8d7849db
VS		 59{
60 /* paranoia */
5e7234c9 61 if (!adjusted_mode->crtc_htotal)
8d7849db
VS		 62 return 1;
63
5e7234c9
VS		 64 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
65 1000 * adjusted_mode->crtc_htotal);
8d7849db
VS		 66}
67
26ff2762
ACO		 68/**
69 * intel_pipe_update_start() - start update of a set of display registers
70 * @crtc: the crtc of which the registers are going to be updated
71 * @start_vbl_count: vblank counter return pointer used for error checking
72 *
73 * Mark the start of an update to pipe registers that should be updated
74 * atomically regarding vblank. If the next vblank will happens within
75 * the next 100 us, this function waits until the vblank passes.
76 *
77 * After a successful call to this function, interrupts will be disabled
78 * until a subsequent call to intel_pipe_update_end(). That is done to
79 * avoid random delays. The value written to @start_vbl_count should be
80 * supplied to intel_pipe_update_end() for error checking.
26ff2762 81 */
34e0adbb 82void intel_pipe_update_start(struct intel_crtc *crtc)
8d7849db 83{
124abe07 84 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
8d7849db
VS		 85 long timeout = msecs_to_jiffies_timeout(1);
86 int scanline, min, max, vblank_start;
210871b6 87 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
8d7849db
VS		 88 DEFINE_WAIT(wait);
89
124abe07
VS		 90 vblank_start = adjusted_mode->crtc_vblank_start;
91 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
8d7849db
VS		 92 vblank_start = DIV_ROUND_UP(vblank_start, 2);
93
94 /* FIXME needs to be calibrated sensibly */
dfd2e9ab 95 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100);
8d7849db
VS		 96 max = vblank_start - 1;
97
8f539a83 98 local_irq_disable();
8f539a83 99
8d7849db 100 if (min <= 0 || max <= 0)
8f539a83 101 return;
8d7849db 102
1e3feefd 103 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
8f539a83 104 return;
8d7849db 105
d637ce3f
JB		 106 crtc->debug.min_vbl = min;
107 crtc->debug.max_vbl = max;
108 trace_i915_pipe_update_start(crtc);
25ef284a 109
8d7849db
VS		 110 for (;;) {
111 /*
112 * prepare_to_wait() has a memory barrier, which guarantees
113 * other CPUs can see the task state update by the time we
114 * read the scanline.
115 */
210871b6 116 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
8d7849db
VS		 117
118 scanline = intel_get_crtc_scanline(crtc);
119 if (scanline < min || scanline > max)
120 break;
121
122 if (timeout <= 0) {
123 DRM_ERROR("Potential atomic update failure on pipe %c\n",
124 pipe_name(crtc->pipe));
125 break;
126 }
127
128 local_irq_enable();
129
130 timeout = schedule_timeout(timeout);
131
132 local_irq_disable();
133 }
134
210871b6 135 finish_wait(wq, &wait);
8d7849db 136
1e3feefd 137 drm_crtc_vblank_put(&crtc->base);
8d7849db 138
eb120ef6
JB		 139 crtc->debug.scanline_start = scanline;
140 crtc->debug.start_vbl_time = ktime_get();
a2991414 141 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
8d7849db 142
d637ce3f 143 trace_i915_pipe_update_vblank_evaded(crtc);
8d7849db
VS		 144}
145
26ff2762
ACO		 146/**
147 * intel_pipe_update_end() - end update of a set of display registers
148 * @crtc: the crtc of which the registers were updated
149 * @start_vbl_count: start vblank counter (used for error checking)
150 *
151 * Mark the end of an update started with intel_pipe_update_start(). This
152 * re-enables interrupts and verifies the update was actually completed
153 * before a vblank using the value of @start_vbl_count.
154 */
51cbaf01 155void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
8d7849db 156{
8d7849db 157 enum pipe pipe = crtc->pipe;
eb120ef6 158 int scanline_end = intel_get_crtc_scanline(crtc);
a2991414 159 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
85a62bf9 160 ktime_t end_vbl_time = ktime_get();
8d7849db 161
51cbaf01
ML		 162 if (work) {
163 work->flip_queued_vblank = end_vbl_count;
164 smp_mb__before_atomic();
165 atomic_set(&work->pending, 1);
166 }
167
d637ce3f 168 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
25ef284a 169
1f7528c4
DV		 170 /* We're still in the vblank-evade critical section, this can't race.
171 * Would be slightly nice to just grab the vblank count and arm the
172 * event outside of the critical section - the spinlock might spin for a
173 * while ... */
174 if (crtc->base.state->event) {
175 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
176
177 spin_lock(&crtc->base.dev->event_lock);
178 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
179 spin_unlock(&crtc->base.dev->event_lock);
180
181 crtc->base.state->event = NULL;
182 }
183
8d7849db
VS		 184 local_irq_enable();
185
eb120ef6
JB		 186 if (crtc->debug.start_vbl_count &&
187 crtc->debug.start_vbl_count != end_vbl_count) {
188 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
189 pipe_name(pipe), crtc->debug.start_vbl_count,
190 end_vbl_count,
191 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
192 crtc->debug.min_vbl, crtc->debug.max_vbl,
193 crtc->debug.scanline_start, scanline_end);
194 }
8d7849db
VS		 195}
196
dc2a41b4 197static void
2fde1391
ML		 198skl_update_plane(struct drm_plane *drm_plane,
199 const struct intel_crtc_state *crtc_state,
200 const struct intel_plane_state *plane_state)
dc2a41b4
DL		 201{
202 struct drm_device *dev = drm_plane->dev;
fac5e23e 203 struct drm_i915_private *dev_priv = to_i915(dev);
dc2a41b4 204 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
2fde1391 205 struct drm_framebuffer *fb = plane_state->base.fb;
dc2a41b4
DL		 206 const int pipe = intel_plane->pipe;
207 const int plane = intel_plane->plane + 1;
d2196774 208 u32 plane_ctl;
2fde1391 209 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
b63a16f6 210 u32 surf_addr = plane_state->main.offset;
8d0deca8 211 unsigned int rotation = plane_state->base.rotation;
d2196774 212 u32 stride = skl_plane_stride(fb, 0, rotation);
936e71e3
VS		 213 int crtc_x = plane_state->base.dst.x1;
214 int crtc_y = plane_state->base.dst.y1;
215 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
216 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
b63a16f6
VS		 217 uint32_t x = plane_state->main.x;
218 uint32_t y = plane_state->main.y;
936e71e3
VS		 219 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
220 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
dc2a41b4 221
48fe4691 222 plane_ctl = PLANE_CTL_ENABLE |
e12c8ce8 223 PLANE_CTL_PIPE_GAMMA_ENABLE |
48fe4691 224 PLANE_CTL_PIPE_CSC_ENABLE;
dc2a41b4 225
c331879c
CK		 226 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
227 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
b321803d 228
c331879c 229 plane_ctl |= skl_plane_ctl_rotation(rotation);
dc2a41b4 230
47ecbb20
VS		 231 if (key->flags) {
232 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
233 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
234 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
235 }
236
237 if (key->flags & I915_SET_COLORKEY_DESTINATION)
238 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
239 else if (key->flags & I915_SET_COLORKEY_SOURCE)
240 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
241
6687c906
VS		 242 /* Sizes are 0 based */
243 src_w--;
244 src_h--;
245 crtc_w--;
246 crtc_h--;
247
248 I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
ef78ec94 249 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
6687c906 250 I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w);
c331879c
CK		 251
252 /* program plane scaler */
2fde1391 253 if (plane_state->scaler_id >= 0) {
2fde1391 254 int scaler_id = plane_state->scaler_id;
7494bcdc 255 const struct intel_scaler *scaler;
c331879c
CK		 256
257 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
258 PS_PLANE_SEL(plane));
7494bcdc
ID		 259
260 scaler = &crtc_state->scaler_state.scalers[scaler_id];
261
262 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
263 PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode);
c331879c
CK		 264 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
265 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
266 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
267 ((crtc_w + 1) << 16)|(crtc_h + 1));
268
269 I915_WRITE(PLANE_POS(pipe, plane), 0);
270 } else {
271 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
272 }
273
dc2a41b4 274 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
6687c906
VS		 275 I915_WRITE(PLANE_SURF(pipe, plane),
276 intel_fb_gtt_offset(fb, rotation) + surf_addr);
dc2a41b4
DL		 277 POSTING_READ(PLANE_SURF(pipe, plane));
278}
279
280static void
7fabf5ef 281skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
dc2a41b4 282{
a8ad0d8e 283 struct drm_device *dev = dplane->dev;
fac5e23e 284 struct drm_i915_private *dev_priv = to_i915(dev);
a8ad0d8e 285 struct intel_plane *intel_plane = to_intel_plane(dplane);
dc2a41b4
DL		 286 const int pipe = intel_plane->pipe;
287 const int plane = intel_plane->plane + 1;
288
48fe4691 289 I915_WRITE(PLANE_CTL(pipe, plane), 0);
dc2a41b4 290
2ddc1dad
VS		 291 I915_WRITE(PLANE_SURF(pipe, plane), 0);
292 POSTING_READ(PLANE_SURF(pipe, plane));
dc2a41b4
DL		 293}
294
6ca2aeb2
VS		 295static void
296chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
297{
fac5e23e 298 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
6ca2aeb2
VS		 299 int plane = intel_plane->plane;
300
301 /* Seems RGB data bypasses the CSC always */
302 if (!format_is_yuv(format))
303 return;
304
305 /*
306 * BT.601 limited range YCbCr -> full range RGB
307 *
308 * |r| | 6537 4769 0| |cr |
309 * |g| = |-3330 4769 -1605| x |y-64|
310 * |b| | 0 4769 8263| |cb |
311 *
312 * Cb and Cr apparently come in as signed already, so no
313 * need for any offset. For Y we need to remove the offset.
314 */
315 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
316 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
317 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
318
319 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
320 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
321 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
322 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
323 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
324
325 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
326 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
327 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
328
329 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
330 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
331 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
332}
333
7f1f3851 334static void
2fde1391
ML		 335vlv_update_plane(struct drm_plane *dplane,
336 const struct intel_crtc_state *crtc_state,
337 const struct intel_plane_state *plane_state)
7f1f3851
JB		 338{
339 struct drm_device *dev = dplane->dev;
fac5e23e 340 struct drm_i915_private *dev_priv = to_i915(dev);
7f1f3851 341 struct intel_plane *intel_plane = to_intel_plane(dplane);
2fde1391 342 struct drm_framebuffer *fb = plane_state->base.fb;
7f1f3851
JB		 343 int pipe = intel_plane->pipe;
344 int plane = intel_plane->plane;
345 u32 sprctl;
54ea9da8 346 u32 sprsurf_offset, linear_offset;
8d0deca8 347 unsigned int rotation = dplane->state->rotation;
2fde1391 348 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
936e71e3
VS		 349 int crtc_x = plane_state->base.dst.x1;
350 int crtc_y = plane_state->base.dst.y1;
351 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
352 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
353 uint32_t x = plane_state->base.src.x1 >> 16;
354 uint32_t y = plane_state->base.src.y1 >> 16;
355 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
356 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
7f1f3851 357
48fe4691 358 sprctl = SP_ENABLE;
7f1f3851
JB		 359
360 switch (fb->pixel_format) {
361 case DRM_FORMAT_YUYV:
362 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
363 break;
364 case DRM_FORMAT_YVYU:
365 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
366 break;
367 case DRM_FORMAT_UYVY:
368 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
369 break;
370 case DRM_FORMAT_VYUY:
371 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
372 break;
373 case DRM_FORMAT_RGB565:
374 sprctl |= SP_FORMAT_BGR565;
375 break;
376 case DRM_FORMAT_XRGB8888:
377 sprctl |= SP_FORMAT_BGRX8888;
378 break;
379 case DRM_FORMAT_ARGB8888:
380 sprctl |= SP_FORMAT_BGRA8888;
381 break;
382 case DRM_FORMAT_XBGR2101010:
383 sprctl |= SP_FORMAT_RGBX1010102;
384 break;
385 case DRM_FORMAT_ABGR2101010:
386 sprctl |= SP_FORMAT_RGBA1010102;
387 break;
388 case DRM_FORMAT_XBGR8888:
389 sprctl |= SP_FORMAT_RGBX8888;
390 break;
391 case DRM_FORMAT_ABGR8888:
392 sprctl |= SP_FORMAT_RGBA8888;
393 break;
394 default:
395 /*
396 * If we get here one of the upper layers failed to filter
397 * out the unsupported plane formats
398 */
399 BUG();
400 break;
401 }
402
4ea67bc7
VS		 403 /*
404 * Enable gamma to match primary/cursor plane behaviour.
405 * FIXME should be user controllable via propertiesa.
406 */
407 sprctl |= SP_GAMMA_ENABLE;
408
72618ebf 409 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
7f1f3851
JB		 410 sprctl |= SP_TILED;
411
7f1f3851
JB		 412 /* Sizes are 0 based */
413 src_w--;
414 src_h--;
415 crtc_w--;
416 crtc_h--;
417
2949056c
VS		 418 intel_add_fb_offsets(&x, &y, plane_state, 0);
419 sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
7f1f3851 420
31ad61e4 421 if (rotation == DRM_ROTATE_180) {
76eebda7
VS		 422 sprctl |= SP_ROTATE_180;
423
424 x += src_w;
425 y += src_h;
76eebda7
VS		 426 }
427
2949056c 428 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
6687c906 429
47ecbb20
VS		 430 if (key->flags) {
431 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
432 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
433 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
434 }
435
436 if (key->flags & I915_SET_COLORKEY_SOURCE)
437 sprctl |= SP_SOURCE_KEY;
438
6ca2aeb2
VS		 439 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
440 chv_update_csc(intel_plane, fb->pixel_format);
441
ca6ad025
VS		 442 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
443 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
444
72618ebf 445 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
7f1f3851
JB		 446 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
447 else
448 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
449
c14b0485
VS		 450 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
451
7f1f3851
JB		 452 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
453 I915_WRITE(SPCNTR(pipe, plane), sprctl);
6687c906
VS		 454 I915_WRITE(SPSURF(pipe, plane),
455 intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
b12ce1d8 456 POSTING_READ(SPSURF(pipe, plane));
7f1f3851
JB		 457}
458
459static void
7fabf5ef 460vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
7f1f3851
JB		 461{
462 struct drm_device *dev = dplane->dev;
fac5e23e 463 struct drm_i915_private *dev_priv = to_i915(dev);
7f1f3851
JB		 464 struct intel_plane *intel_plane = to_intel_plane(dplane);
465 int pipe = intel_plane->pipe;
466 int plane = intel_plane->plane;
467
48fe4691
VS		 468 I915_WRITE(SPCNTR(pipe, plane), 0);
469
85ba7b7d 470 I915_WRITE(SPSURF(pipe, plane), 0);
b12ce1d8 471 POSTING_READ(SPSURF(pipe, plane));
7f1f3851
JB		 472}
473
b840d907 474static void
2fde1391
ML		 475ivb_update_plane(struct drm_plane *plane,
476 const struct intel_crtc_state *crtc_state,
477 const struct intel_plane_state *plane_state)
b840d907
JB		 478{
479 struct drm_device *dev = plane->dev;
fac5e23e 480 struct drm_i915_private *dev_priv = to_i915(dev);
b840d907 481 struct intel_plane *intel_plane = to_intel_plane(plane);
2fde1391 482 struct drm_framebuffer *fb = plane_state->base.fb;
47ecbb20 483 enum pipe pipe = intel_plane->pipe;
b840d907 484 u32 sprctl, sprscale = 0;
54ea9da8 485 u32 sprsurf_offset, linear_offset;
8d0deca8 486 unsigned int rotation = plane_state->base.rotation;
2fde1391 487 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
936e71e3
VS		 488 int crtc_x = plane_state->base.dst.x1;
489 int crtc_y = plane_state->base.dst.y1;
490 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
491 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
492 uint32_t x = plane_state->base.src.x1 >> 16;
493 uint32_t y = plane_state->base.src.y1 >> 16;
494 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
495 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
b840d907 496
48fe4691 497 sprctl = SPRITE_ENABLE;
b840d907
JB		 498
499 switch (fb->pixel_format) {
500 case DRM_FORMAT_XBGR8888:
5ee36913 501 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
b840d907
JB		 502 break;
503 case DRM_FORMAT_XRGB8888:
5ee36913 504 sprctl |= SPRITE_FORMAT_RGBX888;
b840d907
JB		 505 break;
506 case DRM_FORMAT_YUYV:
507 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
b840d907
JB		 508 break;
509 case DRM_FORMAT_YVYU:
510 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
b840d907
JB		 511 break;
512 case DRM_FORMAT_UYVY:
513 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
b840d907
JB		 514 break;
515 case DRM_FORMAT_VYUY:
516 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
b840d907
JB		 517 break;
518 default:
28d491df 519 BUG();
b840d907
JB		 520 }
521
4ea67bc7
VS		 522 /*
523 * Enable gamma to match primary/cursor plane behaviour.
524 * FIXME should be user controllable via propertiesa.
525 */
526 sprctl |= SPRITE_GAMMA_ENABLE;
527
72618ebf 528 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
b840d907
JB		 529 sprctl |= SPRITE_TILED;
530
b42c6009 531 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1f5d76db
PZ		 532 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
533 else
534 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
535
6bbfa1c5 536 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
86d3efce
VS		 537 sprctl |= SPRITE_PIPE_CSC_ENABLE;
538
b840d907
JB		 539 /* Sizes are 0 based */
540 src_w--;
541 src_h--;
542 crtc_w--;
543 crtc_h--;
544
8553c18e 545 if (crtc_w != src_w || crtc_h != src_h)
b840d907 546 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
b840d907 547
2949056c
VS		 548 intel_add_fb_offsets(&x, &y, plane_state, 0);
549 sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
5a35e99e 550
31ad61e4 551 if (rotation == DRM_ROTATE_180) {
76eebda7
VS		 552 sprctl |= SPRITE_ROTATE_180;
553
554 /* HSW and BDW does this automagically in hardware */
555 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
556 x += src_w;
557 y += src_h;
76eebda7
VS		 558 }
559 }
560
2949056c 561 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
6687c906 562
47ecbb20
VS		 563 if (key->flags) {
564 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
565 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
566 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
567 }
568
569 if (key->flags & I915_SET_COLORKEY_DESTINATION)
570 sprctl |= SPRITE_DEST_KEY;
571 else if (key->flags & I915_SET_COLORKEY_SOURCE)
572 sprctl |= SPRITE_SOURCE_KEY;
573
ca6ad025
VS		 574 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
575 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
576
5a35e99e
DL		 577 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
578 * register */
b3dc685e 579 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
c54173a8 580 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
72618ebf 581 else if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
b840d907 582 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
5a35e99e
DL		 583 else
584 I915_WRITE(SPRLINOFF(pipe), linear_offset);
c54173a8 585
b840d907 586 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
2d354c34
DL		 587 if (intel_plane->can_scale)
588 I915_WRITE(SPRSCALE(pipe), sprscale);
b840d907 589 I915_WRITE(SPRCTL(pipe), sprctl);
85ba7b7d 590 I915_WRITE(SPRSURF(pipe),
6687c906 591 intel_fb_gtt_offset(fb, rotation) + sprsurf_offset);
b12ce1d8 592 POSTING_READ(SPRSURF(pipe));
b840d907
JB		 593}
594
595static void
7fabf5ef 596ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
b840d907
JB		 597{
598 struct drm_device *dev = plane->dev;
fac5e23e 599 struct drm_i915_private *dev_priv = to_i915(dev);
b840d907
JB		 600 struct intel_plane *intel_plane = to_intel_plane(plane);
601 int pipe = intel_plane->pipe;
602
c562657a 603 I915_WRITE(SPRCTL(pipe), 0);
b840d907 604 /* Can't leave the scaler enabled... */
2d354c34
DL		 605 if (intel_plane->can_scale)
606 I915_WRITE(SPRSCALE(pipe), 0);
5b633d6b 607
b12ce1d8
VS		 608 I915_WRITE(SPRSURF(pipe), 0);
609 POSTING_READ(SPRSURF(pipe));
b840d907
JB		 610}
611
612static void
2fde1391
ML		 613ilk_update_plane(struct drm_plane *plane,
614 const struct intel_crtc_state *crtc_state,
615 const struct intel_plane_state *plane_state)
b840d907
JB		 616{
617 struct drm_device *dev = plane->dev;
fac5e23e 618 struct drm_i915_private *dev_priv = to_i915(dev);
b840d907 619 struct intel_plane *intel_plane = to_intel_plane(plane);
2fde1391 620 struct drm_framebuffer *fb = plane_state->base.fb;
2bd3c3cb 621 int pipe = intel_plane->pipe;
8aaa81a1 622 u32 dvscntr, dvsscale;
54ea9da8 623 u32 dvssurf_offset, linear_offset;
8d0deca8 624 unsigned int rotation = plane_state->base.rotation;
2fde1391 625 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
936e71e3
VS		 626 int crtc_x = plane_state->base.dst.x1;
627 int crtc_y = plane_state->base.dst.y1;
628 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
629 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
630 uint32_t x = plane_state->base.src.x1 >> 16;
631 uint32_t y = plane_state->base.src.y1 >> 16;
632 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
633 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
b840d907 634
48fe4691 635 dvscntr = DVS_ENABLE;
b840d907
JB		 636
637 switch (fb->pixel_format) {
638 case DRM_FORMAT_XBGR8888:
ab2f9df1 639 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
b840d907
JB		 640 break;
641 case DRM_FORMAT_XRGB8888:
ab2f9df1 642 dvscntr |= DVS_FORMAT_RGBX888;
b840d907
JB		 643 break;
644 case DRM_FORMAT_YUYV:
645 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
b840d907
JB		 646 break;
647 case DRM_FORMAT_YVYU:
648 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
b840d907
JB		 649 break;
650 case DRM_FORMAT_UYVY:
651 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
b840d907
JB		 652 break;
653 case DRM_FORMAT_VYUY:
654 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
b840d907
JB		 655 break;
656 default:
28d491df 657 BUG();
b840d907
JB		 658 }
659
4ea67bc7
VS		 660 /*
661 * Enable gamma to match primary/cursor plane behaviour.
662 * FIXME should be user controllable via propertiesa.
663 */
664 dvscntr |= DVS_GAMMA_ENABLE;
665
72618ebf 666 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
b840d907
JB		 667 dvscntr |= DVS_TILED;
668
d1686ae3
CW		 669 if (IS_GEN6(dev))
670 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
b840d907
JB		 671
672 /* Sizes are 0 based */
673 src_w--;
674 src_h--;
675 crtc_w--;
676 crtc_h--;
677
8aaa81a1 678 dvsscale = 0;
8368f014 679 if (crtc_w != src_w || crtc_h != src_h)
b840d907
JB		 680 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
681
2949056c
VS		 682 intel_add_fb_offsets(&x, &y, plane_state, 0);
683 dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
5a35e99e 684
31ad61e4 685 if (rotation == DRM_ROTATE_180) {
76eebda7
VS		 686 dvscntr |= DVS_ROTATE_180;
687
688 x += src_w;
689 y += src_h;
76eebda7
VS		 690 }
691
2949056c 692 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
6687c906 693
47ecbb20
VS		 694 if (key->flags) {
695 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
696 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
697 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
698 }
699
700 if (key->flags & I915_SET_COLORKEY_DESTINATION)
701 dvscntr |= DVS_DEST_KEY;
702 else if (key->flags & I915_SET_COLORKEY_SOURCE)
703 dvscntr |= DVS_SOURCE_KEY;
704
ca6ad025
VS		 705 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
706 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
707
72618ebf 708 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
b840d907 709 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
5a35e99e
DL		 710 else
711 I915_WRITE(DVSLINOFF(pipe), linear_offset);
b840d907 712
b840d907
JB		 713 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
714 I915_WRITE(DVSSCALE(pipe), dvsscale);
715 I915_WRITE(DVSCNTR(pipe), dvscntr);
85ba7b7d 716 I915_WRITE(DVSSURF(pipe),
6687c906 717 intel_fb_gtt_offset(fb, rotation) + dvssurf_offset);
b12ce1d8 718 POSTING_READ(DVSSURF(pipe));
b840d907
JB		 719}
720
721static void
7fabf5ef 722ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
b840d907
JB		 723{
724 struct drm_device *dev = plane->dev;
fac5e23e 725 struct drm_i915_private *dev_priv = to_i915(dev);
b840d907
JB		 726 struct intel_plane *intel_plane = to_intel_plane(plane);
727 int pipe = intel_plane->pipe;
728
48fe4691 729 I915_WRITE(DVSCNTR(pipe), 0);
b840d907
JB		 730 /* Disable the scaler */
731 I915_WRITE(DVSSCALE(pipe), 0);
48fe4691 732
85ba7b7d 733 I915_WRITE(DVSSURF(pipe), 0);
b12ce1d8 734 POSTING_READ(DVSSURF(pipe));
b840d907
JB		 735}
736
737static int
96d61a7f 738intel_check_sprite_plane(struct drm_plane *plane,
061e4b8d 739 struct intel_crtc_state *crtc_state,
96d61a7f 740 struct intel_plane_state *state)
b840d907 741{
c331879c 742 struct drm_device *dev = plane->dev;
061e4b8d
ML		 743 struct drm_crtc *crtc = state->base.crtc;
744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b840d907 745 struct intel_plane *intel_plane = to_intel_plane(plane);
2b875c22 746 struct drm_framebuffer *fb = state->base.fb;
96d61a7f
GP		 747 int crtc_x, crtc_y;
748 unsigned int crtc_w, crtc_h;
749 uint32_t src_x, src_y, src_w, src_h;
936e71e3
VS		 750 struct drm_rect *src = &state->base.src;
751 struct drm_rect *dst = &state->base.dst;
96d61a7f 752 const struct drm_rect *clip = &state->clip;
1731693a
VS		 753 int hscale, vscale;
754 int max_scale, min_scale;
225c228a 755 bool can_scale;
b63a16f6 756 int ret;
cf4c7c12 757
f8856a44
VS		 758 src->x1 = state->base.src_x;
759 src->y1 = state->base.src_y;
760 src->x2 = state->base.src_x + state->base.src_w;
761 src->y2 = state->base.src_y + state->base.src_h;
762
763 dst->x1 = state->base.crtc_x;
764 dst->y1 = state->base.crtc_y;
765 dst->x2 = state->base.crtc_x + state->base.crtc_w;
766 dst->y2 = state->base.crtc_y + state->base.crtc_h;
767
cf4c7c12 768 if (!fb) {
936e71e3 769 state->base.visible = false;
da20eabd 770 return 0;
cf4c7c12 771 }
5e1bac2f 772
1731693a
VS		 773 /* Don't modify another pipe's plane */
774 if (intel_plane->pipe != intel_crtc->pipe) {
775 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
b840d907 776 return -EINVAL;
1731693a 777 }
b840d907 778
1731693a
VS		 779 /* FIXME check all gen limits */
780 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
781 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
b840d907 782 return -EINVAL;
1731693a 783 }
b840d907 784
225c228a
CK		 785 /* setup can_scale, min_scale, max_scale */
786 if (INTEL_INFO(dev)->gen >= 9) {
787 /* use scaler when colorkey is not required */
818ed961 788 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
225c228a
CK		 789 can_scale = 1;
790 min_scale = 1;
791 max_scale = skl_max_scale(intel_crtc, crtc_state);
792 } else {
793 can_scale = 0;
794 min_scale = DRM_PLANE_HELPER_NO_SCALING;
795 max_scale = DRM_PLANE_HELPER_NO_SCALING;
796 }
797 } else {
798 can_scale = intel_plane->can_scale;
799 max_scale = intel_plane->max_downscale << 16;
800 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
801 }
802
3c3686cd
VS		 803 /*
804 * FIXME the following code does a bunch of fuzzy adjustments to the
805 * coordinates and sizes. We probably need some way to decide whether
806 * more strict checking should be done instead.
807 */
96d61a7f 808 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
8e7d688b 809 state->base.rotation);
76eebda7 810
96d61a7f 811 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
3c3686cd 812 BUG_ON(hscale < 0);
1731693a 813
96d61a7f 814 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
3c3686cd 815 BUG_ON(vscale < 0);
b840d907 816
936e71e3 817 state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
b840d907 818
96d61a7f
GP		 819 crtc_x = dst->x1;
820 crtc_y = dst->y1;
821 crtc_w = drm_rect_width(dst);
822 crtc_h = drm_rect_height(dst);
2d354c34 823
936e71e3 824 if (state->base.visible) {
3c3686cd 825 /* check again in case clipping clamped the results */
96d61a7f 826 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
3c3686cd
VS		 827 if (hscale < 0) {
828 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
c70f577a
VS		 829 drm_rect_debug_print("src: ", src, true);
830 drm_rect_debug_print("dst: ", dst, false);
3c3686cd
VS		 831
832 return hscale;
833 }
834
96d61a7f 835 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
3c3686cd
VS		 836 if (vscale < 0) {
837 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
c70f577a
VS		 838 drm_rect_debug_print("src: ", src, true);
839 drm_rect_debug_print("dst: ", dst, false);
3c3686cd
VS		 840
841 return vscale;
842 }
843
1731693a 844 /* Make the source viewport size an exact multiple of the scaling factors. */
96d61a7f
GP		 845 drm_rect_adjust_size(src,
846 drm_rect_width(dst) * hscale - drm_rect_width(src),
847 drm_rect_height(dst) * vscale - drm_rect_height(src));
1731693a 848
96d61a7f 849 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
8e7d688b 850 state->base.rotation);
76eebda7 851
1731693a 852 /* sanity check to make sure the src viewport wasn't enlarged */
ea2c67bb
MR		 853 WARN_ON(src->x1 < (int) state->base.src_x ||
854 src->y1 < (int) state->base.src_y ||
855 src->x2 > (int) state->base.src_x + state->base.src_w ||
856 src->y2 > (int) state->base.src_y + state->base.src_h);
1731693a
VS		 857
858 /*
859 * Hardware doesn't handle subpixel coordinates.
860 * Adjust to (macro)pixel boundary, but be careful not to
861 * increase the source viewport size, because that could
862 * push the downscaling factor out of bounds.
1731693a 863 */
96d61a7f
GP		 864 src_x = src->x1 >> 16;
865 src_w = drm_rect_width(src) >> 16;
866 src_y = src->y1 >> 16;
867 src_h = drm_rect_height(src) >> 16;
1731693a
VS		 868
869 if (format_is_yuv(fb->pixel_format)) {
870 src_x &= ~1;
871 src_w &= ~1;
872
873 /*
874 * Must keep src and dst the
875 * same if we can't scale.
876 */
225c228a 877 if (!can_scale)
1731693a
VS		 878 crtc_w &= ~1;
879
880 if (crtc_w == 0)
936e71e3 881 state->base.visible = false;
1731693a
VS		 882 }
883 }
884
885 /* Check size restrictions when scaling */
936e71e3 886 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
1731693a 887 unsigned int width_bytes;
ac484963 888 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
1731693a 889
225c228a 890 WARN_ON(!can_scale);
1731693a
VS		 891
892 /* FIXME interlacing min height is 6 */
893
894 if (crtc_w < 3 || crtc_h < 3)
936e71e3 895 state->base.visible = false;
1731693a
VS		 896
897 if (src_w < 3 || src_h < 3)
936e71e3 898 state->base.visible = false;
1731693a 899
ac484963 900 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1731693a 901
c331879c
CK		 902 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
903 width_bytes > 4096 || fb->pitches[0] > 4096)) {
1731693a
VS		 904 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
905 return -EINVAL;
906 }
907 }
908
936e71e3 909 if (state->base.visible) {
0a5ae1b0
CK		 910 src->x1 = src_x << 16;
911 src->x2 = (src_x + src_w) << 16;
912 src->y1 = src_y << 16;
913 src->y2 = (src_y + src_h) << 16;
96d61a7f
GP		 914 }
915
916 dst->x1 = crtc_x;
917 dst->x2 = crtc_x + crtc_w;
918 dst->y1 = crtc_y;
919 dst->y2 = crtc_y + crtc_h;
920
b63a16f6
VS		 921 if (INTEL_GEN(dev) >= 9) {
922 ret = skl_check_plane_surface(state);
923 if (ret)
924 return ret;
925 }
926
96d61a7f
GP		 927 return 0;
928}
929
8ea30864
JB		 930int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
931 struct drm_file *file_priv)
932{
933 struct drm_intel_sprite_colorkey *set = data;
8ea30864 934 struct drm_plane *plane;
818ed961
ML		 935 struct drm_plane_state *plane_state;
936 struct drm_atomic_state *state;
937 struct drm_modeset_acquire_ctx ctx;
8ea30864
JB		 938 int ret = 0;
939
8ea30864
JB		 940 /* Make sure we don't try to enable both src & dest simultaneously */
941 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
942 return -EINVAL;
943
666a4537 944 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
47ecbb20
VS		 945 set->flags & I915_SET_COLORKEY_DESTINATION)
946 return -EINVAL;
947
7707e653 948 plane = drm_plane_find(dev, set->plane_id);
818ed961
ML		 949 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
950 return -ENOENT;
8ea30864 951
818ed961 952 drm_modeset_acquire_init(&ctx, 0);
6156a456 953
818ed961
ML		 954 state = drm_atomic_state_alloc(plane->dev);
955 if (!state) {
956 ret = -ENOMEM;
957 goto out;
6156a456 958 }
818ed961
ML		 959 state->acquire_ctx = &ctx;
960
961 while (1) {
962 plane_state = drm_atomic_get_plane_state(state, plane);
963 ret = PTR_ERR_OR_ZERO(plane_state);
964 if (!ret) {
965 to_intel_plane_state(plane_state)->ckey = *set;
966 ret = drm_atomic_commit(state);
967 }
6156a456 968
818ed961
ML		 969 if (ret != -EDEADLK)
970 break;
8ea30864 971
818ed961
ML		 972 drm_atomic_state_clear(state);
973 drm_modeset_backoff(&ctx);
974 }
8ea30864 975
818ed961
ML		 976 if (ret)
977 drm_atomic_state_free(state);
5e1bac2f 978
818ed961
ML		 979out:
980 drm_modeset_drop_locks(&ctx);
981 drm_modeset_acquire_fini(&ctx);
982 return ret;
5e1bac2f
JB		 983}
984
dada2d53 985static const uint32_t ilk_plane_formats[] = {
d1686ae3
CW		 986 DRM_FORMAT_XRGB8888,
987 DRM_FORMAT_YUYV,
988 DRM_FORMAT_YVYU,
989 DRM_FORMAT_UYVY,
990 DRM_FORMAT_VYUY,
991};
992
dada2d53 993static const uint32_t snb_plane_formats[] = {
b840d907
JB		 994 DRM_FORMAT_XBGR8888,
995 DRM_FORMAT_XRGB8888,
996 DRM_FORMAT_YUYV,
997 DRM_FORMAT_YVYU,
998 DRM_FORMAT_UYVY,
999 DRM_FORMAT_VYUY,
1000};
1001
dada2d53 1002static const uint32_t vlv_plane_formats[] = {
7f1f3851
JB		 1003 DRM_FORMAT_RGB565,
1004 DRM_FORMAT_ABGR8888,
1005 DRM_FORMAT_ARGB8888,
1006 DRM_FORMAT_XBGR8888,
1007 DRM_FORMAT_XRGB8888,
1008 DRM_FORMAT_XBGR2101010,
1009 DRM_FORMAT_ABGR2101010,
1010 DRM_FORMAT_YUYV,
1011 DRM_FORMAT_YVYU,
1012 DRM_FORMAT_UYVY,
1013 DRM_FORMAT_VYUY,
1014};
1015
dc2a41b4
DL		 1016static uint32_t skl_plane_formats[] = {
1017 DRM_FORMAT_RGB565,
1018 DRM_FORMAT_ABGR8888,
1019 DRM_FORMAT_ARGB8888,
1020 DRM_FORMAT_XBGR8888,
1021 DRM_FORMAT_XRGB8888,
1022 DRM_FORMAT_YUYV,
1023 DRM_FORMAT_YVYU,
1024 DRM_FORMAT_UYVY,
1025 DRM_FORMAT_VYUY,
1026};
1027
b840d907 1028int
7f1f3851 1029intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
b840d907 1030{
fca0ce2a
VS		 1031 struct intel_plane *intel_plane = NULL;
1032 struct intel_plane_state *state = NULL;
b840d907 1033 unsigned long possible_crtcs;
d1686ae3
CW		 1034 const uint32_t *plane_formats;
1035 int num_plane_formats;
b840d907
JB		 1036 int ret;
1037
d1686ae3 1038 if (INTEL_INFO(dev)->gen < 5)
b840d907 1039 return -ENODEV;
b840d907 1040
b14c5679 1041 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
fca0ce2a
VS		 1042 if (!intel_plane) {
1043 ret = -ENOMEM;
1044 goto fail;
1045 }
b840d907 1046
8e7d688b
MR		 1047 state = intel_create_plane_state(&intel_plane->base);
1048 if (!state) {
fca0ce2a
VS		 1049 ret = -ENOMEM;
1050 goto fail;
ea2c67bb 1051 }
8e7d688b 1052 intel_plane->base.state = &state->base;
ea2c67bb 1053
d1686ae3
CW		 1054 switch (INTEL_INFO(dev)->gen) {
1055 case 5:
1056 case 6:
2d354c34 1057 intel_plane->can_scale = true;
b840d907 1058 intel_plane->max_downscale = 16;
d1686ae3
CW		 1059 intel_plane->update_plane = ilk_update_plane;
1060 intel_plane->disable_plane = ilk_disable_plane;
d1686ae3
CW		 1061
1062 if (IS_GEN6(dev)) {
1063 plane_formats = snb_plane_formats;
1064 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1065 } else {
1066 plane_formats = ilk_plane_formats;
1067 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1068 }
1069 break;
1070
1071 case 7:
4e0bbc31 1072 case 8:
d49f7091 1073 if (IS_IVYBRIDGE(dev)) {
2d354c34 1074 intel_plane->can_scale = true;
d49f7091
DL		 1075 intel_plane->max_downscale = 2;
1076 } else {
1077 intel_plane->can_scale = false;
1078 intel_plane->max_downscale = 1;
1079 }
7f1f3851 1080
666a4537 1081 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7f1f3851
JB		 1082 intel_plane->update_plane = vlv_update_plane;
1083 intel_plane->disable_plane = vlv_disable_plane;
7f1f3851
JB		 1084
1085 plane_formats = vlv_plane_formats;
1086 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1087 } else {
7f1f3851
JB		 1088 intel_plane->update_plane = ivb_update_plane;
1089 intel_plane->disable_plane = ivb_disable_plane;
7f1f3851
JB		 1090
1091 plane_formats = snb_plane_formats;
1092 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1093 }
d1686ae3 1094 break;
dc2a41b4 1095 case 9:
c331879c 1096 intel_plane->can_scale = true;
dc2a41b4
DL		 1097 intel_plane->update_plane = skl_update_plane;
1098 intel_plane->disable_plane = skl_disable_plane;
549e2bfb 1099 state->scaler_id = -1;
dc2a41b4
DL		 1100
1101 plane_formats = skl_plane_formats;
1102 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1103 break;
d1686ae3 1104 default:
fca0ce2a
VS		 1105 MISSING_CASE(INTEL_INFO(dev)->gen);
1106 ret = -ENODEV;
1107 goto fail;
b840d907
JB		 1108 }
1109
1110 intel_plane->pipe = pipe;
7f1f3851 1111 intel_plane->plane = plane;
d1b9d039 1112 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
c59cb179 1113 intel_plane->check_plane = intel_check_sprite_plane;
fca0ce2a 1114
b840d907 1115 possible_crtcs = (1 << pipe);
fca0ce2a 1116
38573dc1
VS		 1117 if (INTEL_INFO(dev)->gen >= 9)
1118 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1119 &intel_plane_funcs,
1120 plane_formats, num_plane_formats,
1121 DRM_PLANE_TYPE_OVERLAY,
1122 "plane %d%c", plane + 2, pipe_name(pipe));
1123 else
1124 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1125 &intel_plane_funcs,
1126 plane_formats, num_plane_formats,
1127 DRM_PLANE_TYPE_OVERLAY,
1128 "sprite %c", sprite_name(pipe, plane));
fca0ce2a
VS		 1129 if (ret)
1130 goto fail;
7ed6eeee 1131
3b7a5119 1132 intel_create_rotation_property(dev, intel_plane);
b840d907 1133
ea2c67bb
MR		 1134 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1135
fca0ce2a
VS		 1136 return 0;
1137
1138fail:
1139 kfree(state);
1140 kfree(intel_plane);
1141
b840d907
JB		 1142 return ret;
1143}
Linux kernel - Deliverables
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