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b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
1731693a | 35 | #include <drm/drm_rect.h> |
b840d907 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
b840d907 JB |
38 | #include "i915_drv.h" |
39 | ||
7f1f3851 JB |
40 | static void |
41 | vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb, | |
42 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, | |
43 | unsigned int crtc_w, unsigned int crtc_h, | |
44 | uint32_t x, uint32_t y, | |
45 | uint32_t src_w, uint32_t src_h) | |
46 | { | |
47 | struct drm_device *dev = dplane->dev; | |
48 | struct drm_i915_private *dev_priv = dev->dev_private; | |
49 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
50 | int pipe = intel_plane->pipe; | |
51 | int plane = intel_plane->plane; | |
52 | u32 sprctl; | |
53 | unsigned long sprsurf_offset, linear_offset; | |
54 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
55 | ||
56 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
57 | ||
58 | /* Mask out pixel format bits in case we change it */ | |
59 | sprctl &= ~SP_PIXFORMAT_MASK; | |
60 | sprctl &= ~SP_YUV_BYTE_ORDER_MASK; | |
61 | sprctl &= ~SP_TILED; | |
62 | ||
63 | switch (fb->pixel_format) { | |
64 | case DRM_FORMAT_YUYV: | |
65 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; | |
66 | break; | |
67 | case DRM_FORMAT_YVYU: | |
68 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; | |
69 | break; | |
70 | case DRM_FORMAT_UYVY: | |
71 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; | |
72 | break; | |
73 | case DRM_FORMAT_VYUY: | |
74 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; | |
75 | break; | |
76 | case DRM_FORMAT_RGB565: | |
77 | sprctl |= SP_FORMAT_BGR565; | |
78 | break; | |
79 | case DRM_FORMAT_XRGB8888: | |
80 | sprctl |= SP_FORMAT_BGRX8888; | |
81 | break; | |
82 | case DRM_FORMAT_ARGB8888: | |
83 | sprctl |= SP_FORMAT_BGRA8888; | |
84 | break; | |
85 | case DRM_FORMAT_XBGR2101010: | |
86 | sprctl |= SP_FORMAT_RGBX1010102; | |
87 | break; | |
88 | case DRM_FORMAT_ABGR2101010: | |
89 | sprctl |= SP_FORMAT_RGBA1010102; | |
90 | break; | |
91 | case DRM_FORMAT_XBGR8888: | |
92 | sprctl |= SP_FORMAT_RGBX8888; | |
93 | break; | |
94 | case DRM_FORMAT_ABGR8888: | |
95 | sprctl |= SP_FORMAT_RGBA8888; | |
96 | break; | |
97 | default: | |
98 | /* | |
99 | * If we get here one of the upper layers failed to filter | |
100 | * out the unsupported plane formats | |
101 | */ | |
102 | BUG(); | |
103 | break; | |
104 | } | |
105 | ||
106 | if (obj->tiling_mode != I915_TILING_NONE) | |
107 | sprctl |= SP_TILED; | |
108 | ||
109 | sprctl |= SP_ENABLE; | |
110 | ||
111 | /* Sizes are 0 based */ | |
112 | src_w--; | |
113 | src_h--; | |
114 | crtc_w--; | |
115 | crtc_h--; | |
116 | ||
4c4ff43a | 117 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true); |
7f1f3851 JB |
118 | |
119 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); | |
120 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); | |
121 | ||
122 | linear_offset = y * fb->pitches[0] + x * pixel_size; | |
123 | sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, | |
124 | obj->tiling_mode, | |
125 | pixel_size, | |
126 | fb->pitches[0]); | |
127 | linear_offset -= sprsurf_offset; | |
128 | ||
129 | if (obj->tiling_mode != I915_TILING_NONE) | |
130 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); | |
131 | else | |
132 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); | |
133 | ||
134 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); | |
135 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
f343c5f6 | 136 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
7f1f3851 JB |
137 | sprsurf_offset); |
138 | POSTING_READ(SPSURF(pipe, plane)); | |
139 | } | |
140 | ||
141 | static void | |
142 | vlv_disable_plane(struct drm_plane *dplane) | |
143 | { | |
144 | struct drm_device *dev = dplane->dev; | |
145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
147 | int pipe = intel_plane->pipe; | |
148 | int plane = intel_plane->plane; | |
149 | ||
150 | I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & | |
151 | ~SP_ENABLE); | |
152 | /* Activate double buffered register update */ | |
153 | I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0); | |
154 | POSTING_READ(SPSURF(pipe, plane)); | |
155 | } | |
156 | ||
157 | static int | |
158 | vlv_update_colorkey(struct drm_plane *dplane, | |
159 | struct drm_intel_sprite_colorkey *key) | |
160 | { | |
161 | struct drm_device *dev = dplane->dev; | |
162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
163 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
164 | int pipe = intel_plane->pipe; | |
165 | int plane = intel_plane->plane; | |
166 | u32 sprctl; | |
167 | ||
168 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
169 | return -EINVAL; | |
170 | ||
171 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); | |
172 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); | |
173 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); | |
174 | ||
175 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
176 | sprctl &= ~SP_SOURCE_KEY; | |
177 | if (key->flags & I915_SET_COLORKEY_SOURCE) | |
178 | sprctl |= SP_SOURCE_KEY; | |
179 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
180 | ||
181 | POSTING_READ(SPKEYMSK(pipe, plane)); | |
182 | ||
183 | return 0; | |
184 | } | |
185 | ||
186 | static void | |
187 | vlv_get_colorkey(struct drm_plane *dplane, | |
188 | struct drm_intel_sprite_colorkey *key) | |
189 | { | |
190 | struct drm_device *dev = dplane->dev; | |
191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
192 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
193 | int pipe = intel_plane->pipe; | |
194 | int plane = intel_plane->plane; | |
195 | u32 sprctl; | |
196 | ||
197 | key->min_value = I915_READ(SPKEYMINVAL(pipe, plane)); | |
198 | key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane)); | |
199 | key->channel_mask = I915_READ(SPKEYMSK(pipe, plane)); | |
200 | ||
201 | sprctl = I915_READ(SPCNTR(pipe, plane)); | |
202 | if (sprctl & SP_SOURCE_KEY) | |
203 | key->flags = I915_SET_COLORKEY_SOURCE; | |
204 | else | |
205 | key->flags = I915_SET_COLORKEY_NONE; | |
206 | } | |
207 | ||
b840d907 JB |
208 | static void |
209 | ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |
210 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, | |
211 | unsigned int crtc_w, unsigned int crtc_h, | |
212 | uint32_t x, uint32_t y, | |
213 | uint32_t src_w, uint32_t src_h) | |
214 | { | |
215 | struct drm_device *dev = plane->dev; | |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
217 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
218 | int pipe = intel_plane->pipe; | |
219 | u32 sprctl, sprscale = 0; | |
5a35e99e | 220 | unsigned long sprsurf_offset, linear_offset; |
2bd3c3cb | 221 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2c6602df | 222 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
b840d907 JB |
223 | |
224 | sprctl = I915_READ(SPRCTL(pipe)); | |
225 | ||
226 | /* Mask out pixel format bits in case we change it */ | |
227 | sprctl &= ~SPRITE_PIXFORMAT_MASK; | |
228 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; | |
229 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; | |
e86fe0d3 | 230 | sprctl &= ~SPRITE_TILED; |
b840d907 JB |
231 | |
232 | switch (fb->pixel_format) { | |
233 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 234 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
235 | break; |
236 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 237 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
238 | break; |
239 | case DRM_FORMAT_YUYV: | |
240 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
241 | break; |
242 | case DRM_FORMAT_YVYU: | |
243 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
244 | break; |
245 | case DRM_FORMAT_UYVY: | |
246 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
247 | break; |
248 | case DRM_FORMAT_VYUY: | |
249 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
250 | break; |
251 | default: | |
28d491df | 252 | BUG(); |
b840d907 JB |
253 | } |
254 | ||
255 | if (obj->tiling_mode != I915_TILING_NONE) | |
256 | sprctl |= SPRITE_TILED; | |
257 | ||
258 | /* must disable */ | |
259 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
260 | sprctl |= SPRITE_ENABLE; | |
261 | ||
86d3efce VS |
262 | if (IS_HASWELL(dev)) |
263 | sprctl |= SPRITE_PIPE_CSC_ENABLE; | |
264 | ||
b840d907 JB |
265 | /* Sizes are 0 based */ |
266 | src_w--; | |
267 | src_h--; | |
268 | crtc_w--; | |
269 | crtc_h--; | |
270 | ||
4c4ff43a | 271 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true); |
b840d907 JB |
272 | |
273 | /* | |
274 | * IVB workaround: must disable low power watermarks for at least | |
275 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
276 | * when scaling is disabled. | |
277 | */ | |
278 | if (crtc_w != src_w || crtc_h != src_h) { | |
2c6602df VS |
279 | dev_priv->sprite_scaling_enabled |= 1 << pipe; |
280 | ||
281 | if (!scaling_was_enabled) { | |
828ed3e1 CW |
282 | intel_update_watermarks(dev); |
283 | intel_wait_for_vblank(dev, pipe); | |
284 | } | |
b840d907 | 285 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
2c6602df VS |
286 | } else |
287 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); | |
b840d907 JB |
288 | |
289 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); | |
290 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
c54173a8 | 291 | |
ca320ac4 | 292 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 293 | sprsurf_offset = |
bc752862 CW |
294 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
295 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
296 | linear_offset -= sprsurf_offset; |
297 | ||
298 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET | |
299 | * register */ | |
300 | if (IS_HASWELL(dev)) | |
c54173a8 | 301 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 302 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 303 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
304 | else |
305 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 306 | |
b840d907 | 307 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
308 | if (intel_plane->can_scale) |
309 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 310 | I915_WRITE(SPRCTL(pipe), sprctl); |
f343c5f6 BW |
311 | I915_MODIFY_DISPBASE(SPRSURF(pipe), |
312 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); | |
b840d907 | 313 | POSTING_READ(SPRSURF(pipe)); |
2c6602df VS |
314 | |
315 | /* potentially re-enable LP watermarks */ | |
316 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | |
317 | intel_update_watermarks(dev); | |
b840d907 JB |
318 | } |
319 | ||
320 | static void | |
321 | ivb_disable_plane(struct drm_plane *plane) | |
322 | { | |
323 | struct drm_device *dev = plane->dev; | |
324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
325 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
326 | int pipe = intel_plane->pipe; | |
2c6602df | 327 | bool scaling_was_enabled = dev_priv->sprite_scaling_enabled; |
b840d907 JB |
328 | |
329 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); | |
330 | /* Can't leave the scaler enabled... */ | |
2d354c34 DL |
331 | if (intel_plane->can_scale) |
332 | I915_WRITE(SPRSCALE(pipe), 0); | |
b840d907 | 333 | /* Activate double buffered register update */ |
446f2545 | 334 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
b840d907 | 335 | POSTING_READ(SPRSURF(pipe)); |
828ed3e1 | 336 | |
2c6602df VS |
337 | dev_priv->sprite_scaling_enabled &= ~(1 << pipe); |
338 | ||
4c4ff43a PZ |
339 | intel_update_sprite_watermarks(dev, pipe, 0, 0, false); |
340 | ||
2c6602df VS |
341 | /* potentially re-enable LP watermarks */ |
342 | if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled) | |
343 | intel_update_watermarks(dev); | |
b840d907 JB |
344 | } |
345 | ||
8ea30864 JB |
346 | static int |
347 | ivb_update_colorkey(struct drm_plane *plane, | |
348 | struct drm_intel_sprite_colorkey *key) | |
349 | { | |
350 | struct drm_device *dev = plane->dev; | |
351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
352 | struct intel_plane *intel_plane; | |
353 | u32 sprctl; | |
354 | int ret = 0; | |
355 | ||
356 | intel_plane = to_intel_plane(plane); | |
357 | ||
358 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); | |
359 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); | |
360 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); | |
361 | ||
362 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
363 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); | |
364 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
365 | sprctl |= SPRITE_DEST_KEY; | |
366 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
367 | sprctl |= SPRITE_SOURCE_KEY; | |
368 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); | |
369 | ||
370 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); | |
371 | ||
372 | return ret; | |
373 | } | |
374 | ||
375 | static void | |
376 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) | |
377 | { | |
378 | struct drm_device *dev = plane->dev; | |
379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
380 | struct intel_plane *intel_plane; | |
381 | u32 sprctl; | |
382 | ||
383 | intel_plane = to_intel_plane(plane); | |
384 | ||
385 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); | |
386 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); | |
387 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); | |
388 | key->flags = 0; | |
389 | ||
390 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
391 | ||
392 | if (sprctl & SPRITE_DEST_KEY) | |
393 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
394 | else if (sprctl & SPRITE_SOURCE_KEY) | |
395 | key->flags = I915_SET_COLORKEY_SOURCE; | |
396 | else | |
397 | key->flags = I915_SET_COLORKEY_NONE; | |
398 | } | |
399 | ||
b840d907 | 400 | static void |
d1686ae3 | 401 | ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
b840d907 JB |
402 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
403 | unsigned int crtc_w, unsigned int crtc_h, | |
404 | uint32_t x, uint32_t y, | |
405 | uint32_t src_w, uint32_t src_h) | |
406 | { | |
407 | struct drm_device *dev = plane->dev; | |
408 | struct drm_i915_private *dev_priv = dev->dev_private; | |
409 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2bd3c3cb | 410 | int pipe = intel_plane->pipe; |
5a35e99e | 411 | unsigned long dvssurf_offset, linear_offset; |
8aaa81a1 | 412 | u32 dvscntr, dvsscale; |
2bd3c3cb | 413 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
b840d907 JB |
414 | |
415 | dvscntr = I915_READ(DVSCNTR(pipe)); | |
416 | ||
417 | /* Mask out pixel format bits in case we change it */ | |
418 | dvscntr &= ~DVS_PIXFORMAT_MASK; | |
ab2f9df1 | 419 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
b840d907 | 420 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
79626523 | 421 | dvscntr &= ~DVS_TILED; |
b840d907 JB |
422 | |
423 | switch (fb->pixel_format) { | |
424 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 425 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
426 | break; |
427 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 428 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
429 | break; |
430 | case DRM_FORMAT_YUYV: | |
431 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
432 | break; |
433 | case DRM_FORMAT_YVYU: | |
434 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
435 | break; |
436 | case DRM_FORMAT_UYVY: | |
437 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
438 | break; |
439 | case DRM_FORMAT_VYUY: | |
440 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
441 | break; |
442 | default: | |
28d491df | 443 | BUG(); |
b840d907 JB |
444 | } |
445 | ||
446 | if (obj->tiling_mode != I915_TILING_NONE) | |
447 | dvscntr |= DVS_TILED; | |
448 | ||
d1686ae3 CW |
449 | if (IS_GEN6(dev)) |
450 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
451 | dvscntr |= DVS_ENABLE; |
452 | ||
453 | /* Sizes are 0 based */ | |
454 | src_w--; | |
455 | src_h--; | |
456 | crtc_w--; | |
457 | crtc_h--; | |
458 | ||
4c4ff43a | 459 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true); |
b840d907 | 460 | |
8aaa81a1 CW |
461 | dvsscale = 0; |
462 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) | |
b840d907 JB |
463 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
464 | ||
465 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); | |
466 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
5a35e99e | 467 | |
ca320ac4 | 468 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 469 | dvssurf_offset = |
bc752862 CW |
470 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
471 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
472 | linear_offset -= dvssurf_offset; |
473 | ||
474 | if (obj->tiling_mode != I915_TILING_NONE) | |
b840d907 | 475 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
476 | else |
477 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 478 | |
b840d907 JB |
479 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
480 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
481 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
f343c5f6 BW |
482 | I915_MODIFY_DISPBASE(DVSSURF(pipe), |
483 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); | |
b840d907 JB |
484 | POSTING_READ(DVSSURF(pipe)); |
485 | } | |
486 | ||
487 | static void | |
d1686ae3 | 488 | ilk_disable_plane(struct drm_plane *plane) |
b840d907 JB |
489 | { |
490 | struct drm_device *dev = plane->dev; | |
491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
492 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
493 | int pipe = intel_plane->pipe; | |
494 | ||
495 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); | |
496 | /* Disable the scaler */ | |
497 | I915_WRITE(DVSSCALE(pipe), 0); | |
498 | /* Flush double buffered register updates */ | |
446f2545 | 499 | I915_MODIFY_DISPBASE(DVSSURF(pipe), 0); |
b840d907 JB |
500 | POSTING_READ(DVSSURF(pipe)); |
501 | } | |
502 | ||
175bd420 JB |
503 | static void |
504 | intel_enable_primary(struct drm_crtc *crtc) | |
505 | { | |
506 | struct drm_device *dev = crtc->dev; | |
507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
508 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
509 | int reg = DSPCNTR(intel_crtc->plane); | |
510 | ||
93314b5b CW |
511 | if (!intel_crtc->primary_disabled) |
512 | return; | |
513 | ||
514 | intel_crtc->primary_disabled = false; | |
515 | intel_update_fbc(dev); | |
516 | ||
175bd420 JB |
517 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
518 | } | |
519 | ||
520 | static void | |
521 | intel_disable_primary(struct drm_crtc *crtc) | |
522 | { | |
523 | struct drm_device *dev = crtc->dev; | |
524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
525 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
526 | int reg = DSPCNTR(intel_crtc->plane); | |
527 | ||
93314b5b CW |
528 | if (intel_crtc->primary_disabled) |
529 | return; | |
530 | ||
175bd420 | 531 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
93314b5b CW |
532 | |
533 | intel_crtc->primary_disabled = true; | |
534 | intel_update_fbc(dev); | |
175bd420 JB |
535 | } |
536 | ||
8ea30864 | 537 | static int |
d1686ae3 | 538 | ilk_update_colorkey(struct drm_plane *plane, |
8ea30864 JB |
539 | struct drm_intel_sprite_colorkey *key) |
540 | { | |
541 | struct drm_device *dev = plane->dev; | |
542 | struct drm_i915_private *dev_priv = dev->dev_private; | |
543 | struct intel_plane *intel_plane; | |
544 | u32 dvscntr; | |
545 | int ret = 0; | |
546 | ||
547 | intel_plane = to_intel_plane(plane); | |
548 | ||
549 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); | |
550 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); | |
551 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); | |
552 | ||
553 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
554 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); | |
555 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
556 | dvscntr |= DVS_DEST_KEY; | |
557 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
558 | dvscntr |= DVS_SOURCE_KEY; | |
559 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); | |
560 | ||
561 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); | |
562 | ||
563 | return ret; | |
564 | } | |
565 | ||
566 | static void | |
d1686ae3 | 567 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
8ea30864 JB |
568 | { |
569 | struct drm_device *dev = plane->dev; | |
570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
571 | struct intel_plane *intel_plane; | |
572 | u32 dvscntr; | |
573 | ||
574 | intel_plane = to_intel_plane(plane); | |
575 | ||
576 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); | |
577 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); | |
578 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); | |
579 | key->flags = 0; | |
580 | ||
581 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
582 | ||
583 | if (dvscntr & DVS_DEST_KEY) | |
584 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
585 | else if (dvscntr & DVS_SOURCE_KEY) | |
586 | key->flags = I915_SET_COLORKEY_SOURCE; | |
587 | else | |
588 | key->flags = I915_SET_COLORKEY_NONE; | |
589 | } | |
590 | ||
1731693a VS |
591 | static bool |
592 | format_is_yuv(uint32_t format) | |
593 | { | |
594 | switch (format) { | |
595 | case DRM_FORMAT_YUYV: | |
596 | case DRM_FORMAT_UYVY: | |
597 | case DRM_FORMAT_VYUY: | |
598 | case DRM_FORMAT_YVYU: | |
599 | return true; | |
600 | default: | |
601 | return false; | |
602 | } | |
603 | } | |
604 | ||
b840d907 JB |
605 | static int |
606 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
607 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
608 | unsigned int crtc_w, unsigned int crtc_h, | |
609 | uint32_t src_x, uint32_t src_y, | |
610 | uint32_t src_w, uint32_t src_h) | |
611 | { | |
612 | struct drm_device *dev = plane->dev; | |
613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
614 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
615 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
616 | struct intel_framebuffer *intel_fb; | |
617 | struct drm_i915_gem_object *obj, *old_obj; | |
618 | int pipe = intel_plane->pipe; | |
702e7a56 PZ |
619 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
620 | pipe); | |
b840d907 | 621 | int ret = 0; |
b840d907 | 622 | bool disable_primary = false; |
1731693a VS |
623 | bool visible; |
624 | int hscale, vscale; | |
625 | int max_scale, min_scale; | |
626 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
627 | struct drm_rect src = { | |
628 | /* sample coordinates in 16.16 fixed point */ | |
629 | .x1 = src_x, | |
630 | .x2 = src_x + src_w, | |
631 | .y1 = src_y, | |
632 | .y2 = src_y + src_h, | |
633 | }; | |
634 | struct drm_rect dst = { | |
635 | /* integer pixels */ | |
636 | .x1 = crtc_x, | |
637 | .x2 = crtc_x + crtc_w, | |
638 | .y1 = crtc_y, | |
639 | .y2 = crtc_y + crtc_h, | |
640 | }; | |
641 | const struct drm_rect clip = { | |
642 | .x2 = crtc->mode.hdisplay, | |
643 | .y2 = crtc->mode.vdisplay, | |
644 | }; | |
b840d907 JB |
645 | |
646 | intel_fb = to_intel_framebuffer(fb); | |
647 | obj = intel_fb->obj; | |
648 | ||
649 | old_obj = intel_plane->obj; | |
650 | ||
5e1bac2f JB |
651 | intel_plane->crtc_x = crtc_x; |
652 | intel_plane->crtc_y = crtc_y; | |
653 | intel_plane->crtc_w = crtc_w; | |
654 | intel_plane->crtc_h = crtc_h; | |
655 | intel_plane->src_x = src_x; | |
656 | intel_plane->src_y = src_y; | |
657 | intel_plane->src_w = src_w; | |
658 | intel_plane->src_h = src_h; | |
659 | ||
b840d907 | 660 | /* Pipe must be running... */ |
1731693a VS |
661 | if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) { |
662 | DRM_DEBUG_KMS("Pipe disabled\n"); | |
b840d907 | 663 | return -EINVAL; |
1731693a | 664 | } |
b840d907 | 665 | |
1731693a VS |
666 | /* Don't modify another pipe's plane */ |
667 | if (intel_plane->pipe != intel_crtc->pipe) { | |
668 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); | |
b840d907 | 669 | return -EINVAL; |
1731693a | 670 | } |
b840d907 | 671 | |
1731693a VS |
672 | /* FIXME check all gen limits */ |
673 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { | |
674 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); | |
b840d907 | 675 | return -EINVAL; |
1731693a | 676 | } |
b840d907 | 677 | |
94c6419e DL |
678 | /* Sprite planes can be linear or x-tiled surfaces */ |
679 | switch (obj->tiling_mode) { | |
680 | case I915_TILING_NONE: | |
681 | case I915_TILING_X: | |
682 | break; | |
683 | default: | |
1731693a | 684 | DRM_DEBUG_KMS("Unsupported tiling mode\n"); |
94c6419e DL |
685 | return -EINVAL; |
686 | } | |
687 | ||
3c3686cd VS |
688 | /* |
689 | * FIXME the following code does a bunch of fuzzy adjustments to the | |
690 | * coordinates and sizes. We probably need some way to decide whether | |
691 | * more strict checking should be done instead. | |
692 | */ | |
1731693a VS |
693 | max_scale = intel_plane->max_downscale << 16; |
694 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); | |
695 | ||
3c3686cd VS |
696 | hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale); |
697 | BUG_ON(hscale < 0); | |
1731693a | 698 | |
3c3686cd VS |
699 | vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale); |
700 | BUG_ON(vscale < 0); | |
b840d907 | 701 | |
1731693a | 702 | visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale); |
b840d907 | 703 | |
1731693a VS |
704 | crtc_x = dst.x1; |
705 | crtc_y = dst.y1; | |
706 | crtc_w = drm_rect_width(&dst); | |
707 | crtc_h = drm_rect_height(&dst); | |
2d354c34 | 708 | |
1731693a | 709 | if (visible) { |
3c3686cd VS |
710 | /* check again in case clipping clamped the results */ |
711 | hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale); | |
712 | if (hscale < 0) { | |
713 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); | |
714 | drm_rect_debug_print(&src, true); | |
715 | drm_rect_debug_print(&dst, false); | |
716 | ||
717 | return hscale; | |
718 | } | |
719 | ||
720 | vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale); | |
721 | if (vscale < 0) { | |
722 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); | |
723 | drm_rect_debug_print(&src, true); | |
724 | drm_rect_debug_print(&dst, false); | |
725 | ||
726 | return vscale; | |
727 | } | |
728 | ||
1731693a VS |
729 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
730 | drm_rect_adjust_size(&src, | |
731 | drm_rect_width(&dst) * hscale - drm_rect_width(&src), | |
732 | drm_rect_height(&dst) * vscale - drm_rect_height(&src)); | |
733 | ||
734 | /* sanity check to make sure the src viewport wasn't enlarged */ | |
735 | WARN_ON(src.x1 < (int) src_x || | |
736 | src.y1 < (int) src_y || | |
737 | src.x2 > (int) (src_x + src_w) || | |
738 | src.y2 > (int) (src_y + src_h)); | |
739 | ||
740 | /* | |
741 | * Hardware doesn't handle subpixel coordinates. | |
742 | * Adjust to (macro)pixel boundary, but be careful not to | |
743 | * increase the source viewport size, because that could | |
744 | * push the downscaling factor out of bounds. | |
1731693a VS |
745 | */ |
746 | src_x = src.x1 >> 16; | |
747 | src_w = drm_rect_width(&src) >> 16; | |
748 | src_y = src.y1 >> 16; | |
749 | src_h = drm_rect_height(&src) >> 16; | |
750 | ||
751 | if (format_is_yuv(fb->pixel_format)) { | |
752 | src_x &= ~1; | |
753 | src_w &= ~1; | |
754 | ||
755 | /* | |
756 | * Must keep src and dst the | |
757 | * same if we can't scale. | |
758 | */ | |
759 | if (!intel_plane->can_scale) | |
760 | crtc_w &= ~1; | |
761 | ||
762 | if (crtc_w == 0) | |
763 | visible = false; | |
764 | } | |
765 | } | |
766 | ||
767 | /* Check size restrictions when scaling */ | |
768 | if (visible && (src_w != crtc_w || src_h != crtc_h)) { | |
769 | unsigned int width_bytes; | |
770 | ||
771 | WARN_ON(!intel_plane->can_scale); | |
772 | ||
773 | /* FIXME interlacing min height is 6 */ | |
774 | ||
775 | if (crtc_w < 3 || crtc_h < 3) | |
776 | visible = false; | |
777 | ||
778 | if (src_w < 3 || src_h < 3) | |
779 | visible = false; | |
780 | ||
781 | width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size; | |
782 | ||
783 | if (src_w > 2048 || src_h > 2048 || | |
784 | width_bytes > 4096 || fb->pitches[0] > 4096) { | |
785 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); | |
786 | return -EINVAL; | |
787 | } | |
788 | } | |
789 | ||
790 | dst.x1 = crtc_x; | |
791 | dst.x2 = crtc_x + crtc_w; | |
792 | dst.y1 = crtc_y; | |
793 | dst.y2 = crtc_y + crtc_h; | |
b840d907 JB |
794 | |
795 | /* | |
796 | * If the sprite is completely covering the primary plane, | |
797 | * we can disable the primary and save power. | |
798 | */ | |
1731693a VS |
799 | disable_primary = drm_rect_equals(&dst, &clip); |
800 | WARN_ON(disable_primary && !visible); | |
b840d907 JB |
801 | |
802 | mutex_lock(&dev->struct_mutex); | |
803 | ||
693db184 CW |
804 | /* Note that this will apply the VT-d workaround for scanouts, |
805 | * which is more restrictive than required for sprites. (The | |
806 | * primary plane requires 256KiB alignment with 64 PTE padding, | |
807 | * the sprite planes only require 128KiB alignment and 32 PTE padding. | |
808 | */ | |
b840d907 | 809 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
00c2064b | 810 | if (ret) |
b840d907 | 811 | goto out_unlock; |
b840d907 JB |
812 | |
813 | intel_plane->obj = obj; | |
814 | ||
175bd420 JB |
815 | /* |
816 | * Be sure to re-enable the primary before the sprite is no longer | |
817 | * covering it fully. | |
818 | */ | |
93314b5b | 819 | if (!disable_primary) |
175bd420 | 820 | intel_enable_primary(crtc); |
175bd420 | 821 | |
1731693a VS |
822 | if (visible) |
823 | intel_plane->update_plane(plane, fb, obj, | |
824 | crtc_x, crtc_y, crtc_w, crtc_h, | |
825 | src_x, src_y, src_w, src_h); | |
826 | else | |
827 | intel_plane->disable_plane(plane); | |
b840d907 | 828 | |
93314b5b | 829 | if (disable_primary) |
175bd420 | 830 | intel_disable_primary(crtc); |
175bd420 | 831 | |
b840d907 JB |
832 | /* Unpin old obj after new one is active to avoid ugliness */ |
833 | if (old_obj) { | |
834 | /* | |
835 | * It's fairly common to simply update the position of | |
836 | * an existing object. In that case, we don't need to | |
837 | * wait for vblank to avoid ugliness, we only need to | |
838 | * do the pin & ref bookkeeping. | |
839 | */ | |
840 | if (old_obj != obj) { | |
841 | mutex_unlock(&dev->struct_mutex); | |
842 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
843 | mutex_lock(&dev->struct_mutex); | |
844 | } | |
1690e1eb | 845 | intel_unpin_fb_obj(old_obj); |
b840d907 JB |
846 | } |
847 | ||
848 | out_unlock: | |
849 | mutex_unlock(&dev->struct_mutex); | |
b840d907 JB |
850 | return ret; |
851 | } | |
852 | ||
853 | static int | |
854 | intel_disable_plane(struct drm_plane *plane) | |
855 | { | |
856 | struct drm_device *dev = plane->dev; | |
857 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
858 | int ret = 0; | |
859 | ||
93314b5b | 860 | if (plane->crtc) |
175bd420 | 861 | intel_enable_primary(plane->crtc); |
b840d907 JB |
862 | intel_plane->disable_plane(plane); |
863 | ||
864 | if (!intel_plane->obj) | |
865 | goto out; | |
866 | ||
c626d317 VS |
867 | intel_wait_for_vblank(dev, intel_plane->pipe); |
868 | ||
b840d907 | 869 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 870 | intel_unpin_fb_obj(intel_plane->obj); |
b840d907 JB |
871 | intel_plane->obj = NULL; |
872 | mutex_unlock(&dev->struct_mutex); | |
873 | out: | |
874 | ||
875 | return ret; | |
876 | } | |
877 | ||
878 | static void intel_destroy_plane(struct drm_plane *plane) | |
879 | { | |
880 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
881 | intel_disable_plane(plane); | |
882 | drm_plane_cleanup(plane); | |
883 | kfree(intel_plane); | |
884 | } | |
885 | ||
8ea30864 JB |
886 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
887 | struct drm_file *file_priv) | |
888 | { | |
889 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 JB |
890 | struct drm_mode_object *obj; |
891 | struct drm_plane *plane; | |
892 | struct intel_plane *intel_plane; | |
893 | int ret = 0; | |
894 | ||
1cff8f6b DV |
895 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
896 | return -ENODEV; | |
8ea30864 JB |
897 | |
898 | /* Make sure we don't try to enable both src & dest simultaneously */ | |
899 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
900 | return -EINVAL; | |
901 | ||
a0e99e68 | 902 | drm_modeset_lock_all(dev); |
8ea30864 JB |
903 | |
904 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); | |
905 | if (!obj) { | |
906 | ret = -EINVAL; | |
907 | goto out_unlock; | |
908 | } | |
909 | ||
910 | plane = obj_to_plane(obj); | |
911 | intel_plane = to_intel_plane(plane); | |
912 | ret = intel_plane->update_colorkey(plane, set); | |
913 | ||
914 | out_unlock: | |
a0e99e68 | 915 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
916 | return ret; |
917 | } | |
918 | ||
919 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
920 | struct drm_file *file_priv) | |
921 | { | |
922 | struct drm_intel_sprite_colorkey *get = data; | |
8ea30864 JB |
923 | struct drm_mode_object *obj; |
924 | struct drm_plane *plane; | |
925 | struct intel_plane *intel_plane; | |
926 | int ret = 0; | |
927 | ||
1cff8f6b DV |
928 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
929 | return -ENODEV; | |
8ea30864 | 930 | |
a0e99e68 | 931 | drm_modeset_lock_all(dev); |
8ea30864 JB |
932 | |
933 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); | |
934 | if (!obj) { | |
935 | ret = -EINVAL; | |
936 | goto out_unlock; | |
937 | } | |
938 | ||
939 | plane = obj_to_plane(obj); | |
940 | intel_plane = to_intel_plane(plane); | |
941 | intel_plane->get_colorkey(plane, get); | |
942 | ||
943 | out_unlock: | |
a0e99e68 | 944 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
945 | return ret; |
946 | } | |
947 | ||
5e1bac2f JB |
948 | void intel_plane_restore(struct drm_plane *plane) |
949 | { | |
950 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
951 | ||
952 | if (!plane->crtc || !plane->fb) | |
953 | return; | |
954 | ||
955 | intel_update_plane(plane, plane->crtc, plane->fb, | |
956 | intel_plane->crtc_x, intel_plane->crtc_y, | |
957 | intel_plane->crtc_w, intel_plane->crtc_h, | |
958 | intel_plane->src_x, intel_plane->src_y, | |
959 | intel_plane->src_w, intel_plane->src_h); | |
960 | } | |
961 | ||
bb53d4ae VS |
962 | void intel_plane_disable(struct drm_plane *plane) |
963 | { | |
964 | if (!plane->crtc || !plane->fb) | |
965 | return; | |
966 | ||
967 | intel_disable_plane(plane); | |
968 | } | |
969 | ||
b840d907 JB |
970 | static const struct drm_plane_funcs intel_plane_funcs = { |
971 | .update_plane = intel_update_plane, | |
972 | .disable_plane = intel_disable_plane, | |
973 | .destroy = intel_destroy_plane, | |
974 | }; | |
975 | ||
d1686ae3 CW |
976 | static uint32_t ilk_plane_formats[] = { |
977 | DRM_FORMAT_XRGB8888, | |
978 | DRM_FORMAT_YUYV, | |
979 | DRM_FORMAT_YVYU, | |
980 | DRM_FORMAT_UYVY, | |
981 | DRM_FORMAT_VYUY, | |
982 | }; | |
983 | ||
b840d907 JB |
984 | static uint32_t snb_plane_formats[] = { |
985 | DRM_FORMAT_XBGR8888, | |
986 | DRM_FORMAT_XRGB8888, | |
987 | DRM_FORMAT_YUYV, | |
988 | DRM_FORMAT_YVYU, | |
989 | DRM_FORMAT_UYVY, | |
990 | DRM_FORMAT_VYUY, | |
991 | }; | |
992 | ||
7f1f3851 JB |
993 | static uint32_t vlv_plane_formats[] = { |
994 | DRM_FORMAT_RGB565, | |
995 | DRM_FORMAT_ABGR8888, | |
996 | DRM_FORMAT_ARGB8888, | |
997 | DRM_FORMAT_XBGR8888, | |
998 | DRM_FORMAT_XRGB8888, | |
999 | DRM_FORMAT_XBGR2101010, | |
1000 | DRM_FORMAT_ABGR2101010, | |
1001 | DRM_FORMAT_YUYV, | |
1002 | DRM_FORMAT_YVYU, | |
1003 | DRM_FORMAT_UYVY, | |
1004 | DRM_FORMAT_VYUY, | |
1005 | }; | |
1006 | ||
b840d907 | 1007 | int |
7f1f3851 | 1008 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
b840d907 JB |
1009 | { |
1010 | struct intel_plane *intel_plane; | |
1011 | unsigned long possible_crtcs; | |
d1686ae3 CW |
1012 | const uint32_t *plane_formats; |
1013 | int num_plane_formats; | |
b840d907 JB |
1014 | int ret; |
1015 | ||
d1686ae3 | 1016 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 1017 | return -ENODEV; |
b840d907 JB |
1018 | |
1019 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); | |
1020 | if (!intel_plane) | |
1021 | return -ENOMEM; | |
1022 | ||
d1686ae3 CW |
1023 | switch (INTEL_INFO(dev)->gen) { |
1024 | case 5: | |
1025 | case 6: | |
2d354c34 | 1026 | intel_plane->can_scale = true; |
b840d907 | 1027 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
1028 | intel_plane->update_plane = ilk_update_plane; |
1029 | intel_plane->disable_plane = ilk_disable_plane; | |
1030 | intel_plane->update_colorkey = ilk_update_colorkey; | |
1031 | intel_plane->get_colorkey = ilk_get_colorkey; | |
1032 | ||
1033 | if (IS_GEN6(dev)) { | |
1034 | plane_formats = snb_plane_formats; | |
1035 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1036 | } else { | |
1037 | plane_formats = ilk_plane_formats; | |
1038 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
1039 | } | |
1040 | break; | |
1041 | ||
1042 | case 7: | |
d49f7091 | 1043 | if (IS_IVYBRIDGE(dev)) { |
2d354c34 | 1044 | intel_plane->can_scale = true; |
d49f7091 DL |
1045 | intel_plane->max_downscale = 2; |
1046 | } else { | |
1047 | intel_plane->can_scale = false; | |
1048 | intel_plane->max_downscale = 1; | |
1049 | } | |
7f1f3851 JB |
1050 | |
1051 | if (IS_VALLEYVIEW(dev)) { | |
7f1f3851 JB |
1052 | intel_plane->update_plane = vlv_update_plane; |
1053 | intel_plane->disable_plane = vlv_disable_plane; | |
1054 | intel_plane->update_colorkey = vlv_update_colorkey; | |
1055 | intel_plane->get_colorkey = vlv_get_colorkey; | |
1056 | ||
1057 | plane_formats = vlv_plane_formats; | |
1058 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); | |
1059 | } else { | |
7f1f3851 JB |
1060 | intel_plane->update_plane = ivb_update_plane; |
1061 | intel_plane->disable_plane = ivb_disable_plane; | |
1062 | intel_plane->update_colorkey = ivb_update_colorkey; | |
1063 | intel_plane->get_colorkey = ivb_get_colorkey; | |
1064 | ||
1065 | plane_formats = snb_plane_formats; | |
1066 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1067 | } | |
d1686ae3 CW |
1068 | break; |
1069 | ||
1070 | default: | |
a8b0bbab | 1071 | kfree(intel_plane); |
d1686ae3 | 1072 | return -ENODEV; |
b840d907 JB |
1073 | } |
1074 | ||
1075 | intel_plane->pipe = pipe; | |
7f1f3851 | 1076 | intel_plane->plane = plane; |
b840d907 JB |
1077 | possible_crtcs = (1 << pipe); |
1078 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, | |
d1686ae3 CW |
1079 | &intel_plane_funcs, |
1080 | plane_formats, num_plane_formats, | |
1081 | false); | |
b840d907 JB |
1082 | if (ret) |
1083 | kfree(intel_plane); | |
1084 | ||
1085 | return ret; | |
1086 | } |