Commit | Line | Data |
---|---|---|
b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
1731693a | 35 | #include <drm/drm_rect.h> |
c331879c | 36 | #include <drm/drm_atomic.h> |
ea2c67bb | 37 | #include <drm/drm_plane_helper.h> |
b840d907 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
b840d907 JB |
40 | #include "i915_drv.h" |
41 | ||
6ca2aeb2 VS |
42 | static bool |
43 | format_is_yuv(uint32_t format) | |
44 | { | |
45 | switch (format) { | |
46 | case DRM_FORMAT_YUYV: | |
47 | case DRM_FORMAT_UYVY: | |
48 | case DRM_FORMAT_VYUY: | |
49 | case DRM_FORMAT_YVYU: | |
50 | return true; | |
51 | default: | |
52 | return false; | |
53 | } | |
54 | } | |
55 | ||
dfd2e9ab VS |
56 | int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
57 | int usecs) | |
8d7849db VS |
58 | { |
59 | /* paranoia */ | |
5e7234c9 | 60 | if (!adjusted_mode->crtc_htotal) |
8d7849db VS |
61 | return 1; |
62 | ||
5e7234c9 VS |
63 | return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, |
64 | 1000 * adjusted_mode->crtc_htotal); | |
8d7849db VS |
65 | } |
66 | ||
26ff2762 ACO |
67 | /** |
68 | * intel_pipe_update_start() - start update of a set of display registers | |
69 | * @crtc: the crtc of which the registers are going to be updated | |
70 | * @start_vbl_count: vblank counter return pointer used for error checking | |
71 | * | |
72 | * Mark the start of an update to pipe registers that should be updated | |
73 | * atomically regarding vblank. If the next vblank will happens within | |
74 | * the next 100 us, this function waits until the vblank passes. | |
75 | * | |
76 | * After a successful call to this function, interrupts will be disabled | |
77 | * until a subsequent call to intel_pipe_update_end(). That is done to | |
78 | * avoid random delays. The value written to @start_vbl_count should be | |
79 | * supplied to intel_pipe_update_end() for error checking. | |
26ff2762 | 80 | */ |
34e0adbb | 81 | void intel_pipe_update_start(struct intel_crtc *crtc) |
8d7849db | 82 | { |
124abe07 | 83 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
8d7849db VS |
84 | long timeout = msecs_to_jiffies_timeout(1); |
85 | int scanline, min, max, vblank_start; | |
210871b6 | 86 | wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
8d7849db VS |
87 | DEFINE_WAIT(wait); |
88 | ||
124abe07 VS |
89 | vblank_start = adjusted_mode->crtc_vblank_start; |
90 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
8d7849db VS |
91 | vblank_start = DIV_ROUND_UP(vblank_start, 2); |
92 | ||
93 | /* FIXME needs to be calibrated sensibly */ | |
dfd2e9ab | 94 | min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100); |
8d7849db VS |
95 | max = vblank_start - 1; |
96 | ||
8f539a83 | 97 | local_irq_disable(); |
8f539a83 | 98 | |
8d7849db | 99 | if (min <= 0 || max <= 0) |
8f539a83 | 100 | return; |
8d7849db | 101 | |
1e3feefd | 102 | if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) |
8f539a83 | 103 | return; |
8d7849db | 104 | |
d637ce3f JB |
105 | crtc->debug.min_vbl = min; |
106 | crtc->debug.max_vbl = max; | |
107 | trace_i915_pipe_update_start(crtc); | |
25ef284a | 108 | |
8d7849db VS |
109 | for (;;) { |
110 | /* | |
111 | * prepare_to_wait() has a memory barrier, which guarantees | |
112 | * other CPUs can see the task state update by the time we | |
113 | * read the scanline. | |
114 | */ | |
210871b6 | 115 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
8d7849db VS |
116 | |
117 | scanline = intel_get_crtc_scanline(crtc); | |
118 | if (scanline < min || scanline > max) | |
119 | break; | |
120 | ||
121 | if (timeout <= 0) { | |
122 | DRM_ERROR("Potential atomic update failure on pipe %c\n", | |
123 | pipe_name(crtc->pipe)); | |
124 | break; | |
125 | } | |
126 | ||
127 | local_irq_enable(); | |
128 | ||
129 | timeout = schedule_timeout(timeout); | |
130 | ||
131 | local_irq_disable(); | |
132 | } | |
133 | ||
210871b6 | 134 | finish_wait(wq, &wait); |
8d7849db | 135 | |
1e3feefd | 136 | drm_crtc_vblank_put(&crtc->base); |
8d7849db | 137 | |
eb120ef6 JB |
138 | crtc->debug.scanline_start = scanline; |
139 | crtc->debug.start_vbl_time = ktime_get(); | |
a2991414 | 140 | crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc); |
8d7849db | 141 | |
d637ce3f | 142 | trace_i915_pipe_update_vblank_evaded(crtc); |
8d7849db VS |
143 | } |
144 | ||
26ff2762 ACO |
145 | /** |
146 | * intel_pipe_update_end() - end update of a set of display registers | |
147 | * @crtc: the crtc of which the registers were updated | |
148 | * @start_vbl_count: start vblank counter (used for error checking) | |
149 | * | |
150 | * Mark the end of an update started with intel_pipe_update_start(). This | |
151 | * re-enables interrupts and verifies the update was actually completed | |
152 | * before a vblank using the value of @start_vbl_count. | |
153 | */ | |
51cbaf01 | 154 | void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work) |
8d7849db | 155 | { |
8d7849db | 156 | enum pipe pipe = crtc->pipe; |
eb120ef6 | 157 | int scanline_end = intel_get_crtc_scanline(crtc); |
a2991414 | 158 | u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); |
85a62bf9 | 159 | ktime_t end_vbl_time = ktime_get(); |
8d7849db | 160 | |
51cbaf01 ML |
161 | if (work) { |
162 | work->flip_queued_vblank = end_vbl_count; | |
163 | smp_mb__before_atomic(); | |
164 | atomic_set(&work->pending, 1); | |
165 | } | |
166 | ||
d637ce3f | 167 | trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); |
25ef284a | 168 | |
1f7528c4 DV |
169 | /* We're still in the vblank-evade critical section, this can't race. |
170 | * Would be slightly nice to just grab the vblank count and arm the | |
171 | * event outside of the critical section - the spinlock might spin for a | |
172 | * while ... */ | |
173 | if (crtc->base.state->event) { | |
174 | WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); | |
175 | ||
176 | spin_lock(&crtc->base.dev->event_lock); | |
177 | drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event); | |
178 | spin_unlock(&crtc->base.dev->event_lock); | |
179 | ||
180 | crtc->base.state->event = NULL; | |
181 | } | |
182 | ||
8d7849db VS |
183 | local_irq_enable(); |
184 | ||
eb120ef6 JB |
185 | if (crtc->debug.start_vbl_count && |
186 | crtc->debug.start_vbl_count != end_vbl_count) { | |
187 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", | |
188 | pipe_name(pipe), crtc->debug.start_vbl_count, | |
189 | end_vbl_count, | |
190 | ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), | |
191 | crtc->debug.min_vbl, crtc->debug.max_vbl, | |
192 | crtc->debug.scanline_start, scanline_end); | |
193 | } | |
8d7849db VS |
194 | } |
195 | ||
dc2a41b4 | 196 | static void |
2fde1391 ML |
197 | skl_update_plane(struct drm_plane *drm_plane, |
198 | const struct intel_crtc_state *crtc_state, | |
199 | const struct intel_plane_state *plane_state) | |
dc2a41b4 DL |
200 | { |
201 | struct drm_device *dev = drm_plane->dev; | |
fac5e23e | 202 | struct drm_i915_private *dev_priv = to_i915(dev); |
dc2a41b4 | 203 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); |
2fde1391 | 204 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 205 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
dc2a41b4 DL |
206 | const int pipe = intel_plane->pipe; |
207 | const int plane = intel_plane->plane + 1; | |
3b7a5119 | 208 | u32 plane_ctl, stride_div, stride; |
2fde1391 | 209 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
44eb0cb9 | 210 | u32 surf_addr; |
3b7a5119 | 211 | u32 tile_height, plane_offset, plane_size; |
8d0deca8 | 212 | unsigned int rotation = plane_state->base.rotation; |
3b7a5119 | 213 | int x_offset, y_offset; |
2fde1391 ML |
214 | int crtc_x = plane_state->dst.x1; |
215 | int crtc_y = plane_state->dst.y1; | |
216 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
217 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
218 | uint32_t x = plane_state->src.x1 >> 16; | |
219 | uint32_t y = plane_state->src.y1 >> 16; | |
220 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
221 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
dc2a41b4 | 222 | |
48fe4691 | 223 | plane_ctl = PLANE_CTL_ENABLE | |
e12c8ce8 | 224 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
48fe4691 | 225 | PLANE_CTL_PIPE_CSC_ENABLE; |
dc2a41b4 | 226 | |
c331879c CK |
227 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
228 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
b321803d | 229 | |
c331879c | 230 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
dc2a41b4 | 231 | |
7b49f948 | 232 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d DL |
233 | fb->pixel_format); |
234 | ||
dc2a41b4 DL |
235 | /* Sizes are 0 based */ |
236 | src_w--; | |
237 | src_h--; | |
238 | crtc_w--; | |
239 | crtc_h--; | |
240 | ||
47ecbb20 VS |
241 | if (key->flags) { |
242 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); | |
243 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); | |
244 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); | |
245 | } | |
246 | ||
247 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
248 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
249 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
250 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
251 | ||
dedf278c | 252 | surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); |
121920fa | 253 | |
3b7a5119 | 254 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
255 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
256 | ||
3b7a5119 | 257 | /* stride: Surface height in tiles */ |
832be82f | 258 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 SJ |
259 | stride = DIV_ROUND_UP(fb->height, tile_height); |
260 | plane_size = (src_w << 16) | src_h; | |
261 | x_offset = stride * tile_height - y - (src_h + 1); | |
262 | y_offset = x; | |
263 | } else { | |
264 | stride = fb->pitches[0] / stride_div; | |
265 | plane_size = (src_h << 16) | src_w; | |
266 | x_offset = x; | |
267 | y_offset = y; | |
268 | } | |
269 | plane_offset = y_offset << 16 | x_offset; | |
270 | ||
271 | I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); | |
272 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); | |
3b7a5119 | 273 | I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); |
c331879c CK |
274 | |
275 | /* program plane scaler */ | |
2fde1391 | 276 | if (plane_state->scaler_id >= 0) { |
2fde1391 | 277 | int scaler_id = plane_state->scaler_id; |
7494bcdc | 278 | const struct intel_scaler *scaler; |
c331879c CK |
279 | |
280 | DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, | |
281 | PS_PLANE_SEL(plane)); | |
7494bcdc ID |
282 | |
283 | scaler = &crtc_state->scaler_state.scalers[scaler_id]; | |
284 | ||
285 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), | |
286 | PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode); | |
c331879c CK |
287 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
288 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); | |
289 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), | |
290 | ((crtc_w + 1) << 16)|(crtc_h + 1)); | |
291 | ||
292 | I915_WRITE(PLANE_POS(pipe, plane), 0); | |
293 | } else { | |
294 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); | |
295 | } | |
296 | ||
dc2a41b4 | 297 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); |
121920fa | 298 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
dc2a41b4 DL |
299 | POSTING_READ(PLANE_SURF(pipe, plane)); |
300 | } | |
301 | ||
302 | static void | |
7fabf5ef | 303 | skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
dc2a41b4 | 304 | { |
a8ad0d8e | 305 | struct drm_device *dev = dplane->dev; |
fac5e23e | 306 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8ad0d8e | 307 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
dc2a41b4 DL |
308 | const int pipe = intel_plane->pipe; |
309 | const int plane = intel_plane->plane + 1; | |
310 | ||
48fe4691 | 311 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
dc2a41b4 | 312 | |
2ddc1dad VS |
313 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
314 | POSTING_READ(PLANE_SURF(pipe, plane)); | |
dc2a41b4 DL |
315 | } |
316 | ||
6ca2aeb2 VS |
317 | static void |
318 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) | |
319 | { | |
fac5e23e | 320 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); |
6ca2aeb2 VS |
321 | int plane = intel_plane->plane; |
322 | ||
323 | /* Seems RGB data bypasses the CSC always */ | |
324 | if (!format_is_yuv(format)) | |
325 | return; | |
326 | ||
327 | /* | |
328 | * BT.601 limited range YCbCr -> full range RGB | |
329 | * | |
330 | * |r| | 6537 4769 0| |cr | | |
331 | * |g| = |-3330 4769 -1605| x |y-64| | |
332 | * |b| | 0 4769 8263| |cb | | |
333 | * | |
334 | * Cb and Cr apparently come in as signed already, so no | |
335 | * need for any offset. For Y we need to remove the offset. | |
336 | */ | |
337 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); | |
338 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
339 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
340 | ||
341 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); | |
342 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); | |
343 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); | |
344 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); | |
345 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); | |
346 | ||
347 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); | |
348 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
349 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
350 | ||
351 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
352 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
353 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
354 | } | |
355 | ||
7f1f3851 | 356 | static void |
2fde1391 ML |
357 | vlv_update_plane(struct drm_plane *dplane, |
358 | const struct intel_crtc_state *crtc_state, | |
359 | const struct intel_plane_state *plane_state) | |
7f1f3851 JB |
360 | { |
361 | struct drm_device *dev = dplane->dev; | |
fac5e23e | 362 | struct drm_i915_private *dev_priv = to_i915(dev); |
7f1f3851 | 363 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
2fde1391 | 364 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 365 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7f1f3851 JB |
366 | int pipe = intel_plane->pipe; |
367 | int plane = intel_plane->plane; | |
368 | u32 sprctl; | |
54ea9da8 | 369 | u32 sprsurf_offset, linear_offset; |
8d0deca8 | 370 | unsigned int rotation = dplane->state->rotation; |
ac484963 | 371 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2fde1391 ML |
372 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
373 | int crtc_x = plane_state->dst.x1; | |
374 | int crtc_y = plane_state->dst.y1; | |
375 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
376 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
377 | uint32_t x = plane_state->src.x1 >> 16; | |
378 | uint32_t y = plane_state->src.y1 >> 16; | |
379 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
380 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
7f1f3851 | 381 | |
48fe4691 | 382 | sprctl = SP_ENABLE; |
7f1f3851 JB |
383 | |
384 | switch (fb->pixel_format) { | |
385 | case DRM_FORMAT_YUYV: | |
386 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; | |
387 | break; | |
388 | case DRM_FORMAT_YVYU: | |
389 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; | |
390 | break; | |
391 | case DRM_FORMAT_UYVY: | |
392 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; | |
393 | break; | |
394 | case DRM_FORMAT_VYUY: | |
395 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; | |
396 | break; | |
397 | case DRM_FORMAT_RGB565: | |
398 | sprctl |= SP_FORMAT_BGR565; | |
399 | break; | |
400 | case DRM_FORMAT_XRGB8888: | |
401 | sprctl |= SP_FORMAT_BGRX8888; | |
402 | break; | |
403 | case DRM_FORMAT_ARGB8888: | |
404 | sprctl |= SP_FORMAT_BGRA8888; | |
405 | break; | |
406 | case DRM_FORMAT_XBGR2101010: | |
407 | sprctl |= SP_FORMAT_RGBX1010102; | |
408 | break; | |
409 | case DRM_FORMAT_ABGR2101010: | |
410 | sprctl |= SP_FORMAT_RGBA1010102; | |
411 | break; | |
412 | case DRM_FORMAT_XBGR8888: | |
413 | sprctl |= SP_FORMAT_RGBX8888; | |
414 | break; | |
415 | case DRM_FORMAT_ABGR8888: | |
416 | sprctl |= SP_FORMAT_RGBA8888; | |
417 | break; | |
418 | default: | |
419 | /* | |
420 | * If we get here one of the upper layers failed to filter | |
421 | * out the unsupported plane formats | |
422 | */ | |
423 | BUG(); | |
424 | break; | |
425 | } | |
426 | ||
4ea67bc7 VS |
427 | /* |
428 | * Enable gamma to match primary/cursor plane behaviour. | |
429 | * FIXME should be user controllable via propertiesa. | |
430 | */ | |
431 | sprctl |= SP_GAMMA_ENABLE; | |
432 | ||
7f1f3851 JB |
433 | if (obj->tiling_mode != I915_TILING_NONE) |
434 | sprctl |= SP_TILED; | |
435 | ||
7f1f3851 JB |
436 | /* Sizes are 0 based */ |
437 | src_w--; | |
438 | src_h--; | |
439 | crtc_w--; | |
440 | crtc_h--; | |
441 | ||
ac484963 | 442 | linear_offset = y * fb->pitches[0] + x * cpp; |
4f2d9934 | 443 | sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 444 | fb->pitches[0], rotation); |
7f1f3851 JB |
445 | linear_offset -= sprsurf_offset; |
446 | ||
8d0deca8 | 447 | if (rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
448 | sprctl |= SP_ROTATE_180; |
449 | ||
450 | x += src_w; | |
451 | y += src_h; | |
ac484963 | 452 | linear_offset += src_h * fb->pitches[0] + src_w * cpp; |
76eebda7 VS |
453 | } |
454 | ||
47ecbb20 VS |
455 | if (key->flags) { |
456 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); | |
457 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); | |
458 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); | |
459 | } | |
460 | ||
461 | if (key->flags & I915_SET_COLORKEY_SOURCE) | |
462 | sprctl |= SP_SOURCE_KEY; | |
463 | ||
6ca2aeb2 VS |
464 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
465 | chv_update_csc(intel_plane, fb->pixel_format); | |
466 | ||
ca6ad025 VS |
467 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
468 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); | |
469 | ||
7f1f3851 JB |
470 | if (obj->tiling_mode != I915_TILING_NONE) |
471 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); | |
472 | else | |
473 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); | |
474 | ||
c14b0485 VS |
475 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
476 | ||
7f1f3851 JB |
477 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
478 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
85ba7b7d DV |
479 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
480 | sprsurf_offset); | |
b12ce1d8 | 481 | POSTING_READ(SPSURF(pipe, plane)); |
7f1f3851 JB |
482 | } |
483 | ||
484 | static void | |
7fabf5ef | 485 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
7f1f3851 JB |
486 | { |
487 | struct drm_device *dev = dplane->dev; | |
fac5e23e | 488 | struct drm_i915_private *dev_priv = to_i915(dev); |
7f1f3851 JB |
489 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
490 | int pipe = intel_plane->pipe; | |
491 | int plane = intel_plane->plane; | |
492 | ||
48fe4691 VS |
493 | I915_WRITE(SPCNTR(pipe, plane), 0); |
494 | ||
85ba7b7d | 495 | I915_WRITE(SPSURF(pipe, plane), 0); |
b12ce1d8 | 496 | POSTING_READ(SPSURF(pipe, plane)); |
7f1f3851 JB |
497 | } |
498 | ||
b840d907 | 499 | static void |
2fde1391 ML |
500 | ivb_update_plane(struct drm_plane *plane, |
501 | const struct intel_crtc_state *crtc_state, | |
502 | const struct intel_plane_state *plane_state) | |
b840d907 JB |
503 | { |
504 | struct drm_device *dev = plane->dev; | |
fac5e23e | 505 | struct drm_i915_private *dev_priv = to_i915(dev); |
b840d907 | 506 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2fde1391 | 507 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 508 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
47ecbb20 | 509 | enum pipe pipe = intel_plane->pipe; |
b840d907 | 510 | u32 sprctl, sprscale = 0; |
54ea9da8 | 511 | u32 sprsurf_offset, linear_offset; |
8d0deca8 | 512 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 513 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2fde1391 ML |
514 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
515 | int crtc_x = plane_state->dst.x1; | |
516 | int crtc_y = plane_state->dst.y1; | |
517 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
518 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
519 | uint32_t x = plane_state->src.x1 >> 16; | |
520 | uint32_t y = plane_state->src.y1 >> 16; | |
521 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
522 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
b840d907 | 523 | |
48fe4691 | 524 | sprctl = SPRITE_ENABLE; |
b840d907 JB |
525 | |
526 | switch (fb->pixel_format) { | |
527 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 528 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
529 | break; |
530 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 531 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
532 | break; |
533 | case DRM_FORMAT_YUYV: | |
534 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
535 | break; |
536 | case DRM_FORMAT_YVYU: | |
537 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
538 | break; |
539 | case DRM_FORMAT_UYVY: | |
540 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
541 | break; |
542 | case DRM_FORMAT_VYUY: | |
543 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
544 | break; |
545 | default: | |
28d491df | 546 | BUG(); |
b840d907 JB |
547 | } |
548 | ||
4ea67bc7 VS |
549 | /* |
550 | * Enable gamma to match primary/cursor plane behaviour. | |
551 | * FIXME should be user controllable via propertiesa. | |
552 | */ | |
553 | sprctl |= SPRITE_GAMMA_ENABLE; | |
554 | ||
b840d907 JB |
555 | if (obj->tiling_mode != I915_TILING_NONE) |
556 | sprctl |= SPRITE_TILED; | |
557 | ||
b42c6009 | 558 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
559 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
560 | else | |
561 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
562 | ||
6bbfa1c5 | 563 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
86d3efce VS |
564 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
565 | ||
b840d907 JB |
566 | /* Sizes are 0 based */ |
567 | src_w--; | |
568 | src_h--; | |
569 | crtc_w--; | |
570 | crtc_h--; | |
571 | ||
8553c18e | 572 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 | 573 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
b840d907 | 574 | |
ac484963 | 575 | linear_offset = y * fb->pitches[0] + x * cpp; |
4f2d9934 | 576 | sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 577 | fb->pitches[0], rotation); |
5a35e99e DL |
578 | linear_offset -= sprsurf_offset; |
579 | ||
8d0deca8 | 580 | if (rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
581 | sprctl |= SPRITE_ROTATE_180; |
582 | ||
583 | /* HSW and BDW does this automagically in hardware */ | |
584 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
585 | x += src_w; | |
586 | y += src_h; | |
ac484963 | 587 | linear_offset += src_h * fb->pitches[0] + src_w * cpp; |
76eebda7 VS |
588 | } |
589 | } | |
590 | ||
47ecbb20 VS |
591 | if (key->flags) { |
592 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); | |
593 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); | |
594 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); | |
595 | } | |
596 | ||
597 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
598 | sprctl |= SPRITE_DEST_KEY; | |
599 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
600 | sprctl |= SPRITE_SOURCE_KEY; | |
601 | ||
ca6ad025 VS |
602 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
603 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
604 | ||
5a35e99e DL |
605 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
606 | * register */ | |
b3dc685e | 607 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
c54173a8 | 608 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 609 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 610 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
611 | else |
612 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 613 | |
b840d907 | 614 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
615 | if (intel_plane->can_scale) |
616 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 617 | I915_WRITE(SPRCTL(pipe), sprctl); |
85ba7b7d DV |
618 | I915_WRITE(SPRSURF(pipe), |
619 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); | |
b12ce1d8 | 620 | POSTING_READ(SPRSURF(pipe)); |
b840d907 JB |
621 | } |
622 | ||
623 | static void | |
7fabf5ef | 624 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
625 | { |
626 | struct drm_device *dev = plane->dev; | |
fac5e23e | 627 | struct drm_i915_private *dev_priv = to_i915(dev); |
b840d907 JB |
628 | struct intel_plane *intel_plane = to_intel_plane(plane); |
629 | int pipe = intel_plane->pipe; | |
630 | ||
c562657a | 631 | I915_WRITE(SPRCTL(pipe), 0); |
b840d907 | 632 | /* Can't leave the scaler enabled... */ |
2d354c34 DL |
633 | if (intel_plane->can_scale) |
634 | I915_WRITE(SPRSCALE(pipe), 0); | |
5b633d6b | 635 | |
b12ce1d8 VS |
636 | I915_WRITE(SPRSURF(pipe), 0); |
637 | POSTING_READ(SPRSURF(pipe)); | |
b840d907 JB |
638 | } |
639 | ||
640 | static void | |
2fde1391 ML |
641 | ilk_update_plane(struct drm_plane *plane, |
642 | const struct intel_crtc_state *crtc_state, | |
643 | const struct intel_plane_state *plane_state) | |
b840d907 JB |
644 | { |
645 | struct drm_device *dev = plane->dev; | |
fac5e23e | 646 | struct drm_i915_private *dev_priv = to_i915(dev); |
b840d907 | 647 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2fde1391 | 648 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 649 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2bd3c3cb | 650 | int pipe = intel_plane->pipe; |
8aaa81a1 | 651 | u32 dvscntr, dvsscale; |
54ea9da8 | 652 | u32 dvssurf_offset, linear_offset; |
8d0deca8 | 653 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 654 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2fde1391 ML |
655 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
656 | int crtc_x = plane_state->dst.x1; | |
657 | int crtc_y = plane_state->dst.y1; | |
658 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
659 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
660 | uint32_t x = plane_state->src.x1 >> 16; | |
661 | uint32_t y = plane_state->src.y1 >> 16; | |
662 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
663 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
b840d907 | 664 | |
48fe4691 | 665 | dvscntr = DVS_ENABLE; |
b840d907 JB |
666 | |
667 | switch (fb->pixel_format) { | |
668 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 669 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
670 | break; |
671 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 672 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
673 | break; |
674 | case DRM_FORMAT_YUYV: | |
675 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
676 | break; |
677 | case DRM_FORMAT_YVYU: | |
678 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
679 | break; |
680 | case DRM_FORMAT_UYVY: | |
681 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
682 | break; |
683 | case DRM_FORMAT_VYUY: | |
684 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
685 | break; |
686 | default: | |
28d491df | 687 | BUG(); |
b840d907 JB |
688 | } |
689 | ||
4ea67bc7 VS |
690 | /* |
691 | * Enable gamma to match primary/cursor plane behaviour. | |
692 | * FIXME should be user controllable via propertiesa. | |
693 | */ | |
694 | dvscntr |= DVS_GAMMA_ENABLE; | |
695 | ||
b840d907 JB |
696 | if (obj->tiling_mode != I915_TILING_NONE) |
697 | dvscntr |= DVS_TILED; | |
698 | ||
d1686ae3 CW |
699 | if (IS_GEN6(dev)) |
700 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
701 | |
702 | /* Sizes are 0 based */ | |
703 | src_w--; | |
704 | src_h--; | |
705 | crtc_w--; | |
706 | crtc_h--; | |
707 | ||
8aaa81a1 | 708 | dvsscale = 0; |
8368f014 | 709 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 JB |
710 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
711 | ||
ac484963 | 712 | linear_offset = y * fb->pitches[0] + x * cpp; |
4f2d9934 | 713 | dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 714 | fb->pitches[0], rotation); |
5a35e99e DL |
715 | linear_offset -= dvssurf_offset; |
716 | ||
8d0deca8 | 717 | if (rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
718 | dvscntr |= DVS_ROTATE_180; |
719 | ||
720 | x += src_w; | |
721 | y += src_h; | |
ac484963 | 722 | linear_offset += src_h * fb->pitches[0] + src_w * cpp; |
76eebda7 VS |
723 | } |
724 | ||
47ecbb20 VS |
725 | if (key->flags) { |
726 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); | |
727 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); | |
728 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); | |
729 | } | |
730 | ||
731 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
732 | dvscntr |= DVS_DEST_KEY; | |
733 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
734 | dvscntr |= DVS_SOURCE_KEY; | |
735 | ||
ca6ad025 VS |
736 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
737 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
738 | ||
5a35e99e | 739 | if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 740 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
741 | else |
742 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 743 | |
b840d907 JB |
744 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
745 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
746 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
85ba7b7d DV |
747 | I915_WRITE(DVSSURF(pipe), |
748 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); | |
b12ce1d8 | 749 | POSTING_READ(DVSSURF(pipe)); |
b840d907 JB |
750 | } |
751 | ||
752 | static void | |
7fabf5ef | 753 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
754 | { |
755 | struct drm_device *dev = plane->dev; | |
fac5e23e | 756 | struct drm_i915_private *dev_priv = to_i915(dev); |
b840d907 JB |
757 | struct intel_plane *intel_plane = to_intel_plane(plane); |
758 | int pipe = intel_plane->pipe; | |
759 | ||
48fe4691 | 760 | I915_WRITE(DVSCNTR(pipe), 0); |
b840d907 JB |
761 | /* Disable the scaler */ |
762 | I915_WRITE(DVSSCALE(pipe), 0); | |
48fe4691 | 763 | |
85ba7b7d | 764 | I915_WRITE(DVSSURF(pipe), 0); |
b12ce1d8 | 765 | POSTING_READ(DVSSURF(pipe)); |
b840d907 JB |
766 | } |
767 | ||
768 | static int | |
96d61a7f | 769 | intel_check_sprite_plane(struct drm_plane *plane, |
061e4b8d | 770 | struct intel_crtc_state *crtc_state, |
96d61a7f | 771 | struct intel_plane_state *state) |
b840d907 | 772 | { |
c331879c | 773 | struct drm_device *dev = plane->dev; |
061e4b8d ML |
774 | struct drm_crtc *crtc = state->base.crtc; |
775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b840d907 | 776 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 777 | struct drm_framebuffer *fb = state->base.fb; |
96d61a7f GP |
778 | int crtc_x, crtc_y; |
779 | unsigned int crtc_w, crtc_h; | |
780 | uint32_t src_x, src_y, src_w, src_h; | |
781 | struct drm_rect *src = &state->src; | |
782 | struct drm_rect *dst = &state->dst; | |
96d61a7f | 783 | const struct drm_rect *clip = &state->clip; |
1731693a VS |
784 | int hscale, vscale; |
785 | int max_scale, min_scale; | |
225c228a | 786 | bool can_scale; |
cf4c7c12 MR |
787 | |
788 | if (!fb) { | |
789 | state->visible = false; | |
da20eabd | 790 | return 0; |
cf4c7c12 | 791 | } |
5e1bac2f | 792 | |
1731693a VS |
793 | /* Don't modify another pipe's plane */ |
794 | if (intel_plane->pipe != intel_crtc->pipe) { | |
795 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); | |
b840d907 | 796 | return -EINVAL; |
1731693a | 797 | } |
b840d907 | 798 | |
1731693a VS |
799 | /* FIXME check all gen limits */ |
800 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { | |
801 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); | |
b840d907 | 802 | return -EINVAL; |
1731693a | 803 | } |
b840d907 | 804 | |
225c228a CK |
805 | /* setup can_scale, min_scale, max_scale */ |
806 | if (INTEL_INFO(dev)->gen >= 9) { | |
807 | /* use scaler when colorkey is not required */ | |
818ed961 | 808 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { |
225c228a CK |
809 | can_scale = 1; |
810 | min_scale = 1; | |
811 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
812 | } else { | |
813 | can_scale = 0; | |
814 | min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
815 | max_scale = DRM_PLANE_HELPER_NO_SCALING; | |
816 | } | |
817 | } else { | |
818 | can_scale = intel_plane->can_scale; | |
819 | max_scale = intel_plane->max_downscale << 16; | |
820 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); | |
821 | } | |
822 | ||
3c3686cd VS |
823 | /* |
824 | * FIXME the following code does a bunch of fuzzy adjustments to the | |
825 | * coordinates and sizes. We probably need some way to decide whether | |
826 | * more strict checking should be done instead. | |
827 | */ | |
96d61a7f | 828 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
8e7d688b | 829 | state->base.rotation); |
76eebda7 | 830 | |
96d61a7f | 831 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 832 | BUG_ON(hscale < 0); |
1731693a | 833 | |
96d61a7f | 834 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 835 | BUG_ON(vscale < 0); |
b840d907 | 836 | |
818ed961 | 837 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
b840d907 | 838 | |
96d61a7f GP |
839 | crtc_x = dst->x1; |
840 | crtc_y = dst->y1; | |
841 | crtc_w = drm_rect_width(dst); | |
842 | crtc_h = drm_rect_height(dst); | |
2d354c34 | 843 | |
96d61a7f | 844 | if (state->visible) { |
3c3686cd | 845 | /* check again in case clipping clamped the results */ |
96d61a7f | 846 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
847 | if (hscale < 0) { |
848 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); | |
c70f577a VS |
849 | drm_rect_debug_print("src: ", src, true); |
850 | drm_rect_debug_print("dst: ", dst, false); | |
3c3686cd VS |
851 | |
852 | return hscale; | |
853 | } | |
854 | ||
96d61a7f | 855 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
856 | if (vscale < 0) { |
857 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); | |
c70f577a VS |
858 | drm_rect_debug_print("src: ", src, true); |
859 | drm_rect_debug_print("dst: ", dst, false); | |
3c3686cd VS |
860 | |
861 | return vscale; | |
862 | } | |
863 | ||
1731693a | 864 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
96d61a7f GP |
865 | drm_rect_adjust_size(src, |
866 | drm_rect_width(dst) * hscale - drm_rect_width(src), | |
867 | drm_rect_height(dst) * vscale - drm_rect_height(src)); | |
1731693a | 868 | |
96d61a7f | 869 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
8e7d688b | 870 | state->base.rotation); |
76eebda7 | 871 | |
1731693a | 872 | /* sanity check to make sure the src viewport wasn't enlarged */ |
ea2c67bb MR |
873 | WARN_ON(src->x1 < (int) state->base.src_x || |
874 | src->y1 < (int) state->base.src_y || | |
875 | src->x2 > (int) state->base.src_x + state->base.src_w || | |
876 | src->y2 > (int) state->base.src_y + state->base.src_h); | |
1731693a VS |
877 | |
878 | /* | |
879 | * Hardware doesn't handle subpixel coordinates. | |
880 | * Adjust to (macro)pixel boundary, but be careful not to | |
881 | * increase the source viewport size, because that could | |
882 | * push the downscaling factor out of bounds. | |
1731693a | 883 | */ |
96d61a7f GP |
884 | src_x = src->x1 >> 16; |
885 | src_w = drm_rect_width(src) >> 16; | |
886 | src_y = src->y1 >> 16; | |
887 | src_h = drm_rect_height(src) >> 16; | |
1731693a VS |
888 | |
889 | if (format_is_yuv(fb->pixel_format)) { | |
890 | src_x &= ~1; | |
891 | src_w &= ~1; | |
892 | ||
893 | /* | |
894 | * Must keep src and dst the | |
895 | * same if we can't scale. | |
896 | */ | |
225c228a | 897 | if (!can_scale) |
1731693a VS |
898 | crtc_w &= ~1; |
899 | ||
900 | if (crtc_w == 0) | |
96d61a7f | 901 | state->visible = false; |
1731693a VS |
902 | } |
903 | } | |
904 | ||
905 | /* Check size restrictions when scaling */ | |
96d61a7f | 906 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
1731693a | 907 | unsigned int width_bytes; |
ac484963 | 908 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
1731693a | 909 | |
225c228a | 910 | WARN_ON(!can_scale); |
1731693a VS |
911 | |
912 | /* FIXME interlacing min height is 6 */ | |
913 | ||
914 | if (crtc_w < 3 || crtc_h < 3) | |
96d61a7f | 915 | state->visible = false; |
1731693a VS |
916 | |
917 | if (src_w < 3 || src_h < 3) | |
96d61a7f | 918 | state->visible = false; |
1731693a | 919 | |
ac484963 | 920 | width_bytes = ((src_x * cpp) & 63) + src_w * cpp; |
1731693a | 921 | |
c331879c CK |
922 | if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || |
923 | width_bytes > 4096 || fb->pitches[0] > 4096)) { | |
1731693a VS |
924 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
925 | return -EINVAL; | |
926 | } | |
927 | } | |
928 | ||
96d61a7f | 929 | if (state->visible) { |
0a5ae1b0 CK |
930 | src->x1 = src_x << 16; |
931 | src->x2 = (src_x + src_w) << 16; | |
932 | src->y1 = src_y << 16; | |
933 | src->y2 = (src_y + src_h) << 16; | |
96d61a7f GP |
934 | } |
935 | ||
936 | dst->x1 = crtc_x; | |
937 | dst->x2 = crtc_x + crtc_w; | |
938 | dst->y1 = crtc_y; | |
939 | dst->y2 = crtc_y + crtc_h; | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
8ea30864 JB |
944 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
945 | struct drm_file *file_priv) | |
946 | { | |
947 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 | 948 | struct drm_plane *plane; |
818ed961 ML |
949 | struct drm_plane_state *plane_state; |
950 | struct drm_atomic_state *state; | |
951 | struct drm_modeset_acquire_ctx ctx; | |
8ea30864 JB |
952 | int ret = 0; |
953 | ||
8ea30864 JB |
954 | /* Make sure we don't try to enable both src & dest simultaneously */ |
955 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
956 | return -EINVAL; | |
957 | ||
666a4537 | 958 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
47ecbb20 VS |
959 | set->flags & I915_SET_COLORKEY_DESTINATION) |
960 | return -EINVAL; | |
961 | ||
7707e653 | 962 | plane = drm_plane_find(dev, set->plane_id); |
818ed961 ML |
963 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) |
964 | return -ENOENT; | |
8ea30864 | 965 | |
818ed961 | 966 | drm_modeset_acquire_init(&ctx, 0); |
6156a456 | 967 | |
818ed961 ML |
968 | state = drm_atomic_state_alloc(plane->dev); |
969 | if (!state) { | |
970 | ret = -ENOMEM; | |
971 | goto out; | |
6156a456 | 972 | } |
818ed961 ML |
973 | state->acquire_ctx = &ctx; |
974 | ||
975 | while (1) { | |
976 | plane_state = drm_atomic_get_plane_state(state, plane); | |
977 | ret = PTR_ERR_OR_ZERO(plane_state); | |
978 | if (!ret) { | |
979 | to_intel_plane_state(plane_state)->ckey = *set; | |
980 | ret = drm_atomic_commit(state); | |
981 | } | |
6156a456 | 982 | |
818ed961 ML |
983 | if (ret != -EDEADLK) |
984 | break; | |
8ea30864 | 985 | |
818ed961 ML |
986 | drm_atomic_state_clear(state); |
987 | drm_modeset_backoff(&ctx); | |
988 | } | |
8ea30864 | 989 | |
818ed961 ML |
990 | if (ret) |
991 | drm_atomic_state_free(state); | |
5e1bac2f | 992 | |
818ed961 ML |
993 | out: |
994 | drm_modeset_drop_locks(&ctx); | |
995 | drm_modeset_acquire_fini(&ctx); | |
996 | return ret; | |
5e1bac2f JB |
997 | } |
998 | ||
dada2d53 | 999 | static const uint32_t ilk_plane_formats[] = { |
d1686ae3 CW |
1000 | DRM_FORMAT_XRGB8888, |
1001 | DRM_FORMAT_YUYV, | |
1002 | DRM_FORMAT_YVYU, | |
1003 | DRM_FORMAT_UYVY, | |
1004 | DRM_FORMAT_VYUY, | |
1005 | }; | |
1006 | ||
dada2d53 | 1007 | static const uint32_t snb_plane_formats[] = { |
b840d907 JB |
1008 | DRM_FORMAT_XBGR8888, |
1009 | DRM_FORMAT_XRGB8888, | |
1010 | DRM_FORMAT_YUYV, | |
1011 | DRM_FORMAT_YVYU, | |
1012 | DRM_FORMAT_UYVY, | |
1013 | DRM_FORMAT_VYUY, | |
1014 | }; | |
1015 | ||
dada2d53 | 1016 | static const uint32_t vlv_plane_formats[] = { |
7f1f3851 JB |
1017 | DRM_FORMAT_RGB565, |
1018 | DRM_FORMAT_ABGR8888, | |
1019 | DRM_FORMAT_ARGB8888, | |
1020 | DRM_FORMAT_XBGR8888, | |
1021 | DRM_FORMAT_XRGB8888, | |
1022 | DRM_FORMAT_XBGR2101010, | |
1023 | DRM_FORMAT_ABGR2101010, | |
1024 | DRM_FORMAT_YUYV, | |
1025 | DRM_FORMAT_YVYU, | |
1026 | DRM_FORMAT_UYVY, | |
1027 | DRM_FORMAT_VYUY, | |
1028 | }; | |
1029 | ||
dc2a41b4 DL |
1030 | static uint32_t skl_plane_formats[] = { |
1031 | DRM_FORMAT_RGB565, | |
1032 | DRM_FORMAT_ABGR8888, | |
1033 | DRM_FORMAT_ARGB8888, | |
1034 | DRM_FORMAT_XBGR8888, | |
1035 | DRM_FORMAT_XRGB8888, | |
1036 | DRM_FORMAT_YUYV, | |
1037 | DRM_FORMAT_YVYU, | |
1038 | DRM_FORMAT_UYVY, | |
1039 | DRM_FORMAT_VYUY, | |
1040 | }; | |
1041 | ||
b840d907 | 1042 | int |
7f1f3851 | 1043 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
b840d907 | 1044 | { |
fca0ce2a VS |
1045 | struct intel_plane *intel_plane = NULL; |
1046 | struct intel_plane_state *state = NULL; | |
b840d907 | 1047 | unsigned long possible_crtcs; |
d1686ae3 CW |
1048 | const uint32_t *plane_formats; |
1049 | int num_plane_formats; | |
b840d907 JB |
1050 | int ret; |
1051 | ||
d1686ae3 | 1052 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 1053 | return -ENODEV; |
b840d907 | 1054 | |
b14c5679 | 1055 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
fca0ce2a VS |
1056 | if (!intel_plane) { |
1057 | ret = -ENOMEM; | |
1058 | goto fail; | |
1059 | } | |
b840d907 | 1060 | |
8e7d688b MR |
1061 | state = intel_create_plane_state(&intel_plane->base); |
1062 | if (!state) { | |
fca0ce2a VS |
1063 | ret = -ENOMEM; |
1064 | goto fail; | |
ea2c67bb | 1065 | } |
8e7d688b | 1066 | intel_plane->base.state = &state->base; |
ea2c67bb | 1067 | |
d1686ae3 CW |
1068 | switch (INTEL_INFO(dev)->gen) { |
1069 | case 5: | |
1070 | case 6: | |
2d354c34 | 1071 | intel_plane->can_scale = true; |
b840d907 | 1072 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
1073 | intel_plane->update_plane = ilk_update_plane; |
1074 | intel_plane->disable_plane = ilk_disable_plane; | |
d1686ae3 CW |
1075 | |
1076 | if (IS_GEN6(dev)) { | |
1077 | plane_formats = snb_plane_formats; | |
1078 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1079 | } else { | |
1080 | plane_formats = ilk_plane_formats; | |
1081 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
1082 | } | |
1083 | break; | |
1084 | ||
1085 | case 7: | |
4e0bbc31 | 1086 | case 8: |
d49f7091 | 1087 | if (IS_IVYBRIDGE(dev)) { |
2d354c34 | 1088 | intel_plane->can_scale = true; |
d49f7091 DL |
1089 | intel_plane->max_downscale = 2; |
1090 | } else { | |
1091 | intel_plane->can_scale = false; | |
1092 | intel_plane->max_downscale = 1; | |
1093 | } | |
7f1f3851 | 1094 | |
666a4537 | 1095 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
7f1f3851 JB |
1096 | intel_plane->update_plane = vlv_update_plane; |
1097 | intel_plane->disable_plane = vlv_disable_plane; | |
7f1f3851 JB |
1098 | |
1099 | plane_formats = vlv_plane_formats; | |
1100 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); | |
1101 | } else { | |
7f1f3851 JB |
1102 | intel_plane->update_plane = ivb_update_plane; |
1103 | intel_plane->disable_plane = ivb_disable_plane; | |
7f1f3851 JB |
1104 | |
1105 | plane_formats = snb_plane_formats; | |
1106 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1107 | } | |
d1686ae3 | 1108 | break; |
dc2a41b4 | 1109 | case 9: |
c331879c | 1110 | intel_plane->can_scale = true; |
dc2a41b4 DL |
1111 | intel_plane->update_plane = skl_update_plane; |
1112 | intel_plane->disable_plane = skl_disable_plane; | |
549e2bfb | 1113 | state->scaler_id = -1; |
dc2a41b4 DL |
1114 | |
1115 | plane_formats = skl_plane_formats; | |
1116 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); | |
1117 | break; | |
d1686ae3 | 1118 | default: |
fca0ce2a VS |
1119 | MISSING_CASE(INTEL_INFO(dev)->gen); |
1120 | ret = -ENODEV; | |
1121 | goto fail; | |
b840d907 JB |
1122 | } |
1123 | ||
1124 | intel_plane->pipe = pipe; | |
7f1f3851 | 1125 | intel_plane->plane = plane; |
d1b9d039 | 1126 | intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); |
c59cb179 | 1127 | intel_plane->check_plane = intel_check_sprite_plane; |
fca0ce2a | 1128 | |
b840d907 | 1129 | possible_crtcs = (1 << pipe); |
fca0ce2a | 1130 | |
38573dc1 VS |
1131 | if (INTEL_INFO(dev)->gen >= 9) |
1132 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, | |
1133 | &intel_plane_funcs, | |
1134 | plane_formats, num_plane_formats, | |
1135 | DRM_PLANE_TYPE_OVERLAY, | |
1136 | "plane %d%c", plane + 2, pipe_name(pipe)); | |
1137 | else | |
1138 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, | |
1139 | &intel_plane_funcs, | |
1140 | plane_formats, num_plane_formats, | |
1141 | DRM_PLANE_TYPE_OVERLAY, | |
1142 | "sprite %c", sprite_name(pipe, plane)); | |
fca0ce2a VS |
1143 | if (ret) |
1144 | goto fail; | |
7ed6eeee | 1145 | |
3b7a5119 | 1146 | intel_create_rotation_property(dev, intel_plane); |
b840d907 | 1147 | |
ea2c67bb MR |
1148 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
1149 | ||
fca0ce2a VS |
1150 | return 0; |
1151 | ||
1152 | fail: | |
1153 | kfree(state); | |
1154 | kfree(intel_plane); | |
1155 | ||
b840d907 JB |
1156 | return ret; |
1157 | } |