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b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
1731693a | 35 | #include <drm/drm_rect.h> |
ea2c67bb | 36 | #include <drm/drm_plane_helper.h> |
b840d907 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
b840d907 JB |
39 | #include "i915_drv.h" |
40 | ||
6ca2aeb2 VS |
41 | static bool |
42 | format_is_yuv(uint32_t format) | |
43 | { | |
44 | switch (format) { | |
45 | case DRM_FORMAT_YUYV: | |
46 | case DRM_FORMAT_UYVY: | |
47 | case DRM_FORMAT_VYUY: | |
48 | case DRM_FORMAT_YVYU: | |
49 | return true; | |
50 | default: | |
51 | return false; | |
52 | } | |
53 | } | |
54 | ||
8d7849db VS |
55 | static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs) |
56 | { | |
57 | /* paranoia */ | |
58 | if (!mode->crtc_htotal) | |
59 | return 1; | |
60 | ||
61 | return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal); | |
62 | } | |
63 | ||
26ff2762 ACO |
64 | /** |
65 | * intel_pipe_update_start() - start update of a set of display registers | |
66 | * @crtc: the crtc of which the registers are going to be updated | |
67 | * @start_vbl_count: vblank counter return pointer used for error checking | |
68 | * | |
69 | * Mark the start of an update to pipe registers that should be updated | |
70 | * atomically regarding vblank. If the next vblank will happens within | |
71 | * the next 100 us, this function waits until the vblank passes. | |
72 | * | |
73 | * After a successful call to this function, interrupts will be disabled | |
74 | * until a subsequent call to intel_pipe_update_end(). That is done to | |
75 | * avoid random delays. The value written to @start_vbl_count should be | |
76 | * supplied to intel_pipe_update_end() for error checking. | |
77 | * | |
78 | * Return: true if the call was successful | |
79 | */ | |
9362c7c5 | 80 | bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) |
8d7849db VS |
81 | { |
82 | struct drm_device *dev = crtc->base.dev; | |
6e3c9717 | 83 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
8d7849db VS |
84 | enum pipe pipe = crtc->pipe; |
85 | long timeout = msecs_to_jiffies_timeout(1); | |
86 | int scanline, min, max, vblank_start; | |
210871b6 | 87 | wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
8d7849db VS |
88 | DEFINE_WAIT(wait); |
89 | ||
8d7849db VS |
90 | vblank_start = mode->crtc_vblank_start; |
91 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
92 | vblank_start = DIV_ROUND_UP(vblank_start, 2); | |
93 | ||
94 | /* FIXME needs to be calibrated sensibly */ | |
95 | min = vblank_start - usecs_to_scanlines(mode, 100); | |
96 | max = vblank_start - 1; | |
97 | ||
98 | if (min <= 0 || max <= 0) | |
99 | return false; | |
100 | ||
1e3feefd | 101 | if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) |
8d7849db VS |
102 | return false; |
103 | ||
104 | local_irq_disable(); | |
105 | ||
25ef284a VS |
106 | trace_i915_pipe_update_start(crtc, min, max); |
107 | ||
8d7849db VS |
108 | for (;;) { |
109 | /* | |
110 | * prepare_to_wait() has a memory barrier, which guarantees | |
111 | * other CPUs can see the task state update by the time we | |
112 | * read the scanline. | |
113 | */ | |
210871b6 | 114 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
8d7849db VS |
115 | |
116 | scanline = intel_get_crtc_scanline(crtc); | |
117 | if (scanline < min || scanline > max) | |
118 | break; | |
119 | ||
120 | if (timeout <= 0) { | |
121 | DRM_ERROR("Potential atomic update failure on pipe %c\n", | |
122 | pipe_name(crtc->pipe)); | |
123 | break; | |
124 | } | |
125 | ||
126 | local_irq_enable(); | |
127 | ||
128 | timeout = schedule_timeout(timeout); | |
129 | ||
130 | local_irq_disable(); | |
131 | } | |
132 | ||
210871b6 | 133 | finish_wait(wq, &wait); |
8d7849db | 134 | |
1e3feefd | 135 | drm_crtc_vblank_put(&crtc->base); |
8d7849db VS |
136 | |
137 | *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe); | |
138 | ||
25ef284a VS |
139 | trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count); |
140 | ||
8d7849db VS |
141 | return true; |
142 | } | |
143 | ||
26ff2762 ACO |
144 | /** |
145 | * intel_pipe_update_end() - end update of a set of display registers | |
146 | * @crtc: the crtc of which the registers were updated | |
147 | * @start_vbl_count: start vblank counter (used for error checking) | |
148 | * | |
149 | * Mark the end of an update started with intel_pipe_update_start(). This | |
150 | * re-enables interrupts and verifies the update was actually completed | |
151 | * before a vblank using the value of @start_vbl_count. | |
152 | */ | |
9362c7c5 | 153 | void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) |
8d7849db VS |
154 | { |
155 | struct drm_device *dev = crtc->base.dev; | |
156 | enum pipe pipe = crtc->pipe; | |
157 | u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); | |
158 | ||
25ef284a VS |
159 | trace_i915_pipe_update_end(crtc, end_vbl_count); |
160 | ||
8d7849db VS |
161 | local_irq_enable(); |
162 | ||
163 | if (start_vbl_count != end_vbl_count) | |
164 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n", | |
165 | pipe_name(pipe), start_vbl_count, end_vbl_count); | |
166 | } | |
167 | ||
5b633d6b VS |
168 | static void intel_update_primary_plane(struct intel_crtc *crtc) |
169 | { | |
170 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
171 | int reg = DSPCNTR(crtc->plane); | |
172 | ||
173 | if (crtc->primary_enabled) | |
174 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); | |
175 | else | |
176 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); | |
177 | } | |
178 | ||
dc2a41b4 DL |
179 | static void |
180 | skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, | |
181 | struct drm_framebuffer *fb, | |
bdd7554d | 182 | int crtc_x, int crtc_y, |
dc2a41b4 DL |
183 | unsigned int crtc_w, unsigned int crtc_h, |
184 | uint32_t x, uint32_t y, | |
185 | uint32_t src_w, uint32_t src_h) | |
186 | { | |
187 | struct drm_device *dev = drm_plane->dev; | |
188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
189 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); | |
bdd7554d | 190 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
dc2a41b4 DL |
191 | const int pipe = intel_plane->pipe; |
192 | const int plane = intel_plane->plane + 1; | |
b321803d | 193 | u32 plane_ctl, stride_div; |
dc2a41b4 | 194 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
47ecbb20 | 195 | const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey; |
121920fa | 196 | unsigned long surf_addr; |
dc2a41b4 | 197 | |
48fe4691 VS |
198 | plane_ctl = PLANE_CTL_ENABLE | |
199 | PLANE_CTL_PIPE_CSC_ENABLE; | |
dc2a41b4 DL |
200 | |
201 | switch (fb->pixel_format) { | |
202 | case DRM_FORMAT_RGB565: | |
203 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
204 | break; | |
205 | case DRM_FORMAT_XBGR8888: | |
206 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; | |
207 | break; | |
208 | case DRM_FORMAT_XRGB8888: | |
209 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
210 | break; | |
211 | /* | |
212 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
213 | * to be already pre-multiplied. We need to add a knob (or a different | |
214 | * DRM_FORMAT) for user-space to configure that. | |
215 | */ | |
216 | case DRM_FORMAT_ABGR8888: | |
217 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | | |
218 | PLANE_CTL_ORDER_RGBX | | |
219 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
220 | break; | |
221 | case DRM_FORMAT_ARGB8888: | |
222 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | | |
223 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
224 | break; | |
225 | case DRM_FORMAT_YUYV: | |
226 | plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; | |
227 | break; | |
228 | case DRM_FORMAT_YVYU: | |
229 | plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; | |
230 | break; | |
231 | case DRM_FORMAT_UYVY: | |
232 | plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; | |
233 | break; | |
234 | case DRM_FORMAT_VYUY: | |
235 | plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; | |
236 | break; | |
237 | default: | |
238 | BUG(); | |
239 | } | |
240 | ||
66ebf567 TU |
241 | switch (fb->modifier[0]) { |
242 | case DRM_FORMAT_MOD_NONE: | |
dc2a41b4 | 243 | break; |
66ebf567 | 244 | case I915_FORMAT_MOD_X_TILED: |
dc2a41b4 | 245 | plane_ctl |= PLANE_CTL_TILED_X; |
b321803d DL |
246 | break; |
247 | case I915_FORMAT_MOD_Y_TILED: | |
248 | plane_ctl |= PLANE_CTL_TILED_Y; | |
249 | break; | |
250 | case I915_FORMAT_MOD_Yf_TILED: | |
251 | plane_ctl |= PLANE_CTL_TILED_YF; | |
dc2a41b4 DL |
252 | break; |
253 | default: | |
b321803d | 254 | MISSING_CASE(fb->modifier[0]); |
dc2a41b4 | 255 | } |
b321803d | 256 | |
8e7d688b | 257 | if (drm_plane->state->rotation == BIT(DRM_ROTATE_180)) |
1447dde0 | 258 | plane_ctl |= PLANE_CTL_ROTATE_180; |
dc2a41b4 | 259 | |
dc2a41b4 DL |
260 | intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, |
261 | pixel_size, true, | |
262 | src_w != crtc_w || src_h != crtc_h); | |
263 | ||
b321803d DL |
264 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
265 | fb->pixel_format); | |
266 | ||
dc2a41b4 DL |
267 | /* Sizes are 0 based */ |
268 | src_w--; | |
269 | src_h--; | |
270 | crtc_w--; | |
271 | crtc_h--; | |
272 | ||
47ecbb20 VS |
273 | if (key->flags) { |
274 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); | |
275 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); | |
276 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); | |
277 | } | |
278 | ||
279 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
280 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
281 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
282 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
283 | ||
121920fa TU |
284 | surf_addr = intel_plane_obj_offset(intel_plane, obj); |
285 | ||
dc2a41b4 | 286 | I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x); |
b321803d | 287 | I915_WRITE(PLANE_STRIDE(pipe, plane), fb->pitches[0] / stride_div); |
dc2a41b4 DL |
288 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); |
289 | I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w); | |
290 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); | |
121920fa | 291 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
dc2a41b4 DL |
292 | POSTING_READ(PLANE_SURF(pipe, plane)); |
293 | } | |
294 | ||
295 | static void | |
296 | skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc) | |
297 | { | |
298 | struct drm_device *dev = drm_plane->dev; | |
299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
300 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); | |
301 | const int pipe = intel_plane->pipe; | |
302 | const int plane = intel_plane->plane + 1; | |
303 | ||
48fe4691 | 304 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
dc2a41b4 DL |
305 | |
306 | /* Activate double buffered register update */ | |
2ddc1dad VS |
307 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
308 | POSTING_READ(PLANE_SURF(pipe, plane)); | |
dc2a41b4 DL |
309 | |
310 | intel_update_sprite_watermarks(drm_plane, crtc, 0, 0, 0, false, false); | |
311 | } | |
312 | ||
6ca2aeb2 VS |
313 | static void |
314 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) | |
315 | { | |
316 | struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; | |
317 | int plane = intel_plane->plane; | |
318 | ||
319 | /* Seems RGB data bypasses the CSC always */ | |
320 | if (!format_is_yuv(format)) | |
321 | return; | |
322 | ||
323 | /* | |
324 | * BT.601 limited range YCbCr -> full range RGB | |
325 | * | |
326 | * |r| | 6537 4769 0| |cr | | |
327 | * |g| = |-3330 4769 -1605| x |y-64| | |
328 | * |b| | 0 4769 8263| |cb | | |
329 | * | |
330 | * Cb and Cr apparently come in as signed already, so no | |
331 | * need for any offset. For Y we need to remove the offset. | |
332 | */ | |
333 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); | |
334 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
335 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
336 | ||
337 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); | |
338 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); | |
339 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); | |
340 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); | |
341 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); | |
342 | ||
343 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); | |
344 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
345 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
346 | ||
347 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
348 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
349 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
350 | } | |
351 | ||
7f1f3851 | 352 | static void |
b39d53f6 VS |
353 | vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, |
354 | struct drm_framebuffer *fb, | |
bdd7554d | 355 | int crtc_x, int crtc_y, |
7f1f3851 JB |
356 | unsigned int crtc_w, unsigned int crtc_h, |
357 | uint32_t x, uint32_t y, | |
358 | uint32_t src_w, uint32_t src_h) | |
359 | { | |
360 | struct drm_device *dev = dplane->dev; | |
361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
362 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
8d7849db | 363 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bdd7554d | 364 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7f1f3851 JB |
365 | int pipe = intel_plane->pipe; |
366 | int plane = intel_plane->plane; | |
367 | u32 sprctl; | |
368 | unsigned long sprsurf_offset, linear_offset; | |
369 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
47ecbb20 | 370 | const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey; |
7f1f3851 | 371 | |
48fe4691 | 372 | sprctl = SP_ENABLE; |
7f1f3851 JB |
373 | |
374 | switch (fb->pixel_format) { | |
375 | case DRM_FORMAT_YUYV: | |
376 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; | |
377 | break; | |
378 | case DRM_FORMAT_YVYU: | |
379 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; | |
380 | break; | |
381 | case DRM_FORMAT_UYVY: | |
382 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; | |
383 | break; | |
384 | case DRM_FORMAT_VYUY: | |
385 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; | |
386 | break; | |
387 | case DRM_FORMAT_RGB565: | |
388 | sprctl |= SP_FORMAT_BGR565; | |
389 | break; | |
390 | case DRM_FORMAT_XRGB8888: | |
391 | sprctl |= SP_FORMAT_BGRX8888; | |
392 | break; | |
393 | case DRM_FORMAT_ARGB8888: | |
394 | sprctl |= SP_FORMAT_BGRA8888; | |
395 | break; | |
396 | case DRM_FORMAT_XBGR2101010: | |
397 | sprctl |= SP_FORMAT_RGBX1010102; | |
398 | break; | |
399 | case DRM_FORMAT_ABGR2101010: | |
400 | sprctl |= SP_FORMAT_RGBA1010102; | |
401 | break; | |
402 | case DRM_FORMAT_XBGR8888: | |
403 | sprctl |= SP_FORMAT_RGBX8888; | |
404 | break; | |
405 | case DRM_FORMAT_ABGR8888: | |
406 | sprctl |= SP_FORMAT_RGBA8888; | |
407 | break; | |
408 | default: | |
409 | /* | |
410 | * If we get here one of the upper layers failed to filter | |
411 | * out the unsupported plane formats | |
412 | */ | |
413 | BUG(); | |
414 | break; | |
415 | } | |
416 | ||
4ea67bc7 VS |
417 | /* |
418 | * Enable gamma to match primary/cursor plane behaviour. | |
419 | * FIXME should be user controllable via propertiesa. | |
420 | */ | |
421 | sprctl |= SP_GAMMA_ENABLE; | |
422 | ||
7f1f3851 JB |
423 | if (obj->tiling_mode != I915_TILING_NONE) |
424 | sprctl |= SP_TILED; | |
425 | ||
ed57cb8a DL |
426 | intel_update_sprite_watermarks(dplane, crtc, src_w, src_h, |
427 | pixel_size, true, | |
67ca28f3 VS |
428 | src_w != crtc_w || src_h != crtc_h); |
429 | ||
7f1f3851 JB |
430 | /* Sizes are 0 based */ |
431 | src_w--; | |
432 | src_h--; | |
433 | crtc_w--; | |
434 | crtc_h--; | |
435 | ||
7f1f3851 JB |
436 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
437 | sprsurf_offset = intel_gen4_compute_page_offset(&x, &y, | |
438 | obj->tiling_mode, | |
439 | pixel_size, | |
440 | fb->pitches[0]); | |
441 | linear_offset -= sprsurf_offset; | |
442 | ||
8e7d688b | 443 | if (dplane->state->rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
444 | sprctl |= SP_ROTATE_180; |
445 | ||
446 | x += src_w; | |
447 | y += src_h; | |
448 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; | |
449 | } | |
450 | ||
5b633d6b VS |
451 | intel_update_primary_plane(intel_crtc); |
452 | ||
47ecbb20 VS |
453 | if (key->flags) { |
454 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); | |
455 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); | |
456 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); | |
457 | } | |
458 | ||
459 | if (key->flags & I915_SET_COLORKEY_SOURCE) | |
460 | sprctl |= SP_SOURCE_KEY; | |
461 | ||
6ca2aeb2 VS |
462 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
463 | chv_update_csc(intel_plane, fb->pixel_format); | |
464 | ||
ca6ad025 VS |
465 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
466 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); | |
467 | ||
7f1f3851 JB |
468 | if (obj->tiling_mode != I915_TILING_NONE) |
469 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); | |
470 | else | |
471 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); | |
472 | ||
c14b0485 VS |
473 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
474 | ||
7f1f3851 JB |
475 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
476 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
85ba7b7d DV |
477 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
478 | sprsurf_offset); | |
5b633d6b VS |
479 | |
480 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
7f1f3851 JB |
481 | } |
482 | ||
483 | static void | |
b39d53f6 | 484 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
7f1f3851 JB |
485 | { |
486 | struct drm_device *dev = dplane->dev; | |
487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
488 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
8d7849db | 489 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7f1f3851 JB |
490 | int pipe = intel_plane->pipe; |
491 | int plane = intel_plane->plane; | |
492 | ||
5b633d6b VS |
493 | intel_update_primary_plane(intel_crtc); |
494 | ||
48fe4691 VS |
495 | I915_WRITE(SPCNTR(pipe, plane), 0); |
496 | ||
7f1f3851 | 497 | /* Activate double buffered register update */ |
85ba7b7d | 498 | I915_WRITE(SPSURF(pipe, plane), 0); |
5b633d6b VS |
499 | |
500 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
a95fd8ca | 501 | |
ed57cb8a | 502 | intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); |
7f1f3851 JB |
503 | } |
504 | ||
7f1f3851 | 505 | |
b840d907 | 506 | static void |
b39d53f6 VS |
507 | ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
508 | struct drm_framebuffer *fb, | |
bdd7554d | 509 | int crtc_x, int crtc_y, |
b840d907 JB |
510 | unsigned int crtc_w, unsigned int crtc_h, |
511 | uint32_t x, uint32_t y, | |
512 | uint32_t src_w, uint32_t src_h) | |
513 | { | |
514 | struct drm_device *dev = plane->dev; | |
515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
516 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
8d7849db | 517 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bdd7554d | 518 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
47ecbb20 | 519 | enum pipe pipe = intel_plane->pipe; |
b840d907 | 520 | u32 sprctl, sprscale = 0; |
5a35e99e | 521 | unsigned long sprsurf_offset, linear_offset; |
2bd3c3cb | 522 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
47ecbb20 | 523 | const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey; |
b840d907 | 524 | |
48fe4691 | 525 | sprctl = SPRITE_ENABLE; |
b840d907 JB |
526 | |
527 | switch (fb->pixel_format) { | |
528 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 529 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
530 | break; |
531 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 532 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
533 | break; |
534 | case DRM_FORMAT_YUYV: | |
535 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
536 | break; |
537 | case DRM_FORMAT_YVYU: | |
538 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
539 | break; |
540 | case DRM_FORMAT_UYVY: | |
541 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
542 | break; |
543 | case DRM_FORMAT_VYUY: | |
544 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
545 | break; |
546 | default: | |
28d491df | 547 | BUG(); |
b840d907 JB |
548 | } |
549 | ||
4ea67bc7 VS |
550 | /* |
551 | * Enable gamma to match primary/cursor plane behaviour. | |
552 | * FIXME should be user controllable via propertiesa. | |
553 | */ | |
554 | sprctl |= SPRITE_GAMMA_ENABLE; | |
555 | ||
b840d907 JB |
556 | if (obj->tiling_mode != I915_TILING_NONE) |
557 | sprctl |= SPRITE_TILED; | |
558 | ||
b42c6009 | 559 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
560 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
561 | else | |
562 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
563 | ||
6bbfa1c5 | 564 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
86d3efce VS |
565 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
566 | ||
ed57cb8a DL |
567 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size, |
568 | true, | |
67ca28f3 VS |
569 | src_w != crtc_w || src_h != crtc_h); |
570 | ||
b840d907 JB |
571 | /* Sizes are 0 based */ |
572 | src_w--; | |
573 | src_h--; | |
574 | crtc_w--; | |
575 | crtc_h--; | |
576 | ||
8553c18e | 577 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 | 578 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
b840d907 | 579 | |
ca320ac4 | 580 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 581 | sprsurf_offset = |
bc752862 CW |
582 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
583 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
584 | linear_offset -= sprsurf_offset; |
585 | ||
8e7d688b | 586 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
587 | sprctl |= SPRITE_ROTATE_180; |
588 | ||
589 | /* HSW and BDW does this automagically in hardware */ | |
590 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
591 | x += src_w; | |
592 | y += src_h; | |
593 | linear_offset += src_h * fb->pitches[0] + | |
594 | src_w * pixel_size; | |
595 | } | |
596 | } | |
597 | ||
5b633d6b VS |
598 | intel_update_primary_plane(intel_crtc); |
599 | ||
47ecbb20 VS |
600 | if (key->flags) { |
601 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); | |
602 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); | |
603 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); | |
604 | } | |
605 | ||
606 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
607 | sprctl |= SPRITE_DEST_KEY; | |
608 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
609 | sprctl |= SPRITE_SOURCE_KEY; | |
610 | ||
ca6ad025 VS |
611 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
612 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
613 | ||
5a35e99e DL |
614 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
615 | * register */ | |
b3dc685e | 616 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
c54173a8 | 617 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 618 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 619 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
620 | else |
621 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 622 | |
b840d907 | 623 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
624 | if (intel_plane->can_scale) |
625 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 626 | I915_WRITE(SPRCTL(pipe), sprctl); |
85ba7b7d DV |
627 | I915_WRITE(SPRSURF(pipe), |
628 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); | |
5b633d6b VS |
629 | |
630 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
b840d907 JB |
631 | } |
632 | ||
633 | static void | |
b39d53f6 | 634 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
635 | { |
636 | struct drm_device *dev = plane->dev; | |
637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
638 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
8d7849db | 639 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b840d907 JB |
640 | int pipe = intel_plane->pipe; |
641 | ||
5b633d6b VS |
642 | intel_update_primary_plane(intel_crtc); |
643 | ||
b840d907 JB |
644 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); |
645 | /* Can't leave the scaler enabled... */ | |
2d354c34 DL |
646 | if (intel_plane->can_scale) |
647 | I915_WRITE(SPRSCALE(pipe), 0); | |
b840d907 | 648 | /* Activate double buffered register update */ |
85ba7b7d | 649 | I915_WRITE(SPRSURF(pipe), 0); |
5b633d6b VS |
650 | |
651 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
b840d907 JB |
652 | } |
653 | ||
654 | static void | |
b39d53f6 VS |
655 | ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, |
656 | struct drm_framebuffer *fb, | |
bdd7554d | 657 | int crtc_x, int crtc_y, |
b840d907 JB |
658 | unsigned int crtc_w, unsigned int crtc_h, |
659 | uint32_t x, uint32_t y, | |
660 | uint32_t src_w, uint32_t src_h) | |
661 | { | |
662 | struct drm_device *dev = plane->dev; | |
663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
664 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
8d7849db | 665 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bdd7554d | 666 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2bd3c3cb | 667 | int pipe = intel_plane->pipe; |
5a35e99e | 668 | unsigned long dvssurf_offset, linear_offset; |
8aaa81a1 | 669 | u32 dvscntr, dvsscale; |
2bd3c3cb | 670 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
47ecbb20 | 671 | const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey; |
b840d907 | 672 | |
48fe4691 | 673 | dvscntr = DVS_ENABLE; |
b840d907 JB |
674 | |
675 | switch (fb->pixel_format) { | |
676 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 677 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
678 | break; |
679 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 680 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
681 | break; |
682 | case DRM_FORMAT_YUYV: | |
683 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
684 | break; |
685 | case DRM_FORMAT_YVYU: | |
686 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
687 | break; |
688 | case DRM_FORMAT_UYVY: | |
689 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
690 | break; |
691 | case DRM_FORMAT_VYUY: | |
692 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
693 | break; |
694 | default: | |
28d491df | 695 | BUG(); |
b840d907 JB |
696 | } |
697 | ||
4ea67bc7 VS |
698 | /* |
699 | * Enable gamma to match primary/cursor plane behaviour. | |
700 | * FIXME should be user controllable via propertiesa. | |
701 | */ | |
702 | dvscntr |= DVS_GAMMA_ENABLE; | |
703 | ||
b840d907 JB |
704 | if (obj->tiling_mode != I915_TILING_NONE) |
705 | dvscntr |= DVS_TILED; | |
706 | ||
d1686ae3 CW |
707 | if (IS_GEN6(dev)) |
708 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 | 709 | |
ed57cb8a DL |
710 | intel_update_sprite_watermarks(plane, crtc, src_w, src_h, |
711 | pixel_size, true, | |
67ca28f3 VS |
712 | src_w != crtc_w || src_h != crtc_h); |
713 | ||
b840d907 JB |
714 | /* Sizes are 0 based */ |
715 | src_w--; | |
716 | src_h--; | |
717 | crtc_w--; | |
718 | crtc_h--; | |
719 | ||
8aaa81a1 | 720 | dvsscale = 0; |
8368f014 | 721 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 JB |
722 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
723 | ||
ca320ac4 | 724 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
5a35e99e | 725 | dvssurf_offset = |
bc752862 CW |
726 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
727 | pixel_size, fb->pitches[0]); | |
5a35e99e DL |
728 | linear_offset -= dvssurf_offset; |
729 | ||
8e7d688b | 730 | if (plane->state->rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
731 | dvscntr |= DVS_ROTATE_180; |
732 | ||
733 | x += src_w; | |
734 | y += src_h; | |
735 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; | |
736 | } | |
737 | ||
5b633d6b VS |
738 | intel_update_primary_plane(intel_crtc); |
739 | ||
47ecbb20 VS |
740 | if (key->flags) { |
741 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); | |
742 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); | |
743 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); | |
744 | } | |
745 | ||
746 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
747 | dvscntr |= DVS_DEST_KEY; | |
748 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
749 | dvscntr |= DVS_SOURCE_KEY; | |
750 | ||
ca6ad025 VS |
751 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
752 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
753 | ||
5a35e99e | 754 | if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 755 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
756 | else |
757 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 758 | |
b840d907 JB |
759 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
760 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
761 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
85ba7b7d DV |
762 | I915_WRITE(DVSSURF(pipe), |
763 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); | |
5b633d6b VS |
764 | |
765 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
b840d907 JB |
766 | } |
767 | ||
768 | static void | |
b39d53f6 | 769 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
770 | { |
771 | struct drm_device *dev = plane->dev; | |
772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
773 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
8d7849db | 774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b840d907 JB |
775 | int pipe = intel_plane->pipe; |
776 | ||
5b633d6b VS |
777 | intel_update_primary_plane(intel_crtc); |
778 | ||
48fe4691 | 779 | I915_WRITE(DVSCNTR(pipe), 0); |
b840d907 JB |
780 | /* Disable the scaler */ |
781 | I915_WRITE(DVSSCALE(pipe), 0); | |
48fe4691 | 782 | |
b840d907 | 783 | /* Flush double buffered register updates */ |
85ba7b7d | 784 | I915_WRITE(DVSSURF(pipe), 0); |
5b633d6b VS |
785 | |
786 | intel_flush_primary_plane(dev_priv, intel_crtc->plane); | |
b840d907 JB |
787 | } |
788 | ||
32b7eeec MR |
789 | /** |
790 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
791 | * @crtc: the CRTC whose primary plane was just enabled | |
792 | * | |
793 | * Performs potentially sleeping operations that must be done after the primary | |
794 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
795 | * called due to an explicit primary plane update, or due to an implicit | |
796 | * re-enable that is caused when a sprite plane is updated to no longer | |
797 | * completely hide the primary plane. | |
798 | */ | |
799 | void | |
5b633d6b | 800 | intel_post_enable_primary(struct drm_crtc *crtc) |
175bd420 JB |
801 | { |
802 | struct drm_device *dev = crtc->dev; | |
175bd420 | 803 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
abae50ed | 804 | |
33c3b0d1 VS |
805 | /* |
806 | * BDW signals flip done immediately if the plane | |
807 | * is disabled, even if the plane enable is already | |
808 | * armed to occur at the next vblank :( | |
809 | */ | |
810 | if (IS_BROADWELL(dev)) | |
811 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
812 | ||
20bc8673 VS |
813 | /* |
814 | * FIXME IPS should be fine as long as one plane is | |
815 | * enabled, but in practice it seems to have problems | |
816 | * when going from primary only to sprite only and vice | |
817 | * versa. | |
818 | */ | |
cea165c3 | 819 | hsw_enable_ips(intel_crtc); |
20bc8673 | 820 | |
82284b6b | 821 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 822 | intel_fbc_update(dev); |
82284b6b | 823 | mutex_unlock(&dev->struct_mutex); |
175bd420 JB |
824 | } |
825 | ||
32b7eeec MR |
826 | /** |
827 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
828 | * @crtc: the CRTC whose primary plane is to be disabled | |
829 | * | |
830 | * Performs potentially sleeping operations that must be done before the | |
831 | * primary plane is enabled, such as updating FBC and IPS. Note that this may | |
832 | * be called due to an explicit primary plane update, or due to an implicit | |
833 | * disable that is caused when a sprite plane completely hides the primary | |
834 | * plane. | |
835 | */ | |
836 | void | |
5b633d6b | 837 | intel_pre_disable_primary(struct drm_crtc *crtc) |
175bd420 JB |
838 | { |
839 | struct drm_device *dev = crtc->dev; | |
840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
82284b6b VS |
842 | |
843 | mutex_lock(&dev->struct_mutex); | |
e35fef21 | 844 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 845 | intel_fbc_disable(dev); |
82284b6b | 846 | mutex_unlock(&dev->struct_mutex); |
abae50ed | 847 | |
20bc8673 VS |
848 | /* |
849 | * FIXME IPS should be fine as long as one plane is | |
850 | * enabled, but in practice it seems to have problems | |
851 | * when going from primary only to sprite only and vice | |
852 | * versa. | |
853 | */ | |
854 | hsw_disable_ips(intel_crtc); | |
175bd420 JB |
855 | } |
856 | ||
efb31d15 VS |
857 | static bool colorkey_enabled(struct intel_plane *intel_plane) |
858 | { | |
47ecbb20 | 859 | return intel_plane->ckey.flags != I915_SET_COLORKEY_NONE; |
efb31d15 VS |
860 | } |
861 | ||
b840d907 | 862 | static int |
96d61a7f GP |
863 | intel_check_sprite_plane(struct drm_plane *plane, |
864 | struct intel_plane_state *state) | |
b840d907 | 865 | { |
2b875c22 | 866 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); |
b840d907 | 867 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 868 | struct drm_framebuffer *fb = state->base.fb; |
96d61a7f GP |
869 | int crtc_x, crtc_y; |
870 | unsigned int crtc_w, crtc_h; | |
871 | uint32_t src_x, src_y, src_w, src_h; | |
872 | struct drm_rect *src = &state->src; | |
873 | struct drm_rect *dst = &state->dst; | |
96d61a7f | 874 | const struct drm_rect *clip = &state->clip; |
1731693a VS |
875 | int hscale, vscale; |
876 | int max_scale, min_scale; | |
cf4c7c12 MR |
877 | int pixel_size; |
878 | ||
ea2c67bb MR |
879 | intel_crtc = intel_crtc ? intel_crtc : to_intel_crtc(plane->crtc); |
880 | ||
cf4c7c12 MR |
881 | if (!fb) { |
882 | state->visible = false; | |
32b7eeec | 883 | goto finish; |
cf4c7c12 | 884 | } |
5e1bac2f | 885 | |
1731693a VS |
886 | /* Don't modify another pipe's plane */ |
887 | if (intel_plane->pipe != intel_crtc->pipe) { | |
888 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); | |
b840d907 | 889 | return -EINVAL; |
1731693a | 890 | } |
b840d907 | 891 | |
1731693a VS |
892 | /* FIXME check all gen limits */ |
893 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { | |
894 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); | |
b840d907 | 895 | return -EINVAL; |
1731693a | 896 | } |
b840d907 | 897 | |
3c3686cd VS |
898 | /* |
899 | * FIXME the following code does a bunch of fuzzy adjustments to the | |
900 | * coordinates and sizes. We probably need some way to decide whether | |
901 | * more strict checking should be done instead. | |
902 | */ | |
1731693a VS |
903 | max_scale = intel_plane->max_downscale << 16; |
904 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); | |
905 | ||
96d61a7f | 906 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
8e7d688b | 907 | state->base.rotation); |
76eebda7 | 908 | |
96d61a7f | 909 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 910 | BUG_ON(hscale < 0); |
1731693a | 911 | |
96d61a7f | 912 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 913 | BUG_ON(vscale < 0); |
b840d907 | 914 | |
96d61a7f | 915 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
b840d907 | 916 | |
96d61a7f GP |
917 | crtc_x = dst->x1; |
918 | crtc_y = dst->y1; | |
919 | crtc_w = drm_rect_width(dst); | |
920 | crtc_h = drm_rect_height(dst); | |
2d354c34 | 921 | |
96d61a7f | 922 | if (state->visible) { |
3c3686cd | 923 | /* check again in case clipping clamped the results */ |
96d61a7f | 924 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
925 | if (hscale < 0) { |
926 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); | |
96d61a7f GP |
927 | drm_rect_debug_print(src, true); |
928 | drm_rect_debug_print(dst, false); | |
3c3686cd VS |
929 | |
930 | return hscale; | |
931 | } | |
932 | ||
96d61a7f | 933 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
934 | if (vscale < 0) { |
935 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); | |
96d61a7f GP |
936 | drm_rect_debug_print(src, true); |
937 | drm_rect_debug_print(dst, false); | |
3c3686cd VS |
938 | |
939 | return vscale; | |
940 | } | |
941 | ||
1731693a | 942 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
96d61a7f GP |
943 | drm_rect_adjust_size(src, |
944 | drm_rect_width(dst) * hscale - drm_rect_width(src), | |
945 | drm_rect_height(dst) * vscale - drm_rect_height(src)); | |
1731693a | 946 | |
96d61a7f | 947 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
8e7d688b | 948 | state->base.rotation); |
76eebda7 | 949 | |
1731693a | 950 | /* sanity check to make sure the src viewport wasn't enlarged */ |
ea2c67bb MR |
951 | WARN_ON(src->x1 < (int) state->base.src_x || |
952 | src->y1 < (int) state->base.src_y || | |
953 | src->x2 > (int) state->base.src_x + state->base.src_w || | |
954 | src->y2 > (int) state->base.src_y + state->base.src_h); | |
1731693a VS |
955 | |
956 | /* | |
957 | * Hardware doesn't handle subpixel coordinates. | |
958 | * Adjust to (macro)pixel boundary, but be careful not to | |
959 | * increase the source viewport size, because that could | |
960 | * push the downscaling factor out of bounds. | |
1731693a | 961 | */ |
96d61a7f GP |
962 | src_x = src->x1 >> 16; |
963 | src_w = drm_rect_width(src) >> 16; | |
964 | src_y = src->y1 >> 16; | |
965 | src_h = drm_rect_height(src) >> 16; | |
1731693a VS |
966 | |
967 | if (format_is_yuv(fb->pixel_format)) { | |
968 | src_x &= ~1; | |
969 | src_w &= ~1; | |
970 | ||
971 | /* | |
972 | * Must keep src and dst the | |
973 | * same if we can't scale. | |
974 | */ | |
975 | if (!intel_plane->can_scale) | |
976 | crtc_w &= ~1; | |
977 | ||
978 | if (crtc_w == 0) | |
96d61a7f | 979 | state->visible = false; |
1731693a VS |
980 | } |
981 | } | |
982 | ||
983 | /* Check size restrictions when scaling */ | |
96d61a7f | 984 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
1731693a VS |
985 | unsigned int width_bytes; |
986 | ||
987 | WARN_ON(!intel_plane->can_scale); | |
988 | ||
989 | /* FIXME interlacing min height is 6 */ | |
990 | ||
991 | if (crtc_w < 3 || crtc_h < 3) | |
96d61a7f | 992 | state->visible = false; |
1731693a VS |
993 | |
994 | if (src_w < 3 || src_h < 3) | |
96d61a7f | 995 | state->visible = false; |
1731693a | 996 | |
cf4c7c12 | 997 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
96d61a7f GP |
998 | width_bytes = ((src_x * pixel_size) & 63) + |
999 | src_w * pixel_size; | |
1731693a VS |
1000 | |
1001 | if (src_w > 2048 || src_h > 2048 || | |
1002 | width_bytes > 4096 || fb->pitches[0] > 4096) { | |
1003 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); | |
1004 | return -EINVAL; | |
1005 | } | |
1006 | } | |
1007 | ||
96d61a7f GP |
1008 | if (state->visible) { |
1009 | src->x1 = src_x; | |
1010 | src->x2 = src_x + src_w; | |
1011 | src->y1 = src_y; | |
1012 | src->y2 = src_y + src_h; | |
1013 | } | |
1014 | ||
1015 | dst->x1 = crtc_x; | |
1016 | dst->x2 = crtc_x + crtc_w; | |
1017 | dst->y1 = crtc_y; | |
1018 | dst->y2 = crtc_y + crtc_h; | |
1019 | ||
32b7eeec MR |
1020 | finish: |
1021 | /* | |
1022 | * If the sprite is completely covering the primary plane, | |
1023 | * we can disable the primary and save power. | |
1024 | */ | |
1025 | state->hides_primary = fb != NULL && drm_rect_equals(dst, clip) && | |
1026 | !colorkey_enabled(intel_plane); | |
1027 | WARN_ON(state->hides_primary && !state->visible && intel_crtc->active); | |
1028 | ||
1029 | if (intel_crtc->active) { | |
1030 | if (intel_crtc->primary_enabled == state->hides_primary) | |
1031 | intel_crtc->atomic.wait_for_flips = true; | |
1032 | ||
1033 | if (intel_crtc->primary_enabled && state->hides_primary) | |
1034 | intel_crtc->atomic.pre_disable_primary = true; | |
1035 | ||
1036 | intel_crtc->atomic.fb_bits |= | |
1037 | INTEL_FRONTBUFFER_SPRITE(intel_crtc->pipe); | |
1038 | ||
1039 | if (!intel_crtc->primary_enabled && !state->hides_primary) | |
1040 | intel_crtc->atomic.post_enable_primary = true; | |
0fda6568 | 1041 | |
1fc0a8f7 | 1042 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 1043 | intel_crtc->atomic.update_wm = true; |
08fd59fc MR |
1044 | |
1045 | if (!state->visible) { | |
1046 | /* | |
1047 | * Avoid underruns when disabling the sprite. | |
1048 | * FIXME remove once watermark updates are done properly. | |
1049 | */ | |
1050 | intel_crtc->atomic.wait_vblank = true; | |
1051 | intel_crtc->atomic.update_sprite_watermarks |= | |
1052 | (1 << drm_plane_index(plane)); | |
1053 | } | |
32b7eeec MR |
1054 | } |
1055 | ||
96d61a7f GP |
1056 | return 0; |
1057 | } | |
1058 | ||
34aa50a9 GP |
1059 | static void |
1060 | intel_commit_sprite_plane(struct drm_plane *plane, | |
1061 | struct intel_plane_state *state) | |
1062 | { | |
2b875c22 | 1063 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 1064 | struct intel_crtc *intel_crtc; |
34aa50a9 | 1065 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 1066 | struct drm_framebuffer *fb = state->base.fb; |
34aa50a9 GP |
1067 | int crtc_x, crtc_y; |
1068 | unsigned int crtc_w, crtc_h; | |
1069 | uint32_t src_x, src_y, src_w, src_h; | |
34aa50a9 | 1070 | |
ea2c67bb MR |
1071 | crtc = crtc ? crtc : plane->crtc; |
1072 | intel_crtc = to_intel_crtc(crtc); | |
1073 | ||
bdd7554d | 1074 | plane->fb = fb; |
b840d907 | 1075 | |
03c5b25f | 1076 | if (intel_crtc->active) { |
32b7eeec | 1077 | intel_crtc->primary_enabled = !state->hides_primary; |
03c5b25f | 1078 | |
96d61a7f GP |
1079 | if (state->visible) { |
1080 | crtc_x = state->dst.x1; | |
e259f172 | 1081 | crtc_y = state->dst.y1; |
96d61a7f GP |
1082 | crtc_w = drm_rect_width(&state->dst); |
1083 | crtc_h = drm_rect_height(&state->dst); | |
1084 | src_x = state->src.x1; | |
1085 | src_y = state->src.y1; | |
1086 | src_w = drm_rect_width(&state->src); | |
1087 | src_h = drm_rect_height(&state->src); | |
bdd7554d | 1088 | intel_plane->update_plane(plane, crtc, fb, |
03c5b25f VS |
1089 | crtc_x, crtc_y, crtc_w, crtc_h, |
1090 | src_x, src_y, src_w, src_h); | |
96d61a7f | 1091 | } else { |
03c5b25f | 1092 | intel_plane->disable_plane(plane, crtc); |
96d61a7f | 1093 | } |
03c5b25f | 1094 | } |
b840d907 JB |
1095 | } |
1096 | ||
8ea30864 JB |
1097 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
1098 | struct drm_file *file_priv) | |
1099 | { | |
1100 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 JB |
1101 | struct drm_plane *plane; |
1102 | struct intel_plane *intel_plane; | |
1103 | int ret = 0; | |
1104 | ||
8ea30864 JB |
1105 | /* Make sure we don't try to enable both src & dest simultaneously */ |
1106 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
1107 | return -EINVAL; | |
1108 | ||
47ecbb20 VS |
1109 | if (IS_VALLEYVIEW(dev) && |
1110 | set->flags & I915_SET_COLORKEY_DESTINATION) | |
1111 | return -EINVAL; | |
1112 | ||
a0e99e68 | 1113 | drm_modeset_lock_all(dev); |
8ea30864 | 1114 | |
7707e653 RC |
1115 | plane = drm_plane_find(dev, set->plane_id); |
1116 | if (!plane) { | |
3f2c2057 | 1117 | ret = -ENOENT; |
8ea30864 JB |
1118 | goto out_unlock; |
1119 | } | |
1120 | ||
8ea30864 | 1121 | intel_plane = to_intel_plane(plane); |
47ecbb20 VS |
1122 | intel_plane->ckey = *set; |
1123 | ||
1124 | /* | |
1125 | * The only way this could fail would be due to | |
1126 | * the current plane state being unsupportable already, | |
1127 | * and we dont't consider that an error for the | |
1128 | * colorkey ioctl. So just ignore any error. | |
1129 | */ | |
1130 | intel_plane_restore(plane); | |
8ea30864 JB |
1131 | |
1132 | out_unlock: | |
a0e99e68 | 1133 | drm_modeset_unlock_all(dev); |
8ea30864 JB |
1134 | return ret; |
1135 | } | |
1136 | ||
e57465f3 | 1137 | int intel_plane_restore(struct drm_plane *plane) |
5e1bac2f | 1138 | { |
6e721fb1 | 1139 | if (!plane->crtc || !plane->state->fb) |
e57465f3 | 1140 | return 0; |
5e1bac2f | 1141 | |
6e721fb1 | 1142 | return plane->funcs->update_plane(plane, plane->crtc, plane->state->fb, |
53a366b9 MR |
1143 | plane->state->crtc_x, plane->state->crtc_y, |
1144 | plane->state->crtc_w, plane->state->crtc_h, | |
1145 | plane->state->src_x, plane->state->src_y, | |
1146 | plane->state->src_w, plane->state->src_h); | |
5e1bac2f JB |
1147 | } |
1148 | ||
d1686ae3 CW |
1149 | static uint32_t ilk_plane_formats[] = { |
1150 | DRM_FORMAT_XRGB8888, | |
1151 | DRM_FORMAT_YUYV, | |
1152 | DRM_FORMAT_YVYU, | |
1153 | DRM_FORMAT_UYVY, | |
1154 | DRM_FORMAT_VYUY, | |
1155 | }; | |
1156 | ||
b840d907 JB |
1157 | static uint32_t snb_plane_formats[] = { |
1158 | DRM_FORMAT_XBGR8888, | |
1159 | DRM_FORMAT_XRGB8888, | |
1160 | DRM_FORMAT_YUYV, | |
1161 | DRM_FORMAT_YVYU, | |
1162 | DRM_FORMAT_UYVY, | |
1163 | DRM_FORMAT_VYUY, | |
1164 | }; | |
1165 | ||
7f1f3851 JB |
1166 | static uint32_t vlv_plane_formats[] = { |
1167 | DRM_FORMAT_RGB565, | |
1168 | DRM_FORMAT_ABGR8888, | |
1169 | DRM_FORMAT_ARGB8888, | |
1170 | DRM_FORMAT_XBGR8888, | |
1171 | DRM_FORMAT_XRGB8888, | |
1172 | DRM_FORMAT_XBGR2101010, | |
1173 | DRM_FORMAT_ABGR2101010, | |
1174 | DRM_FORMAT_YUYV, | |
1175 | DRM_FORMAT_YVYU, | |
1176 | DRM_FORMAT_UYVY, | |
1177 | DRM_FORMAT_VYUY, | |
1178 | }; | |
1179 | ||
dc2a41b4 DL |
1180 | static uint32_t skl_plane_formats[] = { |
1181 | DRM_FORMAT_RGB565, | |
1182 | DRM_FORMAT_ABGR8888, | |
1183 | DRM_FORMAT_ARGB8888, | |
1184 | DRM_FORMAT_XBGR8888, | |
1185 | DRM_FORMAT_XRGB8888, | |
1186 | DRM_FORMAT_YUYV, | |
1187 | DRM_FORMAT_YVYU, | |
1188 | DRM_FORMAT_UYVY, | |
1189 | DRM_FORMAT_VYUY, | |
1190 | }; | |
1191 | ||
b840d907 | 1192 | int |
7f1f3851 | 1193 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
b840d907 JB |
1194 | { |
1195 | struct intel_plane *intel_plane; | |
8e7d688b | 1196 | struct intel_plane_state *state; |
b840d907 | 1197 | unsigned long possible_crtcs; |
d1686ae3 CW |
1198 | const uint32_t *plane_formats; |
1199 | int num_plane_formats; | |
b840d907 JB |
1200 | int ret; |
1201 | ||
d1686ae3 | 1202 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 1203 | return -ENODEV; |
b840d907 | 1204 | |
b14c5679 | 1205 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
b840d907 JB |
1206 | if (!intel_plane) |
1207 | return -ENOMEM; | |
1208 | ||
8e7d688b MR |
1209 | state = intel_create_plane_state(&intel_plane->base); |
1210 | if (!state) { | |
ea2c67bb MR |
1211 | kfree(intel_plane); |
1212 | return -ENOMEM; | |
1213 | } | |
8e7d688b | 1214 | intel_plane->base.state = &state->base; |
ea2c67bb | 1215 | |
d1686ae3 CW |
1216 | switch (INTEL_INFO(dev)->gen) { |
1217 | case 5: | |
1218 | case 6: | |
2d354c34 | 1219 | intel_plane->can_scale = true; |
b840d907 | 1220 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
1221 | intel_plane->update_plane = ilk_update_plane; |
1222 | intel_plane->disable_plane = ilk_disable_plane; | |
d1686ae3 CW |
1223 | |
1224 | if (IS_GEN6(dev)) { | |
1225 | plane_formats = snb_plane_formats; | |
1226 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1227 | } else { | |
1228 | plane_formats = ilk_plane_formats; | |
1229 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
1230 | } | |
1231 | break; | |
1232 | ||
1233 | case 7: | |
4e0bbc31 | 1234 | case 8: |
d49f7091 | 1235 | if (IS_IVYBRIDGE(dev)) { |
2d354c34 | 1236 | intel_plane->can_scale = true; |
d49f7091 DL |
1237 | intel_plane->max_downscale = 2; |
1238 | } else { | |
1239 | intel_plane->can_scale = false; | |
1240 | intel_plane->max_downscale = 1; | |
1241 | } | |
7f1f3851 JB |
1242 | |
1243 | if (IS_VALLEYVIEW(dev)) { | |
7f1f3851 JB |
1244 | intel_plane->update_plane = vlv_update_plane; |
1245 | intel_plane->disable_plane = vlv_disable_plane; | |
7f1f3851 JB |
1246 | |
1247 | plane_formats = vlv_plane_formats; | |
1248 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); | |
1249 | } else { | |
7f1f3851 JB |
1250 | intel_plane->update_plane = ivb_update_plane; |
1251 | intel_plane->disable_plane = ivb_disable_plane; | |
7f1f3851 JB |
1252 | |
1253 | plane_formats = snb_plane_formats; | |
1254 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1255 | } | |
d1686ae3 | 1256 | break; |
dc2a41b4 DL |
1257 | case 9: |
1258 | /* | |
1259 | * FIXME: Skylake planes can be scaled (with some restrictions), | |
1260 | * but this is for another time. | |
1261 | */ | |
1262 | intel_plane->can_scale = false; | |
1263 | intel_plane->max_downscale = 1; | |
1264 | intel_plane->update_plane = skl_update_plane; | |
1265 | intel_plane->disable_plane = skl_disable_plane; | |
dc2a41b4 DL |
1266 | |
1267 | plane_formats = skl_plane_formats; | |
1268 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); | |
1269 | break; | |
d1686ae3 | 1270 | default: |
a8b0bbab | 1271 | kfree(intel_plane); |
d1686ae3 | 1272 | return -ENODEV; |
b840d907 JB |
1273 | } |
1274 | ||
1275 | intel_plane->pipe = pipe; | |
7f1f3851 | 1276 | intel_plane->plane = plane; |
c59cb179 MR |
1277 | intel_plane->check_plane = intel_check_sprite_plane; |
1278 | intel_plane->commit_plane = intel_commit_sprite_plane; | |
b840d907 | 1279 | possible_crtcs = (1 << pipe); |
8fe8a3fe | 1280 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, |
65a3fea0 | 1281 | &intel_plane_funcs, |
8fe8a3fe DF |
1282 | plane_formats, num_plane_formats, |
1283 | DRM_PLANE_TYPE_OVERLAY); | |
7ed6eeee | 1284 | if (ret) { |
b840d907 | 1285 | kfree(intel_plane); |
7ed6eeee VS |
1286 | goto out; |
1287 | } | |
1288 | ||
1289 | if (!dev->mode_config.rotation_property) | |
1290 | dev->mode_config.rotation_property = | |
1291 | drm_mode_create_rotation_property(dev, | |
1292 | BIT(DRM_ROTATE_0) | | |
1293 | BIT(DRM_ROTATE_180)); | |
1294 | ||
1295 | if (dev->mode_config.rotation_property) | |
1296 | drm_object_attach_property(&intel_plane->base.base, | |
1297 | dev->mode_config.rotation_property, | |
8e7d688b | 1298 | state->base.rotation); |
b840d907 | 1299 | |
ea2c67bb MR |
1300 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
1301 | ||
7ed6eeee | 1302 | out: |
b840d907 JB |
1303 | return ret; |
1304 | } |