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drm/gma500: Return -ENOENT when a mode object can't be found
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sprite.c
CommitLineData
b840d907
JB		 1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_fourcc.h>
1731693a 35#include <drm/drm_rect.h>
b840d907 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
b840d907
JB		 38#include "i915_drv.h"
39
7f1f3851 40static void
b39d53f6
VS		 41vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
42 struct drm_framebuffer *fb,
7f1f3851
JB		 43 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
44 unsigned int crtc_w, unsigned int crtc_h,
45 uint32_t x, uint32_t y,
46 uint32_t src_w, uint32_t src_h)
47{
48 struct drm_device *dev = dplane->dev;
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 struct intel_plane *intel_plane = to_intel_plane(dplane);
51 int pipe = intel_plane->pipe;
52 int plane = intel_plane->plane;
53 u32 sprctl;
54 unsigned long sprsurf_offset, linear_offset;
55 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
56
57 sprctl = I915_READ(SPCNTR(pipe, plane));
58
59 /* Mask out pixel format bits in case we change it */
60 sprctl &= ~SP_PIXFORMAT_MASK;
61 sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
62 sprctl &= ~SP_TILED;
63
64 switch (fb->pixel_format) {
65 case DRM_FORMAT_YUYV:
66 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
67 break;
68 case DRM_FORMAT_YVYU:
69 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
70 break;
71 case DRM_FORMAT_UYVY:
72 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
73 break;
74 case DRM_FORMAT_VYUY:
75 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
76 break;
77 case DRM_FORMAT_RGB565:
78 sprctl |= SP_FORMAT_BGR565;
79 break;
80 case DRM_FORMAT_XRGB8888:
81 sprctl |= SP_FORMAT_BGRX8888;
82 break;
83 case DRM_FORMAT_ARGB8888:
84 sprctl |= SP_FORMAT_BGRA8888;
85 break;
86 case DRM_FORMAT_XBGR2101010:
87 sprctl |= SP_FORMAT_RGBX1010102;
88 break;
89 case DRM_FORMAT_ABGR2101010:
90 sprctl |= SP_FORMAT_RGBA1010102;
91 break;
92 case DRM_FORMAT_XBGR8888:
93 sprctl |= SP_FORMAT_RGBX8888;
94 break;
95 case DRM_FORMAT_ABGR8888:
96 sprctl |= SP_FORMAT_RGBA8888;
97 break;
98 default:
99 /*
100 * If we get here one of the upper layers failed to filter
101 * out the unsupported plane formats
102 */
103 BUG();
104 break;
105 }
106
107 if (obj->tiling_mode != I915_TILING_NONE)
108 sprctl |= SP_TILED;
109
110 sprctl |= SP_ENABLE;
111
adf3d35e 112 intel_update_sprite_watermarks(dplane, crtc, src_w, pixel_size, true,
67ca28f3
VS		 113 src_w != crtc_w || src_h != crtc_h);
114
7f1f3851
JB		 115 /* Sizes are 0 based */
116 src_w--;
117 src_h--;
118 crtc_w--;
119 crtc_h--;
120
7f1f3851
JB		 121 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
122 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
123
124 linear_offset = y * fb->pitches[0] + x * pixel_size;
125 sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
126 obj->tiling_mode,
127 pixel_size,
128 fb->pitches[0]);
129 linear_offset -= sprsurf_offset;
130
131 if (obj->tiling_mode != I915_TILING_NONE)
132 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
133 else
134 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
135
136 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
137 I915_WRITE(SPCNTR(pipe, plane), sprctl);
f343c5f6 138 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
7f1f3851
JB		 139 sprsurf_offset);
140 POSTING_READ(SPSURF(pipe, plane));
141}
142
143static void
b39d53f6 144vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
7f1f3851
JB		 145{
146 struct drm_device *dev = dplane->dev;
147 struct drm_i915_private *dev_priv = dev->dev_private;
148 struct intel_plane *intel_plane = to_intel_plane(dplane);
149 int pipe = intel_plane->pipe;
150 int plane = intel_plane->plane;
151
152 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
153 ~SP_ENABLE);
154 /* Activate double buffered register update */
155 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
156 POSTING_READ(SPSURF(pipe, plane));
a95fd8ca
VS		 157
158 intel_update_sprite_watermarks(dplane, crtc, 0, 0, false, false);
7f1f3851
JB		 159}
160
161static int
162vlv_update_colorkey(struct drm_plane *dplane,
163 struct drm_intel_sprite_colorkey *key)
164{
165 struct drm_device *dev = dplane->dev;
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct intel_plane *intel_plane = to_intel_plane(dplane);
168 int pipe = intel_plane->pipe;
169 int plane = intel_plane->plane;
170 u32 sprctl;
171
172 if (key->flags & I915_SET_COLORKEY_DESTINATION)
173 return -EINVAL;
174
175 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
176 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
177 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
178
179 sprctl = I915_READ(SPCNTR(pipe, plane));
180 sprctl &= ~SP_SOURCE_KEY;
181 if (key->flags & I915_SET_COLORKEY_SOURCE)
182 sprctl |= SP_SOURCE_KEY;
183 I915_WRITE(SPCNTR(pipe, plane), sprctl);
184
185 POSTING_READ(SPKEYMSK(pipe, plane));
186
187 return 0;
188}
189
190static void
191vlv_get_colorkey(struct drm_plane *dplane,
192 struct drm_intel_sprite_colorkey *key)
193{
194 struct drm_device *dev = dplane->dev;
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 struct intel_plane *intel_plane = to_intel_plane(dplane);
197 int pipe = intel_plane->pipe;
198 int plane = intel_plane->plane;
199 u32 sprctl;
200
201 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
202 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
203 key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
204
205 sprctl = I915_READ(SPCNTR(pipe, plane));
206 if (sprctl & SP_SOURCE_KEY)
207 key->flags = I915_SET_COLORKEY_SOURCE;
208 else
209 key->flags = I915_SET_COLORKEY_NONE;
210}
211
b840d907 212static void
b39d53f6
VS		 213ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
214 struct drm_framebuffer *fb,
b840d907
JB		 215 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
216 unsigned int crtc_w, unsigned int crtc_h,
217 uint32_t x, uint32_t y,
218 uint32_t src_w, uint32_t src_h)
219{
220 struct drm_device *dev = plane->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
222 struct intel_plane *intel_plane = to_intel_plane(plane);
223 int pipe = intel_plane->pipe;
224 u32 sprctl, sprscale = 0;
5a35e99e 225 unsigned long sprsurf_offset, linear_offset;
2bd3c3cb 226 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2c6602df 227 bool scaling_was_enabled = dev_priv->sprite_scaling_enabled;
b840d907
JB		 228
229 sprctl = I915_READ(SPRCTL(pipe));
230
231 /* Mask out pixel format bits in case we change it */
232 sprctl &= ~SPRITE_PIXFORMAT_MASK;
233 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
234 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
e86fe0d3 235 sprctl &= ~SPRITE_TILED;
b840d907
JB		 236
237 switch (fb->pixel_format) {
238 case DRM_FORMAT_XBGR8888:
5ee36913 239 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
b840d907
JB		 240 break;
241 case DRM_FORMAT_XRGB8888:
5ee36913 242 sprctl |= SPRITE_FORMAT_RGBX888;
b840d907
JB		 243 break;
244 case DRM_FORMAT_YUYV:
245 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
b840d907
JB		 246 break;
247 case DRM_FORMAT_YVYU:
248 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
b840d907
JB		 249 break;
250 case DRM_FORMAT_UYVY:
251 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
b840d907
JB		 252 break;
253 case DRM_FORMAT_VYUY:
254 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
b840d907
JB		 255 break;
256 default:
28d491df 257 BUG();
b840d907
JB		 258 }
259
260 if (obj->tiling_mode != I915_TILING_NONE)
261 sprctl |= SPRITE_TILED;
262
1f5d76db
PZ		 263 if (IS_HASWELL(dev))
264 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
265 else
266 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
267
b840d907
JB		 268 sprctl |= SPRITE_ENABLE;
269
86d3efce
VS		 270 if (IS_HASWELL(dev))
271 sprctl |= SPRITE_PIPE_CSC_ENABLE;
272
adf3d35e 273 intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true,
67ca28f3
VS		 274 src_w != crtc_w || src_h != crtc_h);
275
b840d907
JB		 276 /* Sizes are 0 based */
277 src_w--;
278 src_h--;
279 crtc_w--;
280 crtc_h--;
281
b840d907
JB		 282 /*
283 * IVB workaround: must disable low power watermarks for at least
284 * one frame before enabling scaling. LP watermarks can be re-enabled
285 * when scaling is disabled.
286 */
287 if (crtc_w != src_w || crtc_h != src_h) {
2c6602df
VS		 288 dev_priv->sprite_scaling_enabled |= 1 << pipe;
289
290 if (!scaling_was_enabled) {
46ba614c 291 intel_update_watermarks(crtc);
828ed3e1
CW		 292 intel_wait_for_vblank(dev, pipe);
293 }
b840d907 294 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
2c6602df
VS		 295 } else
296 dev_priv->sprite_scaling_enabled &= ~(1 << pipe);
b840d907
JB		 297
298 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
299 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
c54173a8 300
ca320ac4 301 linear_offset = y * fb->pitches[0] + x * pixel_size;
5a35e99e 302 sprsurf_offset =
bc752862
CW		 303 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
304 pixel_size, fb->pitches[0]);
5a35e99e
DL		 305 linear_offset -= sprsurf_offset;
306
307 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
308 * register */
309 if (IS_HASWELL(dev))
c54173a8 310 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
5a35e99e 311 else if (obj->tiling_mode != I915_TILING_NONE)
b840d907 312 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
5a35e99e
DL		 313 else
314 I915_WRITE(SPRLINOFF(pipe), linear_offset);
c54173a8 315
b840d907 316 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
2d354c34
DL		 317 if (intel_plane->can_scale)
318 I915_WRITE(SPRSCALE(pipe), sprscale);
b840d907 319 I915_WRITE(SPRCTL(pipe), sprctl);
f343c5f6
BW		 320 I915_MODIFY_DISPBASE(SPRSURF(pipe),
321 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
b840d907 322 POSTING_READ(SPRSURF(pipe));
2c6602df
VS		 323
324 /* potentially re-enable LP watermarks */
325 if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
46ba614c 326 intel_update_watermarks(crtc);
b840d907
JB		 327}
328
329static void
b39d53f6 330ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
b840d907
JB		 331{
332 struct drm_device *dev = plane->dev;
333 struct drm_i915_private *dev_priv = dev->dev_private;
334 struct intel_plane *intel_plane = to_intel_plane(plane);
335 int pipe = intel_plane->pipe;
2c6602df 336 bool scaling_was_enabled = dev_priv->sprite_scaling_enabled;
b840d907
JB		 337
338 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
339 /* Can't leave the scaler enabled... */
2d354c34
DL		 340 if (intel_plane->can_scale)
341 I915_WRITE(SPRSCALE(pipe), 0);
b840d907 342 /* Activate double buffered register update */
446f2545 343 I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
b840d907 344 POSTING_READ(SPRSURF(pipe));
828ed3e1 345
2c6602df
VS		 346 dev_priv->sprite_scaling_enabled &= ~(1 << pipe);
347
adf3d35e 348 intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false);
4c4ff43a 349
2c6602df
VS		 350 /* potentially re-enable LP watermarks */
351 if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
46ba614c 352 intel_update_watermarks(crtc);
b840d907
JB		 353}
354
8ea30864
JB		 355static int
356ivb_update_colorkey(struct drm_plane *plane,
357 struct drm_intel_sprite_colorkey *key)
358{
359 struct drm_device *dev = plane->dev;
360 struct drm_i915_private *dev_priv = dev->dev_private;
361 struct intel_plane *intel_plane;
362 u32 sprctl;
363 int ret = 0;
364
365 intel_plane = to_intel_plane(plane);
366
367 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
368 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
369 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
370
371 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
372 sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
373 if (key->flags & I915_SET_COLORKEY_DESTINATION)
374 sprctl |= SPRITE_DEST_KEY;
375 else if (key->flags & I915_SET_COLORKEY_SOURCE)
376 sprctl |= SPRITE_SOURCE_KEY;
377 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
378
379 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
380
381 return ret;
382}
383
384static void
385ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
386{
387 struct drm_device *dev = plane->dev;
388 struct drm_i915_private *dev_priv = dev->dev_private;
389 struct intel_plane *intel_plane;
390 u32 sprctl;
391
392 intel_plane = to_intel_plane(plane);
393
394 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
395 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
396 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
397 key->flags = 0;
398
399 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
400
401 if (sprctl & SPRITE_DEST_KEY)
402 key->flags = I915_SET_COLORKEY_DESTINATION;
403 else if (sprctl & SPRITE_SOURCE_KEY)
404 key->flags = I915_SET_COLORKEY_SOURCE;
405 else
406 key->flags = I915_SET_COLORKEY_NONE;
407}
408
b840d907 409static void
b39d53f6
VS		 410ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
411 struct drm_framebuffer *fb,
b840d907
JB		 412 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
413 unsigned int crtc_w, unsigned int crtc_h,
414 uint32_t x, uint32_t y,
415 uint32_t src_w, uint32_t src_h)
416{
417 struct drm_device *dev = plane->dev;
418 struct drm_i915_private *dev_priv = dev->dev_private;
419 struct intel_plane *intel_plane = to_intel_plane(plane);
2bd3c3cb 420 int pipe = intel_plane->pipe;
5a35e99e 421 unsigned long dvssurf_offset, linear_offset;
8aaa81a1 422 u32 dvscntr, dvsscale;
2bd3c3cb 423 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
b840d907
JB		 424
425 dvscntr = I915_READ(DVSCNTR(pipe));
426
427 /* Mask out pixel format bits in case we change it */
428 dvscntr &= ~DVS_PIXFORMAT_MASK;
ab2f9df1 429 dvscntr &= ~DVS_RGB_ORDER_XBGR;
b840d907 430 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
79626523 431 dvscntr &= ~DVS_TILED;
b840d907
JB		 432
433 switch (fb->pixel_format) {
434 case DRM_FORMAT_XBGR8888:
ab2f9df1 435 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
b840d907
JB		 436 break;
437 case DRM_FORMAT_XRGB8888:
ab2f9df1 438 dvscntr |= DVS_FORMAT_RGBX888;
b840d907
JB		 439 break;
440 case DRM_FORMAT_YUYV:
441 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
b840d907
JB		 442 break;
443 case DRM_FORMAT_YVYU:
444 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
b840d907
JB		 445 break;
446 case DRM_FORMAT_UYVY:
447 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
b840d907
JB		 448 break;
449 case DRM_FORMAT_VYUY:
450 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
b840d907
JB		 451 break;
452 default:
28d491df 453 BUG();
b840d907
JB		 454 }
455
456 if (obj->tiling_mode != I915_TILING_NONE)
457 dvscntr |= DVS_TILED;
458
d1686ae3
CW		 459 if (IS_GEN6(dev))
460 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
b840d907
JB		 461 dvscntr |= DVS_ENABLE;
462
adf3d35e 463 intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true,
67ca28f3
VS		 464 src_w != crtc_w || src_h != crtc_h);
465
b840d907
JB		 466 /* Sizes are 0 based */
467 src_w--;
468 src_h--;
469 crtc_w--;
470 crtc_h--;
471
8aaa81a1
CW		 472 dvsscale = 0;
473 if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
b840d907
JB		 474 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
475
476 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
477 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
5a35e99e 478
ca320ac4 479 linear_offset = y * fb->pitches[0] + x * pixel_size;
5a35e99e 480 dvssurf_offset =
bc752862
CW		 481 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
482 pixel_size, fb->pitches[0]);
5a35e99e
DL		 483 linear_offset -= dvssurf_offset;
484
485 if (obj->tiling_mode != I915_TILING_NONE)
b840d907 486 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
5a35e99e
DL		 487 else
488 I915_WRITE(DVSLINOFF(pipe), linear_offset);
b840d907 489
b840d907
JB		 490 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
491 I915_WRITE(DVSSCALE(pipe), dvsscale);
492 I915_WRITE(DVSCNTR(pipe), dvscntr);
f343c5f6
BW		 493 I915_MODIFY_DISPBASE(DVSSURF(pipe),
494 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
b840d907
JB		 495 POSTING_READ(DVSSURF(pipe));
496}
497
498static void
b39d53f6 499ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
b840d907
JB		 500{
501 struct drm_device *dev = plane->dev;
502 struct drm_i915_private *dev_priv = dev->dev_private;
503 struct intel_plane *intel_plane = to_intel_plane(plane);
504 int pipe = intel_plane->pipe;
505
506 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
507 /* Disable the scaler */
508 I915_WRITE(DVSSCALE(pipe), 0);
509 /* Flush double buffered register updates */
446f2545 510 I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
b840d907 511 POSTING_READ(DVSSURF(pipe));
a95fd8ca
VS		 512
513 intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false);
b840d907
JB		 514}
515
175bd420
JB		 516static void
517intel_enable_primary(struct drm_crtc *crtc)
518{
519 struct drm_device *dev = crtc->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
522 int reg = DSPCNTR(intel_crtc->plane);
523
4c445e0e 524 if (intel_crtc->primary_enabled)
93314b5b
CW		 525 return;
526
4c445e0e 527 intel_crtc->primary_enabled = true;
82284b6b 528
abae50ed 529 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
0fc9f599 530 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
abae50ed 531
20bc8673
VS		 532 /*
533 * FIXME IPS should be fine as long as one plane is
534 * enabled, but in practice it seems to have problems
535 * when going from primary only to sprite only and vice
536 * versa.
537 */
538 if (intel_crtc->config.ips_enabled) {
539 intel_wait_for_vblank(dev, intel_crtc->pipe);
540 hsw_enable_ips(intel_crtc);
541 }
542
82284b6b 543 mutex_lock(&dev->struct_mutex);
93314b5b 544 intel_update_fbc(dev);
82284b6b 545 mutex_unlock(&dev->struct_mutex);
175bd420
JB		 546}
547
548static void
549intel_disable_primary(struct drm_crtc *crtc)
550{
551 struct drm_device *dev = crtc->dev;
552 struct drm_i915_private *dev_priv = dev->dev_private;
553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
554 int reg = DSPCNTR(intel_crtc->plane);
555
4c445e0e 556 if (!intel_crtc->primary_enabled)
93314b5b
CW		 557 return;
558
4c445e0e 559 intel_crtc->primary_enabled = false;
82284b6b
VS		 560
561 mutex_lock(&dev->struct_mutex);
abae50ed
VS		 562 if (dev_priv->fbc.plane == intel_crtc->plane)
563 intel_disable_fbc(dev);
82284b6b 564 mutex_unlock(&dev->struct_mutex);
abae50ed 565
20bc8673
VS		 566 /*
567 * FIXME IPS should be fine as long as one plane is
568 * enabled, but in practice it seems to have problems
569 * when going from primary only to sprite only and vice
570 * versa.
571 */
572 hsw_disable_ips(intel_crtc);
573
abae50ed 574 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
0fc9f599 575 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
175bd420
JB		 576}
577
8ea30864 578static int
d1686ae3 579ilk_update_colorkey(struct drm_plane *plane,
8ea30864
JB		 580 struct drm_intel_sprite_colorkey *key)
581{
582 struct drm_device *dev = plane->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 struct intel_plane *intel_plane;
585 u32 dvscntr;
586 int ret = 0;
587
588 intel_plane = to_intel_plane(plane);
589
590 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
591 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
592 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
593
594 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
595 dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
596 if (key->flags & I915_SET_COLORKEY_DESTINATION)
597 dvscntr |= DVS_DEST_KEY;
598 else if (key->flags & I915_SET_COLORKEY_SOURCE)
599 dvscntr |= DVS_SOURCE_KEY;
600 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
601
602 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
603
604 return ret;
605}
606
607static void
d1686ae3 608ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
8ea30864
JB		 609{
610 struct drm_device *dev = plane->dev;
611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct intel_plane *intel_plane;
613 u32 dvscntr;
614
615 intel_plane = to_intel_plane(plane);
616
617 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
618 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
619 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
620 key->flags = 0;
621
622 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
623
624 if (dvscntr & DVS_DEST_KEY)
625 key->flags = I915_SET_COLORKEY_DESTINATION;
626 else if (dvscntr & DVS_SOURCE_KEY)
627 key->flags = I915_SET_COLORKEY_SOURCE;
628 else
629 key->flags = I915_SET_COLORKEY_NONE;
630}
631
1731693a
VS		 632static bool
633format_is_yuv(uint32_t format)
634{
635 switch (format) {
636 case DRM_FORMAT_YUYV:
637 case DRM_FORMAT_UYVY:
638 case DRM_FORMAT_VYUY:
639 case DRM_FORMAT_YVYU:
640 return true;
641 default:
642 return false;
643 }
644}
645
b840d907
JB		 646static int
647intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
648 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
649 unsigned int crtc_w, unsigned int crtc_h,
650 uint32_t src_x, uint32_t src_y,
651 uint32_t src_w, uint32_t src_h)
652{
653 struct drm_device *dev = plane->dev;
b840d907
JB		 654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
655 struct intel_plane *intel_plane = to_intel_plane(plane);
2afd9efd
VS		 656 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
657 struct drm_i915_gem_object *obj = intel_fb->obj;
658 struct drm_i915_gem_object *old_obj = intel_plane->obj;
659 int ret;
b840d907 660 bool disable_primary = false;
1731693a
VS		 661 bool visible;
662 int hscale, vscale;
663 int max_scale, min_scale;
664 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
665 struct drm_rect src = {
666 /* sample coordinates in 16.16 fixed point */
667 .x1 = src_x,
668 .x2 = src_x + src_w,
669 .y1 = src_y,
670 .y2 = src_y + src_h,
671 };
672 struct drm_rect dst = {
673 /* integer pixels */
674 .x1 = crtc_x,
675 .x2 = crtc_x + crtc_w,
676 .y1 = crtc_y,
677 .y2 = crtc_y + crtc_h,
678 };
679 const struct drm_rect clip = {
03c5b25f
VS		 680 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
681 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
1731693a 682 };
098ebd6b
VS		 683 const struct {
684 int crtc_x, crtc_y;
685 unsigned int crtc_w, crtc_h;
686 uint32_t src_x, src_y, src_w, src_h;
687 } orig = {
688 .crtc_x = crtc_x,
689 .crtc_y = crtc_y,
690 .crtc_w = crtc_w,
691 .crtc_h = crtc_h,
692 .src_x = src_x,
693 .src_y = src_y,
694 .src_w = src_w,
695 .src_h = src_h,
696 };
5e1bac2f 697
1731693a
VS		 698 /* Don't modify another pipe's plane */
699 if (intel_plane->pipe != intel_crtc->pipe) {
700 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
b840d907 701 return -EINVAL;
1731693a 702 }
b840d907 703
1731693a
VS		 704 /* FIXME check all gen limits */
705 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
706 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
b840d907 707 return -EINVAL;
1731693a 708 }
b840d907 709
94c6419e
DL		 710 /* Sprite planes can be linear or x-tiled surfaces */
711 switch (obj->tiling_mode) {
712 case I915_TILING_NONE:
713 case I915_TILING_X:
714 break;
715 default:
1731693a 716 DRM_DEBUG_KMS("Unsupported tiling mode\n");
94c6419e
DL		 717 return -EINVAL;
718 }
719
3c3686cd
VS		 720 /*
721 * FIXME the following code does a bunch of fuzzy adjustments to the
722 * coordinates and sizes. We probably need some way to decide whether
723 * more strict checking should be done instead.
724 */
1731693a
VS		 725 max_scale = intel_plane->max_downscale << 16;
726 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
727
3c3686cd
VS		 728 hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale);
729 BUG_ON(hscale < 0);
1731693a 730
3c3686cd
VS		 731 vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale);
732 BUG_ON(vscale < 0);
b840d907 733
1731693a 734 visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale);
b840d907 735
1731693a
VS		 736 crtc_x = dst.x1;
737 crtc_y = dst.y1;
738 crtc_w = drm_rect_width(&dst);
739 crtc_h = drm_rect_height(&dst);
2d354c34 740
1731693a 741 if (visible) {
3c3686cd
VS		 742 /* check again in case clipping clamped the results */
743 hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale);
744 if (hscale < 0) {
745 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
746 drm_rect_debug_print(&src, true);
747 drm_rect_debug_print(&dst, false);
748
749 return hscale;
750 }
751
752 vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale);
753 if (vscale < 0) {
754 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
755 drm_rect_debug_print(&src, true);
756 drm_rect_debug_print(&dst, false);
757
758 return vscale;
759 }
760
1731693a
VS		 761 /* Make the source viewport size an exact multiple of the scaling factors. */
762 drm_rect_adjust_size(&src,
763 drm_rect_width(&dst) * hscale - drm_rect_width(&src),
764 drm_rect_height(&dst) * vscale - drm_rect_height(&src));
765
766 /* sanity check to make sure the src viewport wasn't enlarged */
767 WARN_ON(src.x1 < (int) src_x ||
768 src.y1 < (int) src_y ||
769 src.x2 > (int) (src_x + src_w) ||
770 src.y2 > (int) (src_y + src_h));
771
772 /*
773 * Hardware doesn't handle subpixel coordinates.
774 * Adjust to (macro)pixel boundary, but be careful not to
775 * increase the source viewport size, because that could
776 * push the downscaling factor out of bounds.
1731693a
VS		 777 */
778 src_x = src.x1 >> 16;
779 src_w = drm_rect_width(&src) >> 16;
780 src_y = src.y1 >> 16;
781 src_h = drm_rect_height(&src) >> 16;
782
783 if (format_is_yuv(fb->pixel_format)) {
784 src_x &= ~1;
785 src_w &= ~1;
786
787 /*
788 * Must keep src and dst the
789 * same if we can't scale.
790 */
791 if (!intel_plane->can_scale)
792 crtc_w &= ~1;
793
794 if (crtc_w == 0)
795 visible = false;
796 }
797 }
798
799 /* Check size restrictions when scaling */
800 if (visible && (src_w != crtc_w || src_h != crtc_h)) {
801 unsigned int width_bytes;
802
803 WARN_ON(!intel_plane->can_scale);
804
805 /* FIXME interlacing min height is 6 */
806
807 if (crtc_w < 3 || crtc_h < 3)
808 visible = false;
809
810 if (src_w < 3 || src_h < 3)
811 visible = false;
812
813 width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size;
814
815 if (src_w > 2048 || src_h > 2048 ||
816 width_bytes > 4096 || fb->pitches[0] > 4096) {
817 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
818 return -EINVAL;
819 }
820 }
821
822 dst.x1 = crtc_x;
823 dst.x2 = crtc_x + crtc_w;
824 dst.y1 = crtc_y;
825 dst.y2 = crtc_y + crtc_h;
b840d907
JB		 826
827 /*
828 * If the sprite is completely covering the primary plane,
829 * we can disable the primary and save power.
830 */
1731693a 831 disable_primary = drm_rect_equals(&dst, &clip);
03c5b25f 832 WARN_ON(disable_primary && !visible && intel_crtc->active);
b840d907
JB		 833
834 mutex_lock(&dev->struct_mutex);
835
693db184
CW		 836 /* Note that this will apply the VT-d workaround for scanouts,
837 * which is more restrictive than required for sprites. (The
838 * primary plane requires 256KiB alignment with 64 PTE padding,
839 * the sprite planes only require 128KiB alignment and 32 PTE padding.
840 */
b840d907 841 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
82284b6b
VS		 842
843 mutex_unlock(&dev->struct_mutex);
844
00c2064b 845 if (ret)
82284b6b 846 return ret;
b840d907 847
098ebd6b
VS		 848 intel_plane->crtc_x = orig.crtc_x;
849 intel_plane->crtc_y = orig.crtc_y;
850 intel_plane->crtc_w = orig.crtc_w;
851 intel_plane->crtc_h = orig.crtc_h;
852 intel_plane->src_x = orig.src_x;
853 intel_plane->src_y = orig.src_y;
854 intel_plane->src_w = orig.src_w;
855 intel_plane->src_h = orig.src_h;
b840d907
JB		 856 intel_plane->obj = obj;
857
03c5b25f
VS		 858 if (intel_crtc->active) {
859 /*
860 * Be sure to re-enable the primary before the sprite is no longer
861 * covering it fully.
862 */
863 if (!disable_primary)
864 intel_enable_primary(crtc);
865
866 if (visible)
867 intel_plane->update_plane(plane, crtc, fb, obj,
868 crtc_x, crtc_y, crtc_w, crtc_h,
869 src_x, src_y, src_w, src_h);
870 else
871 intel_plane->disable_plane(plane, crtc);
872
873 if (disable_primary)
874 intel_disable_primary(crtc);
875 }
175bd420 876
b840d907
JB		 877 /* Unpin old obj after new one is active to avoid ugliness */
878 if (old_obj) {
879 /*
880 * It's fairly common to simply update the position of
881 * an existing object. In that case, we don't need to
882 * wait for vblank to avoid ugliness, we only need to
883 * do the pin & ref bookkeeping.
884 */
82284b6b 885 if (old_obj != obj && intel_crtc->active)
2afd9efd 886 intel_wait_for_vblank(dev, intel_crtc->pipe);
82284b6b
VS		 887
888 mutex_lock(&dev->struct_mutex);
1690e1eb 889 intel_unpin_fb_obj(old_obj);
82284b6b 890 mutex_unlock(&dev->struct_mutex);
b840d907
JB		 891 }
892
82284b6b 893 return 0;
b840d907
JB		 894}
895
896static int
897intel_disable_plane(struct drm_plane *plane)
898{
899 struct drm_device *dev = plane->dev;
900 struct intel_plane *intel_plane = to_intel_plane(plane);
03c5b25f 901 struct intel_crtc *intel_crtc;
b840d907 902
88a94a58
VS		 903 if (!plane->fb)
904 return 0;
905
906 if (WARN_ON(!plane->crtc))
907 return -EINVAL;
908
03c5b25f
VS		 909 intel_crtc = to_intel_crtc(plane->crtc);
910
911 if (intel_crtc->active) {
912 intel_enable_primary(plane->crtc);
913 intel_plane->disable_plane(plane, plane->crtc);
914 }
b840d907 915
5f3fb46b
VS		 916 if (intel_plane->obj) {
917 if (intel_crtc->active)
918 intel_wait_for_vblank(dev, intel_plane->pipe);
c626d317 919
5f3fb46b
VS		 920 mutex_lock(&dev->struct_mutex);
921 intel_unpin_fb_obj(intel_plane->obj);
922 mutex_unlock(&dev->struct_mutex);
82284b6b 923
5f3fb46b
VS		 924 intel_plane->obj = NULL;
925 }
b840d907 926
5f3fb46b 927 return 0;
b840d907
JB		 928}
929
930static void intel_destroy_plane(struct drm_plane *plane)
931{
932 struct intel_plane *intel_plane = to_intel_plane(plane);
933 intel_disable_plane(plane);
934 drm_plane_cleanup(plane);
935 kfree(intel_plane);
936}
937
8ea30864
JB		 938int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
939 struct drm_file *file_priv)
940{
941 struct drm_intel_sprite_colorkey *set = data;
8ea30864
JB		 942 struct drm_mode_object *obj;
943 struct drm_plane *plane;
944 struct intel_plane *intel_plane;
945 int ret = 0;
946
1cff8f6b
DV		 947 if (!drm_core_check_feature(dev, DRIVER_MODESET))
948 return -ENODEV;
8ea30864
JB		 949
950 /* Make sure we don't try to enable both src & dest simultaneously */
951 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
952 return -EINVAL;
953
a0e99e68 954 drm_modeset_lock_all(dev);
8ea30864
JB		 955
956 obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
957 if (!obj) {
958 ret = -EINVAL;
959 goto out_unlock;
960 }
961
962 plane = obj_to_plane(obj);
963 intel_plane = to_intel_plane(plane);
964 ret = intel_plane->update_colorkey(plane, set);
965
966out_unlock:
a0e99e68 967 drm_modeset_unlock_all(dev);
8ea30864
JB		 968 return ret;
969}
970
971int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
972 struct drm_file *file_priv)
973{
974 struct drm_intel_sprite_colorkey *get = data;
8ea30864
JB		 975 struct drm_mode_object *obj;
976 struct drm_plane *plane;
977 struct intel_plane *intel_plane;
978 int ret = 0;
979
1cff8f6b
DV		 980 if (!drm_core_check_feature(dev, DRIVER_MODESET))
981 return -ENODEV;
8ea30864 982
a0e99e68 983 drm_modeset_lock_all(dev);
8ea30864
JB		 984
985 obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
986 if (!obj) {
987 ret = -EINVAL;
988 goto out_unlock;
989 }
990
991 plane = obj_to_plane(obj);
992 intel_plane = to_intel_plane(plane);
993 intel_plane->get_colorkey(plane, get);
994
995out_unlock:
a0e99e68 996 drm_modeset_unlock_all(dev);
8ea30864
JB		 997 return ret;
998}
999
5e1bac2f
JB		 1000void intel_plane_restore(struct drm_plane *plane)
1001{
1002 struct intel_plane *intel_plane = to_intel_plane(plane);
1003
1004 if (!plane->crtc || !plane->fb)
1005 return;
1006
1007 intel_update_plane(plane, plane->crtc, plane->fb,
1008 intel_plane->crtc_x, intel_plane->crtc_y,
1009 intel_plane->crtc_w, intel_plane->crtc_h,
1010 intel_plane->src_x, intel_plane->src_y,
1011 intel_plane->src_w, intel_plane->src_h);
1012}
1013
bb53d4ae
VS		 1014void intel_plane_disable(struct drm_plane *plane)
1015{
1016 if (!plane->crtc || !plane->fb)
1017 return;
1018
1019 intel_disable_plane(plane);
1020}
1021
b840d907
JB		 1022static const struct drm_plane_funcs intel_plane_funcs = {
1023 .update_plane = intel_update_plane,
1024 .disable_plane = intel_disable_plane,
1025 .destroy = intel_destroy_plane,
1026};
1027
d1686ae3
CW		 1028static uint32_t ilk_plane_formats[] = {
1029 DRM_FORMAT_XRGB8888,
1030 DRM_FORMAT_YUYV,
1031 DRM_FORMAT_YVYU,
1032 DRM_FORMAT_UYVY,
1033 DRM_FORMAT_VYUY,
1034};
1035
b840d907
JB		 1036static uint32_t snb_plane_formats[] = {
1037 DRM_FORMAT_XBGR8888,
1038 DRM_FORMAT_XRGB8888,
1039 DRM_FORMAT_YUYV,
1040 DRM_FORMAT_YVYU,
1041 DRM_FORMAT_UYVY,
1042 DRM_FORMAT_VYUY,
1043};
1044
7f1f3851
JB		 1045static uint32_t vlv_plane_formats[] = {
1046 DRM_FORMAT_RGB565,
1047 DRM_FORMAT_ABGR8888,
1048 DRM_FORMAT_ARGB8888,
1049 DRM_FORMAT_XBGR8888,
1050 DRM_FORMAT_XRGB8888,
1051 DRM_FORMAT_XBGR2101010,
1052 DRM_FORMAT_ABGR2101010,
1053 DRM_FORMAT_YUYV,
1054 DRM_FORMAT_YVYU,
1055 DRM_FORMAT_UYVY,
1056 DRM_FORMAT_VYUY,
1057};
1058
b840d907 1059int
7f1f3851 1060intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
b840d907
JB		 1061{
1062 struct intel_plane *intel_plane;
1063 unsigned long possible_crtcs;
d1686ae3
CW		 1064 const uint32_t *plane_formats;
1065 int num_plane_formats;
b840d907
JB		 1066 int ret;
1067
d1686ae3 1068 if (INTEL_INFO(dev)->gen < 5)
b840d907 1069 return -ENODEV;
b840d907 1070
b14c5679 1071 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
b840d907
JB		 1072 if (!intel_plane)
1073 return -ENOMEM;
1074
d1686ae3
CW		 1075 switch (INTEL_INFO(dev)->gen) {
1076 case 5:
1077 case 6:
2d354c34 1078 intel_plane->can_scale = true;
b840d907 1079 intel_plane->max_downscale = 16;
d1686ae3
CW		 1080 intel_plane->update_plane = ilk_update_plane;
1081 intel_plane->disable_plane = ilk_disable_plane;
1082 intel_plane->update_colorkey = ilk_update_colorkey;
1083 intel_plane->get_colorkey = ilk_get_colorkey;
1084
1085 if (IS_GEN6(dev)) {
1086 plane_formats = snb_plane_formats;
1087 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1088 } else {
1089 plane_formats = ilk_plane_formats;
1090 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1091 }
1092 break;
1093
1094 case 7:
d49f7091 1095 if (IS_IVYBRIDGE(dev)) {
2d354c34 1096 intel_plane->can_scale = true;
d49f7091
DL		 1097 intel_plane->max_downscale = 2;
1098 } else {
1099 intel_plane->can_scale = false;
1100 intel_plane->max_downscale = 1;
1101 }
7f1f3851
JB		 1102
1103 if (IS_VALLEYVIEW(dev)) {
7f1f3851
JB		 1104 intel_plane->update_plane = vlv_update_plane;
1105 intel_plane->disable_plane = vlv_disable_plane;
1106 intel_plane->update_colorkey = vlv_update_colorkey;
1107 intel_plane->get_colorkey = vlv_get_colorkey;
1108
1109 plane_formats = vlv_plane_formats;
1110 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1111 } else {
7f1f3851
JB		 1112 intel_plane->update_plane = ivb_update_plane;
1113 intel_plane->disable_plane = ivb_disable_plane;
1114 intel_plane->update_colorkey = ivb_update_colorkey;
1115 intel_plane->get_colorkey = ivb_get_colorkey;
1116
1117 plane_formats = snb_plane_formats;
1118 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1119 }
d1686ae3
CW		 1120 break;
1121
1122 default:
a8b0bbab 1123 kfree(intel_plane);
d1686ae3 1124 return -ENODEV;
b840d907
JB		 1125 }
1126
1127 intel_plane->pipe = pipe;
7f1f3851 1128 intel_plane->plane = plane;
b840d907
JB		 1129 possible_crtcs = (1 << pipe);
1130 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
d1686ae3
CW		 1131 &intel_plane_funcs,
1132 plane_formats, num_plane_formats,
1133 false);
b840d907
JB		 1134 if (ret)
1135 kfree(intel_plane);
1136
1137 return ret;
1138}
Linux kernel - Deliverables
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