Commit | Line | Data |
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b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
1731693a | 35 | #include <drm/drm_rect.h> |
c331879c | 36 | #include <drm/drm_atomic.h> |
ea2c67bb | 37 | #include <drm/drm_plane_helper.h> |
b840d907 | 38 | #include "intel_drv.h" |
5d723d7a | 39 | #include "intel_frontbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
b840d907 JB |
41 | #include "i915_drv.h" |
42 | ||
6ca2aeb2 VS |
43 | static bool |
44 | format_is_yuv(uint32_t format) | |
45 | { | |
46 | switch (format) { | |
47 | case DRM_FORMAT_YUYV: | |
48 | case DRM_FORMAT_UYVY: | |
49 | case DRM_FORMAT_VYUY: | |
50 | case DRM_FORMAT_YVYU: | |
51 | return true; | |
52 | default: | |
53 | return false; | |
54 | } | |
55 | } | |
56 | ||
5e7234c9 VS |
57 | static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
58 | int usecs) | |
8d7849db VS |
59 | { |
60 | /* paranoia */ | |
5e7234c9 | 61 | if (!adjusted_mode->crtc_htotal) |
8d7849db VS |
62 | return 1; |
63 | ||
5e7234c9 VS |
64 | return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, |
65 | 1000 * adjusted_mode->crtc_htotal); | |
8d7849db VS |
66 | } |
67 | ||
26ff2762 ACO |
68 | /** |
69 | * intel_pipe_update_start() - start update of a set of display registers | |
70 | * @crtc: the crtc of which the registers are going to be updated | |
71 | * @start_vbl_count: vblank counter return pointer used for error checking | |
72 | * | |
73 | * Mark the start of an update to pipe registers that should be updated | |
74 | * atomically regarding vblank. If the next vblank will happens within | |
75 | * the next 100 us, this function waits until the vblank passes. | |
76 | * | |
77 | * After a successful call to this function, interrupts will be disabled | |
78 | * until a subsequent call to intel_pipe_update_end(). That is done to | |
79 | * avoid random delays. The value written to @start_vbl_count should be | |
80 | * supplied to intel_pipe_update_end() for error checking. | |
26ff2762 | 81 | */ |
34e0adbb | 82 | void intel_pipe_update_start(struct intel_crtc *crtc) |
8d7849db | 83 | { |
124abe07 | 84 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
8d7849db VS |
85 | long timeout = msecs_to_jiffies_timeout(1); |
86 | int scanline, min, max, vblank_start; | |
210871b6 | 87 | wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
8d7849db VS |
88 | DEFINE_WAIT(wait); |
89 | ||
124abe07 VS |
90 | vblank_start = adjusted_mode->crtc_vblank_start; |
91 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
8d7849db VS |
92 | vblank_start = DIV_ROUND_UP(vblank_start, 2); |
93 | ||
94 | /* FIXME needs to be calibrated sensibly */ | |
124abe07 | 95 | min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); |
8d7849db VS |
96 | max = vblank_start - 1; |
97 | ||
8f539a83 | 98 | local_irq_disable(); |
8f539a83 | 99 | |
8d7849db | 100 | if (min <= 0 || max <= 0) |
8f539a83 | 101 | return; |
8d7849db | 102 | |
1e3feefd | 103 | if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) |
8f539a83 | 104 | return; |
8d7849db | 105 | |
d637ce3f JB |
106 | crtc->debug.min_vbl = min; |
107 | crtc->debug.max_vbl = max; | |
108 | trace_i915_pipe_update_start(crtc); | |
25ef284a | 109 | |
8d7849db VS |
110 | for (;;) { |
111 | /* | |
112 | * prepare_to_wait() has a memory barrier, which guarantees | |
113 | * other CPUs can see the task state update by the time we | |
114 | * read the scanline. | |
115 | */ | |
210871b6 | 116 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
8d7849db VS |
117 | |
118 | scanline = intel_get_crtc_scanline(crtc); | |
119 | if (scanline < min || scanline > max) | |
120 | break; | |
121 | ||
122 | if (timeout <= 0) { | |
123 | DRM_ERROR("Potential atomic update failure on pipe %c\n", | |
124 | pipe_name(crtc->pipe)); | |
125 | break; | |
126 | } | |
127 | ||
128 | local_irq_enable(); | |
129 | ||
130 | timeout = schedule_timeout(timeout); | |
131 | ||
132 | local_irq_disable(); | |
133 | } | |
134 | ||
210871b6 | 135 | finish_wait(wq, &wait); |
8d7849db | 136 | |
1e3feefd | 137 | drm_crtc_vblank_put(&crtc->base); |
8d7849db | 138 | |
eb120ef6 JB |
139 | crtc->debug.scanline_start = scanline; |
140 | crtc->debug.start_vbl_time = ktime_get(); | |
a2991414 | 141 | crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc); |
8d7849db | 142 | |
d637ce3f | 143 | trace_i915_pipe_update_vblank_evaded(crtc); |
8d7849db VS |
144 | } |
145 | ||
26ff2762 ACO |
146 | /** |
147 | * intel_pipe_update_end() - end update of a set of display registers | |
148 | * @crtc: the crtc of which the registers were updated | |
149 | * @start_vbl_count: start vblank counter (used for error checking) | |
150 | * | |
151 | * Mark the end of an update started with intel_pipe_update_start(). This | |
152 | * re-enables interrupts and verifies the update was actually completed | |
153 | * before a vblank using the value of @start_vbl_count. | |
154 | */ | |
51cbaf01 | 155 | void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work) |
8d7849db | 156 | { |
8d7849db | 157 | enum pipe pipe = crtc->pipe; |
eb120ef6 | 158 | int scanline_end = intel_get_crtc_scanline(crtc); |
a2991414 | 159 | u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); |
85a62bf9 | 160 | ktime_t end_vbl_time = ktime_get(); |
8d7849db | 161 | |
51cbaf01 ML |
162 | if (work) { |
163 | work->flip_queued_vblank = end_vbl_count; | |
164 | smp_mb__before_atomic(); | |
165 | atomic_set(&work->pending, 1); | |
166 | } | |
167 | ||
d637ce3f | 168 | trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); |
25ef284a | 169 | |
1f7528c4 DV |
170 | /* We're still in the vblank-evade critical section, this can't race. |
171 | * Would be slightly nice to just grab the vblank count and arm the | |
172 | * event outside of the critical section - the spinlock might spin for a | |
173 | * while ... */ | |
174 | if (crtc->base.state->event) { | |
175 | WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); | |
176 | ||
177 | spin_lock(&crtc->base.dev->event_lock); | |
178 | drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event); | |
179 | spin_unlock(&crtc->base.dev->event_lock); | |
180 | ||
181 | crtc->base.state->event = NULL; | |
182 | } | |
183 | ||
8d7849db VS |
184 | local_irq_enable(); |
185 | ||
eb120ef6 JB |
186 | if (crtc->debug.start_vbl_count && |
187 | crtc->debug.start_vbl_count != end_vbl_count) { | |
188 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", | |
189 | pipe_name(pipe), crtc->debug.start_vbl_count, | |
190 | end_vbl_count, | |
191 | ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), | |
192 | crtc->debug.min_vbl, crtc->debug.max_vbl, | |
193 | crtc->debug.scanline_start, scanline_end); | |
194 | } | |
8d7849db VS |
195 | } |
196 | ||
dc2a41b4 | 197 | static void |
2fde1391 ML |
198 | skl_update_plane(struct drm_plane *drm_plane, |
199 | const struct intel_crtc_state *crtc_state, | |
200 | const struct intel_plane_state *plane_state) | |
dc2a41b4 DL |
201 | { |
202 | struct drm_device *dev = drm_plane->dev; | |
fac5e23e | 203 | struct drm_i915_private *dev_priv = to_i915(dev); |
dc2a41b4 | 204 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); |
2fde1391 | 205 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 206 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
dc2a41b4 DL |
207 | const int pipe = intel_plane->pipe; |
208 | const int plane = intel_plane->plane + 1; | |
3b7a5119 | 209 | u32 plane_ctl, stride_div, stride; |
2fde1391 | 210 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
44eb0cb9 | 211 | u32 surf_addr; |
3b7a5119 | 212 | u32 tile_height, plane_offset, plane_size; |
8d0deca8 | 213 | unsigned int rotation = plane_state->base.rotation; |
3b7a5119 | 214 | int x_offset, y_offset; |
2fde1391 ML |
215 | int crtc_x = plane_state->dst.x1; |
216 | int crtc_y = plane_state->dst.y1; | |
217 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
218 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
219 | uint32_t x = plane_state->src.x1 >> 16; | |
220 | uint32_t y = plane_state->src.y1 >> 16; | |
221 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
222 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
dc2a41b4 | 223 | |
48fe4691 | 224 | plane_ctl = PLANE_CTL_ENABLE | |
e12c8ce8 | 225 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
48fe4691 | 226 | PLANE_CTL_PIPE_CSC_ENABLE; |
dc2a41b4 | 227 | |
c331879c CK |
228 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
229 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
b321803d | 230 | |
c331879c | 231 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
dc2a41b4 | 232 | |
7b49f948 | 233 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d DL |
234 | fb->pixel_format); |
235 | ||
dc2a41b4 DL |
236 | /* Sizes are 0 based */ |
237 | src_w--; | |
238 | src_h--; | |
239 | crtc_w--; | |
240 | crtc_h--; | |
241 | ||
47ecbb20 VS |
242 | if (key->flags) { |
243 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); | |
244 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); | |
245 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); | |
246 | } | |
247 | ||
248 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
249 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
250 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
251 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
252 | ||
dedf278c | 253 | surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); |
121920fa | 254 | |
3b7a5119 | 255 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
256 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
257 | ||
3b7a5119 | 258 | /* stride: Surface height in tiles */ |
832be82f | 259 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 SJ |
260 | stride = DIV_ROUND_UP(fb->height, tile_height); |
261 | plane_size = (src_w << 16) | src_h; | |
262 | x_offset = stride * tile_height - y - (src_h + 1); | |
263 | y_offset = x; | |
264 | } else { | |
265 | stride = fb->pitches[0] / stride_div; | |
266 | plane_size = (src_h << 16) | src_w; | |
267 | x_offset = x; | |
268 | y_offset = y; | |
269 | } | |
270 | plane_offset = y_offset << 16 | x_offset; | |
271 | ||
272 | I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); | |
273 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); | |
3b7a5119 | 274 | I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); |
c331879c CK |
275 | |
276 | /* program plane scaler */ | |
2fde1391 | 277 | if (plane_state->scaler_id >= 0) { |
2fde1391 | 278 | int scaler_id = plane_state->scaler_id; |
7494bcdc | 279 | const struct intel_scaler *scaler; |
c331879c CK |
280 | |
281 | DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, | |
282 | PS_PLANE_SEL(plane)); | |
7494bcdc ID |
283 | |
284 | scaler = &crtc_state->scaler_state.scalers[scaler_id]; | |
285 | ||
286 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), | |
287 | PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode); | |
c331879c CK |
288 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); |
289 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); | |
290 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), | |
291 | ((crtc_w + 1) << 16)|(crtc_h + 1)); | |
292 | ||
293 | I915_WRITE(PLANE_POS(pipe, plane), 0); | |
294 | } else { | |
295 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); | |
296 | } | |
297 | ||
dc2a41b4 | 298 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); |
121920fa | 299 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
dc2a41b4 DL |
300 | POSTING_READ(PLANE_SURF(pipe, plane)); |
301 | } | |
302 | ||
303 | static void | |
7fabf5ef | 304 | skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
dc2a41b4 | 305 | { |
a8ad0d8e | 306 | struct drm_device *dev = dplane->dev; |
fac5e23e | 307 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8ad0d8e | 308 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
dc2a41b4 DL |
309 | const int pipe = intel_plane->pipe; |
310 | const int plane = intel_plane->plane + 1; | |
311 | ||
48fe4691 | 312 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
dc2a41b4 | 313 | |
2ddc1dad VS |
314 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
315 | POSTING_READ(PLANE_SURF(pipe, plane)); | |
dc2a41b4 DL |
316 | } |
317 | ||
6ca2aeb2 VS |
318 | static void |
319 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) | |
320 | { | |
fac5e23e | 321 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); |
6ca2aeb2 VS |
322 | int plane = intel_plane->plane; |
323 | ||
324 | /* Seems RGB data bypasses the CSC always */ | |
325 | if (!format_is_yuv(format)) | |
326 | return; | |
327 | ||
328 | /* | |
329 | * BT.601 limited range YCbCr -> full range RGB | |
330 | * | |
331 | * |r| | 6537 4769 0| |cr | | |
332 | * |g| = |-3330 4769 -1605| x |y-64| | |
333 | * |b| | 0 4769 8263| |cb | | |
334 | * | |
335 | * Cb and Cr apparently come in as signed already, so no | |
336 | * need for any offset. For Y we need to remove the offset. | |
337 | */ | |
338 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); | |
339 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
340 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
341 | ||
342 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); | |
343 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); | |
344 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); | |
345 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); | |
346 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); | |
347 | ||
348 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); | |
349 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
350 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
351 | ||
352 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
353 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
354 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
355 | } | |
356 | ||
7f1f3851 | 357 | static void |
2fde1391 ML |
358 | vlv_update_plane(struct drm_plane *dplane, |
359 | const struct intel_crtc_state *crtc_state, | |
360 | const struct intel_plane_state *plane_state) | |
7f1f3851 JB |
361 | { |
362 | struct drm_device *dev = dplane->dev; | |
fac5e23e | 363 | struct drm_i915_private *dev_priv = to_i915(dev); |
7f1f3851 | 364 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
2fde1391 | 365 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 366 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7f1f3851 JB |
367 | int pipe = intel_plane->pipe; |
368 | int plane = intel_plane->plane; | |
369 | u32 sprctl; | |
54ea9da8 | 370 | u32 sprsurf_offset, linear_offset; |
8d0deca8 | 371 | unsigned int rotation = dplane->state->rotation; |
ac484963 | 372 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2fde1391 ML |
373 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
374 | int crtc_x = plane_state->dst.x1; | |
375 | int crtc_y = plane_state->dst.y1; | |
376 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
377 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
378 | uint32_t x = plane_state->src.x1 >> 16; | |
379 | uint32_t y = plane_state->src.y1 >> 16; | |
380 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
381 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
7f1f3851 | 382 | |
48fe4691 | 383 | sprctl = SP_ENABLE; |
7f1f3851 JB |
384 | |
385 | switch (fb->pixel_format) { | |
386 | case DRM_FORMAT_YUYV: | |
387 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; | |
388 | break; | |
389 | case DRM_FORMAT_YVYU: | |
390 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; | |
391 | break; | |
392 | case DRM_FORMAT_UYVY: | |
393 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; | |
394 | break; | |
395 | case DRM_FORMAT_VYUY: | |
396 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; | |
397 | break; | |
398 | case DRM_FORMAT_RGB565: | |
399 | sprctl |= SP_FORMAT_BGR565; | |
400 | break; | |
401 | case DRM_FORMAT_XRGB8888: | |
402 | sprctl |= SP_FORMAT_BGRX8888; | |
403 | break; | |
404 | case DRM_FORMAT_ARGB8888: | |
405 | sprctl |= SP_FORMAT_BGRA8888; | |
406 | break; | |
407 | case DRM_FORMAT_XBGR2101010: | |
408 | sprctl |= SP_FORMAT_RGBX1010102; | |
409 | break; | |
410 | case DRM_FORMAT_ABGR2101010: | |
411 | sprctl |= SP_FORMAT_RGBA1010102; | |
412 | break; | |
413 | case DRM_FORMAT_XBGR8888: | |
414 | sprctl |= SP_FORMAT_RGBX8888; | |
415 | break; | |
416 | case DRM_FORMAT_ABGR8888: | |
417 | sprctl |= SP_FORMAT_RGBA8888; | |
418 | break; | |
419 | default: | |
420 | /* | |
421 | * If we get here one of the upper layers failed to filter | |
422 | * out the unsupported plane formats | |
423 | */ | |
424 | BUG(); | |
425 | break; | |
426 | } | |
427 | ||
4ea67bc7 VS |
428 | /* |
429 | * Enable gamma to match primary/cursor plane behaviour. | |
430 | * FIXME should be user controllable via propertiesa. | |
431 | */ | |
432 | sprctl |= SP_GAMMA_ENABLE; | |
433 | ||
7f1f3851 JB |
434 | if (obj->tiling_mode != I915_TILING_NONE) |
435 | sprctl |= SP_TILED; | |
436 | ||
7f1f3851 JB |
437 | /* Sizes are 0 based */ |
438 | src_w--; | |
439 | src_h--; | |
440 | crtc_w--; | |
441 | crtc_h--; | |
442 | ||
ac484963 | 443 | linear_offset = y * fb->pitches[0] + x * cpp; |
4f2d9934 | 444 | sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 445 | fb->pitches[0], rotation); |
7f1f3851 JB |
446 | linear_offset -= sprsurf_offset; |
447 | ||
8d0deca8 | 448 | if (rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
449 | sprctl |= SP_ROTATE_180; |
450 | ||
451 | x += src_w; | |
452 | y += src_h; | |
ac484963 | 453 | linear_offset += src_h * fb->pitches[0] + src_w * cpp; |
76eebda7 VS |
454 | } |
455 | ||
47ecbb20 VS |
456 | if (key->flags) { |
457 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); | |
458 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); | |
459 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); | |
460 | } | |
461 | ||
462 | if (key->flags & I915_SET_COLORKEY_SOURCE) | |
463 | sprctl |= SP_SOURCE_KEY; | |
464 | ||
6ca2aeb2 VS |
465 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
466 | chv_update_csc(intel_plane, fb->pixel_format); | |
467 | ||
ca6ad025 VS |
468 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
469 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); | |
470 | ||
7f1f3851 JB |
471 | if (obj->tiling_mode != I915_TILING_NONE) |
472 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); | |
473 | else | |
474 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); | |
475 | ||
c14b0485 VS |
476 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
477 | ||
7f1f3851 JB |
478 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
479 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
85ba7b7d DV |
480 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
481 | sprsurf_offset); | |
b12ce1d8 | 482 | POSTING_READ(SPSURF(pipe, plane)); |
7f1f3851 JB |
483 | } |
484 | ||
485 | static void | |
7fabf5ef | 486 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
7f1f3851 JB |
487 | { |
488 | struct drm_device *dev = dplane->dev; | |
fac5e23e | 489 | struct drm_i915_private *dev_priv = to_i915(dev); |
7f1f3851 JB |
490 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
491 | int pipe = intel_plane->pipe; | |
492 | int plane = intel_plane->plane; | |
493 | ||
48fe4691 VS |
494 | I915_WRITE(SPCNTR(pipe, plane), 0); |
495 | ||
85ba7b7d | 496 | I915_WRITE(SPSURF(pipe, plane), 0); |
b12ce1d8 | 497 | POSTING_READ(SPSURF(pipe, plane)); |
7f1f3851 JB |
498 | } |
499 | ||
b840d907 | 500 | static void |
2fde1391 ML |
501 | ivb_update_plane(struct drm_plane *plane, |
502 | const struct intel_crtc_state *crtc_state, | |
503 | const struct intel_plane_state *plane_state) | |
b840d907 JB |
504 | { |
505 | struct drm_device *dev = plane->dev; | |
fac5e23e | 506 | struct drm_i915_private *dev_priv = to_i915(dev); |
b840d907 | 507 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2fde1391 | 508 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 509 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
47ecbb20 | 510 | enum pipe pipe = intel_plane->pipe; |
b840d907 | 511 | u32 sprctl, sprscale = 0; |
54ea9da8 | 512 | u32 sprsurf_offset, linear_offset; |
8d0deca8 | 513 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 514 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2fde1391 ML |
515 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
516 | int crtc_x = plane_state->dst.x1; | |
517 | int crtc_y = plane_state->dst.y1; | |
518 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
519 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
520 | uint32_t x = plane_state->src.x1 >> 16; | |
521 | uint32_t y = plane_state->src.y1 >> 16; | |
522 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
523 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
b840d907 | 524 | |
48fe4691 | 525 | sprctl = SPRITE_ENABLE; |
b840d907 JB |
526 | |
527 | switch (fb->pixel_format) { | |
528 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 529 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
530 | break; |
531 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 532 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
533 | break; |
534 | case DRM_FORMAT_YUYV: | |
535 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
536 | break; |
537 | case DRM_FORMAT_YVYU: | |
538 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
539 | break; |
540 | case DRM_FORMAT_UYVY: | |
541 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
542 | break; |
543 | case DRM_FORMAT_VYUY: | |
544 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
545 | break; |
546 | default: | |
28d491df | 547 | BUG(); |
b840d907 JB |
548 | } |
549 | ||
4ea67bc7 VS |
550 | /* |
551 | * Enable gamma to match primary/cursor plane behaviour. | |
552 | * FIXME should be user controllable via propertiesa. | |
553 | */ | |
554 | sprctl |= SPRITE_GAMMA_ENABLE; | |
555 | ||
b840d907 JB |
556 | if (obj->tiling_mode != I915_TILING_NONE) |
557 | sprctl |= SPRITE_TILED; | |
558 | ||
b42c6009 | 559 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
560 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
561 | else | |
562 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
563 | ||
6bbfa1c5 | 564 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
86d3efce VS |
565 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
566 | ||
b840d907 JB |
567 | /* Sizes are 0 based */ |
568 | src_w--; | |
569 | src_h--; | |
570 | crtc_w--; | |
571 | crtc_h--; | |
572 | ||
8553c18e | 573 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 | 574 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
b840d907 | 575 | |
ac484963 | 576 | linear_offset = y * fb->pitches[0] + x * cpp; |
4f2d9934 | 577 | sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 578 | fb->pitches[0], rotation); |
5a35e99e DL |
579 | linear_offset -= sprsurf_offset; |
580 | ||
8d0deca8 | 581 | if (rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
582 | sprctl |= SPRITE_ROTATE_180; |
583 | ||
584 | /* HSW and BDW does this automagically in hardware */ | |
585 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
586 | x += src_w; | |
587 | y += src_h; | |
ac484963 | 588 | linear_offset += src_h * fb->pitches[0] + src_w * cpp; |
76eebda7 VS |
589 | } |
590 | } | |
591 | ||
47ecbb20 VS |
592 | if (key->flags) { |
593 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); | |
594 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); | |
595 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); | |
596 | } | |
597 | ||
598 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
599 | sprctl |= SPRITE_DEST_KEY; | |
600 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
601 | sprctl |= SPRITE_SOURCE_KEY; | |
602 | ||
ca6ad025 VS |
603 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
604 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
605 | ||
5a35e99e DL |
606 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
607 | * register */ | |
b3dc685e | 608 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
c54173a8 | 609 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 610 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 611 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
612 | else |
613 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 614 | |
b840d907 | 615 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
616 | if (intel_plane->can_scale) |
617 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 618 | I915_WRITE(SPRCTL(pipe), sprctl); |
85ba7b7d DV |
619 | I915_WRITE(SPRSURF(pipe), |
620 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); | |
b12ce1d8 | 621 | POSTING_READ(SPRSURF(pipe)); |
b840d907 JB |
622 | } |
623 | ||
624 | static void | |
7fabf5ef | 625 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
626 | { |
627 | struct drm_device *dev = plane->dev; | |
fac5e23e | 628 | struct drm_i915_private *dev_priv = to_i915(dev); |
b840d907 JB |
629 | struct intel_plane *intel_plane = to_intel_plane(plane); |
630 | int pipe = intel_plane->pipe; | |
631 | ||
c562657a | 632 | I915_WRITE(SPRCTL(pipe), 0); |
b840d907 | 633 | /* Can't leave the scaler enabled... */ |
2d354c34 DL |
634 | if (intel_plane->can_scale) |
635 | I915_WRITE(SPRSCALE(pipe), 0); | |
5b633d6b | 636 | |
b12ce1d8 VS |
637 | I915_WRITE(SPRSURF(pipe), 0); |
638 | POSTING_READ(SPRSURF(pipe)); | |
b840d907 JB |
639 | } |
640 | ||
641 | static void | |
2fde1391 ML |
642 | ilk_update_plane(struct drm_plane *plane, |
643 | const struct intel_crtc_state *crtc_state, | |
644 | const struct intel_plane_state *plane_state) | |
b840d907 JB |
645 | { |
646 | struct drm_device *dev = plane->dev; | |
fac5e23e | 647 | struct drm_i915_private *dev_priv = to_i915(dev); |
b840d907 | 648 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2fde1391 | 649 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 650 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2bd3c3cb | 651 | int pipe = intel_plane->pipe; |
8aaa81a1 | 652 | u32 dvscntr, dvsscale; |
54ea9da8 | 653 | u32 dvssurf_offset, linear_offset; |
8d0deca8 | 654 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 655 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
2fde1391 ML |
656 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
657 | int crtc_x = plane_state->dst.x1; | |
658 | int crtc_y = plane_state->dst.y1; | |
659 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
660 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
661 | uint32_t x = plane_state->src.x1 >> 16; | |
662 | uint32_t y = plane_state->src.y1 >> 16; | |
663 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
664 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
b840d907 | 665 | |
48fe4691 | 666 | dvscntr = DVS_ENABLE; |
b840d907 JB |
667 | |
668 | switch (fb->pixel_format) { | |
669 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 670 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
671 | break; |
672 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 673 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
674 | break; |
675 | case DRM_FORMAT_YUYV: | |
676 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
677 | break; |
678 | case DRM_FORMAT_YVYU: | |
679 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
680 | break; |
681 | case DRM_FORMAT_UYVY: | |
682 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
683 | break; |
684 | case DRM_FORMAT_VYUY: | |
685 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
686 | break; |
687 | default: | |
28d491df | 688 | BUG(); |
b840d907 JB |
689 | } |
690 | ||
4ea67bc7 VS |
691 | /* |
692 | * Enable gamma to match primary/cursor plane behaviour. | |
693 | * FIXME should be user controllable via propertiesa. | |
694 | */ | |
695 | dvscntr |= DVS_GAMMA_ENABLE; | |
696 | ||
b840d907 JB |
697 | if (obj->tiling_mode != I915_TILING_NONE) |
698 | dvscntr |= DVS_TILED; | |
699 | ||
d1686ae3 CW |
700 | if (IS_GEN6(dev)) |
701 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
702 | |
703 | /* Sizes are 0 based */ | |
704 | src_w--; | |
705 | src_h--; | |
706 | crtc_w--; | |
707 | crtc_h--; | |
708 | ||
8aaa81a1 | 709 | dvsscale = 0; |
8368f014 | 710 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 JB |
711 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
712 | ||
ac484963 | 713 | linear_offset = y * fb->pitches[0] + x * cpp; |
4f2d9934 | 714 | dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 715 | fb->pitches[0], rotation); |
5a35e99e DL |
716 | linear_offset -= dvssurf_offset; |
717 | ||
8d0deca8 | 718 | if (rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
719 | dvscntr |= DVS_ROTATE_180; |
720 | ||
721 | x += src_w; | |
722 | y += src_h; | |
ac484963 | 723 | linear_offset += src_h * fb->pitches[0] + src_w * cpp; |
76eebda7 VS |
724 | } |
725 | ||
47ecbb20 VS |
726 | if (key->flags) { |
727 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); | |
728 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); | |
729 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); | |
730 | } | |
731 | ||
732 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
733 | dvscntr |= DVS_DEST_KEY; | |
734 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
735 | dvscntr |= DVS_SOURCE_KEY; | |
736 | ||
ca6ad025 VS |
737 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
738 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
739 | ||
5a35e99e | 740 | if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 741 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
742 | else |
743 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 744 | |
b840d907 JB |
745 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
746 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
747 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
85ba7b7d DV |
748 | I915_WRITE(DVSSURF(pipe), |
749 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); | |
b12ce1d8 | 750 | POSTING_READ(DVSSURF(pipe)); |
b840d907 JB |
751 | } |
752 | ||
753 | static void | |
7fabf5ef | 754 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
755 | { |
756 | struct drm_device *dev = plane->dev; | |
fac5e23e | 757 | struct drm_i915_private *dev_priv = to_i915(dev); |
b840d907 JB |
758 | struct intel_plane *intel_plane = to_intel_plane(plane); |
759 | int pipe = intel_plane->pipe; | |
760 | ||
48fe4691 | 761 | I915_WRITE(DVSCNTR(pipe), 0); |
b840d907 JB |
762 | /* Disable the scaler */ |
763 | I915_WRITE(DVSSCALE(pipe), 0); | |
48fe4691 | 764 | |
85ba7b7d | 765 | I915_WRITE(DVSSURF(pipe), 0); |
b12ce1d8 | 766 | POSTING_READ(DVSSURF(pipe)); |
b840d907 JB |
767 | } |
768 | ||
769 | static int | |
96d61a7f | 770 | intel_check_sprite_plane(struct drm_plane *plane, |
061e4b8d | 771 | struct intel_crtc_state *crtc_state, |
96d61a7f | 772 | struct intel_plane_state *state) |
b840d907 | 773 | { |
c331879c | 774 | struct drm_device *dev = plane->dev; |
061e4b8d ML |
775 | struct drm_crtc *crtc = state->base.crtc; |
776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b840d907 | 777 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 778 | struct drm_framebuffer *fb = state->base.fb; |
96d61a7f GP |
779 | int crtc_x, crtc_y; |
780 | unsigned int crtc_w, crtc_h; | |
781 | uint32_t src_x, src_y, src_w, src_h; | |
782 | struct drm_rect *src = &state->src; | |
783 | struct drm_rect *dst = &state->dst; | |
96d61a7f | 784 | const struct drm_rect *clip = &state->clip; |
1731693a VS |
785 | int hscale, vscale; |
786 | int max_scale, min_scale; | |
225c228a | 787 | bool can_scale; |
cf4c7c12 MR |
788 | |
789 | if (!fb) { | |
790 | state->visible = false; | |
da20eabd | 791 | return 0; |
cf4c7c12 | 792 | } |
5e1bac2f | 793 | |
1731693a VS |
794 | /* Don't modify another pipe's plane */ |
795 | if (intel_plane->pipe != intel_crtc->pipe) { | |
796 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); | |
b840d907 | 797 | return -EINVAL; |
1731693a | 798 | } |
b840d907 | 799 | |
1731693a VS |
800 | /* FIXME check all gen limits */ |
801 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { | |
802 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); | |
b840d907 | 803 | return -EINVAL; |
1731693a | 804 | } |
b840d907 | 805 | |
225c228a CK |
806 | /* setup can_scale, min_scale, max_scale */ |
807 | if (INTEL_INFO(dev)->gen >= 9) { | |
808 | /* use scaler when colorkey is not required */ | |
818ed961 | 809 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { |
225c228a CK |
810 | can_scale = 1; |
811 | min_scale = 1; | |
812 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
813 | } else { | |
814 | can_scale = 0; | |
815 | min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
816 | max_scale = DRM_PLANE_HELPER_NO_SCALING; | |
817 | } | |
818 | } else { | |
819 | can_scale = intel_plane->can_scale; | |
820 | max_scale = intel_plane->max_downscale << 16; | |
821 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); | |
822 | } | |
823 | ||
3c3686cd VS |
824 | /* |
825 | * FIXME the following code does a bunch of fuzzy adjustments to the | |
826 | * coordinates and sizes. We probably need some way to decide whether | |
827 | * more strict checking should be done instead. | |
828 | */ | |
96d61a7f | 829 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
8e7d688b | 830 | state->base.rotation); |
76eebda7 | 831 | |
96d61a7f | 832 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 833 | BUG_ON(hscale < 0); |
1731693a | 834 | |
96d61a7f | 835 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 836 | BUG_ON(vscale < 0); |
b840d907 | 837 | |
818ed961 | 838 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
b840d907 | 839 | |
96d61a7f GP |
840 | crtc_x = dst->x1; |
841 | crtc_y = dst->y1; | |
842 | crtc_w = drm_rect_width(dst); | |
843 | crtc_h = drm_rect_height(dst); | |
2d354c34 | 844 | |
96d61a7f | 845 | if (state->visible) { |
3c3686cd | 846 | /* check again in case clipping clamped the results */ |
96d61a7f | 847 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
848 | if (hscale < 0) { |
849 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); | |
c70f577a VS |
850 | drm_rect_debug_print("src: ", src, true); |
851 | drm_rect_debug_print("dst: ", dst, false); | |
3c3686cd VS |
852 | |
853 | return hscale; | |
854 | } | |
855 | ||
96d61a7f | 856 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
857 | if (vscale < 0) { |
858 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); | |
c70f577a VS |
859 | drm_rect_debug_print("src: ", src, true); |
860 | drm_rect_debug_print("dst: ", dst, false); | |
3c3686cd VS |
861 | |
862 | return vscale; | |
863 | } | |
864 | ||
1731693a | 865 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
96d61a7f GP |
866 | drm_rect_adjust_size(src, |
867 | drm_rect_width(dst) * hscale - drm_rect_width(src), | |
868 | drm_rect_height(dst) * vscale - drm_rect_height(src)); | |
1731693a | 869 | |
96d61a7f | 870 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
8e7d688b | 871 | state->base.rotation); |
76eebda7 | 872 | |
1731693a | 873 | /* sanity check to make sure the src viewport wasn't enlarged */ |
ea2c67bb MR |
874 | WARN_ON(src->x1 < (int) state->base.src_x || |
875 | src->y1 < (int) state->base.src_y || | |
876 | src->x2 > (int) state->base.src_x + state->base.src_w || | |
877 | src->y2 > (int) state->base.src_y + state->base.src_h); | |
1731693a VS |
878 | |
879 | /* | |
880 | * Hardware doesn't handle subpixel coordinates. | |
881 | * Adjust to (macro)pixel boundary, but be careful not to | |
882 | * increase the source viewport size, because that could | |
883 | * push the downscaling factor out of bounds. | |
1731693a | 884 | */ |
96d61a7f GP |
885 | src_x = src->x1 >> 16; |
886 | src_w = drm_rect_width(src) >> 16; | |
887 | src_y = src->y1 >> 16; | |
888 | src_h = drm_rect_height(src) >> 16; | |
1731693a VS |
889 | |
890 | if (format_is_yuv(fb->pixel_format)) { | |
891 | src_x &= ~1; | |
892 | src_w &= ~1; | |
893 | ||
894 | /* | |
895 | * Must keep src and dst the | |
896 | * same if we can't scale. | |
897 | */ | |
225c228a | 898 | if (!can_scale) |
1731693a VS |
899 | crtc_w &= ~1; |
900 | ||
901 | if (crtc_w == 0) | |
96d61a7f | 902 | state->visible = false; |
1731693a VS |
903 | } |
904 | } | |
905 | ||
906 | /* Check size restrictions when scaling */ | |
96d61a7f | 907 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
1731693a | 908 | unsigned int width_bytes; |
ac484963 | 909 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
1731693a | 910 | |
225c228a | 911 | WARN_ON(!can_scale); |
1731693a VS |
912 | |
913 | /* FIXME interlacing min height is 6 */ | |
914 | ||
915 | if (crtc_w < 3 || crtc_h < 3) | |
96d61a7f | 916 | state->visible = false; |
1731693a VS |
917 | |
918 | if (src_w < 3 || src_h < 3) | |
96d61a7f | 919 | state->visible = false; |
1731693a | 920 | |
ac484963 | 921 | width_bytes = ((src_x * cpp) & 63) + src_w * cpp; |
1731693a | 922 | |
c331879c CK |
923 | if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || |
924 | width_bytes > 4096 || fb->pitches[0] > 4096)) { | |
1731693a VS |
925 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
926 | return -EINVAL; | |
927 | } | |
928 | } | |
929 | ||
96d61a7f | 930 | if (state->visible) { |
0a5ae1b0 CK |
931 | src->x1 = src_x << 16; |
932 | src->x2 = (src_x + src_w) << 16; | |
933 | src->y1 = src_y << 16; | |
934 | src->y2 = (src_y + src_h) << 16; | |
96d61a7f GP |
935 | } |
936 | ||
937 | dst->x1 = crtc_x; | |
938 | dst->x2 = crtc_x + crtc_w; | |
939 | dst->y1 = crtc_y; | |
940 | dst->y2 = crtc_y + crtc_h; | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
8ea30864 JB |
945 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
946 | struct drm_file *file_priv) | |
947 | { | |
948 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 | 949 | struct drm_plane *plane; |
818ed961 ML |
950 | struct drm_plane_state *plane_state; |
951 | struct drm_atomic_state *state; | |
952 | struct drm_modeset_acquire_ctx ctx; | |
8ea30864 JB |
953 | int ret = 0; |
954 | ||
8ea30864 JB |
955 | /* Make sure we don't try to enable both src & dest simultaneously */ |
956 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
957 | return -EINVAL; | |
958 | ||
666a4537 | 959 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
47ecbb20 VS |
960 | set->flags & I915_SET_COLORKEY_DESTINATION) |
961 | return -EINVAL; | |
962 | ||
7707e653 | 963 | plane = drm_plane_find(dev, set->plane_id); |
818ed961 ML |
964 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) |
965 | return -ENOENT; | |
8ea30864 | 966 | |
818ed961 | 967 | drm_modeset_acquire_init(&ctx, 0); |
6156a456 | 968 | |
818ed961 ML |
969 | state = drm_atomic_state_alloc(plane->dev); |
970 | if (!state) { | |
971 | ret = -ENOMEM; | |
972 | goto out; | |
6156a456 | 973 | } |
818ed961 ML |
974 | state->acquire_ctx = &ctx; |
975 | ||
976 | while (1) { | |
977 | plane_state = drm_atomic_get_plane_state(state, plane); | |
978 | ret = PTR_ERR_OR_ZERO(plane_state); | |
979 | if (!ret) { | |
980 | to_intel_plane_state(plane_state)->ckey = *set; | |
981 | ret = drm_atomic_commit(state); | |
982 | } | |
6156a456 | 983 | |
818ed961 ML |
984 | if (ret != -EDEADLK) |
985 | break; | |
8ea30864 | 986 | |
818ed961 ML |
987 | drm_atomic_state_clear(state); |
988 | drm_modeset_backoff(&ctx); | |
989 | } | |
8ea30864 | 990 | |
818ed961 ML |
991 | if (ret) |
992 | drm_atomic_state_free(state); | |
5e1bac2f | 993 | |
818ed961 ML |
994 | out: |
995 | drm_modeset_drop_locks(&ctx); | |
996 | drm_modeset_acquire_fini(&ctx); | |
997 | return ret; | |
5e1bac2f JB |
998 | } |
999 | ||
dada2d53 | 1000 | static const uint32_t ilk_plane_formats[] = { |
d1686ae3 CW |
1001 | DRM_FORMAT_XRGB8888, |
1002 | DRM_FORMAT_YUYV, | |
1003 | DRM_FORMAT_YVYU, | |
1004 | DRM_FORMAT_UYVY, | |
1005 | DRM_FORMAT_VYUY, | |
1006 | }; | |
1007 | ||
dada2d53 | 1008 | static const uint32_t snb_plane_formats[] = { |
b840d907 JB |
1009 | DRM_FORMAT_XBGR8888, |
1010 | DRM_FORMAT_XRGB8888, | |
1011 | DRM_FORMAT_YUYV, | |
1012 | DRM_FORMAT_YVYU, | |
1013 | DRM_FORMAT_UYVY, | |
1014 | DRM_FORMAT_VYUY, | |
1015 | }; | |
1016 | ||
dada2d53 | 1017 | static const uint32_t vlv_plane_formats[] = { |
7f1f3851 JB |
1018 | DRM_FORMAT_RGB565, |
1019 | DRM_FORMAT_ABGR8888, | |
1020 | DRM_FORMAT_ARGB8888, | |
1021 | DRM_FORMAT_XBGR8888, | |
1022 | DRM_FORMAT_XRGB8888, | |
1023 | DRM_FORMAT_XBGR2101010, | |
1024 | DRM_FORMAT_ABGR2101010, | |
1025 | DRM_FORMAT_YUYV, | |
1026 | DRM_FORMAT_YVYU, | |
1027 | DRM_FORMAT_UYVY, | |
1028 | DRM_FORMAT_VYUY, | |
1029 | }; | |
1030 | ||
dc2a41b4 DL |
1031 | static uint32_t skl_plane_formats[] = { |
1032 | DRM_FORMAT_RGB565, | |
1033 | DRM_FORMAT_ABGR8888, | |
1034 | DRM_FORMAT_ARGB8888, | |
1035 | DRM_FORMAT_XBGR8888, | |
1036 | DRM_FORMAT_XRGB8888, | |
1037 | DRM_FORMAT_YUYV, | |
1038 | DRM_FORMAT_YVYU, | |
1039 | DRM_FORMAT_UYVY, | |
1040 | DRM_FORMAT_VYUY, | |
1041 | }; | |
1042 | ||
b840d907 | 1043 | int |
7f1f3851 | 1044 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
b840d907 | 1045 | { |
fca0ce2a VS |
1046 | struct intel_plane *intel_plane = NULL; |
1047 | struct intel_plane_state *state = NULL; | |
b840d907 | 1048 | unsigned long possible_crtcs; |
d1686ae3 CW |
1049 | const uint32_t *plane_formats; |
1050 | int num_plane_formats; | |
b840d907 JB |
1051 | int ret; |
1052 | ||
d1686ae3 | 1053 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 1054 | return -ENODEV; |
b840d907 | 1055 | |
b14c5679 | 1056 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
fca0ce2a VS |
1057 | if (!intel_plane) { |
1058 | ret = -ENOMEM; | |
1059 | goto fail; | |
1060 | } | |
b840d907 | 1061 | |
8e7d688b MR |
1062 | state = intel_create_plane_state(&intel_plane->base); |
1063 | if (!state) { | |
fca0ce2a VS |
1064 | ret = -ENOMEM; |
1065 | goto fail; | |
ea2c67bb | 1066 | } |
8e7d688b | 1067 | intel_plane->base.state = &state->base; |
ea2c67bb | 1068 | |
d1686ae3 CW |
1069 | switch (INTEL_INFO(dev)->gen) { |
1070 | case 5: | |
1071 | case 6: | |
2d354c34 | 1072 | intel_plane->can_scale = true; |
b840d907 | 1073 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
1074 | intel_plane->update_plane = ilk_update_plane; |
1075 | intel_plane->disable_plane = ilk_disable_plane; | |
d1686ae3 CW |
1076 | |
1077 | if (IS_GEN6(dev)) { | |
1078 | plane_formats = snb_plane_formats; | |
1079 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1080 | } else { | |
1081 | plane_formats = ilk_plane_formats; | |
1082 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
1083 | } | |
1084 | break; | |
1085 | ||
1086 | case 7: | |
4e0bbc31 | 1087 | case 8: |
d49f7091 | 1088 | if (IS_IVYBRIDGE(dev)) { |
2d354c34 | 1089 | intel_plane->can_scale = true; |
d49f7091 DL |
1090 | intel_plane->max_downscale = 2; |
1091 | } else { | |
1092 | intel_plane->can_scale = false; | |
1093 | intel_plane->max_downscale = 1; | |
1094 | } | |
7f1f3851 | 1095 | |
666a4537 | 1096 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
7f1f3851 JB |
1097 | intel_plane->update_plane = vlv_update_plane; |
1098 | intel_plane->disable_plane = vlv_disable_plane; | |
7f1f3851 JB |
1099 | |
1100 | plane_formats = vlv_plane_formats; | |
1101 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); | |
1102 | } else { | |
7f1f3851 JB |
1103 | intel_plane->update_plane = ivb_update_plane; |
1104 | intel_plane->disable_plane = ivb_disable_plane; | |
7f1f3851 JB |
1105 | |
1106 | plane_formats = snb_plane_formats; | |
1107 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1108 | } | |
d1686ae3 | 1109 | break; |
dc2a41b4 | 1110 | case 9: |
c331879c | 1111 | intel_plane->can_scale = true; |
dc2a41b4 DL |
1112 | intel_plane->update_plane = skl_update_plane; |
1113 | intel_plane->disable_plane = skl_disable_plane; | |
549e2bfb | 1114 | state->scaler_id = -1; |
dc2a41b4 DL |
1115 | |
1116 | plane_formats = skl_plane_formats; | |
1117 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); | |
1118 | break; | |
d1686ae3 | 1119 | default: |
fca0ce2a VS |
1120 | MISSING_CASE(INTEL_INFO(dev)->gen); |
1121 | ret = -ENODEV; | |
1122 | goto fail; | |
b840d907 JB |
1123 | } |
1124 | ||
1125 | intel_plane->pipe = pipe; | |
7f1f3851 | 1126 | intel_plane->plane = plane; |
d1b9d039 | 1127 | intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); |
c59cb179 | 1128 | intel_plane->check_plane = intel_check_sprite_plane; |
fca0ce2a | 1129 | |
b840d907 | 1130 | possible_crtcs = (1 << pipe); |
fca0ce2a | 1131 | |
38573dc1 VS |
1132 | if (INTEL_INFO(dev)->gen >= 9) |
1133 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, | |
1134 | &intel_plane_funcs, | |
1135 | plane_formats, num_plane_formats, | |
1136 | DRM_PLANE_TYPE_OVERLAY, | |
1137 | "plane %d%c", plane + 2, pipe_name(pipe)); | |
1138 | else | |
1139 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, | |
1140 | &intel_plane_funcs, | |
1141 | plane_formats, num_plane_formats, | |
1142 | DRM_PLANE_TYPE_OVERLAY, | |
1143 | "sprite %c", sprite_name(pipe, plane)); | |
fca0ce2a VS |
1144 | if (ret) |
1145 | goto fail; | |
7ed6eeee | 1146 | |
3b7a5119 | 1147 | intel_create_rotation_property(dev, intel_plane); |
b840d907 | 1148 | |
ea2c67bb MR |
1149 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
1150 | ||
fca0ce2a VS |
1151 | return 0; |
1152 | ||
1153 | fail: | |
1154 | kfree(state); | |
1155 | kfree(intel_plane); | |
1156 | ||
b840d907 JB |
1157 | return ret; |
1158 | } |