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b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
32 | #include "drmP.h" | |
33 | #include "drm_crtc.h" | |
34 | #include "drm_fourcc.h" | |
35 | #include "intel_drv.h" | |
36 | #include "i915_drm.h" | |
37 | #include "i915_drv.h" | |
38 | ||
39 | static void | |
40 | ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |
41 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, | |
42 | unsigned int crtc_w, unsigned int crtc_h, | |
43 | uint32_t x, uint32_t y, | |
44 | uint32_t src_w, uint32_t src_h) | |
45 | { | |
46 | struct drm_device *dev = plane->dev; | |
47 | struct drm_i915_private *dev_priv = dev->dev_private; | |
48 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
49 | int pipe = intel_plane->pipe; | |
50 | u32 sprctl, sprscale = 0; | |
51 | int pixel_size; | |
52 | ||
53 | sprctl = I915_READ(SPRCTL(pipe)); | |
54 | ||
55 | /* Mask out pixel format bits in case we change it */ | |
56 | sprctl &= ~SPRITE_PIXFORMAT_MASK; | |
57 | sprctl &= ~SPRITE_RGB_ORDER_RGBX; | |
58 | sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; | |
59 | ||
60 | switch (fb->pixel_format) { | |
61 | case DRM_FORMAT_XBGR8888: | |
62 | sprctl |= SPRITE_FORMAT_RGBX888; | |
63 | pixel_size = 4; | |
64 | break; | |
65 | case DRM_FORMAT_XRGB8888: | |
66 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; | |
67 | pixel_size = 4; | |
68 | break; | |
69 | case DRM_FORMAT_YUYV: | |
70 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
71 | pixel_size = 2; | |
72 | break; | |
73 | case DRM_FORMAT_YVYU: | |
74 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
75 | pixel_size = 2; | |
76 | break; | |
77 | case DRM_FORMAT_UYVY: | |
78 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
79 | pixel_size = 2; | |
80 | break; | |
81 | case DRM_FORMAT_VYUY: | |
82 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
83 | pixel_size = 2; | |
84 | break; | |
85 | default: | |
86 | DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n"); | |
87 | sprctl |= DVS_FORMAT_RGBX888; | |
88 | pixel_size = 4; | |
89 | break; | |
90 | } | |
91 | ||
92 | if (obj->tiling_mode != I915_TILING_NONE) | |
93 | sprctl |= SPRITE_TILED; | |
94 | ||
95 | /* must disable */ | |
96 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
97 | sprctl |= SPRITE_ENABLE; | |
98 | ||
99 | /* Sizes are 0 based */ | |
100 | src_w--; | |
101 | src_h--; | |
102 | crtc_w--; | |
103 | crtc_h--; | |
104 | ||
105 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); | |
106 | ||
107 | /* | |
108 | * IVB workaround: must disable low power watermarks for at least | |
109 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
110 | * when scaling is disabled. | |
111 | */ | |
112 | if (crtc_w != src_w || crtc_h != src_h) { | |
828ed3e1 CW |
113 | if (!dev_priv->sprite_scaling_enabled) { |
114 | dev_priv->sprite_scaling_enabled = true; | |
115 | intel_update_watermarks(dev); | |
116 | intel_wait_for_vblank(dev, pipe); | |
117 | } | |
b840d907 JB |
118 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
119 | } else { | |
828ed3e1 CW |
120 | if (dev_priv->sprite_scaling_enabled) { |
121 | dev_priv->sprite_scaling_enabled = false; | |
122 | /* potentially re-enable LP watermarks */ | |
123 | intel_update_watermarks(dev); | |
124 | } | |
b840d907 JB |
125 | } |
126 | ||
127 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); | |
128 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
129 | if (obj->tiling_mode != I915_TILING_NONE) { | |
130 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); | |
131 | } else { | |
132 | unsigned long offset; | |
133 | ||
134 | offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); | |
135 | I915_WRITE(SPRLINOFF(pipe), offset); | |
136 | } | |
137 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); | |
138 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
139 | I915_WRITE(SPRCTL(pipe), sprctl); | |
446f2545 | 140 | I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset); |
b840d907 JB |
141 | POSTING_READ(SPRSURF(pipe)); |
142 | } | |
143 | ||
144 | static void | |
145 | ivb_disable_plane(struct drm_plane *plane) | |
146 | { | |
147 | struct drm_device *dev = plane->dev; | |
148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
149 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
150 | int pipe = intel_plane->pipe; | |
151 | ||
152 | I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); | |
153 | /* Can't leave the scaler enabled... */ | |
154 | I915_WRITE(SPRSCALE(pipe), 0); | |
155 | /* Activate double buffered register update */ | |
446f2545 | 156 | I915_MODIFY_DISPBASE(SPRSURF(pipe), 0); |
b840d907 | 157 | POSTING_READ(SPRSURF(pipe)); |
828ed3e1 CW |
158 | |
159 | dev_priv->sprite_scaling_enabled = false; | |
160 | intel_update_watermarks(dev); | |
b840d907 JB |
161 | } |
162 | ||
8ea30864 JB |
163 | static int |
164 | ivb_update_colorkey(struct drm_plane *plane, | |
165 | struct drm_intel_sprite_colorkey *key) | |
166 | { | |
167 | struct drm_device *dev = plane->dev; | |
168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
169 | struct intel_plane *intel_plane; | |
170 | u32 sprctl; | |
171 | int ret = 0; | |
172 | ||
173 | intel_plane = to_intel_plane(plane); | |
174 | ||
175 | I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value); | |
176 | I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value); | |
177 | I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask); | |
178 | ||
179 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
180 | sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY); | |
181 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
182 | sprctl |= SPRITE_DEST_KEY; | |
183 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
184 | sprctl |= SPRITE_SOURCE_KEY; | |
185 | I915_WRITE(SPRCTL(intel_plane->pipe), sprctl); | |
186 | ||
187 | POSTING_READ(SPRKEYMSK(intel_plane->pipe)); | |
188 | ||
189 | return ret; | |
190 | } | |
191 | ||
192 | static void | |
193 | ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) | |
194 | { | |
195 | struct drm_device *dev = plane->dev; | |
196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
197 | struct intel_plane *intel_plane; | |
198 | u32 sprctl; | |
199 | ||
200 | intel_plane = to_intel_plane(plane); | |
201 | ||
202 | key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe)); | |
203 | key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe)); | |
204 | key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe)); | |
205 | key->flags = 0; | |
206 | ||
207 | sprctl = I915_READ(SPRCTL(intel_plane->pipe)); | |
208 | ||
209 | if (sprctl & SPRITE_DEST_KEY) | |
210 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
211 | else if (sprctl & SPRITE_SOURCE_KEY) | |
212 | key->flags = I915_SET_COLORKEY_SOURCE; | |
213 | else | |
214 | key->flags = I915_SET_COLORKEY_NONE; | |
215 | } | |
216 | ||
b840d907 | 217 | static void |
d1686ae3 | 218 | ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, |
b840d907 JB |
219 | struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, |
220 | unsigned int crtc_w, unsigned int crtc_h, | |
221 | uint32_t x, uint32_t y, | |
222 | uint32_t src_w, uint32_t src_h) | |
223 | { | |
224 | struct drm_device *dev = plane->dev; | |
225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
226 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
227 | int pipe = intel_plane->pipe, pixel_size; | |
8aaa81a1 | 228 | u32 dvscntr, dvsscale; |
b840d907 JB |
229 | |
230 | dvscntr = I915_READ(DVSCNTR(pipe)); | |
231 | ||
232 | /* Mask out pixel format bits in case we change it */ | |
233 | dvscntr &= ~DVS_PIXFORMAT_MASK; | |
ab2f9df1 | 234 | dvscntr &= ~DVS_RGB_ORDER_XBGR; |
b840d907 JB |
235 | dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; |
236 | ||
237 | switch (fb->pixel_format) { | |
238 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 239 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
240 | pixel_size = 4; |
241 | break; | |
242 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 243 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
244 | pixel_size = 4; |
245 | break; | |
246 | case DRM_FORMAT_YUYV: | |
247 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
248 | pixel_size = 2; | |
249 | break; | |
250 | case DRM_FORMAT_YVYU: | |
251 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
252 | pixel_size = 2; | |
253 | break; | |
254 | case DRM_FORMAT_UYVY: | |
255 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
256 | pixel_size = 2; | |
257 | break; | |
258 | case DRM_FORMAT_VYUY: | |
259 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
260 | pixel_size = 2; | |
261 | break; | |
262 | default: | |
263 | DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n"); | |
264 | dvscntr |= DVS_FORMAT_RGBX888; | |
265 | pixel_size = 4; | |
266 | break; | |
267 | } | |
268 | ||
269 | if (obj->tiling_mode != I915_TILING_NONE) | |
270 | dvscntr |= DVS_TILED; | |
271 | ||
d1686ae3 CW |
272 | if (IS_GEN6(dev)) |
273 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
274 | dvscntr |= DVS_ENABLE; |
275 | ||
276 | /* Sizes are 0 based */ | |
277 | src_w--; | |
278 | src_h--; | |
279 | crtc_w--; | |
280 | crtc_h--; | |
281 | ||
282 | intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size); | |
283 | ||
8aaa81a1 CW |
284 | dvsscale = 0; |
285 | if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h) | |
b840d907 JB |
286 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
287 | ||
288 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); | |
289 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
290 | if (obj->tiling_mode != I915_TILING_NONE) { | |
291 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); | |
292 | } else { | |
293 | unsigned long offset; | |
294 | ||
295 | offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); | |
296 | I915_WRITE(DVSLINOFF(pipe), offset); | |
297 | } | |
298 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); | |
299 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
300 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
446f2545 | 301 | I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset); |
b840d907 JB |
302 | POSTING_READ(DVSSURF(pipe)); |
303 | } | |
304 | ||
305 | static void | |
d1686ae3 | 306 | ilk_disable_plane(struct drm_plane *plane) |
b840d907 JB |
307 | { |
308 | struct drm_device *dev = plane->dev; | |
309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
310 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
311 | int pipe = intel_plane->pipe; | |
312 | ||
313 | I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE); | |
314 | /* Disable the scaler */ | |
315 | I915_WRITE(DVSSCALE(pipe), 0); | |
316 | /* Flush double buffered register updates */ | |
446f2545 | 317 | I915_MODIFY_DISPBASE(DVSSURF(pipe), 0); |
b840d907 JB |
318 | POSTING_READ(DVSSURF(pipe)); |
319 | } | |
320 | ||
175bd420 JB |
321 | static void |
322 | intel_enable_primary(struct drm_crtc *crtc) | |
323 | { | |
324 | struct drm_device *dev = crtc->dev; | |
325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
326 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
327 | int reg = DSPCNTR(intel_crtc->plane); | |
328 | ||
93314b5b CW |
329 | if (!intel_crtc->primary_disabled) |
330 | return; | |
331 | ||
332 | intel_crtc->primary_disabled = false; | |
333 | intel_update_fbc(dev); | |
334 | ||
175bd420 JB |
335 | I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); |
336 | } | |
337 | ||
338 | static void | |
339 | intel_disable_primary(struct drm_crtc *crtc) | |
340 | { | |
341 | struct drm_device *dev = crtc->dev; | |
342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
343 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
344 | int reg = DSPCNTR(intel_crtc->plane); | |
345 | ||
93314b5b CW |
346 | if (intel_crtc->primary_disabled) |
347 | return; | |
348 | ||
175bd420 | 349 | I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); |
93314b5b CW |
350 | |
351 | intel_crtc->primary_disabled = true; | |
352 | intel_update_fbc(dev); | |
175bd420 JB |
353 | } |
354 | ||
8ea30864 | 355 | static int |
d1686ae3 | 356 | ilk_update_colorkey(struct drm_plane *plane, |
8ea30864 JB |
357 | struct drm_intel_sprite_colorkey *key) |
358 | { | |
359 | struct drm_device *dev = plane->dev; | |
360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
361 | struct intel_plane *intel_plane; | |
362 | u32 dvscntr; | |
363 | int ret = 0; | |
364 | ||
365 | intel_plane = to_intel_plane(plane); | |
366 | ||
367 | I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value); | |
368 | I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value); | |
369 | I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask); | |
370 | ||
371 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
372 | dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY); | |
373 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
374 | dvscntr |= DVS_DEST_KEY; | |
375 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
376 | dvscntr |= DVS_SOURCE_KEY; | |
377 | I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr); | |
378 | ||
379 | POSTING_READ(DVSKEYMSK(intel_plane->pipe)); | |
380 | ||
381 | return ret; | |
382 | } | |
383 | ||
384 | static void | |
d1686ae3 | 385 | ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key) |
8ea30864 JB |
386 | { |
387 | struct drm_device *dev = plane->dev; | |
388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
389 | struct intel_plane *intel_plane; | |
390 | u32 dvscntr; | |
391 | ||
392 | intel_plane = to_intel_plane(plane); | |
393 | ||
394 | key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe)); | |
395 | key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe)); | |
396 | key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe)); | |
397 | key->flags = 0; | |
398 | ||
399 | dvscntr = I915_READ(DVSCNTR(intel_plane->pipe)); | |
400 | ||
401 | if (dvscntr & DVS_DEST_KEY) | |
402 | key->flags = I915_SET_COLORKEY_DESTINATION; | |
403 | else if (dvscntr & DVS_SOURCE_KEY) | |
404 | key->flags = I915_SET_COLORKEY_SOURCE; | |
405 | else | |
406 | key->flags = I915_SET_COLORKEY_NONE; | |
407 | } | |
408 | ||
b840d907 JB |
409 | static int |
410 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
411 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
412 | unsigned int crtc_w, unsigned int crtc_h, | |
413 | uint32_t src_x, uint32_t src_y, | |
414 | uint32_t src_w, uint32_t src_h) | |
415 | { | |
416 | struct drm_device *dev = plane->dev; | |
417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
418 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
419 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
420 | struct intel_framebuffer *intel_fb; | |
421 | struct drm_i915_gem_object *obj, *old_obj; | |
422 | int pipe = intel_plane->pipe; | |
423 | int ret = 0; | |
424 | int x = src_x >> 16, y = src_y >> 16; | |
425 | int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay; | |
426 | bool disable_primary = false; | |
427 | ||
428 | intel_fb = to_intel_framebuffer(fb); | |
429 | obj = intel_fb->obj; | |
430 | ||
431 | old_obj = intel_plane->obj; | |
432 | ||
b4db1e35 JB |
433 | src_w = src_w >> 16; |
434 | src_h = src_h >> 16; | |
435 | ||
b840d907 JB |
436 | /* Pipe must be running... */ |
437 | if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE)) | |
438 | return -EINVAL; | |
439 | ||
440 | if (crtc_x >= primary_w || crtc_y >= primary_h) | |
441 | return -EINVAL; | |
442 | ||
443 | /* Don't modify another pipe's plane */ | |
444 | if (intel_plane->pipe != intel_crtc->pipe) | |
445 | return -EINVAL; | |
446 | ||
447 | /* | |
448 | * Clamp the width & height into the visible area. Note we don't | |
449 | * try to scale the source if part of the visible region is offscreen. | |
450 | * The caller must handle that by adjusting source offset and size. | |
451 | */ | |
452 | if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) { | |
453 | crtc_w += crtc_x; | |
454 | crtc_x = 0; | |
455 | } | |
456 | if ((crtc_x + crtc_w) <= 0) /* Nothing to display */ | |
457 | goto out; | |
458 | if ((crtc_x + crtc_w) > primary_w) | |
459 | crtc_w = primary_w - crtc_x; | |
460 | ||
461 | if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) { | |
462 | crtc_h += crtc_y; | |
463 | crtc_y = 0; | |
464 | } | |
465 | if ((crtc_y + crtc_h) <= 0) /* Nothing to display */ | |
466 | goto out; | |
467 | if (crtc_y + crtc_h > primary_h) | |
468 | crtc_h = primary_h - crtc_y; | |
469 | ||
470 | if (!crtc_w || !crtc_h) /* Again, nothing to display */ | |
471 | goto out; | |
472 | ||
473 | /* | |
474 | * We can take a larger source and scale it down, but | |
475 | * only so much... 16x is the max on SNB. | |
476 | */ | |
477 | if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale) | |
478 | return -EINVAL; | |
479 | ||
480 | /* | |
481 | * If the sprite is completely covering the primary plane, | |
482 | * we can disable the primary and save power. | |
483 | */ | |
484 | if ((crtc_x == 0) && (crtc_y == 0) && | |
485 | (crtc_w == primary_w) && (crtc_h == primary_h)) | |
486 | disable_primary = true; | |
487 | ||
488 | mutex_lock(&dev->struct_mutex); | |
489 | ||
490 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); | |
00c2064b | 491 | if (ret) |
b840d907 | 492 | goto out_unlock; |
b840d907 JB |
493 | |
494 | intel_plane->obj = obj; | |
495 | ||
175bd420 JB |
496 | /* |
497 | * Be sure to re-enable the primary before the sprite is no longer | |
498 | * covering it fully. | |
499 | */ | |
93314b5b | 500 | if (!disable_primary) |
175bd420 | 501 | intel_enable_primary(crtc); |
175bd420 | 502 | |
b840d907 JB |
503 | intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y, |
504 | crtc_w, crtc_h, x, y, src_w, src_h); | |
505 | ||
93314b5b | 506 | if (disable_primary) |
175bd420 | 507 | intel_disable_primary(crtc); |
175bd420 | 508 | |
b840d907 JB |
509 | /* Unpin old obj after new one is active to avoid ugliness */ |
510 | if (old_obj) { | |
511 | /* | |
512 | * It's fairly common to simply update the position of | |
513 | * an existing object. In that case, we don't need to | |
514 | * wait for vblank to avoid ugliness, we only need to | |
515 | * do the pin & ref bookkeeping. | |
516 | */ | |
517 | if (old_obj != obj) { | |
518 | mutex_unlock(&dev->struct_mutex); | |
519 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
520 | mutex_lock(&dev->struct_mutex); | |
521 | } | |
1690e1eb | 522 | intel_unpin_fb_obj(old_obj); |
b840d907 JB |
523 | } |
524 | ||
525 | out_unlock: | |
526 | mutex_unlock(&dev->struct_mutex); | |
527 | out: | |
528 | return ret; | |
529 | } | |
530 | ||
531 | static int | |
532 | intel_disable_plane(struct drm_plane *plane) | |
533 | { | |
534 | struct drm_device *dev = plane->dev; | |
535 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
536 | int ret = 0; | |
537 | ||
93314b5b | 538 | if (plane->crtc) |
175bd420 | 539 | intel_enable_primary(plane->crtc); |
b840d907 JB |
540 | intel_plane->disable_plane(plane); |
541 | ||
542 | if (!intel_plane->obj) | |
543 | goto out; | |
544 | ||
545 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 546 | intel_unpin_fb_obj(intel_plane->obj); |
b840d907 JB |
547 | intel_plane->obj = NULL; |
548 | mutex_unlock(&dev->struct_mutex); | |
549 | out: | |
550 | ||
551 | return ret; | |
552 | } | |
553 | ||
554 | static void intel_destroy_plane(struct drm_plane *plane) | |
555 | { | |
556 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
557 | intel_disable_plane(plane); | |
558 | drm_plane_cleanup(plane); | |
559 | kfree(intel_plane); | |
560 | } | |
561 | ||
8ea30864 JB |
562 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
563 | struct drm_file *file_priv) | |
564 | { | |
565 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 JB |
566 | struct drm_mode_object *obj; |
567 | struct drm_plane *plane; | |
568 | struct intel_plane *intel_plane; | |
569 | int ret = 0; | |
570 | ||
1cff8f6b DV |
571 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
572 | return -ENODEV; | |
8ea30864 JB |
573 | |
574 | /* Make sure we don't try to enable both src & dest simultaneously */ | |
575 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
576 | return -EINVAL; | |
577 | ||
578 | mutex_lock(&dev->mode_config.mutex); | |
579 | ||
580 | obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE); | |
581 | if (!obj) { | |
582 | ret = -EINVAL; | |
583 | goto out_unlock; | |
584 | } | |
585 | ||
586 | plane = obj_to_plane(obj); | |
587 | intel_plane = to_intel_plane(plane); | |
588 | ret = intel_plane->update_colorkey(plane, set); | |
589 | ||
590 | out_unlock: | |
591 | mutex_unlock(&dev->mode_config.mutex); | |
592 | return ret; | |
593 | } | |
594 | ||
595 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
596 | struct drm_file *file_priv) | |
597 | { | |
598 | struct drm_intel_sprite_colorkey *get = data; | |
8ea30864 JB |
599 | struct drm_mode_object *obj; |
600 | struct drm_plane *plane; | |
601 | struct intel_plane *intel_plane; | |
602 | int ret = 0; | |
603 | ||
1cff8f6b DV |
604 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
605 | return -ENODEV; | |
8ea30864 JB |
606 | |
607 | mutex_lock(&dev->mode_config.mutex); | |
608 | ||
609 | obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE); | |
610 | if (!obj) { | |
611 | ret = -EINVAL; | |
612 | goto out_unlock; | |
613 | } | |
614 | ||
615 | plane = obj_to_plane(obj); | |
616 | intel_plane = to_intel_plane(plane); | |
617 | intel_plane->get_colorkey(plane, get); | |
618 | ||
619 | out_unlock: | |
620 | mutex_unlock(&dev->mode_config.mutex); | |
621 | return ret; | |
622 | } | |
623 | ||
b840d907 JB |
624 | static const struct drm_plane_funcs intel_plane_funcs = { |
625 | .update_plane = intel_update_plane, | |
626 | .disable_plane = intel_disable_plane, | |
627 | .destroy = intel_destroy_plane, | |
628 | }; | |
629 | ||
d1686ae3 CW |
630 | static uint32_t ilk_plane_formats[] = { |
631 | DRM_FORMAT_XRGB8888, | |
632 | DRM_FORMAT_YUYV, | |
633 | DRM_FORMAT_YVYU, | |
634 | DRM_FORMAT_UYVY, | |
635 | DRM_FORMAT_VYUY, | |
636 | }; | |
637 | ||
b840d907 JB |
638 | static uint32_t snb_plane_formats[] = { |
639 | DRM_FORMAT_XBGR8888, | |
640 | DRM_FORMAT_XRGB8888, | |
641 | DRM_FORMAT_YUYV, | |
642 | DRM_FORMAT_YVYU, | |
643 | DRM_FORMAT_UYVY, | |
644 | DRM_FORMAT_VYUY, | |
645 | }; | |
646 | ||
647 | int | |
648 | intel_plane_init(struct drm_device *dev, enum pipe pipe) | |
649 | { | |
650 | struct intel_plane *intel_plane; | |
651 | unsigned long possible_crtcs; | |
d1686ae3 CW |
652 | const uint32_t *plane_formats; |
653 | int num_plane_formats; | |
b840d907 JB |
654 | int ret; |
655 | ||
d1686ae3 | 656 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 657 | return -ENODEV; |
b840d907 JB |
658 | |
659 | intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL); | |
660 | if (!intel_plane) | |
661 | return -ENOMEM; | |
662 | ||
d1686ae3 CW |
663 | switch (INTEL_INFO(dev)->gen) { |
664 | case 5: | |
665 | case 6: | |
b840d907 | 666 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
667 | intel_plane->update_plane = ilk_update_plane; |
668 | intel_plane->disable_plane = ilk_disable_plane; | |
669 | intel_plane->update_colorkey = ilk_update_colorkey; | |
670 | intel_plane->get_colorkey = ilk_get_colorkey; | |
671 | ||
672 | if (IS_GEN6(dev)) { | |
673 | plane_formats = snb_plane_formats; | |
674 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
675 | } else { | |
676 | plane_formats = ilk_plane_formats; | |
677 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
678 | } | |
679 | break; | |
680 | ||
681 | case 7: | |
b840d907 JB |
682 | intel_plane->max_downscale = 2; |
683 | intel_plane->update_plane = ivb_update_plane; | |
684 | intel_plane->disable_plane = ivb_disable_plane; | |
8ea30864 JB |
685 | intel_plane->update_colorkey = ivb_update_colorkey; |
686 | intel_plane->get_colorkey = ivb_get_colorkey; | |
d1686ae3 CW |
687 | |
688 | plane_formats = snb_plane_formats; | |
689 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
690 | break; | |
691 | ||
692 | default: | |
693 | return -ENODEV; | |
b840d907 JB |
694 | } |
695 | ||
696 | intel_plane->pipe = pipe; | |
697 | possible_crtcs = (1 << pipe); | |
698 | ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs, | |
d1686ae3 CW |
699 | &intel_plane_funcs, |
700 | plane_formats, num_plane_formats, | |
701 | false); | |
b840d907 JB |
702 | if (ret) |
703 | kfree(intel_plane); | |
704 | ||
705 | return ret; | |
706 | } | |
707 |