Commit | Line | Data |
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b840d907 JB |
1 | /* |
2 | * Copyright © 2011 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Jesse Barnes <jbarnes@virtuousgeek.org> | |
25 | * | |
26 | * New plane/sprite handling. | |
27 | * | |
28 | * The older chips had a separate interface for programming plane related | |
29 | * registers; newer ones are much simpler and we can use the new DRM plane | |
30 | * support. | |
31 | */ | |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_fourcc.h> | |
1731693a | 35 | #include <drm/drm_rect.h> |
c331879c | 36 | #include <drm/drm_atomic.h> |
ea2c67bb | 37 | #include <drm/drm_plane_helper.h> |
b840d907 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
b840d907 JB |
40 | #include "i915_drv.h" |
41 | ||
6ca2aeb2 VS |
42 | static bool |
43 | format_is_yuv(uint32_t format) | |
44 | { | |
45 | switch (format) { | |
46 | case DRM_FORMAT_YUYV: | |
47 | case DRM_FORMAT_UYVY: | |
48 | case DRM_FORMAT_VYUY: | |
49 | case DRM_FORMAT_YVYU: | |
50 | return true; | |
51 | default: | |
52 | return false; | |
53 | } | |
54 | } | |
55 | ||
5e7234c9 VS |
56 | static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, |
57 | int usecs) | |
8d7849db VS |
58 | { |
59 | /* paranoia */ | |
5e7234c9 | 60 | if (!adjusted_mode->crtc_htotal) |
8d7849db VS |
61 | return 1; |
62 | ||
5e7234c9 VS |
63 | return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, |
64 | 1000 * adjusted_mode->crtc_htotal); | |
8d7849db VS |
65 | } |
66 | ||
26ff2762 ACO |
67 | /** |
68 | * intel_pipe_update_start() - start update of a set of display registers | |
69 | * @crtc: the crtc of which the registers are going to be updated | |
70 | * @start_vbl_count: vblank counter return pointer used for error checking | |
71 | * | |
72 | * Mark the start of an update to pipe registers that should be updated | |
73 | * atomically regarding vblank. If the next vblank will happens within | |
74 | * the next 100 us, this function waits until the vblank passes. | |
75 | * | |
76 | * After a successful call to this function, interrupts will be disabled | |
77 | * until a subsequent call to intel_pipe_update_end(). That is done to | |
78 | * avoid random delays. The value written to @start_vbl_count should be | |
79 | * supplied to intel_pipe_update_end() for error checking. | |
26ff2762 | 80 | */ |
34e0adbb | 81 | void intel_pipe_update_start(struct intel_crtc *crtc) |
8d7849db VS |
82 | { |
83 | struct drm_device *dev = crtc->base.dev; | |
124abe07 | 84 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
8d7849db VS |
85 | enum pipe pipe = crtc->pipe; |
86 | long timeout = msecs_to_jiffies_timeout(1); | |
87 | int scanline, min, max, vblank_start; | |
210871b6 | 88 | wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); |
8d7849db VS |
89 | DEFINE_WAIT(wait); |
90 | ||
124abe07 VS |
91 | vblank_start = adjusted_mode->crtc_vblank_start; |
92 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
8d7849db VS |
93 | vblank_start = DIV_ROUND_UP(vblank_start, 2); |
94 | ||
95 | /* FIXME needs to be calibrated sensibly */ | |
124abe07 | 96 | min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); |
8d7849db VS |
97 | max = vblank_start - 1; |
98 | ||
8f539a83 | 99 | local_irq_disable(); |
8f539a83 | 100 | |
8d7849db | 101 | if (min <= 0 || max <= 0) |
8f539a83 | 102 | return; |
8d7849db | 103 | |
1e3feefd | 104 | if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) |
8f539a83 | 105 | return; |
8d7849db | 106 | |
d637ce3f JB |
107 | crtc->debug.min_vbl = min; |
108 | crtc->debug.max_vbl = max; | |
109 | trace_i915_pipe_update_start(crtc); | |
25ef284a | 110 | |
8d7849db VS |
111 | for (;;) { |
112 | /* | |
113 | * prepare_to_wait() has a memory barrier, which guarantees | |
114 | * other CPUs can see the task state update by the time we | |
115 | * read the scanline. | |
116 | */ | |
210871b6 | 117 | prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); |
8d7849db VS |
118 | |
119 | scanline = intel_get_crtc_scanline(crtc); | |
120 | if (scanline < min || scanline > max) | |
121 | break; | |
122 | ||
123 | if (timeout <= 0) { | |
124 | DRM_ERROR("Potential atomic update failure on pipe %c\n", | |
125 | pipe_name(crtc->pipe)); | |
126 | break; | |
127 | } | |
128 | ||
129 | local_irq_enable(); | |
130 | ||
131 | timeout = schedule_timeout(timeout); | |
132 | ||
133 | local_irq_disable(); | |
134 | } | |
135 | ||
210871b6 | 136 | finish_wait(wq, &wait); |
8d7849db | 137 | |
1e3feefd | 138 | drm_crtc_vblank_put(&crtc->base); |
8d7849db | 139 | |
eb120ef6 JB |
140 | crtc->debug.scanline_start = scanline; |
141 | crtc->debug.start_vbl_time = ktime_get(); | |
142 | crtc->debug.start_vbl_count = | |
143 | dev->driver->get_vblank_counter(dev, pipe); | |
8d7849db | 144 | |
d637ce3f | 145 | trace_i915_pipe_update_vblank_evaded(crtc); |
8d7849db VS |
146 | } |
147 | ||
26ff2762 ACO |
148 | /** |
149 | * intel_pipe_update_end() - end update of a set of display registers | |
150 | * @crtc: the crtc of which the registers were updated | |
151 | * @start_vbl_count: start vblank counter (used for error checking) | |
152 | * | |
153 | * Mark the end of an update started with intel_pipe_update_start(). This | |
154 | * re-enables interrupts and verifies the update was actually completed | |
155 | * before a vblank using the value of @start_vbl_count. | |
156 | */ | |
34e0adbb | 157 | void intel_pipe_update_end(struct intel_crtc *crtc) |
8d7849db VS |
158 | { |
159 | struct drm_device *dev = crtc->base.dev; | |
160 | enum pipe pipe = crtc->pipe; | |
eb120ef6 | 161 | int scanline_end = intel_get_crtc_scanline(crtc); |
8d7849db | 162 | u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); |
85a62bf9 | 163 | ktime_t end_vbl_time = ktime_get(); |
8d7849db | 164 | |
d637ce3f | 165 | trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); |
25ef284a | 166 | |
8d7849db VS |
167 | local_irq_enable(); |
168 | ||
eb120ef6 JB |
169 | if (crtc->debug.start_vbl_count && |
170 | crtc->debug.start_vbl_count != end_vbl_count) { | |
171 | DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", | |
172 | pipe_name(pipe), crtc->debug.start_vbl_count, | |
173 | end_vbl_count, | |
174 | ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), | |
175 | crtc->debug.min_vbl, crtc->debug.max_vbl, | |
176 | crtc->debug.scanline_start, scanline_end); | |
177 | } | |
8d7849db VS |
178 | } |
179 | ||
dc2a41b4 | 180 | static void |
2fde1391 ML |
181 | skl_update_plane(struct drm_plane *drm_plane, |
182 | const struct intel_crtc_state *crtc_state, | |
183 | const struct intel_plane_state *plane_state) | |
dc2a41b4 DL |
184 | { |
185 | struct drm_device *dev = drm_plane->dev; | |
186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
187 | struct intel_plane *intel_plane = to_intel_plane(drm_plane); | |
2fde1391 | 188 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 189 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
dc2a41b4 DL |
190 | const int pipe = intel_plane->pipe; |
191 | const int plane = intel_plane->plane + 1; | |
3b7a5119 | 192 | u32 plane_ctl, stride_div, stride; |
2fde1391 | 193 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
44eb0cb9 | 194 | u32 surf_addr; |
3b7a5119 SJ |
195 | u32 tile_height, plane_offset, plane_size; |
196 | unsigned int rotation; | |
197 | int x_offset, y_offset; | |
2fde1391 ML |
198 | int crtc_x = plane_state->dst.x1; |
199 | int crtc_y = plane_state->dst.y1; | |
200 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
201 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
202 | uint32_t x = plane_state->src.x1 >> 16; | |
203 | uint32_t y = plane_state->src.y1 >> 16; | |
204 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
205 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
206 | const struct intel_scaler *scaler = | |
207 | &crtc_state->scaler_state.scalers[plane_state->scaler_id]; | |
dc2a41b4 | 208 | |
48fe4691 | 209 | plane_ctl = PLANE_CTL_ENABLE | |
e12c8ce8 | 210 | PLANE_CTL_PIPE_GAMMA_ENABLE | |
48fe4691 | 211 | PLANE_CTL_PIPE_CSC_ENABLE; |
dc2a41b4 | 212 | |
c331879c CK |
213 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); |
214 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
b321803d | 215 | |
2fde1391 | 216 | rotation = plane_state->base.rotation; |
c331879c | 217 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
dc2a41b4 | 218 | |
b321803d DL |
219 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], |
220 | fb->pixel_format); | |
221 | ||
dc2a41b4 DL |
222 | /* Sizes are 0 based */ |
223 | src_w--; | |
224 | src_h--; | |
225 | crtc_w--; | |
226 | crtc_h--; | |
227 | ||
47ecbb20 VS |
228 | if (key->flags) { |
229 | I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); | |
230 | I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); | |
231 | I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); | |
232 | } | |
233 | ||
234 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
235 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
236 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
237 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
238 | ||
dedf278c | 239 | surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); |
121920fa | 240 | |
3b7a5119 SJ |
241 | if (intel_rotation_90_or_270(rotation)) { |
242 | /* stride: Surface height in tiles */ | |
2614f17d | 243 | tile_height = intel_tile_height(dev, fb->pixel_format, |
fe47ea0c | 244 | fb->modifier[0], 0); |
3b7a5119 SJ |
245 | stride = DIV_ROUND_UP(fb->height, tile_height); |
246 | plane_size = (src_w << 16) | src_h; | |
247 | x_offset = stride * tile_height - y - (src_h + 1); | |
248 | y_offset = x; | |
249 | } else { | |
250 | stride = fb->pitches[0] / stride_div; | |
251 | plane_size = (src_h << 16) | src_w; | |
252 | x_offset = x; | |
253 | y_offset = y; | |
254 | } | |
255 | plane_offset = y_offset << 16 | x_offset; | |
256 | ||
257 | I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); | |
258 | I915_WRITE(PLANE_STRIDE(pipe, plane), stride); | |
3b7a5119 | 259 | I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); |
c331879c CK |
260 | |
261 | /* program plane scaler */ | |
2fde1391 | 262 | if (plane_state->scaler_id >= 0) { |
c331879c | 263 | uint32_t ps_ctrl = 0; |
2fde1391 | 264 | int scaler_id = plane_state->scaler_id; |
c331879c CK |
265 | |
266 | DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, | |
267 | PS_PLANE_SEL(plane)); | |
2fde1391 | 268 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode; |
c331879c CK |
269 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
270 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
271 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); | |
272 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), | |
273 | ((crtc_w + 1) << 16)|(crtc_h + 1)); | |
274 | ||
275 | I915_WRITE(PLANE_POS(pipe, plane), 0); | |
276 | } else { | |
277 | I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); | |
278 | } | |
279 | ||
dc2a41b4 | 280 | I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); |
121920fa | 281 | I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); |
dc2a41b4 DL |
282 | POSTING_READ(PLANE_SURF(pipe, plane)); |
283 | } | |
284 | ||
285 | static void | |
7fabf5ef | 286 | skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
dc2a41b4 | 287 | { |
a8ad0d8e | 288 | struct drm_device *dev = dplane->dev; |
dc2a41b4 | 289 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8ad0d8e | 290 | struct intel_plane *intel_plane = to_intel_plane(dplane); |
dc2a41b4 DL |
291 | const int pipe = intel_plane->pipe; |
292 | const int plane = intel_plane->plane + 1; | |
293 | ||
48fe4691 | 294 | I915_WRITE(PLANE_CTL(pipe, plane), 0); |
dc2a41b4 | 295 | |
2ddc1dad VS |
296 | I915_WRITE(PLANE_SURF(pipe, plane), 0); |
297 | POSTING_READ(PLANE_SURF(pipe, plane)); | |
dc2a41b4 DL |
298 | } |
299 | ||
6ca2aeb2 VS |
300 | static void |
301 | chv_update_csc(struct intel_plane *intel_plane, uint32_t format) | |
302 | { | |
303 | struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; | |
304 | int plane = intel_plane->plane; | |
305 | ||
306 | /* Seems RGB data bypasses the CSC always */ | |
307 | if (!format_is_yuv(format)) | |
308 | return; | |
309 | ||
310 | /* | |
311 | * BT.601 limited range YCbCr -> full range RGB | |
312 | * | |
313 | * |r| | 6537 4769 0| |cr | | |
314 | * |g| = |-3330 4769 -1605| x |y-64| | |
315 | * |b| | 0 4769 8263| |cb | | |
316 | * | |
317 | * Cb and Cr apparently come in as signed already, so no | |
318 | * need for any offset. For Y we need to remove the offset. | |
319 | */ | |
320 | I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); | |
321 | I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
322 | I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); | |
323 | ||
324 | I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); | |
325 | I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); | |
326 | I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); | |
327 | I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); | |
328 | I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); | |
329 | ||
330 | I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); | |
331 | I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
332 | I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); | |
333 | ||
334 | I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
335 | I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
336 | I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); | |
337 | } | |
338 | ||
7f1f3851 | 339 | static void |
2fde1391 ML |
340 | vlv_update_plane(struct drm_plane *dplane, |
341 | const struct intel_crtc_state *crtc_state, | |
342 | const struct intel_plane_state *plane_state) | |
7f1f3851 JB |
343 | { |
344 | struct drm_device *dev = dplane->dev; | |
345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
346 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
2fde1391 | 347 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 348 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7f1f3851 JB |
349 | int pipe = intel_plane->pipe; |
350 | int plane = intel_plane->plane; | |
351 | u32 sprctl; | |
352 | unsigned long sprsurf_offset, linear_offset; | |
353 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2fde1391 ML |
354 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
355 | int crtc_x = plane_state->dst.x1; | |
356 | int crtc_y = plane_state->dst.y1; | |
357 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
358 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
359 | uint32_t x = plane_state->src.x1 >> 16; | |
360 | uint32_t y = plane_state->src.y1 >> 16; | |
361 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
362 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
7f1f3851 | 363 | |
48fe4691 | 364 | sprctl = SP_ENABLE; |
7f1f3851 JB |
365 | |
366 | switch (fb->pixel_format) { | |
367 | case DRM_FORMAT_YUYV: | |
368 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; | |
369 | break; | |
370 | case DRM_FORMAT_YVYU: | |
371 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; | |
372 | break; | |
373 | case DRM_FORMAT_UYVY: | |
374 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; | |
375 | break; | |
376 | case DRM_FORMAT_VYUY: | |
377 | sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; | |
378 | break; | |
379 | case DRM_FORMAT_RGB565: | |
380 | sprctl |= SP_FORMAT_BGR565; | |
381 | break; | |
382 | case DRM_FORMAT_XRGB8888: | |
383 | sprctl |= SP_FORMAT_BGRX8888; | |
384 | break; | |
385 | case DRM_FORMAT_ARGB8888: | |
386 | sprctl |= SP_FORMAT_BGRA8888; | |
387 | break; | |
388 | case DRM_FORMAT_XBGR2101010: | |
389 | sprctl |= SP_FORMAT_RGBX1010102; | |
390 | break; | |
391 | case DRM_FORMAT_ABGR2101010: | |
392 | sprctl |= SP_FORMAT_RGBA1010102; | |
393 | break; | |
394 | case DRM_FORMAT_XBGR8888: | |
395 | sprctl |= SP_FORMAT_RGBX8888; | |
396 | break; | |
397 | case DRM_FORMAT_ABGR8888: | |
398 | sprctl |= SP_FORMAT_RGBA8888; | |
399 | break; | |
400 | default: | |
401 | /* | |
402 | * If we get here one of the upper layers failed to filter | |
403 | * out the unsupported plane formats | |
404 | */ | |
405 | BUG(); | |
406 | break; | |
407 | } | |
408 | ||
4ea67bc7 VS |
409 | /* |
410 | * Enable gamma to match primary/cursor plane behaviour. | |
411 | * FIXME should be user controllable via propertiesa. | |
412 | */ | |
413 | sprctl |= SP_GAMMA_ENABLE; | |
414 | ||
7f1f3851 JB |
415 | if (obj->tiling_mode != I915_TILING_NONE) |
416 | sprctl |= SP_TILED; | |
417 | ||
7f1f3851 JB |
418 | /* Sizes are 0 based */ |
419 | src_w--; | |
420 | src_h--; | |
421 | crtc_w--; | |
422 | crtc_h--; | |
423 | ||
7f1f3851 | 424 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
b5c65338 VS |
425 | sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y, |
426 | fb->modifier[0], | |
7f1f3851 JB |
427 | pixel_size, |
428 | fb->pitches[0]); | |
429 | linear_offset -= sprsurf_offset; | |
430 | ||
2fde1391 | 431 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
432 | sprctl |= SP_ROTATE_180; |
433 | ||
434 | x += src_w; | |
435 | y += src_h; | |
436 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; | |
437 | } | |
438 | ||
47ecbb20 VS |
439 | if (key->flags) { |
440 | I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); | |
441 | I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); | |
442 | I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); | |
443 | } | |
444 | ||
445 | if (key->flags & I915_SET_COLORKEY_SOURCE) | |
446 | sprctl |= SP_SOURCE_KEY; | |
447 | ||
6ca2aeb2 VS |
448 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) |
449 | chv_update_csc(intel_plane, fb->pixel_format); | |
450 | ||
ca6ad025 VS |
451 | I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); |
452 | I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); | |
453 | ||
7f1f3851 JB |
454 | if (obj->tiling_mode != I915_TILING_NONE) |
455 | I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); | |
456 | else | |
457 | I915_WRITE(SPLINOFF(pipe, plane), linear_offset); | |
458 | ||
c14b0485 VS |
459 | I915_WRITE(SPCONSTALPHA(pipe, plane), 0); |
460 | ||
7f1f3851 JB |
461 | I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); |
462 | I915_WRITE(SPCNTR(pipe, plane), sprctl); | |
85ba7b7d DV |
463 | I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + |
464 | sprsurf_offset); | |
b12ce1d8 | 465 | POSTING_READ(SPSURF(pipe, plane)); |
7f1f3851 JB |
466 | } |
467 | ||
468 | static void | |
7fabf5ef | 469 | vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) |
7f1f3851 JB |
470 | { |
471 | struct drm_device *dev = dplane->dev; | |
472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
473 | struct intel_plane *intel_plane = to_intel_plane(dplane); | |
474 | int pipe = intel_plane->pipe; | |
475 | int plane = intel_plane->plane; | |
476 | ||
48fe4691 VS |
477 | I915_WRITE(SPCNTR(pipe, plane), 0); |
478 | ||
85ba7b7d | 479 | I915_WRITE(SPSURF(pipe, plane), 0); |
b12ce1d8 | 480 | POSTING_READ(SPSURF(pipe, plane)); |
7f1f3851 JB |
481 | } |
482 | ||
b840d907 | 483 | static void |
2fde1391 ML |
484 | ivb_update_plane(struct drm_plane *plane, |
485 | const struct intel_crtc_state *crtc_state, | |
486 | const struct intel_plane_state *plane_state) | |
b840d907 JB |
487 | { |
488 | struct drm_device *dev = plane->dev; | |
489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
490 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2fde1391 | 491 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 492 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
47ecbb20 | 493 | enum pipe pipe = intel_plane->pipe; |
b840d907 | 494 | u32 sprctl, sprscale = 0; |
5a35e99e | 495 | unsigned long sprsurf_offset, linear_offset; |
2bd3c3cb | 496 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2fde1391 ML |
497 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
498 | int crtc_x = plane_state->dst.x1; | |
499 | int crtc_y = plane_state->dst.y1; | |
500 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
501 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
502 | uint32_t x = plane_state->src.x1 >> 16; | |
503 | uint32_t y = plane_state->src.y1 >> 16; | |
504 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
505 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
b840d907 | 506 | |
48fe4691 | 507 | sprctl = SPRITE_ENABLE; |
b840d907 JB |
508 | |
509 | switch (fb->pixel_format) { | |
510 | case DRM_FORMAT_XBGR8888: | |
5ee36913 | 511 | sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; |
b840d907 JB |
512 | break; |
513 | case DRM_FORMAT_XRGB8888: | |
5ee36913 | 514 | sprctl |= SPRITE_FORMAT_RGBX888; |
b840d907 JB |
515 | break; |
516 | case DRM_FORMAT_YUYV: | |
517 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; | |
b840d907 JB |
518 | break; |
519 | case DRM_FORMAT_YVYU: | |
520 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; | |
b840d907 JB |
521 | break; |
522 | case DRM_FORMAT_UYVY: | |
523 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; | |
b840d907 JB |
524 | break; |
525 | case DRM_FORMAT_VYUY: | |
526 | sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; | |
b840d907 JB |
527 | break; |
528 | default: | |
28d491df | 529 | BUG(); |
b840d907 JB |
530 | } |
531 | ||
4ea67bc7 VS |
532 | /* |
533 | * Enable gamma to match primary/cursor plane behaviour. | |
534 | * FIXME should be user controllable via propertiesa. | |
535 | */ | |
536 | sprctl |= SPRITE_GAMMA_ENABLE; | |
537 | ||
b840d907 JB |
538 | if (obj->tiling_mode != I915_TILING_NONE) |
539 | sprctl |= SPRITE_TILED; | |
540 | ||
b42c6009 | 541 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
542 | sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; |
543 | else | |
544 | sprctl |= SPRITE_TRICKLE_FEED_DISABLE; | |
545 | ||
6bbfa1c5 | 546 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
86d3efce VS |
547 | sprctl |= SPRITE_PIPE_CSC_ENABLE; |
548 | ||
b840d907 JB |
549 | /* Sizes are 0 based */ |
550 | src_w--; | |
551 | src_h--; | |
552 | crtc_w--; | |
553 | crtc_h--; | |
554 | ||
8553c18e | 555 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 | 556 | sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; |
b840d907 | 557 | |
ca320ac4 | 558 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
b5c65338 VS |
559 | sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y, |
560 | fb->modifier[0], | |
561 | pixel_size, | |
562 | fb->pitches[0]); | |
5a35e99e DL |
563 | linear_offset -= sprsurf_offset; |
564 | ||
2fde1391 | 565 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
566 | sprctl |= SPRITE_ROTATE_180; |
567 | ||
568 | /* HSW and BDW does this automagically in hardware */ | |
569 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
570 | x += src_w; | |
571 | y += src_h; | |
572 | linear_offset += src_h * fb->pitches[0] + | |
573 | src_w * pixel_size; | |
574 | } | |
575 | } | |
576 | ||
47ecbb20 VS |
577 | if (key->flags) { |
578 | I915_WRITE(SPRKEYVAL(pipe), key->min_value); | |
579 | I915_WRITE(SPRKEYMAX(pipe), key->max_value); | |
580 | I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); | |
581 | } | |
582 | ||
583 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
584 | sprctl |= SPRITE_DEST_KEY; | |
585 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
586 | sprctl |= SPRITE_SOURCE_KEY; | |
587 | ||
ca6ad025 VS |
588 | I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); |
589 | I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); | |
590 | ||
5a35e99e DL |
591 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
592 | * register */ | |
b3dc685e | 593 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
c54173a8 | 594 | I915_WRITE(SPROFFSET(pipe), (y << 16) | x); |
5a35e99e | 595 | else if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 596 | I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
597 | else |
598 | I915_WRITE(SPRLINOFF(pipe), linear_offset); | |
c54173a8 | 599 | |
b840d907 | 600 | I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); |
2d354c34 DL |
601 | if (intel_plane->can_scale) |
602 | I915_WRITE(SPRSCALE(pipe), sprscale); | |
b840d907 | 603 | I915_WRITE(SPRCTL(pipe), sprctl); |
85ba7b7d DV |
604 | I915_WRITE(SPRSURF(pipe), |
605 | i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); | |
b12ce1d8 | 606 | POSTING_READ(SPRSURF(pipe)); |
b840d907 JB |
607 | } |
608 | ||
609 | static void | |
7fabf5ef | 610 | ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
611 | { |
612 | struct drm_device *dev = plane->dev; | |
613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
614 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
615 | int pipe = intel_plane->pipe; | |
616 | ||
c562657a | 617 | I915_WRITE(SPRCTL(pipe), 0); |
b840d907 | 618 | /* Can't leave the scaler enabled... */ |
2d354c34 DL |
619 | if (intel_plane->can_scale) |
620 | I915_WRITE(SPRSCALE(pipe), 0); | |
5b633d6b | 621 | |
b12ce1d8 VS |
622 | I915_WRITE(SPRSURF(pipe), 0); |
623 | POSTING_READ(SPRSURF(pipe)); | |
b840d907 JB |
624 | } |
625 | ||
626 | static void | |
2fde1391 ML |
627 | ilk_update_plane(struct drm_plane *plane, |
628 | const struct intel_crtc_state *crtc_state, | |
629 | const struct intel_plane_state *plane_state) | |
b840d907 JB |
630 | { |
631 | struct drm_device *dev = plane->dev; | |
632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
633 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2fde1391 | 634 | struct drm_framebuffer *fb = plane_state->base.fb; |
bdd7554d | 635 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
2bd3c3cb | 636 | int pipe = intel_plane->pipe; |
5a35e99e | 637 | unsigned long dvssurf_offset, linear_offset; |
8aaa81a1 | 638 | u32 dvscntr, dvsscale; |
2bd3c3cb | 639 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2fde1391 ML |
640 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
641 | int crtc_x = plane_state->dst.x1; | |
642 | int crtc_y = plane_state->dst.y1; | |
643 | uint32_t crtc_w = drm_rect_width(&plane_state->dst); | |
644 | uint32_t crtc_h = drm_rect_height(&plane_state->dst); | |
645 | uint32_t x = plane_state->src.x1 >> 16; | |
646 | uint32_t y = plane_state->src.y1 >> 16; | |
647 | uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; | |
648 | uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; | |
b840d907 | 649 | |
48fe4691 | 650 | dvscntr = DVS_ENABLE; |
b840d907 JB |
651 | |
652 | switch (fb->pixel_format) { | |
653 | case DRM_FORMAT_XBGR8888: | |
ab2f9df1 | 654 | dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; |
b840d907 JB |
655 | break; |
656 | case DRM_FORMAT_XRGB8888: | |
ab2f9df1 | 657 | dvscntr |= DVS_FORMAT_RGBX888; |
b840d907 JB |
658 | break; |
659 | case DRM_FORMAT_YUYV: | |
660 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; | |
b840d907 JB |
661 | break; |
662 | case DRM_FORMAT_YVYU: | |
663 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; | |
b840d907 JB |
664 | break; |
665 | case DRM_FORMAT_UYVY: | |
666 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; | |
b840d907 JB |
667 | break; |
668 | case DRM_FORMAT_VYUY: | |
669 | dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; | |
b840d907 JB |
670 | break; |
671 | default: | |
28d491df | 672 | BUG(); |
b840d907 JB |
673 | } |
674 | ||
4ea67bc7 VS |
675 | /* |
676 | * Enable gamma to match primary/cursor plane behaviour. | |
677 | * FIXME should be user controllable via propertiesa. | |
678 | */ | |
679 | dvscntr |= DVS_GAMMA_ENABLE; | |
680 | ||
b840d907 JB |
681 | if (obj->tiling_mode != I915_TILING_NONE) |
682 | dvscntr |= DVS_TILED; | |
683 | ||
d1686ae3 CW |
684 | if (IS_GEN6(dev)) |
685 | dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ | |
b840d907 JB |
686 | |
687 | /* Sizes are 0 based */ | |
688 | src_w--; | |
689 | src_h--; | |
690 | crtc_w--; | |
691 | crtc_h--; | |
692 | ||
8aaa81a1 | 693 | dvsscale = 0; |
8368f014 | 694 | if (crtc_w != src_w || crtc_h != src_h) |
b840d907 JB |
695 | dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; |
696 | ||
ca320ac4 | 697 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
b5c65338 VS |
698 | dvssurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y, |
699 | fb->modifier[0], | |
700 | pixel_size, | |
701 | fb->pitches[0]); | |
5a35e99e DL |
702 | linear_offset -= dvssurf_offset; |
703 | ||
2fde1391 | 704 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
76eebda7 VS |
705 | dvscntr |= DVS_ROTATE_180; |
706 | ||
707 | x += src_w; | |
708 | y += src_h; | |
709 | linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; | |
710 | } | |
711 | ||
47ecbb20 VS |
712 | if (key->flags) { |
713 | I915_WRITE(DVSKEYVAL(pipe), key->min_value); | |
714 | I915_WRITE(DVSKEYMAX(pipe), key->max_value); | |
715 | I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); | |
716 | } | |
717 | ||
718 | if (key->flags & I915_SET_COLORKEY_DESTINATION) | |
719 | dvscntr |= DVS_DEST_KEY; | |
720 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
721 | dvscntr |= DVS_SOURCE_KEY; | |
722 | ||
ca6ad025 VS |
723 | I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); |
724 | I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); | |
725 | ||
5a35e99e | 726 | if (obj->tiling_mode != I915_TILING_NONE) |
b840d907 | 727 | I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); |
5a35e99e DL |
728 | else |
729 | I915_WRITE(DVSLINOFF(pipe), linear_offset); | |
b840d907 | 730 | |
b840d907 JB |
731 | I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); |
732 | I915_WRITE(DVSSCALE(pipe), dvsscale); | |
733 | I915_WRITE(DVSCNTR(pipe), dvscntr); | |
85ba7b7d DV |
734 | I915_WRITE(DVSSURF(pipe), |
735 | i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); | |
b12ce1d8 | 736 | POSTING_READ(DVSSURF(pipe)); |
b840d907 JB |
737 | } |
738 | ||
739 | static void | |
7fabf5ef | 740 | ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) |
b840d907 JB |
741 | { |
742 | struct drm_device *dev = plane->dev; | |
743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
744 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
745 | int pipe = intel_plane->pipe; | |
746 | ||
48fe4691 | 747 | I915_WRITE(DVSCNTR(pipe), 0); |
b840d907 JB |
748 | /* Disable the scaler */ |
749 | I915_WRITE(DVSSCALE(pipe), 0); | |
48fe4691 | 750 | |
85ba7b7d | 751 | I915_WRITE(DVSSURF(pipe), 0); |
b12ce1d8 | 752 | POSTING_READ(DVSSURF(pipe)); |
b840d907 JB |
753 | } |
754 | ||
755 | static int | |
96d61a7f | 756 | intel_check_sprite_plane(struct drm_plane *plane, |
061e4b8d | 757 | struct intel_crtc_state *crtc_state, |
96d61a7f | 758 | struct intel_plane_state *state) |
b840d907 | 759 | { |
c331879c | 760 | struct drm_device *dev = plane->dev; |
061e4b8d ML |
761 | struct drm_crtc *crtc = state->base.crtc; |
762 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b840d907 | 763 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 764 | struct drm_framebuffer *fb = state->base.fb; |
96d61a7f GP |
765 | int crtc_x, crtc_y; |
766 | unsigned int crtc_w, crtc_h; | |
767 | uint32_t src_x, src_y, src_w, src_h; | |
768 | struct drm_rect *src = &state->src; | |
769 | struct drm_rect *dst = &state->dst; | |
96d61a7f | 770 | const struct drm_rect *clip = &state->clip; |
1731693a VS |
771 | int hscale, vscale; |
772 | int max_scale, min_scale; | |
225c228a | 773 | bool can_scale; |
cf4c7c12 MR |
774 | int pixel_size; |
775 | ||
776 | if (!fb) { | |
777 | state->visible = false; | |
da20eabd | 778 | return 0; |
cf4c7c12 | 779 | } |
5e1bac2f | 780 | |
1731693a VS |
781 | /* Don't modify another pipe's plane */ |
782 | if (intel_plane->pipe != intel_crtc->pipe) { | |
783 | DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); | |
b840d907 | 784 | return -EINVAL; |
1731693a | 785 | } |
b840d907 | 786 | |
1731693a VS |
787 | /* FIXME check all gen limits */ |
788 | if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { | |
789 | DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); | |
b840d907 | 790 | return -EINVAL; |
1731693a | 791 | } |
b840d907 | 792 | |
225c228a CK |
793 | /* setup can_scale, min_scale, max_scale */ |
794 | if (INTEL_INFO(dev)->gen >= 9) { | |
795 | /* use scaler when colorkey is not required */ | |
818ed961 | 796 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { |
225c228a CK |
797 | can_scale = 1; |
798 | min_scale = 1; | |
799 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
800 | } else { | |
801 | can_scale = 0; | |
802 | min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
803 | max_scale = DRM_PLANE_HELPER_NO_SCALING; | |
804 | } | |
805 | } else { | |
806 | can_scale = intel_plane->can_scale; | |
807 | max_scale = intel_plane->max_downscale << 16; | |
808 | min_scale = intel_plane->can_scale ? 1 : (1 << 16); | |
809 | } | |
810 | ||
3c3686cd VS |
811 | /* |
812 | * FIXME the following code does a bunch of fuzzy adjustments to the | |
813 | * coordinates and sizes. We probably need some way to decide whether | |
814 | * more strict checking should be done instead. | |
815 | */ | |
96d61a7f | 816 | drm_rect_rotate(src, fb->width << 16, fb->height << 16, |
8e7d688b | 817 | state->base.rotation); |
76eebda7 | 818 | |
96d61a7f | 819 | hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 820 | BUG_ON(hscale < 0); |
1731693a | 821 | |
96d61a7f | 822 | vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); |
3c3686cd | 823 | BUG_ON(vscale < 0); |
b840d907 | 824 | |
818ed961 | 825 | state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); |
b840d907 | 826 | |
96d61a7f GP |
827 | crtc_x = dst->x1; |
828 | crtc_y = dst->y1; | |
829 | crtc_w = drm_rect_width(dst); | |
830 | crtc_h = drm_rect_height(dst); | |
2d354c34 | 831 | |
96d61a7f | 832 | if (state->visible) { |
3c3686cd | 833 | /* check again in case clipping clamped the results */ |
96d61a7f | 834 | hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
835 | if (hscale < 0) { |
836 | DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); | |
c70f577a VS |
837 | drm_rect_debug_print("src: ", src, true); |
838 | drm_rect_debug_print("dst: ", dst, false); | |
3c3686cd VS |
839 | |
840 | return hscale; | |
841 | } | |
842 | ||
96d61a7f | 843 | vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); |
3c3686cd VS |
844 | if (vscale < 0) { |
845 | DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); | |
c70f577a VS |
846 | drm_rect_debug_print("src: ", src, true); |
847 | drm_rect_debug_print("dst: ", dst, false); | |
3c3686cd VS |
848 | |
849 | return vscale; | |
850 | } | |
851 | ||
1731693a | 852 | /* Make the source viewport size an exact multiple of the scaling factors. */ |
96d61a7f GP |
853 | drm_rect_adjust_size(src, |
854 | drm_rect_width(dst) * hscale - drm_rect_width(src), | |
855 | drm_rect_height(dst) * vscale - drm_rect_height(src)); | |
1731693a | 856 | |
96d61a7f | 857 | drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, |
8e7d688b | 858 | state->base.rotation); |
76eebda7 | 859 | |
1731693a | 860 | /* sanity check to make sure the src viewport wasn't enlarged */ |
ea2c67bb MR |
861 | WARN_ON(src->x1 < (int) state->base.src_x || |
862 | src->y1 < (int) state->base.src_y || | |
863 | src->x2 > (int) state->base.src_x + state->base.src_w || | |
864 | src->y2 > (int) state->base.src_y + state->base.src_h); | |
1731693a VS |
865 | |
866 | /* | |
867 | * Hardware doesn't handle subpixel coordinates. | |
868 | * Adjust to (macro)pixel boundary, but be careful not to | |
869 | * increase the source viewport size, because that could | |
870 | * push the downscaling factor out of bounds. | |
1731693a | 871 | */ |
96d61a7f GP |
872 | src_x = src->x1 >> 16; |
873 | src_w = drm_rect_width(src) >> 16; | |
874 | src_y = src->y1 >> 16; | |
875 | src_h = drm_rect_height(src) >> 16; | |
1731693a VS |
876 | |
877 | if (format_is_yuv(fb->pixel_format)) { | |
878 | src_x &= ~1; | |
879 | src_w &= ~1; | |
880 | ||
881 | /* | |
882 | * Must keep src and dst the | |
883 | * same if we can't scale. | |
884 | */ | |
225c228a | 885 | if (!can_scale) |
1731693a VS |
886 | crtc_w &= ~1; |
887 | ||
888 | if (crtc_w == 0) | |
96d61a7f | 889 | state->visible = false; |
1731693a VS |
890 | } |
891 | } | |
892 | ||
893 | /* Check size restrictions when scaling */ | |
96d61a7f | 894 | if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { |
1731693a VS |
895 | unsigned int width_bytes; |
896 | ||
225c228a | 897 | WARN_ON(!can_scale); |
1731693a VS |
898 | |
899 | /* FIXME interlacing min height is 6 */ | |
900 | ||
901 | if (crtc_w < 3 || crtc_h < 3) | |
96d61a7f | 902 | state->visible = false; |
1731693a VS |
903 | |
904 | if (src_w < 3 || src_h < 3) | |
96d61a7f | 905 | state->visible = false; |
1731693a | 906 | |
cf4c7c12 | 907 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
96d61a7f GP |
908 | width_bytes = ((src_x * pixel_size) & 63) + |
909 | src_w * pixel_size; | |
1731693a | 910 | |
c331879c CK |
911 | if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || |
912 | width_bytes > 4096 || fb->pitches[0] > 4096)) { | |
1731693a VS |
913 | DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); |
914 | return -EINVAL; | |
915 | } | |
916 | } | |
917 | ||
96d61a7f | 918 | if (state->visible) { |
0a5ae1b0 CK |
919 | src->x1 = src_x << 16; |
920 | src->x2 = (src_x + src_w) << 16; | |
921 | src->y1 = src_y << 16; | |
922 | src->y2 = (src_y + src_h) << 16; | |
96d61a7f GP |
923 | } |
924 | ||
925 | dst->x1 = crtc_x; | |
926 | dst->x2 = crtc_x + crtc_w; | |
927 | dst->y1 = crtc_y; | |
928 | dst->y2 = crtc_y + crtc_h; | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
8ea30864 JB |
933 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
934 | struct drm_file *file_priv) | |
935 | { | |
936 | struct drm_intel_sprite_colorkey *set = data; | |
8ea30864 | 937 | struct drm_plane *plane; |
818ed961 ML |
938 | struct drm_plane_state *plane_state; |
939 | struct drm_atomic_state *state; | |
940 | struct drm_modeset_acquire_ctx ctx; | |
8ea30864 JB |
941 | int ret = 0; |
942 | ||
8ea30864 JB |
943 | /* Make sure we don't try to enable both src & dest simultaneously */ |
944 | if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) | |
945 | return -EINVAL; | |
946 | ||
666a4537 | 947 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
47ecbb20 VS |
948 | set->flags & I915_SET_COLORKEY_DESTINATION) |
949 | return -EINVAL; | |
950 | ||
7707e653 | 951 | plane = drm_plane_find(dev, set->plane_id); |
818ed961 ML |
952 | if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) |
953 | return -ENOENT; | |
8ea30864 | 954 | |
818ed961 | 955 | drm_modeset_acquire_init(&ctx, 0); |
6156a456 | 956 | |
818ed961 ML |
957 | state = drm_atomic_state_alloc(plane->dev); |
958 | if (!state) { | |
959 | ret = -ENOMEM; | |
960 | goto out; | |
6156a456 | 961 | } |
818ed961 ML |
962 | state->acquire_ctx = &ctx; |
963 | ||
964 | while (1) { | |
965 | plane_state = drm_atomic_get_plane_state(state, plane); | |
966 | ret = PTR_ERR_OR_ZERO(plane_state); | |
967 | if (!ret) { | |
968 | to_intel_plane_state(plane_state)->ckey = *set; | |
969 | ret = drm_atomic_commit(state); | |
970 | } | |
6156a456 | 971 | |
818ed961 ML |
972 | if (ret != -EDEADLK) |
973 | break; | |
8ea30864 | 974 | |
818ed961 ML |
975 | drm_atomic_state_clear(state); |
976 | drm_modeset_backoff(&ctx); | |
977 | } | |
8ea30864 | 978 | |
818ed961 ML |
979 | if (ret) |
980 | drm_atomic_state_free(state); | |
5e1bac2f | 981 | |
818ed961 ML |
982 | out: |
983 | drm_modeset_drop_locks(&ctx); | |
984 | drm_modeset_acquire_fini(&ctx); | |
985 | return ret; | |
5e1bac2f JB |
986 | } |
987 | ||
dada2d53 | 988 | static const uint32_t ilk_plane_formats[] = { |
d1686ae3 CW |
989 | DRM_FORMAT_XRGB8888, |
990 | DRM_FORMAT_YUYV, | |
991 | DRM_FORMAT_YVYU, | |
992 | DRM_FORMAT_UYVY, | |
993 | DRM_FORMAT_VYUY, | |
994 | }; | |
995 | ||
dada2d53 | 996 | static const uint32_t snb_plane_formats[] = { |
b840d907 JB |
997 | DRM_FORMAT_XBGR8888, |
998 | DRM_FORMAT_XRGB8888, | |
999 | DRM_FORMAT_YUYV, | |
1000 | DRM_FORMAT_YVYU, | |
1001 | DRM_FORMAT_UYVY, | |
1002 | DRM_FORMAT_VYUY, | |
1003 | }; | |
1004 | ||
dada2d53 | 1005 | static const uint32_t vlv_plane_formats[] = { |
7f1f3851 JB |
1006 | DRM_FORMAT_RGB565, |
1007 | DRM_FORMAT_ABGR8888, | |
1008 | DRM_FORMAT_ARGB8888, | |
1009 | DRM_FORMAT_XBGR8888, | |
1010 | DRM_FORMAT_XRGB8888, | |
1011 | DRM_FORMAT_XBGR2101010, | |
1012 | DRM_FORMAT_ABGR2101010, | |
1013 | DRM_FORMAT_YUYV, | |
1014 | DRM_FORMAT_YVYU, | |
1015 | DRM_FORMAT_UYVY, | |
1016 | DRM_FORMAT_VYUY, | |
1017 | }; | |
1018 | ||
dc2a41b4 DL |
1019 | static uint32_t skl_plane_formats[] = { |
1020 | DRM_FORMAT_RGB565, | |
1021 | DRM_FORMAT_ABGR8888, | |
1022 | DRM_FORMAT_ARGB8888, | |
1023 | DRM_FORMAT_XBGR8888, | |
1024 | DRM_FORMAT_XRGB8888, | |
1025 | DRM_FORMAT_YUYV, | |
1026 | DRM_FORMAT_YVYU, | |
1027 | DRM_FORMAT_UYVY, | |
1028 | DRM_FORMAT_VYUY, | |
1029 | }; | |
1030 | ||
b840d907 | 1031 | int |
7f1f3851 | 1032 | intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) |
b840d907 JB |
1033 | { |
1034 | struct intel_plane *intel_plane; | |
8e7d688b | 1035 | struct intel_plane_state *state; |
b840d907 | 1036 | unsigned long possible_crtcs; |
d1686ae3 CW |
1037 | const uint32_t *plane_formats; |
1038 | int num_plane_formats; | |
b840d907 JB |
1039 | int ret; |
1040 | ||
d1686ae3 | 1041 | if (INTEL_INFO(dev)->gen < 5) |
b840d907 | 1042 | return -ENODEV; |
b840d907 | 1043 | |
b14c5679 | 1044 | intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); |
b840d907 JB |
1045 | if (!intel_plane) |
1046 | return -ENOMEM; | |
1047 | ||
8e7d688b MR |
1048 | state = intel_create_plane_state(&intel_plane->base); |
1049 | if (!state) { | |
ea2c67bb MR |
1050 | kfree(intel_plane); |
1051 | return -ENOMEM; | |
1052 | } | |
8e7d688b | 1053 | intel_plane->base.state = &state->base; |
ea2c67bb | 1054 | |
d1686ae3 CW |
1055 | switch (INTEL_INFO(dev)->gen) { |
1056 | case 5: | |
1057 | case 6: | |
2d354c34 | 1058 | intel_plane->can_scale = true; |
b840d907 | 1059 | intel_plane->max_downscale = 16; |
d1686ae3 CW |
1060 | intel_plane->update_plane = ilk_update_plane; |
1061 | intel_plane->disable_plane = ilk_disable_plane; | |
d1686ae3 CW |
1062 | |
1063 | if (IS_GEN6(dev)) { | |
1064 | plane_formats = snb_plane_formats; | |
1065 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1066 | } else { | |
1067 | plane_formats = ilk_plane_formats; | |
1068 | num_plane_formats = ARRAY_SIZE(ilk_plane_formats); | |
1069 | } | |
1070 | break; | |
1071 | ||
1072 | case 7: | |
4e0bbc31 | 1073 | case 8: |
d49f7091 | 1074 | if (IS_IVYBRIDGE(dev)) { |
2d354c34 | 1075 | intel_plane->can_scale = true; |
d49f7091 DL |
1076 | intel_plane->max_downscale = 2; |
1077 | } else { | |
1078 | intel_plane->can_scale = false; | |
1079 | intel_plane->max_downscale = 1; | |
1080 | } | |
7f1f3851 | 1081 | |
666a4537 | 1082 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
7f1f3851 JB |
1083 | intel_plane->update_plane = vlv_update_plane; |
1084 | intel_plane->disable_plane = vlv_disable_plane; | |
7f1f3851 JB |
1085 | |
1086 | plane_formats = vlv_plane_formats; | |
1087 | num_plane_formats = ARRAY_SIZE(vlv_plane_formats); | |
1088 | } else { | |
7f1f3851 JB |
1089 | intel_plane->update_plane = ivb_update_plane; |
1090 | intel_plane->disable_plane = ivb_disable_plane; | |
7f1f3851 JB |
1091 | |
1092 | plane_formats = snb_plane_formats; | |
1093 | num_plane_formats = ARRAY_SIZE(snb_plane_formats); | |
1094 | } | |
d1686ae3 | 1095 | break; |
dc2a41b4 | 1096 | case 9: |
c331879c | 1097 | intel_plane->can_scale = true; |
dc2a41b4 DL |
1098 | intel_plane->update_plane = skl_update_plane; |
1099 | intel_plane->disable_plane = skl_disable_plane; | |
549e2bfb | 1100 | state->scaler_id = -1; |
dc2a41b4 DL |
1101 | |
1102 | plane_formats = skl_plane_formats; | |
1103 | num_plane_formats = ARRAY_SIZE(skl_plane_formats); | |
1104 | break; | |
d1686ae3 | 1105 | default: |
a8b0bbab | 1106 | kfree(intel_plane); |
d1686ae3 | 1107 | return -ENODEV; |
b840d907 JB |
1108 | } |
1109 | ||
1110 | intel_plane->pipe = pipe; | |
7f1f3851 | 1111 | intel_plane->plane = plane; |
d1b9d039 | 1112 | intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); |
c59cb179 | 1113 | intel_plane->check_plane = intel_check_sprite_plane; |
b840d907 | 1114 | possible_crtcs = (1 << pipe); |
8fe8a3fe | 1115 | ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, |
65a3fea0 | 1116 | &intel_plane_funcs, |
8fe8a3fe DF |
1117 | plane_formats, num_plane_formats, |
1118 | DRM_PLANE_TYPE_OVERLAY); | |
7ed6eeee | 1119 | if (ret) { |
b840d907 | 1120 | kfree(intel_plane); |
7ed6eeee VS |
1121 | goto out; |
1122 | } | |
1123 | ||
3b7a5119 | 1124 | intel_create_rotation_property(dev, intel_plane); |
b840d907 | 1125 | |
ea2c67bb MR |
1126 | drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); |
1127 | ||
caf4e252 | 1128 | out: |
b840d907 JB |
1129 | return ret; |
1130 | } |