Commit | Line | Data |
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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
cf9d2890 | 26 | #include "i915_vgpu.h" |
907b28c5 | 27 | |
6daccb0b CW |
28 | #include <linux/pm_runtime.h> |
29 | ||
83e33372 | 30 | #define FORCEWAKE_ACK_TIMEOUT_MS 50 |
907b28c5 | 31 | |
75aa3f63 | 32 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__)) |
6af5d92f | 33 | |
05a2fb15 MK |
34 | static const char * const forcewake_domain_names[] = { |
35 | "render", | |
36 | "blitter", | |
37 | "media", | |
38 | }; | |
39 | ||
40 | const char * | |
48c1026a | 41 | intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) |
05a2fb15 | 42 | { |
53abb679 | 43 | BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); |
05a2fb15 MK |
44 | |
45 | if (id >= 0 && id < FW_DOMAIN_ID_COUNT) | |
46 | return forcewake_domain_names[id]; | |
47 | ||
48 | WARN_ON(id); | |
49 | ||
50 | return "unknown"; | |
51 | } | |
52 | ||
05a2fb15 MK |
53 | static inline void |
54 | fw_domain_reset(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 55 | { |
f0f59a00 | 56 | WARN_ON(!i915_mmio_reg_valid(d->reg_set)); |
05a2fb15 | 57 | __raw_i915_write32(d->i915, d->reg_set, d->val_reset); |
907b28c5 CW |
58 | } |
59 | ||
05a2fb15 MK |
60 | static inline void |
61 | fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 62 | { |
a57a4a67 TU |
63 | d->wake_count++; |
64 | hrtimer_start_range_ns(&d->timer, | |
65 | ktime_set(0, NSEC_PER_MSEC), | |
66 | NSEC_PER_MSEC, | |
67 | HRTIMER_MODE_REL); | |
907b28c5 CW |
68 | } |
69 | ||
05a2fb15 MK |
70 | static inline void |
71 | fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 72 | { |
05a2fb15 MK |
73 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & |
74 | FORCEWAKE_KERNEL) == 0, | |
907b28c5 | 75 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
76 | DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", |
77 | intel_uncore_forcewake_domain_to_str(d->id)); | |
78 | } | |
907b28c5 | 79 | |
05a2fb15 MK |
80 | static inline void |
81 | fw_domain_get(const struct intel_uncore_forcewake_domain *d) | |
82 | { | |
83 | __raw_i915_write32(d->i915, d->reg_set, d->val_set); | |
84 | } | |
907b28c5 | 85 | |
05a2fb15 MK |
86 | static inline void |
87 | fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d) | |
88 | { | |
89 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & | |
90 | FORCEWAKE_KERNEL), | |
907b28c5 | 91 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
92 | DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", |
93 | intel_uncore_forcewake_domain_to_str(d->id)); | |
94 | } | |
907b28c5 | 95 | |
05a2fb15 MK |
96 | static inline void |
97 | fw_domain_put(const struct intel_uncore_forcewake_domain *d) | |
98 | { | |
99 | __raw_i915_write32(d->i915, d->reg_set, d->val_clear); | |
907b28c5 CW |
100 | } |
101 | ||
05a2fb15 MK |
102 | static inline void |
103 | fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 104 | { |
05a2fb15 | 105 | /* something from same cacheline, but not from the set register */ |
f0f59a00 | 106 | if (i915_mmio_reg_valid(d->reg_post)) |
05a2fb15 | 107 | __raw_posting_read(d->i915, d->reg_post); |
907b28c5 CW |
108 | } |
109 | ||
05a2fb15 | 110 | static void |
48c1026a | 111 | fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
907b28c5 | 112 | { |
05a2fb15 | 113 | struct intel_uncore_forcewake_domain *d; |
907b28c5 | 114 | |
33c582c1 | 115 | for_each_fw_domain_masked(d, fw_domains, dev_priv) { |
05a2fb15 MK |
116 | fw_domain_wait_ack_clear(d); |
117 | fw_domain_get(d); | |
05a2fb15 | 118 | } |
4e1176dd TU |
119 | |
120 | for_each_fw_domain_masked(d, fw_domains, dev_priv) | |
121 | fw_domain_wait_ack(d); | |
05a2fb15 | 122 | } |
907b28c5 | 123 | |
05a2fb15 | 124 | static void |
48c1026a | 125 | fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
126 | { |
127 | struct intel_uncore_forcewake_domain *d; | |
907b28c5 | 128 | |
33c582c1 | 129 | for_each_fw_domain_masked(d, fw_domains, dev_priv) { |
05a2fb15 MK |
130 | fw_domain_put(d); |
131 | fw_domain_posting_read(d); | |
132 | } | |
133 | } | |
907b28c5 | 134 | |
05a2fb15 MK |
135 | static void |
136 | fw_domains_posting_read(struct drm_i915_private *dev_priv) | |
137 | { | |
138 | struct intel_uncore_forcewake_domain *d; | |
05a2fb15 MK |
139 | |
140 | /* No need to do for all, just do for first found */ | |
33c582c1 | 141 | for_each_fw_domain(d, dev_priv) { |
05a2fb15 MK |
142 | fw_domain_posting_read(d); |
143 | break; | |
144 | } | |
145 | } | |
146 | ||
147 | static void | |
48c1026a | 148 | fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
149 | { |
150 | struct intel_uncore_forcewake_domain *d; | |
05a2fb15 | 151 | |
3225b2f9 MK |
152 | if (dev_priv->uncore.fw_domains == 0) |
153 | return; | |
f9b3927a | 154 | |
33c582c1 | 155 | for_each_fw_domain_masked(d, fw_domains, dev_priv) |
05a2fb15 MK |
156 | fw_domain_reset(d); |
157 | ||
158 | fw_domains_posting_read(dev_priv); | |
159 | } | |
160 | ||
161 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) | |
162 | { | |
163 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
164 | * thread to wake up. | |
165 | */ | |
166 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & | |
167 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) | |
168 | DRM_ERROR("GT thread status wait timed out\n"); | |
169 | } | |
170 | ||
171 | static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, | |
48c1026a | 172 | enum forcewake_domains fw_domains) |
05a2fb15 MK |
173 | { |
174 | fw_domains_get(dev_priv, fw_domains); | |
907b28c5 | 175 | |
05a2fb15 | 176 | /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ |
c549f738 | 177 | __gen6_gt_wait_for_thread_c0(dev_priv); |
907b28c5 CW |
178 | } |
179 | ||
180 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
181 | { | |
182 | u32 gtfifodbg; | |
6af5d92f CW |
183 | |
184 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
90f256b5 VS |
185 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
186 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); | |
907b28c5 CW |
187 | } |
188 | ||
05a2fb15 | 189 | static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, |
48c1026a | 190 | enum forcewake_domains fw_domains) |
907b28c5 | 191 | { |
05a2fb15 | 192 | fw_domains_put(dev_priv, fw_domains); |
907b28c5 CW |
193 | gen6_gt_check_fifodbg(dev_priv); |
194 | } | |
195 | ||
c32e3788 DG |
196 | static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) |
197 | { | |
198 | u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); | |
199 | ||
200 | return count & GT_FIFO_FREE_ENTRIES_MASK; | |
201 | } | |
202 | ||
907b28c5 CW |
203 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
204 | { | |
205 | int ret = 0; | |
206 | ||
5135d64b D |
207 | /* On VLV, FIFO will be shared by both SW and HW. |
208 | * So, we need to read the FREE_ENTRIES everytime */ | |
2d1fe073 | 209 | if (IS_VALLEYVIEW(dev_priv)) |
c32e3788 | 210 | dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); |
5135d64b | 211 | |
907b28c5 CW |
212 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
213 | int loop = 500; | |
c32e3788 DG |
214 | u32 fifo = fifo_free_entries(dev_priv); |
215 | ||
907b28c5 CW |
216 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
217 | udelay(10); | |
c32e3788 | 218 | fifo = fifo_free_entries(dev_priv); |
907b28c5 CW |
219 | } |
220 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
221 | ++ret; | |
222 | dev_priv->uncore.fifo_count = fifo; | |
223 | } | |
224 | dev_priv->uncore.fifo_count--; | |
225 | ||
226 | return ret; | |
227 | } | |
228 | ||
a57a4a67 TU |
229 | static enum hrtimer_restart |
230 | intel_uncore_fw_release_timer(struct hrtimer *timer) | |
38cff0b1 | 231 | { |
a57a4a67 TU |
232 | struct intel_uncore_forcewake_domain *domain = |
233 | container_of(timer, struct intel_uncore_forcewake_domain, timer); | |
b2cff0db | 234 | unsigned long irqflags; |
38cff0b1 | 235 | |
da5827c3 | 236 | assert_rpm_device_not_suspended(domain->i915); |
38cff0b1 | 237 | |
b2cff0db CW |
238 | spin_lock_irqsave(&domain->i915->uncore.lock, irqflags); |
239 | if (WARN_ON(domain->wake_count == 0)) | |
240 | domain->wake_count++; | |
241 | ||
242 | if (--domain->wake_count == 0) | |
243 | domain->i915->uncore.funcs.force_wake_put(domain->i915, | |
244 | 1 << domain->id); | |
245 | ||
246 | spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags); | |
a57a4a67 TU |
247 | |
248 | return HRTIMER_NORESTART; | |
38cff0b1 ZW |
249 | } |
250 | ||
dc97997a CW |
251 | void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv, |
252 | bool restore) | |
38cff0b1 | 253 | { |
48c1026a | 254 | unsigned long irqflags; |
b2cff0db | 255 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 256 | int retry_count = 100; |
48c1026a | 257 | enum forcewake_domains fw = 0, active_domains; |
38cff0b1 | 258 | |
b2cff0db CW |
259 | /* Hold uncore.lock across reset to prevent any register access |
260 | * with forcewake not set correctly. Wait until all pending | |
261 | * timers are run before holding. | |
262 | */ | |
263 | while (1) { | |
264 | active_domains = 0; | |
38cff0b1 | 265 | |
33c582c1 | 266 | for_each_fw_domain(domain, dev_priv) { |
a57a4a67 | 267 | if (hrtimer_cancel(&domain->timer) == 0) |
b2cff0db | 268 | continue; |
38cff0b1 | 269 | |
a57a4a67 | 270 | intel_uncore_fw_release_timer(&domain->timer); |
b2cff0db | 271 | } |
aec347ab | 272 | |
b2cff0db | 273 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
b2ec142c | 274 | |
33c582c1 | 275 | for_each_fw_domain(domain, dev_priv) { |
a57a4a67 | 276 | if (hrtimer_active(&domain->timer)) |
33c582c1 | 277 | active_domains |= domain->mask; |
b2cff0db | 278 | } |
3123fcaf | 279 | |
b2cff0db CW |
280 | if (active_domains == 0) |
281 | break; | |
aec347ab | 282 | |
b2cff0db CW |
283 | if (--retry_count == 0) { |
284 | DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); | |
285 | break; | |
286 | } | |
0294ae7b | 287 | |
b2cff0db CW |
288 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
289 | cond_resched(); | |
290 | } | |
0294ae7b | 291 | |
b2cff0db CW |
292 | WARN_ON(active_domains); |
293 | ||
33c582c1 | 294 | for_each_fw_domain(domain, dev_priv) |
b2cff0db | 295 | if (domain->wake_count) |
33c582c1 | 296 | fw |= domain->mask; |
b2cff0db CW |
297 | |
298 | if (fw) | |
299 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); | |
ef46e0d2 | 300 | |
05a2fb15 | 301 | fw_domains_reset(dev_priv, FORCEWAKE_ALL); |
38cff0b1 | 302 | |
0294ae7b | 303 | if (restore) { /* If reset with a user forcewake, try to restore */ |
0294ae7b CW |
304 | if (fw) |
305 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); | |
306 | ||
dc97997a | 307 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) |
0294ae7b | 308 | dev_priv->uncore.fifo_count = |
c32e3788 | 309 | fifo_free_entries(dev_priv); |
0294ae7b CW |
310 | } |
311 | ||
b2cff0db | 312 | if (!restore) |
59bad947 | 313 | assert_forcewakes_inactive(dev_priv); |
b2cff0db | 314 | |
0294ae7b | 315 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
ef46e0d2 DV |
316 | } |
317 | ||
c02e85a0 MK |
318 | static u64 gen9_edram_size(struct drm_i915_private *dev_priv) |
319 | { | |
320 | const unsigned int ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; | |
321 | const unsigned int sets[4] = { 1, 1, 2, 2 }; | |
322 | const u32 cap = dev_priv->edram_cap; | |
323 | ||
324 | return EDRAM_NUM_BANKS(cap) * | |
325 | ways[EDRAM_WAYS_IDX(cap)] * | |
326 | sets[EDRAM_SETS_IDX(cap)] * | |
327 | 1024 * 1024; | |
328 | } | |
329 | ||
3accaf7e | 330 | u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv) |
907b28c5 | 331 | { |
3accaf7e MK |
332 | if (!HAS_EDRAM(dev_priv)) |
333 | return 0; | |
334 | ||
c02e85a0 MK |
335 | /* The needed capability bits for size calculation |
336 | * are not there with pre gen9 so return 128MB always. | |
3accaf7e | 337 | */ |
c02e85a0 MK |
338 | if (INTEL_GEN(dev_priv) < 9) |
339 | return 128 * 1024 * 1024; | |
3accaf7e | 340 | |
c02e85a0 | 341 | return gen9_edram_size(dev_priv); |
3accaf7e | 342 | } |
907b28c5 | 343 | |
3accaf7e MK |
344 | static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) |
345 | { | |
346 | if (IS_HASWELL(dev_priv) || | |
347 | IS_BROADWELL(dev_priv) || | |
348 | INTEL_GEN(dev_priv) >= 9) { | |
349 | dev_priv->edram_cap = __raw_i915_read32(dev_priv, | |
350 | HSW_EDRAM_CAP); | |
351 | ||
352 | /* NB: We can't write IDICR yet because we do not have gt funcs | |
18ce3994 | 353 | * set up */ |
3accaf7e MK |
354 | } else { |
355 | dev_priv->edram_cap = 0; | |
18ce3994 | 356 | } |
3accaf7e MK |
357 | |
358 | if (HAS_EDRAM(dev_priv)) | |
359 | DRM_INFO("Found %lluMB of eDRAM\n", | |
360 | intel_uncore_edram_size(dev_priv) / (1024 * 1024)); | |
f9b3927a MK |
361 | } |
362 | ||
8a47eb19 | 363 | static bool |
8ac3e1bb | 364 | fpga_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) |
8a47eb19 MK |
365 | { |
366 | u32 dbg; | |
367 | ||
8a47eb19 MK |
368 | dbg = __raw_i915_read32(dev_priv, FPGA_DBG); |
369 | if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) | |
370 | return false; | |
371 | ||
372 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
373 | ||
374 | return true; | |
375 | } | |
376 | ||
8ac3e1bb MK |
377 | static bool |
378 | vlv_check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) | |
379 | { | |
380 | u32 cer; | |
381 | ||
382 | cer = __raw_i915_read32(dev_priv, CLAIM_ER); | |
383 | if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) | |
384 | return false; | |
385 | ||
386 | __raw_i915_write32(dev_priv, CLAIM_ER, CLAIM_ER_CLR); | |
387 | ||
388 | return true; | |
389 | } | |
390 | ||
391 | static bool | |
392 | check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) | |
393 | { | |
394 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv)) | |
395 | return fpga_check_for_unclaimed_mmio(dev_priv); | |
396 | ||
397 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
398 | return vlv_check_for_unclaimed_mmio(dev_priv); | |
399 | ||
400 | return false; | |
401 | } | |
402 | ||
dc97997a | 403 | static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, |
f9b3927a MK |
404 | bool restore_forcewake) |
405 | { | |
8a47eb19 MK |
406 | /* clear out unclaimed reg detection bit */ |
407 | if (check_for_unclaimed_mmio(dev_priv)) | |
408 | DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n"); | |
907b28c5 | 409 | |
97058870 | 410 | /* clear out old GT FIFO errors */ |
dc97997a | 411 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) |
97058870 VS |
412 | __raw_i915_write32(dev_priv, GTFIFODBG, |
413 | __raw_i915_read32(dev_priv, GTFIFODBG)); | |
414 | ||
a04f90a3 | 415 | /* WaDisableShadowRegForCpd:chv */ |
dc97997a | 416 | if (IS_CHERRYVIEW(dev_priv)) { |
a04f90a3 D |
417 | __raw_i915_write32(dev_priv, GTFIFOCTL, |
418 | __raw_i915_read32(dev_priv, GTFIFOCTL) | | |
419 | GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | | |
420 | GT_FIFO_CTL_RC6_POLICY_STALL); | |
421 | } | |
422 | ||
dc97997a | 423 | intel_uncore_forcewake_reset(dev_priv, restore_forcewake); |
521198a2 MK |
424 | } |
425 | ||
dc97997a CW |
426 | void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, |
427 | bool restore_forcewake) | |
ed493883 | 428 | { |
dc97997a CW |
429 | __intel_uncore_early_sanitize(dev_priv, restore_forcewake); |
430 | i915_check_and_clear_faults(dev_priv); | |
ed493883 ID |
431 | } |
432 | ||
dc97997a | 433 | void intel_uncore_sanitize(struct drm_i915_private *dev_priv) |
521198a2 | 434 | { |
dc97997a | 435 | i915.enable_rc6 = sanitize_rc6_option(dev_priv, i915.enable_rc6); |
274008e8 | 436 | |
907b28c5 | 437 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
54b4f68f | 438 | intel_sanitize_gt_powersave(dev_priv); |
907b28c5 CW |
439 | } |
440 | ||
a6111f7b CW |
441 | static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
442 | enum forcewake_domains fw_domains) | |
443 | { | |
444 | struct intel_uncore_forcewake_domain *domain; | |
a6111f7b CW |
445 | |
446 | if (!dev_priv->uncore.funcs.force_wake_get) | |
447 | return; | |
448 | ||
449 | fw_domains &= dev_priv->uncore.fw_domains; | |
450 | ||
33c582c1 | 451 | for_each_fw_domain_masked(domain, fw_domains, dev_priv) { |
a6111f7b | 452 | if (domain->wake_count++) |
33c582c1 | 453 | fw_domains &= ~domain->mask; |
a6111f7b CW |
454 | } |
455 | ||
456 | if (fw_domains) | |
457 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
458 | } | |
459 | ||
59bad947 MK |
460 | /** |
461 | * intel_uncore_forcewake_get - grab forcewake domain references | |
462 | * @dev_priv: i915 device instance | |
463 | * @fw_domains: forcewake domains to get reference on | |
464 | * | |
465 | * This function can be used get GT's forcewake domain references. | |
466 | * Normal register access will handle the forcewake domains automatically. | |
467 | * However if some sequence requires the GT to not power down a particular | |
468 | * forcewake domains this function should be called at the beginning of the | |
469 | * sequence. And subsequently the reference should be dropped by symmetric | |
470 | * call to intel_unforce_forcewake_put(). Usually caller wants all the domains | |
471 | * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. | |
907b28c5 | 472 | */ |
59bad947 | 473 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 474 | enum forcewake_domains fw_domains) |
907b28c5 CW |
475 | { |
476 | unsigned long irqflags; | |
477 | ||
ab484f8f BW |
478 | if (!dev_priv->uncore.funcs.force_wake_get) |
479 | return; | |
480 | ||
c9b8846a | 481 | assert_rpm_wakelock_held(dev_priv); |
c8c8fb33 | 482 | |
6daccb0b | 483 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
a6111f7b | 484 | __intel_uncore_forcewake_get(dev_priv, fw_domains); |
907b28c5 CW |
485 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
486 | } | |
487 | ||
59bad947 | 488 | /** |
a6111f7b | 489 | * intel_uncore_forcewake_get__locked - grab forcewake domain references |
59bad947 | 490 | * @dev_priv: i915 device instance |
a6111f7b | 491 | * @fw_domains: forcewake domains to get reference on |
59bad947 | 492 | * |
a6111f7b CW |
493 | * See intel_uncore_forcewake_get(). This variant places the onus |
494 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
907b28c5 | 495 | */ |
a6111f7b CW |
496 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, |
497 | enum forcewake_domains fw_domains) | |
498 | { | |
499 | assert_spin_locked(&dev_priv->uncore.lock); | |
500 | ||
501 | if (!dev_priv->uncore.funcs.force_wake_get) | |
502 | return; | |
503 | ||
504 | __intel_uncore_forcewake_get(dev_priv, fw_domains); | |
505 | } | |
506 | ||
507 | static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
508 | enum forcewake_domains fw_domains) | |
907b28c5 | 509 | { |
b2cff0db | 510 | struct intel_uncore_forcewake_domain *domain; |
907b28c5 | 511 | |
ab484f8f BW |
512 | if (!dev_priv->uncore.funcs.force_wake_put) |
513 | return; | |
514 | ||
b2cff0db CW |
515 | fw_domains &= dev_priv->uncore.fw_domains; |
516 | ||
33c582c1 | 517 | for_each_fw_domain_masked(domain, fw_domains, dev_priv) { |
b2cff0db CW |
518 | if (WARN_ON(domain->wake_count == 0)) |
519 | continue; | |
520 | ||
521 | if (--domain->wake_count) | |
522 | continue; | |
523 | ||
05a2fb15 | 524 | fw_domain_arm_timer(domain); |
aec347ab | 525 | } |
a6111f7b | 526 | } |
dc9fb09c | 527 | |
a6111f7b CW |
528 | /** |
529 | * intel_uncore_forcewake_put - release a forcewake domain reference | |
530 | * @dev_priv: i915 device instance | |
531 | * @fw_domains: forcewake domains to put references | |
532 | * | |
533 | * This function drops the device-level forcewakes for specified | |
534 | * domains obtained by intel_uncore_forcewake_get(). | |
535 | */ | |
536 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
537 | enum forcewake_domains fw_domains) | |
538 | { | |
539 | unsigned long irqflags; | |
540 | ||
541 | if (!dev_priv->uncore.funcs.force_wake_put) | |
542 | return; | |
543 | ||
544 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
545 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
907b28c5 CW |
546 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
547 | } | |
548 | ||
a6111f7b CW |
549 | /** |
550 | * intel_uncore_forcewake_put__locked - grab forcewake domain references | |
551 | * @dev_priv: i915 device instance | |
552 | * @fw_domains: forcewake domains to get reference on | |
553 | * | |
554 | * See intel_uncore_forcewake_put(). This variant places the onus | |
555 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
556 | */ | |
557 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
558 | enum forcewake_domains fw_domains) | |
559 | { | |
560 | assert_spin_locked(&dev_priv->uncore.lock); | |
561 | ||
562 | if (!dev_priv->uncore.funcs.force_wake_put) | |
563 | return; | |
564 | ||
565 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
566 | } | |
567 | ||
59bad947 | 568 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) |
e998c40f | 569 | { |
b2cff0db | 570 | struct intel_uncore_forcewake_domain *domain; |
b2cff0db | 571 | |
e998c40f PZ |
572 | if (!dev_priv->uncore.funcs.force_wake_get) |
573 | return; | |
574 | ||
33c582c1 | 575 | for_each_fw_domain(domain, dev_priv) |
b2cff0db | 576 | WARN_ON(domain->wake_count); |
e998c40f PZ |
577 | } |
578 | ||
907b28c5 | 579 | /* We give fast paths for the really cool registers */ |
40181697 | 580 | #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) |
907b28c5 | 581 | |
6863b76c TU |
582 | #define __gen6_reg_read_fw_domains(offset) \ |
583 | ({ \ | |
584 | enum forcewake_domains __fwd; \ | |
585 | if (NEEDS_FORCE_WAKE(offset)) \ | |
586 | __fwd = FORCEWAKE_RENDER; \ | |
587 | else \ | |
588 | __fwd = 0; \ | |
589 | __fwd; \ | |
590 | }) | |
591 | ||
1938e59a | 592 | #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) |
38fb6a40 | 593 | |
1938e59a D |
594 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
595 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
596 | REG_RANGE((reg), 0x5000, 0x8000) || \ | |
597 | REG_RANGE((reg), 0xB000, 0x12000) || \ | |
598 | REG_RANGE((reg), 0x2E000, 0x30000)) | |
599 | ||
600 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ | |
601 | (REG_RANGE((reg), 0x12000, 0x14000) || \ | |
602 | REG_RANGE((reg), 0x22000, 0x24000) || \ | |
603 | REG_RANGE((reg), 0x30000, 0x40000)) | |
604 | ||
6863b76c TU |
605 | #define __vlv_reg_read_fw_domains(offset) \ |
606 | ({ \ | |
607 | enum forcewake_domains __fwd = 0; \ | |
608 | if (!NEEDS_FORCE_WAKE(offset)) \ | |
609 | __fwd = 0; \ | |
610 | else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \ | |
611 | __fwd = FORCEWAKE_RENDER; \ | |
612 | else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \ | |
613 | __fwd = FORCEWAKE_MEDIA; \ | |
614 | __fwd; \ | |
615 | }) | |
616 | ||
617 | static const i915_reg_t gen8_shadowed_regs[] = { | |
6863b76c TU |
618 | GEN6_RPNSWREQ, |
619 | GEN6_RC_VIDEO_FREQ, | |
620 | RING_TAIL(RENDER_RING_BASE), | |
621 | RING_TAIL(GEN6_BSD_RING_BASE), | |
622 | RING_TAIL(VEBOX_RING_BASE), | |
623 | RING_TAIL(BLT_RING_BASE), | |
624 | /* TODO: Other registers are not yet used */ | |
625 | }; | |
626 | ||
627 | static bool is_gen8_shadowed(u32 offset) | |
628 | { | |
629 | int i; | |
630 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) | |
631 | if (offset == gen8_shadowed_regs[i].reg) | |
632 | return true; | |
633 | ||
634 | return false; | |
635 | } | |
636 | ||
637 | #define __gen8_reg_write_fw_domains(offset) \ | |
638 | ({ \ | |
639 | enum forcewake_domains __fwd; \ | |
640 | if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ | |
641 | __fwd = FORCEWAKE_RENDER; \ | |
642 | else \ | |
643 | __fwd = 0; \ | |
644 | __fwd; \ | |
645 | }) | |
646 | ||
1938e59a D |
647 | #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ |
648 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
db5ff4ac | 649 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
1938e59a | 650 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
db5ff4ac | 651 | REG_RANGE((reg), 0xB000, 0xB480) || \ |
1938e59a D |
652 | REG_RANGE((reg), 0xE000, 0xE800)) |
653 | ||
654 | #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ | |
655 | (REG_RANGE((reg), 0x8800, 0x8900) || \ | |
656 | REG_RANGE((reg), 0xD000, 0xD800) || \ | |
657 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
658 | REG_RANGE((reg), 0x1A000, 0x1C000) || \ | |
659 | REG_RANGE((reg), 0x1E800, 0x1EA00) || \ | |
db5ff4ac | 660 | REG_RANGE((reg), 0x30000, 0x38000)) |
1938e59a D |
661 | |
662 | #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ | |
663 | (REG_RANGE((reg), 0x4000, 0x5000) || \ | |
664 | REG_RANGE((reg), 0x8000, 0x8300) || \ | |
665 | REG_RANGE((reg), 0x8500, 0x8600) || \ | |
666 | REG_RANGE((reg), 0x9000, 0xB000) || \ | |
db5ff4ac | 667 | REG_RANGE((reg), 0xF000, 0x10000)) |
38fb6a40 | 668 | |
6863b76c TU |
669 | #define __chv_reg_read_fw_domains(offset) \ |
670 | ({ \ | |
671 | enum forcewake_domains __fwd = 0; \ | |
672 | if (!NEEDS_FORCE_WAKE(offset)) \ | |
673 | __fwd = 0; \ | |
674 | else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ | |
675 | __fwd = FORCEWAKE_RENDER; \ | |
676 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ | |
677 | __fwd = FORCEWAKE_MEDIA; \ | |
678 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ | |
679 | __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ | |
680 | __fwd; \ | |
681 | }) | |
682 | ||
683 | #define __chv_reg_write_fw_domains(offset) \ | |
684 | ({ \ | |
685 | enum forcewake_domains __fwd = 0; \ | |
686 | if (!NEEDS_FORCE_WAKE(offset) || is_gen8_shadowed(offset)) \ | |
687 | __fwd = 0; \ | |
688 | else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ | |
689 | __fwd = FORCEWAKE_RENDER; \ | |
690 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ | |
691 | __fwd = FORCEWAKE_MEDIA; \ | |
692 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ | |
693 | __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ | |
694 | __fwd; \ | |
695 | }) | |
696 | ||
4597a88a | 697 | #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ |
8ee558d8 | 698 | REG_RANGE((reg), 0xB00, 0x2000) |
4597a88a ZW |
699 | |
700 | #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
701 | (REG_RANGE((reg), 0x2000, 0x2700) || \ |
702 | REG_RANGE((reg), 0x3000, 0x4000) || \ | |
4597a88a | 703 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
8ee558d8 | 704 | REG_RANGE((reg), 0x8140, 0x8160) || \ |
4597a88a ZW |
705 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
706 | REG_RANGE((reg), 0x8C00, 0x8D00) || \ | |
707 | REG_RANGE((reg), 0xB000, 0xB480) || \ | |
8ee558d8 AG |
708 | REG_RANGE((reg), 0xE000, 0xE900) || \ |
709 | REG_RANGE((reg), 0x24400, 0x24800)) | |
4597a88a ZW |
710 | |
711 | #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
712 | (REG_RANGE((reg), 0x8130, 0x8140) || \ |
713 | REG_RANGE((reg), 0x8800, 0x8A00) || \ | |
4597a88a ZW |
714 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
715 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
716 | REG_RANGE((reg), 0x1A000, 0x1EA00) || \ | |
717 | REG_RANGE((reg), 0x30000, 0x40000)) | |
718 | ||
719 | #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ | |
720 | REG_RANGE((reg), 0x9400, 0x9800) | |
721 | ||
722 | #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ | |
0c8bfe52 | 723 | ((reg) < 0x40000 && \ |
4597a88a ZW |
724 | !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ |
725 | !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ | |
726 | !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ | |
727 | !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) | |
728 | ||
6863b76c TU |
729 | #define SKL_NEEDS_FORCE_WAKE(reg) \ |
730 | ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) | |
731 | ||
732 | #define __gen9_reg_read_fw_domains(offset) \ | |
733 | ({ \ | |
734 | enum forcewake_domains __fwd; \ | |
735 | if (!SKL_NEEDS_FORCE_WAKE(offset)) \ | |
736 | __fwd = 0; \ | |
737 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ | |
738 | __fwd = FORCEWAKE_RENDER; \ | |
739 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ | |
740 | __fwd = FORCEWAKE_MEDIA; \ | |
741 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ | |
742 | __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ | |
743 | else \ | |
744 | __fwd = FORCEWAKE_BLITTER; \ | |
745 | __fwd; \ | |
746 | }) | |
747 | ||
748 | static const i915_reg_t gen9_shadowed_regs[] = { | |
749 | RING_TAIL(RENDER_RING_BASE), | |
750 | RING_TAIL(GEN6_BSD_RING_BASE), | |
751 | RING_TAIL(VEBOX_RING_BASE), | |
752 | RING_TAIL(BLT_RING_BASE), | |
6863b76c TU |
753 | GEN6_RPNSWREQ, |
754 | GEN6_RC_VIDEO_FREQ, | |
755 | /* TODO: Other registers are not yet used */ | |
756 | }; | |
757 | ||
758 | static bool is_gen9_shadowed(u32 offset) | |
759 | { | |
760 | int i; | |
761 | for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) | |
762 | if (offset == gen9_shadowed_regs[i].reg) | |
763 | return true; | |
764 | ||
765 | return false; | |
766 | } | |
767 | ||
768 | #define __gen9_reg_write_fw_domains(offset) \ | |
769 | ({ \ | |
770 | enum forcewake_domains __fwd; \ | |
771 | if (!SKL_NEEDS_FORCE_WAKE(offset) || is_gen9_shadowed(offset)) \ | |
772 | __fwd = 0; \ | |
773 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ | |
774 | __fwd = FORCEWAKE_RENDER; \ | |
775 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ | |
776 | __fwd = FORCEWAKE_MEDIA; \ | |
777 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ | |
778 | __fwd = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ | |
779 | else \ | |
780 | __fwd = FORCEWAKE_BLITTER; \ | |
781 | __fwd; \ | |
782 | }) | |
783 | ||
907b28c5 CW |
784 | static void |
785 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
786 | { | |
787 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
788 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
789 | * hence harmless to write 0 into. */ | |
6af5d92f | 790 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
791 | } |
792 | ||
793 | static void | |
9c053501 MK |
794 | __unclaimed_reg_debug(struct drm_i915_private *dev_priv, |
795 | const i915_reg_t reg, | |
796 | const bool read, | |
797 | const bool before) | |
907b28c5 | 798 | { |
4bd0a25d MK |
799 | if (WARN(check_for_unclaimed_mmio(dev_priv), |
800 | "Unclaimed register detected %s %s register 0x%x\n", | |
801 | before ? "before" : "after", | |
802 | read ? "reading" : "writing to", | |
803 | i915_mmio_reg_offset(reg))) | |
48572edd | 804 | i915.mmio_debug--; /* Only report the first N failures */ |
907b28c5 CW |
805 | } |
806 | ||
9c053501 MK |
807 | static inline void |
808 | unclaimed_reg_debug(struct drm_i915_private *dev_priv, | |
809 | const i915_reg_t reg, | |
810 | const bool read, | |
811 | const bool before) | |
812 | { | |
813 | if (likely(!i915.mmio_debug)) | |
814 | return; | |
815 | ||
816 | __unclaimed_reg_debug(dev_priv, reg, read, before); | |
817 | } | |
818 | ||
51f67885 | 819 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 820 | u##x val = 0; \ |
da5827c3 | 821 | assert_rpm_wakelock_held(dev_priv); |
5d738795 | 822 | |
51f67885 | 823 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
824 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
825 | return val | |
826 | ||
51f67885 | 827 | #define __gen2_read(x) \ |
0b274481 | 828 | static u##x \ |
f0f59a00 | 829 | gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 830 | GEN2_READ_HEADER(x); \ |
3967018e | 831 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 832 | GEN2_READ_FOOTER; \ |
3967018e BW |
833 | } |
834 | ||
835 | #define __gen5_read(x) \ | |
836 | static u##x \ | |
f0f59a00 | 837 | gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
51f67885 | 838 | GEN2_READ_HEADER(x); \ |
3967018e BW |
839 | ilk_dummy_write(dev_priv); \ |
840 | val = __raw_i915_read##x(dev_priv, reg); \ | |
51f67885 | 841 | GEN2_READ_FOOTER; \ |
3967018e BW |
842 | } |
843 | ||
51f67885 CW |
844 | __gen5_read(8) |
845 | __gen5_read(16) | |
846 | __gen5_read(32) | |
847 | __gen5_read(64) | |
848 | __gen2_read(8) | |
849 | __gen2_read(16) | |
850 | __gen2_read(32) | |
851 | __gen2_read(64) | |
852 | ||
853 | #undef __gen5_read | |
854 | #undef __gen2_read | |
855 | ||
856 | #undef GEN2_READ_FOOTER | |
857 | #undef GEN2_READ_HEADER | |
858 | ||
859 | #define GEN6_READ_HEADER(x) \ | |
f0f59a00 | 860 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
861 | unsigned long irqflags; \ |
862 | u##x val = 0; \ | |
da5827c3 | 863 | assert_rpm_wakelock_held(dev_priv); \ |
9c053501 MK |
864 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
865 | unclaimed_reg_debug(dev_priv, reg, true, true) | |
51f67885 CW |
866 | |
867 | #define GEN6_READ_FOOTER \ | |
9c053501 | 868 | unclaimed_reg_debug(dev_priv, reg, true, false); \ |
51f67885 CW |
869 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
870 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
871 | return val | |
872 | ||
b208ba8e CW |
873 | static inline void __force_wake_auto(struct drm_i915_private *dev_priv, |
874 | enum forcewake_domains fw_domains) | |
b2cff0db CW |
875 | { |
876 | struct intel_uncore_forcewake_domain *domain; | |
b2cff0db CW |
877 | |
878 | if (WARN_ON(!fw_domains)) | |
879 | return; | |
880 | ||
881 | /* Ideally GCC would be constant-fold and eliminate this loop */ | |
33c582c1 | 882 | for_each_fw_domain_masked(domain, fw_domains, dev_priv) { |
b2cff0db | 883 | if (domain->wake_count) { |
33c582c1 | 884 | fw_domains &= ~domain->mask; |
b2cff0db CW |
885 | continue; |
886 | } | |
887 | ||
05a2fb15 | 888 | fw_domain_arm_timer(domain); |
b2cff0db CW |
889 | } |
890 | ||
891 | if (fw_domains) | |
892 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
893 | } | |
894 | ||
3967018e BW |
895 | #define __gen6_read(x) \ |
896 | static u##x \ | |
f0f59a00 | 897 | gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6863b76c | 898 | enum forcewake_domains fw_engine; \ |
51f67885 | 899 | GEN6_READ_HEADER(x); \ |
6863b76c TU |
900 | fw_engine = __gen6_reg_read_fw_domains(offset); \ |
901 | if (fw_engine) \ | |
902 | __force_wake_auto(dev_priv, fw_engine); \ | |
dc9fb09c | 903 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 904 | GEN6_READ_FOOTER; \ |
907b28c5 CW |
905 | } |
906 | ||
940aece4 D |
907 | #define __vlv_read(x) \ |
908 | static u##x \ | |
f0f59a00 | 909 | vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6863b76c | 910 | enum forcewake_domains fw_engine; \ |
51f67885 | 911 | GEN6_READ_HEADER(x); \ |
6863b76c | 912 | fw_engine = __vlv_reg_read_fw_domains(offset); \ |
6a42d0f4 | 913 | if (fw_engine) \ |
b208ba8e | 914 | __force_wake_auto(dev_priv, fw_engine); \ |
6fe72865 | 915 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 916 | GEN6_READ_FOOTER; \ |
940aece4 D |
917 | } |
918 | ||
1938e59a D |
919 | #define __chv_read(x) \ |
920 | static u##x \ | |
f0f59a00 | 921 | chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
6863b76c | 922 | enum forcewake_domains fw_engine; \ |
51f67885 | 923 | GEN6_READ_HEADER(x); \ |
6863b76c | 924 | fw_engine = __chv_reg_read_fw_domains(offset); \ |
6a42d0f4 | 925 | if (fw_engine) \ |
b208ba8e | 926 | __force_wake_auto(dev_priv, fw_engine); \ |
1938e59a | 927 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 928 | GEN6_READ_FOOTER; \ |
1938e59a | 929 | } |
940aece4 | 930 | |
4597a88a ZW |
931 | #define __gen9_read(x) \ |
932 | static u##x \ | |
f0f59a00 | 933 | gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
48c1026a | 934 | enum forcewake_domains fw_engine; \ |
51f67885 | 935 | GEN6_READ_HEADER(x); \ |
6863b76c | 936 | fw_engine = __gen9_reg_read_fw_domains(offset); \ |
b2cff0db | 937 | if (fw_engine) \ |
b208ba8e | 938 | __force_wake_auto(dev_priv, fw_engine); \ |
b2cff0db | 939 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 940 | GEN6_READ_FOOTER; \ |
4597a88a ZW |
941 | } |
942 | ||
943 | __gen9_read(8) | |
944 | __gen9_read(16) | |
945 | __gen9_read(32) | |
946 | __gen9_read(64) | |
1938e59a D |
947 | __chv_read(8) |
948 | __chv_read(16) | |
949 | __chv_read(32) | |
950 | __chv_read(64) | |
940aece4 D |
951 | __vlv_read(8) |
952 | __vlv_read(16) | |
953 | __vlv_read(32) | |
954 | __vlv_read(64) | |
3967018e BW |
955 | __gen6_read(8) |
956 | __gen6_read(16) | |
957 | __gen6_read(32) | |
958 | __gen6_read(64) | |
3967018e | 959 | |
4597a88a | 960 | #undef __gen9_read |
1938e59a | 961 | #undef __chv_read |
940aece4 | 962 | #undef __vlv_read |
3967018e | 963 | #undef __gen6_read |
51f67885 CW |
964 | #undef GEN6_READ_FOOTER |
965 | #undef GEN6_READ_HEADER | |
5d738795 | 966 | |
8a74db7a VS |
967 | #define VGPU_READ_HEADER(x) \ |
968 | unsigned long irqflags; \ | |
969 | u##x val = 0; \ | |
da5827c3 | 970 | assert_rpm_device_not_suspended(dev_priv); \ |
8a74db7a VS |
971 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
972 | ||
973 | #define VGPU_READ_FOOTER \ | |
974 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
975 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
976 | return val | |
977 | ||
978 | #define __vgpu_read(x) \ | |
979 | static u##x \ | |
f0f59a00 | 980 | vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ |
8a74db7a VS |
981 | VGPU_READ_HEADER(x); \ |
982 | val = __raw_i915_read##x(dev_priv, reg); \ | |
983 | VGPU_READ_FOOTER; \ | |
984 | } | |
985 | ||
986 | __vgpu_read(8) | |
987 | __vgpu_read(16) | |
988 | __vgpu_read(32) | |
989 | __vgpu_read(64) | |
990 | ||
991 | #undef __vgpu_read | |
992 | #undef VGPU_READ_FOOTER | |
993 | #undef VGPU_READ_HEADER | |
994 | ||
51f67885 | 995 | #define GEN2_WRITE_HEADER \ |
5d738795 | 996 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
da5827c3 | 997 | assert_rpm_wakelock_held(dev_priv); \ |
907b28c5 | 998 | |
51f67885 | 999 | #define GEN2_WRITE_FOOTER |
0d965301 | 1000 | |
51f67885 | 1001 | #define __gen2_write(x) \ |
0b274481 | 1002 | static void \ |
f0f59a00 | 1003 | gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1004 | GEN2_WRITE_HEADER; \ |
4032ef43 | 1005 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1006 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1007 | } |
1008 | ||
1009 | #define __gen5_write(x) \ | |
1010 | static void \ | |
f0f59a00 | 1011 | gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
51f67885 | 1012 | GEN2_WRITE_HEADER; \ |
4032ef43 BW |
1013 | ilk_dummy_write(dev_priv); \ |
1014 | __raw_i915_write##x(dev_priv, reg, val); \ | |
51f67885 | 1015 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
1016 | } |
1017 | ||
51f67885 CW |
1018 | __gen5_write(8) |
1019 | __gen5_write(16) | |
1020 | __gen5_write(32) | |
1021 | __gen5_write(64) | |
1022 | __gen2_write(8) | |
1023 | __gen2_write(16) | |
1024 | __gen2_write(32) | |
1025 | __gen2_write(64) | |
1026 | ||
1027 | #undef __gen5_write | |
1028 | #undef __gen2_write | |
1029 | ||
1030 | #undef GEN2_WRITE_FOOTER | |
1031 | #undef GEN2_WRITE_HEADER | |
1032 | ||
1033 | #define GEN6_WRITE_HEADER \ | |
f0f59a00 | 1034 | u32 offset = i915_mmio_reg_offset(reg); \ |
51f67885 CW |
1035 | unsigned long irqflags; \ |
1036 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
da5827c3 | 1037 | assert_rpm_wakelock_held(dev_priv); \ |
9c053501 MK |
1038 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ |
1039 | unclaimed_reg_debug(dev_priv, reg, false, true) | |
51f67885 CW |
1040 | |
1041 | #define GEN6_WRITE_FOOTER \ | |
9c053501 | 1042 | unclaimed_reg_debug(dev_priv, reg, false, false); \ |
51f67885 CW |
1043 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) |
1044 | ||
4032ef43 BW |
1045 | #define __gen6_write(x) \ |
1046 | static void \ | |
f0f59a00 | 1047 | gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
4032ef43 | 1048 | u32 __fifo_ret = 0; \ |
51f67885 | 1049 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 1050 | if (NEEDS_FORCE_WAKE(offset)) { \ |
4032ef43 BW |
1051 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
1052 | } \ | |
1053 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1054 | if (unlikely(__fifo_ret)) { \ | |
1055 | gen6_gt_check_fifodbg(dev_priv); \ | |
1056 | } \ | |
51f67885 | 1057 | GEN6_WRITE_FOOTER; \ |
4032ef43 BW |
1058 | } |
1059 | ||
1060 | #define __hsw_write(x) \ | |
1061 | static void \ | |
f0f59a00 | 1062 | hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
907b28c5 | 1063 | u32 __fifo_ret = 0; \ |
51f67885 | 1064 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 1065 | if (NEEDS_FORCE_WAKE(offset)) { \ |
907b28c5 CW |
1066 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
1067 | } \ | |
6af5d92f | 1068 | __raw_i915_write##x(dev_priv, reg, val); \ |
907b28c5 CW |
1069 | if (unlikely(__fifo_ret)) { \ |
1070 | gen6_gt_check_fifodbg(dev_priv); \ | |
1071 | } \ | |
51f67885 | 1072 | GEN6_WRITE_FOOTER; \ |
907b28c5 | 1073 | } |
3967018e | 1074 | |
ab2aa47e BW |
1075 | #define __gen8_write(x) \ |
1076 | static void \ | |
f0f59a00 | 1077 | gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
6863b76c | 1078 | enum forcewake_domains fw_engine; \ |
51f67885 | 1079 | GEN6_WRITE_HEADER; \ |
6863b76c TU |
1080 | fw_engine = __gen8_reg_write_fw_domains(offset); \ |
1081 | if (fw_engine) \ | |
1082 | __force_wake_auto(dev_priv, fw_engine); \ | |
b2cff0db | 1083 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1084 | GEN6_WRITE_FOOTER; \ |
ab2aa47e BW |
1085 | } |
1086 | ||
1938e59a D |
1087 | #define __chv_write(x) \ |
1088 | static void \ | |
f0f59a00 | 1089 | chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \ |
6863b76c | 1090 | enum forcewake_domains fw_engine; \ |
51f67885 | 1091 | GEN6_WRITE_HEADER; \ |
6863b76c | 1092 | fw_engine = __chv_reg_write_fw_domains(offset); \ |
6a42d0f4 | 1093 | if (fw_engine) \ |
b208ba8e | 1094 | __force_wake_auto(dev_priv, fw_engine); \ |
1938e59a | 1095 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1096 | GEN6_WRITE_FOOTER; \ |
1938e59a D |
1097 | } |
1098 | ||
4597a88a ZW |
1099 | #define __gen9_write(x) \ |
1100 | static void \ | |
f0f59a00 | 1101 | gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \ |
4597a88a | 1102 | bool trace) { \ |
48c1026a | 1103 | enum forcewake_domains fw_engine; \ |
51f67885 | 1104 | GEN6_WRITE_HEADER; \ |
6863b76c | 1105 | fw_engine = __gen9_reg_write_fw_domains(offset); \ |
b2cff0db | 1106 | if (fw_engine) \ |
b208ba8e | 1107 | __force_wake_auto(dev_priv, fw_engine); \ |
b2cff0db | 1108 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 1109 | GEN6_WRITE_FOOTER; \ |
4597a88a ZW |
1110 | } |
1111 | ||
1112 | __gen9_write(8) | |
1113 | __gen9_write(16) | |
1114 | __gen9_write(32) | |
1115 | __gen9_write(64) | |
1938e59a D |
1116 | __chv_write(8) |
1117 | __chv_write(16) | |
1118 | __chv_write(32) | |
1119 | __chv_write(64) | |
ab2aa47e BW |
1120 | __gen8_write(8) |
1121 | __gen8_write(16) | |
1122 | __gen8_write(32) | |
1123 | __gen8_write(64) | |
4032ef43 BW |
1124 | __hsw_write(8) |
1125 | __hsw_write(16) | |
1126 | __hsw_write(32) | |
1127 | __hsw_write(64) | |
1128 | __gen6_write(8) | |
1129 | __gen6_write(16) | |
1130 | __gen6_write(32) | |
1131 | __gen6_write(64) | |
4032ef43 | 1132 | |
4597a88a | 1133 | #undef __gen9_write |
1938e59a | 1134 | #undef __chv_write |
ab2aa47e | 1135 | #undef __gen8_write |
4032ef43 BW |
1136 | #undef __hsw_write |
1137 | #undef __gen6_write | |
51f67885 CW |
1138 | #undef GEN6_WRITE_FOOTER |
1139 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1140 | |
8a74db7a VS |
1141 | #define VGPU_WRITE_HEADER \ |
1142 | unsigned long irqflags; \ | |
1143 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
da5827c3 | 1144 | assert_rpm_device_not_suspended(dev_priv); \ |
8a74db7a VS |
1145 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
1146 | ||
1147 | #define VGPU_WRITE_FOOTER \ | |
1148 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
1149 | ||
1150 | #define __vgpu_write(x) \ | |
1151 | static void vgpu_write##x(struct drm_i915_private *dev_priv, \ | |
f0f59a00 | 1152 | i915_reg_t reg, u##x val, bool trace) { \ |
8a74db7a VS |
1153 | VGPU_WRITE_HEADER; \ |
1154 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1155 | VGPU_WRITE_FOOTER; \ | |
1156 | } | |
1157 | ||
1158 | __vgpu_write(8) | |
1159 | __vgpu_write(16) | |
1160 | __vgpu_write(32) | |
1161 | __vgpu_write(64) | |
1162 | ||
1163 | #undef __vgpu_write | |
1164 | #undef VGPU_WRITE_FOOTER | |
1165 | #undef VGPU_WRITE_HEADER | |
1166 | ||
43d942a7 YZ |
1167 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
1168 | do { \ | |
1169 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ | |
1170 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ | |
1171 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ | |
1172 | dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ | |
1173 | } while (0) | |
1174 | ||
1175 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ | |
1176 | do { \ | |
1177 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ | |
1178 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ | |
1179 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ | |
1180 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ | |
1181 | } while (0) | |
1182 | ||
05a2fb15 MK |
1183 | |
1184 | static void fw_domain_init(struct drm_i915_private *dev_priv, | |
48c1026a | 1185 | enum forcewake_domain_id domain_id, |
f0f59a00 VS |
1186 | i915_reg_t reg_set, |
1187 | i915_reg_t reg_ack) | |
05a2fb15 MK |
1188 | { |
1189 | struct intel_uncore_forcewake_domain *d; | |
1190 | ||
1191 | if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) | |
1192 | return; | |
1193 | ||
1194 | d = &dev_priv->uncore.fw_domain[domain_id]; | |
1195 | ||
1196 | WARN_ON(d->wake_count); | |
1197 | ||
1198 | d->wake_count = 0; | |
1199 | d->reg_set = reg_set; | |
1200 | d->reg_ack = reg_ack; | |
1201 | ||
1202 | if (IS_GEN6(dev_priv)) { | |
1203 | d->val_reset = 0; | |
1204 | d->val_set = FORCEWAKE_KERNEL; | |
1205 | d->val_clear = 0; | |
1206 | } else { | |
8543747c | 1207 | /* WaRsClearFWBitsAtReset:bdw,skl */ |
05a2fb15 MK |
1208 | d->val_reset = _MASKED_BIT_DISABLE(0xffff); |
1209 | d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); | |
1210 | d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); | |
1211 | } | |
1212 | ||
666a4537 | 1213 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
05a2fb15 MK |
1214 | d->reg_post = FORCEWAKE_ACK_VLV; |
1215 | else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) | |
1216 | d->reg_post = ECOBUS; | |
05a2fb15 MK |
1217 | |
1218 | d->i915 = dev_priv; | |
1219 | d->id = domain_id; | |
1220 | ||
33c582c1 TU |
1221 | BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); |
1222 | BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER)); | |
1223 | BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); | |
1224 | ||
1225 | d->mask = 1 << domain_id; | |
1226 | ||
a57a4a67 TU |
1227 | hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
1228 | d->timer.function = intel_uncore_fw_release_timer; | |
05a2fb15 MK |
1229 | |
1230 | dev_priv->uncore.fw_domains |= (1 << domain_id); | |
f9b3927a MK |
1231 | |
1232 | fw_domain_reset(d); | |
05a2fb15 MK |
1233 | } |
1234 | ||
dc97997a | 1235 | static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) |
0b274481 | 1236 | { |
2d1fe073 | 1237 | if (INTEL_INFO(dev_priv)->gen <= 5) |
3225b2f9 MK |
1238 | return; |
1239 | ||
dc97997a | 1240 | if (IS_GEN9(dev_priv)) { |
05a2fb15 MK |
1241 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
1242 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
1243 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1244 | FORCEWAKE_RENDER_GEN9, | |
1245 | FORCEWAKE_ACK_RENDER_GEN9); | |
1246 | fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER, | |
1247 | FORCEWAKE_BLITTER_GEN9, | |
1248 | FORCEWAKE_ACK_BLITTER_GEN9); | |
1249 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1250 | FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); | |
dc97997a | 1251 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
05a2fb15 | 1252 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
dc97997a | 1253 | if (!IS_CHERRYVIEW(dev_priv)) |
756c349d MK |
1254 | dev_priv->uncore.funcs.force_wake_put = |
1255 | fw_domains_put_with_fifo; | |
1256 | else | |
1257 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
05a2fb15 MK |
1258 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1259 | FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); | |
1260 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1261 | FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); | |
dc97997a | 1262 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
05a2fb15 MK |
1263 | dev_priv->uncore.funcs.force_wake_get = |
1264 | fw_domains_get_with_thread_status; | |
dc97997a | 1265 | if (IS_HASWELL(dev_priv)) |
3d7d0c85 VS |
1266 | dev_priv->uncore.funcs.force_wake_put = |
1267 | fw_domains_put_with_fifo; | |
1268 | else | |
1269 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
05a2fb15 MK |
1270 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1271 | FORCEWAKE_MT, FORCEWAKE_ACK_HSW); | |
dc97997a | 1272 | } else if (IS_IVYBRIDGE(dev_priv)) { |
0b274481 BW |
1273 | u32 ecobus; |
1274 | ||
1275 | /* IVB configs may use multi-threaded forcewake */ | |
1276 | ||
1277 | /* A small trick here - if the bios hasn't configured | |
1278 | * MT forcewake, and if the device is in RC6, then | |
1279 | * force_wake_mt_get will not wake the device and the | |
1280 | * ECOBUS read will return zero. Which will be | |
1281 | * (correctly) interpreted by the test below as MT | |
1282 | * forcewake being disabled. | |
1283 | */ | |
05a2fb15 MK |
1284 | dev_priv->uncore.funcs.force_wake_get = |
1285 | fw_domains_get_with_thread_status; | |
1286 | dev_priv->uncore.funcs.force_wake_put = | |
1287 | fw_domains_put_with_fifo; | |
1288 | ||
f9b3927a MK |
1289 | /* We need to init first for ECOBUS access and then |
1290 | * determine later if we want to reinit, in case of MT access is | |
6ea2556f MK |
1291 | * not working. In this stage we don't know which flavour this |
1292 | * ivb is, so it is better to reset also the gen6 fw registers | |
1293 | * before the ecobus check. | |
f9b3927a | 1294 | */ |
6ea2556f MK |
1295 | |
1296 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); | |
1297 | __raw_posting_read(dev_priv, ECOBUS); | |
1298 | ||
05a2fb15 MK |
1299 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1300 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); | |
f9b3927a | 1301 | |
556ab7a6 | 1302 | spin_lock_irq(&dev_priv->uncore.lock); |
05a2fb15 | 1303 | fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL); |
0b274481 | 1304 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
05a2fb15 | 1305 | fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL); |
556ab7a6 | 1306 | spin_unlock_irq(&dev_priv->uncore.lock); |
0b274481 | 1307 | |
05a2fb15 | 1308 | if (!(ecobus & FORCEWAKE_MT_ENABLE)) { |
0b274481 BW |
1309 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
1310 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
05a2fb15 MK |
1311 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1312 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 | 1313 | } |
dc97997a | 1314 | } else if (IS_GEN6(dev_priv)) { |
0b274481 | 1315 | dev_priv->uncore.funcs.force_wake_get = |
05a2fb15 | 1316 | fw_domains_get_with_thread_status; |
0b274481 | 1317 | dev_priv->uncore.funcs.force_wake_put = |
05a2fb15 MK |
1318 | fw_domains_put_with_fifo; |
1319 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1320 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 | 1321 | } |
3225b2f9 MK |
1322 | |
1323 | /* All future platforms are expected to require complex power gating */ | |
1324 | WARN_ON(dev_priv->uncore.fw_domains == 0); | |
f9b3927a MK |
1325 | } |
1326 | ||
dc97997a | 1327 | void intel_uncore_init(struct drm_i915_private *dev_priv) |
f9b3927a | 1328 | { |
dc97997a | 1329 | i915_check_vgpu(dev_priv); |
cf9d2890 | 1330 | |
3accaf7e | 1331 | intel_uncore_edram_detect(dev_priv); |
dc97997a CW |
1332 | intel_uncore_fw_domains_init(dev_priv); |
1333 | __intel_uncore_early_sanitize(dev_priv, false); | |
0b274481 | 1334 | |
75714940 MK |
1335 | dev_priv->uncore.unclaimed_mmio_check = 1; |
1336 | ||
dc97997a | 1337 | switch (INTEL_INFO(dev_priv)->gen) { |
ab2aa47e | 1338 | default: |
4597a88a ZW |
1339 | case 9: |
1340 | ASSIGN_WRITE_MMIO_VFUNCS(gen9); | |
1341 | ASSIGN_READ_MMIO_VFUNCS(gen9); | |
1342 | break; | |
1343 | case 8: | |
dc97997a | 1344 | if (IS_CHERRYVIEW(dev_priv)) { |
43d942a7 YZ |
1345 | ASSIGN_WRITE_MMIO_VFUNCS(chv); |
1346 | ASSIGN_READ_MMIO_VFUNCS(chv); | |
1938e59a D |
1347 | |
1348 | } else { | |
43d942a7 YZ |
1349 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
1350 | ASSIGN_READ_MMIO_VFUNCS(gen6); | |
1938e59a | 1351 | } |
ab2aa47e | 1352 | break; |
3967018e BW |
1353 | case 7: |
1354 | case 6: | |
dc97997a | 1355 | if (IS_HASWELL(dev_priv)) { |
43d942a7 | 1356 | ASSIGN_WRITE_MMIO_VFUNCS(hsw); |
4032ef43 | 1357 | } else { |
43d942a7 | 1358 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
4032ef43 | 1359 | } |
940aece4 | 1360 | |
dc97997a | 1361 | if (IS_VALLEYVIEW(dev_priv)) { |
43d942a7 | 1362 | ASSIGN_READ_MMIO_VFUNCS(vlv); |
940aece4 | 1363 | } else { |
43d942a7 | 1364 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
940aece4 | 1365 | } |
3967018e BW |
1366 | break; |
1367 | case 5: | |
43d942a7 YZ |
1368 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
1369 | ASSIGN_READ_MMIO_VFUNCS(gen5); | |
3967018e BW |
1370 | break; |
1371 | case 4: | |
1372 | case 3: | |
1373 | case 2: | |
51f67885 CW |
1374 | ASSIGN_WRITE_MMIO_VFUNCS(gen2); |
1375 | ASSIGN_READ_MMIO_VFUNCS(gen2); | |
3967018e BW |
1376 | break; |
1377 | } | |
ed493883 | 1378 | |
c033666a | 1379 | if (intel_vgpu_active(dev_priv)) { |
3be0bf5a YZ |
1380 | ASSIGN_WRITE_MMIO_VFUNCS(vgpu); |
1381 | ASSIGN_READ_MMIO_VFUNCS(vgpu); | |
1382 | } | |
1383 | ||
dc97997a | 1384 | i915_check_and_clear_faults(dev_priv); |
0b274481 | 1385 | } |
43d942a7 YZ |
1386 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
1387 | #undef ASSIGN_READ_MMIO_VFUNCS | |
0b274481 | 1388 | |
dc97997a | 1389 | void intel_uncore_fini(struct drm_i915_private *dev_priv) |
0b274481 | 1390 | { |
0b274481 | 1391 | /* Paranoia: make sure we have disabled everything before we exit. */ |
dc97997a CW |
1392 | intel_uncore_sanitize(dev_priv); |
1393 | intel_uncore_forcewake_reset(dev_priv, false); | |
0b274481 BW |
1394 | } |
1395 | ||
ae5702d2 | 1396 | #define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1) |
af76ae44 | 1397 | |
907b28c5 | 1398 | static const struct register_whitelist { |
f0f59a00 | 1399 | i915_reg_t offset_ldw, offset_udw; |
907b28c5 | 1400 | uint32_t size; |
af76ae44 DL |
1401 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
1402 | uint32_t gen_bitmask; | |
907b28c5 | 1403 | } whitelist[] = { |
8697600b VS |
1404 | { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), |
1405 | .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), | |
1406 | .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, | |
907b28c5 CW |
1407 | }; |
1408 | ||
1409 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1410 | void *data, struct drm_file *file) | |
1411 | { | |
fac5e23e | 1412 | struct drm_i915_private *dev_priv = to_i915(dev); |
907b28c5 CW |
1413 | struct drm_i915_reg_read *reg = data; |
1414 | struct register_whitelist const *entry = whitelist; | |
648a9bc5 | 1415 | unsigned size; |
f0f59a00 | 1416 | i915_reg_t offset_ldw, offset_udw; |
cf67c70f | 1417 | int i, ret = 0; |
907b28c5 CW |
1418 | |
1419 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
f0f59a00 | 1420 | if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && |
ae5702d2 | 1421 | (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask)) |
907b28c5 CW |
1422 | break; |
1423 | } | |
1424 | ||
1425 | if (i == ARRAY_SIZE(whitelist)) | |
1426 | return -EINVAL; | |
1427 | ||
648a9bc5 CW |
1428 | /* We use the low bits to encode extra flags as the register should |
1429 | * be naturally aligned (and those that are not so aligned merely | |
1430 | * limit the available flags for that register). | |
1431 | */ | |
8697600b VS |
1432 | offset_ldw = entry->offset_ldw; |
1433 | offset_udw = entry->offset_udw; | |
648a9bc5 | 1434 | size = entry->size; |
f0f59a00 | 1435 | size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw); |
648a9bc5 | 1436 | |
cf67c70f PZ |
1437 | intel_runtime_pm_get(dev_priv); |
1438 | ||
648a9bc5 CW |
1439 | switch (size) { |
1440 | case 8 | 1: | |
8697600b | 1441 | reg->val = I915_READ64_2x32(offset_ldw, offset_udw); |
648a9bc5 | 1442 | break; |
907b28c5 | 1443 | case 8: |
8697600b | 1444 | reg->val = I915_READ64(offset_ldw); |
907b28c5 CW |
1445 | break; |
1446 | case 4: | |
8697600b | 1447 | reg->val = I915_READ(offset_ldw); |
907b28c5 CW |
1448 | break; |
1449 | case 2: | |
8697600b | 1450 | reg->val = I915_READ16(offset_ldw); |
907b28c5 CW |
1451 | break; |
1452 | case 1: | |
8697600b | 1453 | reg->val = I915_READ8(offset_ldw); |
907b28c5 CW |
1454 | break; |
1455 | default: | |
cf67c70f PZ |
1456 | ret = -EINVAL; |
1457 | goto out; | |
907b28c5 CW |
1458 | } |
1459 | ||
cf67c70f PZ |
1460 | out: |
1461 | intel_runtime_pm_put(dev_priv); | |
1462 | return ret; | |
907b28c5 CW |
1463 | } |
1464 | ||
dc97997a | 1465 | static int i915_reset_complete(struct pci_dev *pdev) |
907b28c5 CW |
1466 | { |
1467 | u8 gdrst; | |
dc97997a | 1468 | pci_read_config_byte(pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1469 | return (gdrst & GRDOM_RESET_STATUS) == 0; |
907b28c5 CW |
1470 | } |
1471 | ||
dc97997a | 1472 | static int i915_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
907b28c5 | 1473 | { |
91c8a326 | 1474 | struct pci_dev *pdev = dev_priv->drm.pdev; |
dc97997a | 1475 | |
73bbf6bd | 1476 | /* assert reset for at least 20 usec */ |
dc97997a | 1477 | pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
73bbf6bd | 1478 | udelay(20); |
dc97997a | 1479 | pci_write_config_byte(pdev, I915_GDRST, 0); |
907b28c5 | 1480 | |
dc97997a | 1481 | return wait_for(i915_reset_complete(pdev), 500); |
73bbf6bd VS |
1482 | } |
1483 | ||
dc97997a | 1484 | static int g4x_reset_complete(struct pci_dev *pdev) |
73bbf6bd VS |
1485 | { |
1486 | u8 gdrst; | |
dc97997a | 1487 | pci_read_config_byte(pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1488 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
907b28c5 CW |
1489 | } |
1490 | ||
dc97997a | 1491 | static int g33_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
408d4b9e | 1492 | { |
91c8a326 | 1493 | struct pci_dev *pdev = dev_priv->drm.pdev; |
dc97997a CW |
1494 | pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
1495 | return wait_for(g4x_reset_complete(pdev), 500); | |
408d4b9e VS |
1496 | } |
1497 | ||
dc97997a | 1498 | static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
fa4f53c4 | 1499 | { |
91c8a326 | 1500 | struct pci_dev *pdev = dev_priv->drm.pdev; |
fa4f53c4 VS |
1501 | int ret; |
1502 | ||
dc97997a | 1503 | pci_write_config_byte(pdev, I915_GDRST, |
fa4f53c4 | 1504 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
dc97997a | 1505 | ret = wait_for(g4x_reset_complete(pdev), 500); |
fa4f53c4 VS |
1506 | if (ret) |
1507 | return ret; | |
1508 | ||
1509 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1510 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); | |
1511 | POSTING_READ(VDECCLK_GATE_D); | |
1512 | ||
dc97997a | 1513 | pci_write_config_byte(pdev, I915_GDRST, |
fa4f53c4 | 1514 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
dc97997a | 1515 | ret = wait_for(g4x_reset_complete(pdev), 500); |
fa4f53c4 VS |
1516 | if (ret) |
1517 | return ret; | |
1518 | ||
1519 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1520 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); | |
1521 | POSTING_READ(VDECCLK_GATE_D); | |
1522 | ||
dc97997a | 1523 | pci_write_config_byte(pdev, I915_GDRST, 0); |
fa4f53c4 VS |
1524 | |
1525 | return 0; | |
1526 | } | |
1527 | ||
dc97997a CW |
1528 | static int ironlake_do_reset(struct drm_i915_private *dev_priv, |
1529 | unsigned engine_mask) | |
907b28c5 | 1530 | { |
907b28c5 CW |
1531 | int ret; |
1532 | ||
c039b7f2 | 1533 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1534 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
87273b71 CW |
1535 | ret = intel_wait_for_register(dev_priv, |
1536 | ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, | |
1537 | 500); | |
907b28c5 CW |
1538 | if (ret) |
1539 | return ret; | |
1540 | ||
c039b7f2 | 1541 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1542 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
87273b71 CW |
1543 | ret = intel_wait_for_register(dev_priv, |
1544 | ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0, | |
1545 | 500); | |
9aa7250f VS |
1546 | if (ret) |
1547 | return ret; | |
1548 | ||
c039b7f2 | 1549 | I915_WRITE(ILK_GDSR, 0); |
9aa7250f VS |
1550 | |
1551 | return 0; | |
907b28c5 CW |
1552 | } |
1553 | ||
ee4b6faf MK |
1554 | /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */ |
1555 | static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, | |
1556 | u32 hw_domain_mask) | |
907b28c5 | 1557 | { |
907b28c5 CW |
1558 | /* GEN6_GDRST is not in the gt power well, no need to check |
1559 | * for fifo space for the write or forcewake the chip for | |
1560 | * the read | |
1561 | */ | |
ee4b6faf | 1562 | __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask); |
907b28c5 | 1563 | |
ee4b6faf | 1564 | /* Spin waiting for the device to ack the reset requests */ |
4a17fe13 CW |
1565 | return intel_wait_for_register_fw(dev_priv, |
1566 | GEN6_GDRST, hw_domain_mask, 0, | |
1567 | 500); | |
ee4b6faf MK |
1568 | } |
1569 | ||
1570 | /** | |
1571 | * gen6_reset_engines - reset individual engines | |
dc97997a | 1572 | * @dev_priv: i915 device |
ee4b6faf MK |
1573 | * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset |
1574 | * | |
1575 | * This function will reset the individual engines that are set in engine_mask. | |
1576 | * If you provide ALL_ENGINES as mask, full global domain reset will be issued. | |
1577 | * | |
1578 | * Note: It is responsibility of the caller to handle the difference between | |
1579 | * asking full domain reset versus reset for all available individual engines. | |
1580 | * | |
1581 | * Returns 0 on success, nonzero on error. | |
1582 | */ | |
dc97997a CW |
1583 | static int gen6_reset_engines(struct drm_i915_private *dev_priv, |
1584 | unsigned engine_mask) | |
ee4b6faf | 1585 | { |
ee4b6faf MK |
1586 | struct intel_engine_cs *engine; |
1587 | const u32 hw_engine_mask[I915_NUM_ENGINES] = { | |
1588 | [RCS] = GEN6_GRDOM_RENDER, | |
1589 | [BCS] = GEN6_GRDOM_BLT, | |
1590 | [VCS] = GEN6_GRDOM_MEDIA, | |
1591 | [VCS2] = GEN8_GRDOM_MEDIA2, | |
1592 | [VECS] = GEN6_GRDOM_VECS, | |
1593 | }; | |
1594 | u32 hw_mask; | |
1595 | int ret; | |
1596 | ||
1597 | if (engine_mask == ALL_ENGINES) { | |
1598 | hw_mask = GEN6_GRDOM_FULL; | |
1599 | } else { | |
1600 | hw_mask = 0; | |
1601 | for_each_engine_masked(engine, dev_priv, engine_mask) | |
1602 | hw_mask |= hw_engine_mask[engine->id]; | |
1603 | } | |
1604 | ||
1605 | ret = gen6_hw_domain_reset(dev_priv, hw_mask); | |
907b28c5 | 1606 | |
dc97997a | 1607 | intel_uncore_forcewake_reset(dev_priv, true); |
5babf0fc | 1608 | |
907b28c5 CW |
1609 | return ret; |
1610 | } | |
1611 | ||
1758b90e CW |
1612 | /** |
1613 | * intel_wait_for_register_fw - wait until register matches expected state | |
1614 | * @dev_priv: the i915 device | |
1615 | * @reg: the register to read | |
1616 | * @mask: mask to apply to register value | |
1617 | * @value: expected value | |
1618 | * @timeout_ms: timeout in millisecond | |
1619 | * | |
1620 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1621 | * @value after applying the @mask, i.e. it waits until :: |
1622 | * | |
1623 | * (I915_READ_FW(reg) & mask) == value | |
1624 | * | |
1758b90e CW |
1625 | * Otherwise, the wait will timeout after @timeout_ms milliseconds. |
1626 | * | |
1627 | * Note that this routine assumes the caller holds forcewake asserted, it is | |
1628 | * not suitable for very long waits. See intel_wait_for_register() if you | |
1629 | * wish to wait without holding forcewake for the duration (i.e. you expect | |
1630 | * the wait to be slow). | |
1631 | * | |
1632 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1633 | */ | |
1634 | int intel_wait_for_register_fw(struct drm_i915_private *dev_priv, | |
1635 | i915_reg_t reg, | |
1636 | const u32 mask, | |
1637 | const u32 value, | |
1638 | const unsigned long timeout_ms) | |
1639 | { | |
1640 | #define done ((I915_READ_FW(reg) & mask) == value) | |
1641 | int ret = wait_for_us(done, 2); | |
1642 | if (ret) | |
1643 | ret = wait_for(done, timeout_ms); | |
1644 | return ret; | |
1645 | #undef done | |
1646 | } | |
1647 | ||
1648 | /** | |
1649 | * intel_wait_for_register - wait until register matches expected state | |
1650 | * @dev_priv: the i915 device | |
1651 | * @reg: the register to read | |
1652 | * @mask: mask to apply to register value | |
1653 | * @value: expected value | |
1654 | * @timeout_ms: timeout in millisecond | |
1655 | * | |
1656 | * This routine waits until the target register @reg contains the expected | |
3d466cd6 DV |
1657 | * @value after applying the @mask, i.e. it waits until :: |
1658 | * | |
1659 | * (I915_READ(reg) & mask) == value | |
1660 | * | |
1758b90e CW |
1661 | * Otherwise, the wait will timeout after @timeout_ms milliseconds. |
1662 | * | |
1663 | * Returns 0 if the register matches the desired condition, or -ETIMEOUT. | |
1664 | */ | |
1665 | int intel_wait_for_register(struct drm_i915_private *dev_priv, | |
1666 | i915_reg_t reg, | |
1667 | const u32 mask, | |
1668 | const u32 value, | |
1669 | const unsigned long timeout_ms) | |
7fd2d269 | 1670 | { |
1758b90e CW |
1671 | |
1672 | unsigned fw = | |
1673 | intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ); | |
1674 | int ret; | |
1675 | ||
1676 | intel_uncore_forcewake_get(dev_priv, fw); | |
1677 | ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2); | |
1678 | intel_uncore_forcewake_put(dev_priv, fw); | |
1679 | if (ret) | |
1680 | ret = wait_for((I915_READ_NOTRACE(reg) & mask) == value, | |
1681 | timeout_ms); | |
1682 | ||
1683 | return ret; | |
d431440c TE |
1684 | } |
1685 | ||
1686 | static int gen8_request_engine_reset(struct intel_engine_cs *engine) | |
1687 | { | |
c033666a | 1688 | struct drm_i915_private *dev_priv = engine->i915; |
d431440c | 1689 | int ret; |
d431440c TE |
1690 | |
1691 | I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), | |
1692 | _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); | |
1693 | ||
1758b90e CW |
1694 | ret = intel_wait_for_register_fw(dev_priv, |
1695 | RING_RESET_CTL(engine->mmio_base), | |
1696 | RESET_CTL_READY_TO_RESET, | |
1697 | RESET_CTL_READY_TO_RESET, | |
1698 | 700); | |
d431440c TE |
1699 | if (ret) |
1700 | DRM_ERROR("%s: reset request timeout\n", engine->name); | |
1701 | ||
1702 | return ret; | |
1703 | } | |
1704 | ||
1705 | static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine) | |
1706 | { | |
c033666a | 1707 | struct drm_i915_private *dev_priv = engine->i915; |
d431440c TE |
1708 | |
1709 | I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base), | |
1710 | _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); | |
7fd2d269 MK |
1711 | } |
1712 | ||
dc97997a CW |
1713 | static int gen8_reset_engines(struct drm_i915_private *dev_priv, |
1714 | unsigned engine_mask) | |
7fd2d269 | 1715 | { |
7fd2d269 | 1716 | struct intel_engine_cs *engine; |
7fd2d269 | 1717 | |
ee4b6faf | 1718 | for_each_engine_masked(engine, dev_priv, engine_mask) |
d431440c | 1719 | if (gen8_request_engine_reset(engine)) |
7fd2d269 | 1720 | goto not_ready; |
7fd2d269 | 1721 | |
dc97997a | 1722 | return gen6_reset_engines(dev_priv, engine_mask); |
7fd2d269 MK |
1723 | |
1724 | not_ready: | |
ee4b6faf | 1725 | for_each_engine_masked(engine, dev_priv, engine_mask) |
d431440c | 1726 | gen8_unrequest_engine_reset(engine); |
7fd2d269 MK |
1727 | |
1728 | return -EIO; | |
1729 | } | |
1730 | ||
dc97997a CW |
1731 | typedef int (*reset_func)(struct drm_i915_private *, unsigned engine_mask); |
1732 | ||
1733 | static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) | |
907b28c5 | 1734 | { |
b1330fbb CW |
1735 | if (!i915.reset) |
1736 | return NULL; | |
1737 | ||
dc97997a | 1738 | if (INTEL_INFO(dev_priv)->gen >= 8) |
ee4b6faf | 1739 | return gen8_reset_engines; |
dc97997a | 1740 | else if (INTEL_INFO(dev_priv)->gen >= 6) |
ee4b6faf | 1741 | return gen6_reset_engines; |
dc97997a | 1742 | else if (IS_GEN5(dev_priv)) |
49e4d842 | 1743 | return ironlake_do_reset; |
dc97997a | 1744 | else if (IS_G4X(dev_priv)) |
49e4d842 | 1745 | return g4x_do_reset; |
dc97997a | 1746 | else if (IS_G33(dev_priv)) |
49e4d842 | 1747 | return g33_do_reset; |
dc97997a | 1748 | else if (INTEL_INFO(dev_priv)->gen >= 3) |
49e4d842 | 1749 | return i915_do_reset; |
542c184f | 1750 | else |
49e4d842 CW |
1751 | return NULL; |
1752 | } | |
1753 | ||
dc97997a | 1754 | int intel_gpu_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) |
49e4d842 | 1755 | { |
dc97997a | 1756 | reset_func reset; |
99106bc1 | 1757 | int ret; |
49e4d842 | 1758 | |
dc97997a | 1759 | reset = intel_get_gpu_reset(dev_priv); |
49e4d842 | 1760 | if (reset == NULL) |
542c184f | 1761 | return -ENODEV; |
49e4d842 | 1762 | |
99106bc1 MK |
1763 | /* If the power well sleeps during the reset, the reset |
1764 | * request may be dropped and never completes (causing -EIO). | |
1765 | */ | |
1766 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
dc97997a | 1767 | ret = reset(dev_priv, engine_mask); |
99106bc1 MK |
1768 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
1769 | ||
1770 | return ret; | |
49e4d842 CW |
1771 | } |
1772 | ||
dc97997a | 1773 | bool intel_has_gpu_reset(struct drm_i915_private *dev_priv) |
49e4d842 | 1774 | { |
dc97997a | 1775 | return intel_get_gpu_reset(dev_priv) != NULL; |
907b28c5 CW |
1776 | } |
1777 | ||
6b332fa2 AS |
1778 | int intel_guc_reset(struct drm_i915_private *dev_priv) |
1779 | { | |
1780 | int ret; | |
1781 | unsigned long irqflags; | |
1782 | ||
1a3d1898 | 1783 | if (!HAS_GUC(dev_priv)) |
6b332fa2 AS |
1784 | return -EINVAL; |
1785 | ||
1786 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
1787 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
1788 | ||
1789 | ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC); | |
1790 | ||
1791 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
1792 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
1793 | ||
1794 | return ret; | |
1795 | } | |
1796 | ||
fc97618b | 1797 | bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv) |
907b28c5 | 1798 | { |
fc97618b | 1799 | return check_for_unclaimed_mmio(dev_priv); |
907b28c5 | 1800 | } |
75714940 | 1801 | |
bc3b9346 | 1802 | bool |
75714940 MK |
1803 | intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv) |
1804 | { | |
1805 | if (unlikely(i915.mmio_debug || | |
1806 | dev_priv->uncore.unclaimed_mmio_check <= 0)) | |
bc3b9346 | 1807 | return false; |
75714940 MK |
1808 | |
1809 | if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) { | |
1810 | DRM_DEBUG("Unclaimed register detected, " | |
1811 | "enabling oneshot unclaimed register reporting. " | |
1812 | "Please use i915.mmio_debug=N for more information.\n"); | |
1813 | i915.mmio_debug++; | |
1814 | dev_priv->uncore.unclaimed_mmio_check--; | |
bc3b9346 | 1815 | return true; |
75714940 | 1816 | } |
bc3b9346 MK |
1817 | |
1818 | return false; | |
75714940 | 1819 | } |
3756685a TU |
1820 | |
1821 | static enum forcewake_domains | |
1822 | intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, | |
1823 | i915_reg_t reg) | |
1824 | { | |
1825 | enum forcewake_domains fw_domains; | |
1826 | ||
c033666a | 1827 | if (intel_vgpu_active(dev_priv)) |
3756685a TU |
1828 | return 0; |
1829 | ||
c033666a | 1830 | switch (INTEL_GEN(dev_priv)) { |
3756685a TU |
1831 | case 9: |
1832 | fw_domains = __gen9_reg_read_fw_domains(i915_mmio_reg_offset(reg)); | |
1833 | break; | |
1834 | case 8: | |
1835 | if (IS_CHERRYVIEW(dev_priv)) | |
1836 | fw_domains = __chv_reg_read_fw_domains(i915_mmio_reg_offset(reg)); | |
1837 | else | |
1838 | fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg)); | |
1839 | break; | |
1840 | case 7: | |
1841 | case 6: | |
1842 | if (IS_VALLEYVIEW(dev_priv)) | |
1843 | fw_domains = __vlv_reg_read_fw_domains(i915_mmio_reg_offset(reg)); | |
1844 | else | |
1845 | fw_domains = __gen6_reg_read_fw_domains(i915_mmio_reg_offset(reg)); | |
1846 | break; | |
1847 | default: | |
1848 | MISSING_CASE(INTEL_INFO(dev_priv)->gen); | |
1849 | case 5: /* forcewake was introduced with gen6 */ | |
1850 | case 4: | |
1851 | case 3: | |
1852 | case 2: | |
1853 | return 0; | |
1854 | } | |
1855 | ||
1856 | WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); | |
1857 | ||
1858 | return fw_domains; | |
1859 | } | |
1860 | ||
1861 | static enum forcewake_domains | |
1862 | intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, | |
1863 | i915_reg_t reg) | |
1864 | { | |
1865 | enum forcewake_domains fw_domains; | |
1866 | ||
c033666a | 1867 | if (intel_vgpu_active(dev_priv)) |
3756685a TU |
1868 | return 0; |
1869 | ||
c033666a | 1870 | switch (INTEL_GEN(dev_priv)) { |
3756685a TU |
1871 | case 9: |
1872 | fw_domains = __gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg)); | |
1873 | break; | |
1874 | case 8: | |
1875 | if (IS_CHERRYVIEW(dev_priv)) | |
1876 | fw_domains = __chv_reg_write_fw_domains(i915_mmio_reg_offset(reg)); | |
1877 | else | |
1878 | fw_domains = __gen8_reg_write_fw_domains(i915_mmio_reg_offset(reg)); | |
1879 | break; | |
1880 | case 7: | |
1881 | case 6: | |
1882 | fw_domains = FORCEWAKE_RENDER; | |
1883 | break; | |
1884 | default: | |
1885 | MISSING_CASE(INTEL_INFO(dev_priv)->gen); | |
1886 | case 5: | |
1887 | case 4: | |
1888 | case 3: | |
1889 | case 2: | |
1890 | return 0; | |
1891 | } | |
1892 | ||
1893 | WARN_ON(fw_domains & ~dev_priv->uncore.fw_domains); | |
1894 | ||
1895 | return fw_domains; | |
1896 | } | |
1897 | ||
1898 | /** | |
1899 | * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access | |
1900 | * a register | |
1901 | * @dev_priv: pointer to struct drm_i915_private | |
1902 | * @reg: register in question | |
1903 | * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE | |
1904 | * | |
1905 | * Returns a set of forcewake domains required to be taken with for example | |
1906 | * intel_uncore_forcewake_get for the specified register to be accessible in the | |
1907 | * specified mode (read, write or read/write) with raw mmio accessors. | |
1908 | * | |
1909 | * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the | |
1910 | * callers to do FIFO management on their own or risk losing writes. | |
1911 | */ | |
1912 | enum forcewake_domains | |
1913 | intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, | |
1914 | i915_reg_t reg, unsigned int op) | |
1915 | { | |
1916 | enum forcewake_domains fw_domains = 0; | |
1917 | ||
1918 | WARN_ON(!op); | |
1919 | ||
1920 | if (op & FW_REG_READ) | |
1921 | fw_domains = intel_uncore_forcewake_for_read(dev_priv, reg); | |
1922 | ||
1923 | if (op & FW_REG_WRITE) | |
1924 | fw_domains |= intel_uncore_forcewake_for_write(dev_priv, reg); | |
1925 | ||
1926 | return fw_domains; | |
1927 | } |