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drm/i915: Remove duplicate intel_uncore_forcewake_reset.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_uncore.c
CommitLineData
907b28c5
CW		 1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "i915_drv.h"
25#include "intel_drv.h"
26
27#define FORCEWAKE_ACK_TIMEOUT_MS 2
28
6af5d92f
CW		 29#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
43
907b28c5
CW		 44static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
45{
46 u32 gt_thread_status_mask;
47
48 if (IS_HASWELL(dev_priv->dev))
49 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
50 else
51 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
52
53 /* w/a for a sporadic read returning 0 by waiting for the GT
54 * thread to wake up.
55 */
6af5d92f 56 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
907b28c5
CW		 57 DRM_ERROR("GT thread status wait timed out\n");
58}
59
60static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
61{
6af5d92f
CW		 62 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
63 /* something from same cacheline, but !FORCEWAKE */
64 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 65}
66
c8d9a590
D		 67static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
68 int fw_engine)
907b28c5 69{
6af5d92f 70 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
907b28c5
CW		 71 FORCEWAKE_ACK_TIMEOUT_MS))
72 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
73
6af5d92f
CW		 74 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
75 /* something from same cacheline, but !FORCEWAKE */
76 __raw_posting_read(dev_priv, ECOBUS);
907b28c5 77
6af5d92f 78 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
907b28c5
CW		 79 FORCEWAKE_ACK_TIMEOUT_MS))
80 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
81
82 /* WaRsForcewakeWaitTC0:snb */
83 __gen6_gt_wait_for_thread_c0(dev_priv);
84}
85
86static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
87{
6af5d92f 88 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
907b28c5 89 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 90 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 91}
92
c8d9a590
D		 93static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
94 int fw_engine)
907b28c5
CW		 95{
96 u32 forcewake_ack;
97
ab2aa47e 98 if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
907b28c5
CW		 99 forcewake_ack = FORCEWAKE_ACK_HSW;
100 else
101 forcewake_ack = FORCEWAKE_MT_ACK;
102
6af5d92f 103 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
907b28c5
CW		 104 FORCEWAKE_ACK_TIMEOUT_MS))
105 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
106
6af5d92f
CW		 107 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
108 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
907b28c5 109 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 110 __raw_posting_read(dev_priv, ECOBUS);
907b28c5 111
6af5d92f 112 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
907b28c5
CW		 113 FORCEWAKE_ACK_TIMEOUT_MS))
114 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
115
116 /* WaRsForcewakeWaitTC0:ivb,hsw */
0f161f70
BW		 117 if (INTEL_INFO(dev_priv->dev)->gen < 8)
118 __gen6_gt_wait_for_thread_c0(dev_priv);
907b28c5
CW		 119}
120
121static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
122{
123 u32 gtfifodbg;
6af5d92f
CW		 124
125 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
90f256b5
VS		 126 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
127 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
907b28c5
CW		 128}
129
c8d9a590
D		 130static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
131 int fw_engine)
907b28c5 132{
6af5d92f 133 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
907b28c5 134 /* something from same cacheline, but !FORCEWAKE */
6af5d92f 135 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 136 gen6_gt_check_fifodbg(dev_priv);
137}
138
c8d9a590
D		 139static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
140 int fw_engine)
907b28c5 141{
6af5d92f
CW		 142 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
143 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
907b28c5 144 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 145 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 146 gen6_gt_check_fifodbg(dev_priv);
147}
148
149static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
150{
151 int ret = 0;
152
5135d64b
D		 153 /* On VLV, FIFO will be shared by both SW and HW.
154 * So, we need to read the FREE_ENTRIES everytime */
155 if (IS_VALLEYVIEW(dev_priv->dev))
156 dev_priv->uncore.fifo_count =
157 __raw_i915_read32(dev_priv, GTFIFOCTL) &
158 GT_FIFO_FREE_ENTRIES_MASK;
159
907b28c5
CW		 160 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
161 int loop = 500;
46520e2b 162 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
907b28c5
CW		 163 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
164 udelay(10);
46520e2b 165 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
907b28c5
CW		 166 }
167 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
168 ++ret;
169 dev_priv->uncore.fifo_count = fifo;
170 }
171 dev_priv->uncore.fifo_count--;
172
173 return ret;
174}
175
176static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
177{
6af5d92f
CW		 178 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
179 _MASKED_BIT_DISABLE(0xffff));
907b28c5 180 /* something from same cacheline, but !FORCEWAKE_VLV */
6af5d92f 181 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
907b28c5
CW		 182}
183
940aece4
D		 184static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
185 int fw_engine)
907b28c5 186{
940aece4
D		 187 /* Check for Render Engine */
188 if (FORCEWAKE_RENDER & fw_engine) {
189 if (wait_for_atomic((__raw_i915_read32(dev_priv,
190 FORCEWAKE_ACK_VLV) &
191 FORCEWAKE_KERNEL) == 0,
192 FORCEWAKE_ACK_TIMEOUT_MS))
193 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
194
195 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
196 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
197
198 if (wait_for_atomic((__raw_i915_read32(dev_priv,
199 FORCEWAKE_ACK_VLV) &
200 FORCEWAKE_KERNEL),
201 FORCEWAKE_ACK_TIMEOUT_MS))
202 DRM_ERROR("Timed out: waiting for Render to ack.\n");
203 }
907b28c5 204
940aece4
D		 205 /* Check for Media Engine */
206 if (FORCEWAKE_MEDIA & fw_engine) {
207 if (wait_for_atomic((__raw_i915_read32(dev_priv,
208 FORCEWAKE_ACK_MEDIA_VLV) &
209 FORCEWAKE_KERNEL) == 0,
210 FORCEWAKE_ACK_TIMEOUT_MS))
211 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
212
213 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
214 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
215
216 if (wait_for_atomic((__raw_i915_read32(dev_priv,
217 FORCEWAKE_ACK_MEDIA_VLV) &
218 FORCEWAKE_KERNEL),
219 FORCEWAKE_ACK_TIMEOUT_MS))
220 DRM_ERROR("Timed out: waiting for media to ack.\n");
221 }
907b28c5
CW		 222
223 /* WaRsForcewakeWaitTC0:vlv */
224 __gen6_gt_wait_for_thread_c0(dev_priv);
940aece4 225
907b28c5
CW		 226}
227
940aece4
D		 228static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
229 int fw_engine)
907b28c5 230{
940aece4
D		 231
232 /* Check for Render Engine */
233 if (FORCEWAKE_RENDER & fw_engine)
234 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
235 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
236
237
238 /* Check for Media Engine */
239 if (FORCEWAKE_MEDIA & fw_engine)
240 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
241 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
242
907b28c5
CW		 243 /* The below doubles as a POSTING_READ */
244 gen6_gt_check_fifodbg(dev_priv);
940aece4
D		 245
246}
247
248void vlv_force_wake_get(struct drm_i915_private *dev_priv,
249 int fw_engine)
250{
251 unsigned long irqflags;
252
253 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
254 if (FORCEWAKE_RENDER & fw_engine) {
255 if (dev_priv->uncore.fw_rendercount++ == 0)
256 dev_priv->uncore.funcs.force_wake_get(dev_priv,
257 FORCEWAKE_RENDER);
258 }
259 if (FORCEWAKE_MEDIA & fw_engine) {
260 if (dev_priv->uncore.fw_mediacount++ == 0)
261 dev_priv->uncore.funcs.force_wake_get(dev_priv,
262 FORCEWAKE_MEDIA);
263 }
264
265 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
266}
267
268void vlv_force_wake_put(struct drm_i915_private *dev_priv,
269 int fw_engine)
270{
271 unsigned long irqflags;
272
273 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
274
275 if (FORCEWAKE_RENDER & fw_engine) {
276 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
277 if (--dev_priv->uncore.fw_rendercount == 0)
278 dev_priv->uncore.funcs.force_wake_put(dev_priv,
279 FORCEWAKE_RENDER);
280 }
281
282 if (FORCEWAKE_MEDIA & fw_engine) {
283 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
284 if (--dev_priv->uncore.fw_mediacount == 0)
285 dev_priv->uncore.funcs.force_wake_put(dev_priv,
286 FORCEWAKE_MEDIA);
287 }
288
289 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
907b28c5
CW		 290}
291
aec347ab
CW		 292static void gen6_force_wake_work(struct work_struct *work)
293{
294 struct drm_i915_private *dev_priv =
295 container_of(work, typeof(*dev_priv), uncore.force_wake_work.work);
296 unsigned long irqflags;
297
298 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
299 if (--dev_priv->uncore.forcewake_count == 0)
c8d9a590 300 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
aec347ab
CW		 301 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
302}
303
ef46e0d2
DV		 304static void intel_uncore_forcewake_reset(struct drm_device *dev)
305{
306 struct drm_i915_private *dev_priv = dev->dev_private;
307
308 if (IS_VALLEYVIEW(dev)) {
309 vlv_force_wake_reset(dev_priv);
310 } else if (INTEL_INFO(dev)->gen >= 6) {
311 __gen6_gt_force_wake_reset(dev_priv);
312 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
313 __gen6_gt_force_wake_mt_reset(dev_priv);
314 }
315}
316
907b28c5
CW		 317void intel_uncore_early_sanitize(struct drm_device *dev)
318{
319 struct drm_i915_private *dev_priv = dev->dev_private;
320
321 if (HAS_FPGA_DBG_UNCLAIMED(dev))
6af5d92f 322 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
18ce3994
BW		 323
324 if (IS_HASWELL(dev) &&
325 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
326 /* The docs do not explain exactly how the calculation can be
327 * made. It is somewhat guessable, but for now, it's always
328 * 128MB.
329 * NB: We can't write IDICR yet because we do not have gt funcs
330 * set up */
331 dev_priv->ellc_size = 128;
332 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
333 }
907b28c5 334
ef46e0d2 335 intel_uncore_forcewake_reset(dev);
521198a2
MK		 336}
337
338void intel_uncore_sanitize(struct drm_device *dev)
339{
02f4c9e0
CML		 340 struct drm_i915_private *dev_priv = dev->dev_private;
341 u32 reg_val;
342
907b28c5
CW		 343 /* BIOS often leaves RC6 enabled, but disable it for hw init */
344 intel_disable_gt_powersave(dev);
02f4c9e0
CML		 345
346 /* Turn off power gate, require especially for the BIOS less system */
347 if (IS_VALLEYVIEW(dev)) {
348
349 mutex_lock(&dev_priv->rps.hw_lock);
350 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
351
352 if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
353 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
354
355 mutex_unlock(&dev_priv->rps.hw_lock);
356
357 }
907b28c5
CW		 358}
359
360/*
361 * Generally this is called implicitly by the register read function. However,
362 * if some sequence requires the GT to not power down then this function should
363 * be called at the beginning of the sequence followed by a call to
364 * gen6_gt_force_wake_put() at the end of the sequence.
365 */
c8d9a590 366void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
907b28c5
CW		 367{
368 unsigned long irqflags;
369
ab484f8f
BW		 370 if (!dev_priv->uncore.funcs.force_wake_get)
371 return;
372
940aece4
D		 373 /* Redirect to VLV specific routine */
374 if (IS_VALLEYVIEW(dev_priv->dev))
375 return vlv_force_wake_get(dev_priv, fw_engine);
376
907b28c5
CW		 377 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
378 if (dev_priv->uncore.forcewake_count++ == 0)
c8d9a590 379 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
907b28c5
CW		 380 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
381}
382
383/*
384 * see gen6_gt_force_wake_get()
385 */
c8d9a590 386void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
907b28c5
CW		 387{
388 unsigned long irqflags;
389
ab484f8f
BW		 390 if (!dev_priv->uncore.funcs.force_wake_put)
391 return;
392
940aece4
D		 393 /* Redirect to VLV specific routine */
394 if (IS_VALLEYVIEW(dev_priv->dev))
395 return vlv_force_wake_put(dev_priv, fw_engine);
396
397
907b28c5 398 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
aec347ab
CW		 399 if (--dev_priv->uncore.forcewake_count == 0) {
400 dev_priv->uncore.forcewake_count++;
401 mod_delayed_work(dev_priv->wq,
402 &dev_priv->uncore.force_wake_work,
403 1);
404 }
907b28c5
CW		 405 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
406}
407
408/* We give fast paths for the really cool registers */
409#define NEEDS_FORCE_WAKE(dev_priv, reg) \
ab484f8f 410 ((reg) < 0x40000 && (reg) != FORCEWAKE)
907b28c5
CW		 411
412static void
413ilk_dummy_write(struct drm_i915_private *dev_priv)
414{
415 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
416 * the chip from rc6 before touching it for real. MI_MODE is masked,
417 * hence harmless to write 0 into. */
6af5d92f 418 __raw_i915_write32(dev_priv, MI_MODE, 0);
907b28c5
CW		 419}
420
421static void
422hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
423{
ab484f8f 424 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
907b28c5
CW		 425 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
426 reg);
6af5d92f 427 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 428 }
429}
430
431static void
432hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
433{
ab484f8f 434 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
907b28c5 435 DRM_ERROR("Unclaimed write to %x\n", reg);
6af5d92f 436 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 437 }
438}
439
5d738795
BW		 440#define REG_READ_HEADER(x) \
441 unsigned long irqflags; \
442 u##x val = 0; \
443 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
444
445#define REG_READ_FOOTER \
446 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
447 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
448 return val
449
3967018e 450#define __gen4_read(x) \
0b274481 451static u##x \
3967018e
BW		 452gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
453 REG_READ_HEADER(x); \
454 val = __raw_i915_read##x(dev_priv, reg); \
455 REG_READ_FOOTER; \
456}
457
458#define __gen5_read(x) \
459static u##x \
460gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
461 REG_READ_HEADER(x); \
462 ilk_dummy_write(dev_priv); \
463 val = __raw_i915_read##x(dev_priv, reg); \
464 REG_READ_FOOTER; \
465}
466
467#define __gen6_read(x) \
468static u##x \
469gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
5d738795 470 REG_READ_HEADER(x); \
907b28c5
CW		 471 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
472 if (dev_priv->uncore.forcewake_count == 0) \
c8d9a590
D		 473 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
474 FORCEWAKE_ALL); \
6af5d92f 475 val = __raw_i915_read##x(dev_priv, reg); \
907b28c5 476 if (dev_priv->uncore.forcewake_count == 0) \
c8d9a590
D		 477 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
478 FORCEWAKE_ALL); \
907b28c5 479 } else { \
6af5d92f 480 val = __raw_i915_read##x(dev_priv, reg); \
907b28c5 481 } \
5d738795 482 REG_READ_FOOTER; \
907b28c5
CW		 483}
484
940aece4
D		 485#define __vlv_read(x) \
486static u##x \
487vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
488 unsigned fwengine = 0; \
5bc0e85c 489 unsigned *fwcount; \
940aece4
D		 490 REG_READ_HEADER(x); \
491 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
492 fwengine = FORCEWAKE_RENDER; \
493 fwcount = &dev_priv->uncore.fw_rendercount; \
494 } \
495 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
496 fwengine = FORCEWAKE_MEDIA; \
497 fwcount = &dev_priv->uncore.fw_mediacount; \
498 } \
499 if (fwengine != 0) { \
500 if ((*fwcount)++ == 0) \
501 (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
502 fwengine); \
503 val = __raw_i915_read##x(dev_priv, reg); \
504 if (--(*fwcount) == 0) \
505 (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
084054fc 506 fwengine); \
940aece4
D		 507 } else { \
508 val = __raw_i915_read##x(dev_priv, reg); \
509 } \
510 REG_READ_FOOTER; \
511}
512
513
514__vlv_read(8)
515__vlv_read(16)
516__vlv_read(32)
517__vlv_read(64)
3967018e
BW		 518__gen6_read(8)
519__gen6_read(16)
520__gen6_read(32)
521__gen6_read(64)
522__gen5_read(8)
523__gen5_read(16)
524__gen5_read(32)
525__gen5_read(64)
526__gen4_read(8)
527__gen4_read(16)
528__gen4_read(32)
529__gen4_read(64)
530
940aece4 531#undef __vlv_read
3967018e
BW		 532#undef __gen6_read
533#undef __gen5_read
534#undef __gen4_read
5d738795
BW		 535#undef REG_READ_FOOTER
536#undef REG_READ_HEADER
537
538#define REG_WRITE_HEADER \
539 unsigned long irqflags; \
540 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
541 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
907b28c5 542
0d965301
VS		 543#define REG_WRITE_FOOTER \
544 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
545
4032ef43 546#define __gen4_write(x) \
0b274481 547static void \
4032ef43
BW		 548gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
549 REG_WRITE_HEADER; \
550 __raw_i915_write##x(dev_priv, reg, val); \
0d965301 551 REG_WRITE_FOOTER; \
4032ef43
BW		 552}
553
554#define __gen5_write(x) \
555static void \
556gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
557 REG_WRITE_HEADER; \
558 ilk_dummy_write(dev_priv); \
559 __raw_i915_write##x(dev_priv, reg, val); \
0d965301 560 REG_WRITE_FOOTER; \
4032ef43
BW		 561}
562
563#define __gen6_write(x) \
564static void \
565gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
566 u32 __fifo_ret = 0; \
567 REG_WRITE_HEADER; \
568 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
569 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
570 } \
571 __raw_i915_write##x(dev_priv, reg, val); \
572 if (unlikely(__fifo_ret)) { \
573 gen6_gt_check_fifodbg(dev_priv); \
574 } \
0d965301 575 REG_WRITE_FOOTER; \
4032ef43
BW		 576}
577
578#define __hsw_write(x) \
579static void \
580hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
907b28c5 581 u32 __fifo_ret = 0; \
5d738795 582 REG_WRITE_HEADER; \
907b28c5
CW		 583 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
584 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
585 } \
907b28c5 586 hsw_unclaimed_reg_clear(dev_priv, reg); \
6af5d92f 587 __raw_i915_write##x(dev_priv, reg, val); \
907b28c5
CW		 588 if (unlikely(__fifo_ret)) { \
589 gen6_gt_check_fifodbg(dev_priv); \
590 } \
591 hsw_unclaimed_reg_check(dev_priv, reg); \
0d965301 592 REG_WRITE_FOOTER; \
907b28c5 593}
3967018e 594
ab2aa47e
BW		 595static const u32 gen8_shadowed_regs[] = {
596 FORCEWAKE_MT,
597 GEN6_RPNSWREQ,
598 GEN6_RC_VIDEO_FREQ,
599 RING_TAIL(RENDER_RING_BASE),
600 RING_TAIL(GEN6_BSD_RING_BASE),
601 RING_TAIL(VEBOX_RING_BASE),
602 RING_TAIL(BLT_RING_BASE),
603 /* TODO: Other registers are not yet used */
604};
605
606static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
607{
608 int i;
609 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
610 if (reg == gen8_shadowed_regs[i])
611 return true;
612
613 return false;
614}
615
616#define __gen8_write(x) \
617static void \
618gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
619 bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
620 REG_WRITE_HEADER; \
621 if (__needs_put) { \
c8d9a590
D		 622 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
623 FORCEWAKE_ALL); \
ab2aa47e
BW		 624 } \
625 __raw_i915_write##x(dev_priv, reg, val); \
626 if (__needs_put) { \
c8d9a590
D		 627 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
628 FORCEWAKE_ALL); \
ab2aa47e 629 } \
0d965301 630 REG_WRITE_FOOTER; \
ab2aa47e
BW		 631}
632
633__gen8_write(8)
634__gen8_write(16)
635__gen8_write(32)
636__gen8_write(64)
4032ef43
BW		 637__hsw_write(8)
638__hsw_write(16)
639__hsw_write(32)
640__hsw_write(64)
641__gen6_write(8)
642__gen6_write(16)
643__gen6_write(32)
644__gen6_write(64)
645__gen5_write(8)
646__gen5_write(16)
647__gen5_write(32)
648__gen5_write(64)
649__gen4_write(8)
650__gen4_write(16)
651__gen4_write(32)
652__gen4_write(64)
653
ab2aa47e 654#undef __gen8_write
4032ef43
BW		 655#undef __hsw_write
656#undef __gen6_write
657#undef __gen5_write
658#undef __gen4_write
0d965301 659#undef REG_WRITE_FOOTER
5d738795 660#undef REG_WRITE_HEADER
907b28c5 661
0b274481
BW		 662void intel_uncore_init(struct drm_device *dev)
663{
664 struct drm_i915_private *dev_priv = dev->dev_private;
665
666 INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work,
667 gen6_force_wake_work);
668
669 if (IS_VALLEYVIEW(dev)) {
940aece4
D		 670 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
671 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
43d1b647 672 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
0b274481
BW		 673 dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
674 dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
675 } else if (IS_IVYBRIDGE(dev)) {
676 u32 ecobus;
677
678 /* IVB configs may use multi-threaded forcewake */
679
680 /* A small trick here - if the bios hasn't configured
681 * MT forcewake, and if the device is in RC6, then
682 * force_wake_mt_get will not wake the device and the
683 * ECOBUS read will return zero. Which will be
684 * (correctly) interpreted by the test below as MT
685 * forcewake being disabled.
686 */
687 mutex_lock(&dev->struct_mutex);
c8d9a590 688 __gen6_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
0b274481 689 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
c8d9a590 690 __gen6_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
0b274481
BW		 691 mutex_unlock(&dev->struct_mutex);
692
693 if (ecobus & FORCEWAKE_MT_ENABLE) {
694 dev_priv->uncore.funcs.force_wake_get =
695 __gen6_gt_force_wake_mt_get;
696 dev_priv->uncore.funcs.force_wake_put =
697 __gen6_gt_force_wake_mt_put;
698 } else {
699 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
700 DRM_INFO("when using vblank-synced partial screen updates.\n");
701 dev_priv->uncore.funcs.force_wake_get =
702 __gen6_gt_force_wake_get;
703 dev_priv->uncore.funcs.force_wake_put =
704 __gen6_gt_force_wake_put;
705 }
706 } else if (IS_GEN6(dev)) {
707 dev_priv->uncore.funcs.force_wake_get =
708 __gen6_gt_force_wake_get;
709 dev_priv->uncore.funcs.force_wake_put =
710 __gen6_gt_force_wake_put;
711 }
712
3967018e 713 switch (INTEL_INFO(dev)->gen) {
ab2aa47e
BW		 714 default:
715 dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
716 dev_priv->uncore.funcs.mmio_writew = gen8_write16;
717 dev_priv->uncore.funcs.mmio_writel = gen8_write32;
718 dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
719 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
720 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
721 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
722 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
723 break;
3967018e
BW		 724 case 7:
725 case 6:
4032ef43
BW		 726 if (IS_HASWELL(dev)) {
727 dev_priv->uncore.funcs.mmio_writeb = hsw_write8;
728 dev_priv->uncore.funcs.mmio_writew = hsw_write16;
729 dev_priv->uncore.funcs.mmio_writel = hsw_write32;
730 dev_priv->uncore.funcs.mmio_writeq = hsw_write64;
731 } else {
732 dev_priv->uncore.funcs.mmio_writeb = gen6_write8;
733 dev_priv->uncore.funcs.mmio_writew = gen6_write16;
734 dev_priv->uncore.funcs.mmio_writel = gen6_write32;
735 dev_priv->uncore.funcs.mmio_writeq = gen6_write64;
736 }
940aece4
D		 737
738 if (IS_VALLEYVIEW(dev)) {
739 dev_priv->uncore.funcs.mmio_readb = vlv_read8;
740 dev_priv->uncore.funcs.mmio_readw = vlv_read16;
741 dev_priv->uncore.funcs.mmio_readl = vlv_read32;
742 dev_priv->uncore.funcs.mmio_readq = vlv_read64;
743 } else {
744 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
745 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
746 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
747 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
748 }
3967018e
BW		 749 break;
750 case 5:
4032ef43
BW		 751 dev_priv->uncore.funcs.mmio_writeb = gen5_write8;
752 dev_priv->uncore.funcs.mmio_writew = gen5_write16;
753 dev_priv->uncore.funcs.mmio_writel = gen5_write32;
754 dev_priv->uncore.funcs.mmio_writeq = gen5_write64;
3967018e
BW		 755 dev_priv->uncore.funcs.mmio_readb = gen5_read8;
756 dev_priv->uncore.funcs.mmio_readw = gen5_read16;
757 dev_priv->uncore.funcs.mmio_readl = gen5_read32;
758 dev_priv->uncore.funcs.mmio_readq = gen5_read64;
759 break;
760 case 4:
761 case 3:
762 case 2:
4032ef43
BW		 763 dev_priv->uncore.funcs.mmio_writeb = gen4_write8;
764 dev_priv->uncore.funcs.mmio_writew = gen4_write16;
765 dev_priv->uncore.funcs.mmio_writel = gen4_write32;
766 dev_priv->uncore.funcs.mmio_writeq = gen4_write64;
3967018e
BW		 767 dev_priv->uncore.funcs.mmio_readb = gen4_read8;
768 dev_priv->uncore.funcs.mmio_readw = gen4_read16;
769 dev_priv->uncore.funcs.mmio_readl = gen4_read32;
770 dev_priv->uncore.funcs.mmio_readq = gen4_read64;
771 break;
772 }
0b274481
BW		 773}
774
775void intel_uncore_fini(struct drm_device *dev)
776{
777 struct drm_i915_private *dev_priv = dev->dev_private;
778
779 flush_delayed_work(&dev_priv->uncore.force_wake_work);
780
781 /* Paranoia: make sure we have disabled everything before we exit. */
782 intel_uncore_sanitize(dev);
783}
784
907b28c5
CW		 785static const struct register_whitelist {
786 uint64_t offset;
787 uint32_t size;
788 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
789} whitelist[] = {
790 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
791};
792
793int i915_reg_read_ioctl(struct drm_device *dev,
794 void *data, struct drm_file *file)
795{
796 struct drm_i915_private *dev_priv = dev->dev_private;
797 struct drm_i915_reg_read *reg = data;
798 struct register_whitelist const *entry = whitelist;
799 int i;
800
801 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
802 if (entry->offset == reg->offset &&
803 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
804 break;
805 }
806
807 if (i == ARRAY_SIZE(whitelist))
808 return -EINVAL;
809
810 switch (entry->size) {
811 case 8:
812 reg->val = I915_READ64(reg->offset);
813 break;
814 case 4:
815 reg->val = I915_READ(reg->offset);
816 break;
817 case 2:
818 reg->val = I915_READ16(reg->offset);
819 break;
820 case 1:
821 reg->val = I915_READ8(reg->offset);
822 break;
823 default:
824 WARN_ON(1);
825 return -EINVAL;
826 }
827
828 return 0;
829}
830
b6359918
MK		 831int i915_get_reset_stats_ioctl(struct drm_device *dev,
832 void *data, struct drm_file *file)
833{
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 struct drm_i915_reset_stats *args = data;
836 struct i915_ctx_hang_stats *hs;
837 int ret;
838
661df041
MK		 839 if (args->flags || args->pad)
840 return -EINVAL;
841
b6359918
MK		 842 if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
843 return -EPERM;
844
845 ret = mutex_lock_interruptible(&dev->struct_mutex);
846 if (ret)
847 return ret;
848
849 hs = i915_gem_context_get_hang_stats(dev, file, args->ctx_id);
850 if (IS_ERR(hs)) {
851 mutex_unlock(&dev->struct_mutex);
852 return PTR_ERR(hs);
853 }
854
855 if (capable(CAP_SYS_ADMIN))
856 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
857 else
858 args->reset_count = 0;
859
860 args->batch_active = hs->batch_active;
861 args->batch_pending = hs->batch_pending;
862
863 mutex_unlock(&dev->struct_mutex);
864
865 return 0;
866}
867
907b28c5
CW		 868static int i965_reset_complete(struct drm_device *dev)
869{
870 u8 gdrst;
871 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
872 return (gdrst & GRDOM_RESET_ENABLE) == 0;
873}
874
875static int i965_do_reset(struct drm_device *dev)
876{
877 int ret;
878
879 /*
880 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
881 * well as the reset bit (GR/bit 0). Setting the GR bit
882 * triggers the reset; when done, the hardware will clear it.
883 */
884 pci_write_config_byte(dev->pdev, I965_GDRST,
885 GRDOM_RENDER | GRDOM_RESET_ENABLE);
886 ret = wait_for(i965_reset_complete(dev), 500);
887 if (ret)
888 return ret;
889
890 /* We can't reset render&media without also resetting display ... */
891 pci_write_config_byte(dev->pdev, I965_GDRST,
892 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
893
894 ret = wait_for(i965_reset_complete(dev), 500);
895 if (ret)
896 return ret;
897
898 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
899
900 return 0;
901}
902
903static int ironlake_do_reset(struct drm_device *dev)
904{
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 u32 gdrst;
907 int ret;
908
909 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
910 gdrst &= ~GRDOM_MASK;
911 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
912 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
913 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
914 if (ret)
915 return ret;
916
917 /* We can't reset render&media without also resetting display ... */
918 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
919 gdrst &= ~GRDOM_MASK;
920 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
921 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
922 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
923}
924
925static int gen6_do_reset(struct drm_device *dev)
926{
927 struct drm_i915_private *dev_priv = dev->dev_private;
928 int ret;
929 unsigned long irqflags;
930
931 /* Hold uncore.lock across reset to prevent any register access
932 * with forcewake not set correctly
933 */
934 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
935
936 /* Reset the chip */
937
938 /* GEN6_GDRST is not in the gt power well, no need to check
939 * for fifo space for the write or forcewake the chip for
940 * the read
941 */
6af5d92f 942 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
907b28c5
CW		 943
944 /* Spin waiting for the device to ack the reset request */
6af5d92f 945 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
907b28c5 946
521198a2
MK		 947 intel_uncore_forcewake_reset(dev);
948
907b28c5
CW		 949 /* If reset with a user forcewake, try to restore, otherwise turn it off */
950 if (dev_priv->uncore.forcewake_count)
c8d9a590 951 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
907b28c5 952 else
c8d9a590 953 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
907b28c5
CW		 954
955 /* Restore fifo count */
46520e2b 956 dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
907b28c5
CW		 957
958 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
959 return ret;
960}
961
962int intel_gpu_reset(struct drm_device *dev)
963{
964 switch (INTEL_INFO(dev)->gen) {
935e8de9 965 case 8:
907b28c5
CW		 966 case 7:
967 case 6: return gen6_do_reset(dev);
968 case 5: return ironlake_do_reset(dev);
969 case 4: return i965_do_reset(dev);
907b28c5
CW		 970 default: return -ENODEV;
971 }
972}
973
907b28c5
CW		 974void intel_uncore_check_errors(struct drm_device *dev)
975{
976 struct drm_i915_private *dev_priv = dev->dev_private;
977
978 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
6af5d92f 979 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
907b28c5 980 DRM_ERROR("Unclaimed register before interrupt\n");
6af5d92f 981 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 982 }
983}
Linux kernel - Deliverables
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