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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
26 | ||
27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 | |
28 | ||
6af5d92f CW |
29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) | |
31 | ||
32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) | |
33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) | |
34 | ||
35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) | |
37 | ||
38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) | |
39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) | |
40 | ||
41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) | |
42 | ||
b2ec142c PZ |
43 | static void |
44 | assert_device_not_suspended(struct drm_i915_private *dev_priv) | |
45 | { | |
46 | WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, | |
47 | "Device suspended\n"); | |
48 | } | |
6af5d92f | 49 | |
907b28c5 CW |
50 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
51 | { | |
52 | u32 gt_thread_status_mask; | |
53 | ||
54 | if (IS_HASWELL(dev_priv->dev)) | |
55 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; | |
56 | else | |
57 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; | |
58 | ||
59 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
60 | * thread to wake up. | |
61 | */ | |
6af5d92f | 62 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
907b28c5 CW |
63 | DRM_ERROR("GT thread status wait timed out\n"); |
64 | } | |
65 | ||
66 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) | |
67 | { | |
6af5d92f CW |
68 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
69 | /* something from same cacheline, but !FORCEWAKE */ | |
70 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 CW |
71 | } |
72 | ||
c8d9a590 D |
73 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
74 | int fw_engine) | |
907b28c5 | 75 | { |
6af5d92f | 76 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
907b28c5 CW |
77 | FORCEWAKE_ACK_TIMEOUT_MS)) |
78 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
79 | ||
6af5d92f CW |
80 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
81 | /* something from same cacheline, but !FORCEWAKE */ | |
82 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 | 83 | |
6af5d92f | 84 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
907b28c5 CW |
85 | FORCEWAKE_ACK_TIMEOUT_MS)) |
86 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
87 | ||
88 | /* WaRsForcewakeWaitTC0:snb */ | |
89 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
90 | } | |
91 | ||
6a68735a | 92 | static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
907b28c5 | 93 | { |
6af5d92f | 94 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
907b28c5 | 95 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 96 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
97 | } |
98 | ||
6a68735a | 99 | static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
c8d9a590 | 100 | int fw_engine) |
907b28c5 CW |
101 | { |
102 | u32 forcewake_ack; | |
103 | ||
ab2aa47e | 104 | if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) |
907b28c5 CW |
105 | forcewake_ack = FORCEWAKE_ACK_HSW; |
106 | else | |
107 | forcewake_ack = FORCEWAKE_MT_ACK; | |
108 | ||
6af5d92f | 109 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
907b28c5 CW |
110 | FORCEWAKE_ACK_TIMEOUT_MS)) |
111 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
112 | ||
6af5d92f CW |
113 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
114 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 115 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 116 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 | 117 | |
6af5d92f | 118 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
907b28c5 CW |
119 | FORCEWAKE_ACK_TIMEOUT_MS)) |
120 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
121 | ||
122 | /* WaRsForcewakeWaitTC0:ivb,hsw */ | |
0f161f70 BW |
123 | if (INTEL_INFO(dev_priv->dev)->gen < 8) |
124 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
907b28c5 CW |
125 | } |
126 | ||
127 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
128 | { | |
129 | u32 gtfifodbg; | |
6af5d92f CW |
130 | |
131 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
90f256b5 VS |
132 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
133 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); | |
907b28c5 CW |
134 | } |
135 | ||
c8d9a590 D |
136 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
137 | int fw_engine) | |
907b28c5 | 138 | { |
6af5d92f | 139 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
907b28c5 | 140 | /* something from same cacheline, but !FORCEWAKE */ |
6af5d92f | 141 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
142 | gen6_gt_check_fifodbg(dev_priv); |
143 | } | |
144 | ||
6a68735a | 145 | static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, |
c8d9a590 | 146 | int fw_engine) |
907b28c5 | 147 | { |
6af5d92f CW |
148 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
149 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 150 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 151 | __raw_posting_read(dev_priv, ECOBUS); |
6a68735a MK |
152 | |
153 | if (IS_GEN7(dev_priv->dev)) | |
154 | gen6_gt_check_fifodbg(dev_priv); | |
907b28c5 CW |
155 | } |
156 | ||
157 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) | |
158 | { | |
159 | int ret = 0; | |
160 | ||
5135d64b D |
161 | /* On VLV, FIFO will be shared by both SW and HW. |
162 | * So, we need to read the FREE_ENTRIES everytime */ | |
163 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
164 | dev_priv->uncore.fifo_count = | |
165 | __raw_i915_read32(dev_priv, GTFIFOCTL) & | |
166 | GT_FIFO_FREE_ENTRIES_MASK; | |
167 | ||
907b28c5 CW |
168 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
169 | int loop = 500; | |
46520e2b | 170 | u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
907b28c5 CW |
171 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
172 | udelay(10); | |
46520e2b | 173 | fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
907b28c5 CW |
174 | } |
175 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
176 | ++ret; | |
177 | dev_priv->uncore.fifo_count = fifo; | |
178 | } | |
179 | dev_priv->uncore.fifo_count--; | |
180 | ||
181 | return ret; | |
182 | } | |
183 | ||
184 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) | |
185 | { | |
6af5d92f CW |
186 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
187 | _MASKED_BIT_DISABLE(0xffff)); | |
907b28c5 | 188 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
6af5d92f | 189 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
907b28c5 CW |
190 | } |
191 | ||
940aece4 D |
192 | static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, |
193 | int fw_engine) | |
907b28c5 | 194 | { |
940aece4 D |
195 | /* Check for Render Engine */ |
196 | if (FORCEWAKE_RENDER & fw_engine) { | |
197 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
198 | FORCEWAKE_ACK_VLV) & | |
199 | FORCEWAKE_KERNEL) == 0, | |
200 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
201 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); | |
202 | ||
203 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, | |
204 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
205 | ||
206 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
207 | FORCEWAKE_ACK_VLV) & | |
208 | FORCEWAKE_KERNEL), | |
209 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
210 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); | |
211 | } | |
907b28c5 | 212 | |
940aece4 D |
213 | /* Check for Media Engine */ |
214 | if (FORCEWAKE_MEDIA & fw_engine) { | |
215 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
216 | FORCEWAKE_ACK_MEDIA_VLV) & | |
217 | FORCEWAKE_KERNEL) == 0, | |
218 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
219 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); | |
220 | ||
221 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
222 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
223 | ||
224 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
225 | FORCEWAKE_ACK_MEDIA_VLV) & | |
226 | FORCEWAKE_KERNEL), | |
227 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
228 | DRM_ERROR("Timed out: waiting for media to ack.\n"); | |
229 | } | |
907b28c5 CW |
230 | |
231 | /* WaRsForcewakeWaitTC0:vlv */ | |
232 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
940aece4 | 233 | |
907b28c5 CW |
234 | } |
235 | ||
940aece4 D |
236 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
237 | int fw_engine) | |
907b28c5 | 238 | { |
940aece4 D |
239 | |
240 | /* Check for Render Engine */ | |
241 | if (FORCEWAKE_RENDER & fw_engine) | |
242 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, | |
243 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
244 | ||
245 | ||
246 | /* Check for Media Engine */ | |
247 | if (FORCEWAKE_MEDIA & fw_engine) | |
248 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
249 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
250 | ||
907b28c5 CW |
251 | /* The below doubles as a POSTING_READ */ |
252 | gen6_gt_check_fifodbg(dev_priv); | |
940aece4 D |
253 | |
254 | } | |
255 | ||
256 | void vlv_force_wake_get(struct drm_i915_private *dev_priv, | |
257 | int fw_engine) | |
258 | { | |
259 | unsigned long irqflags; | |
260 | ||
261 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
6fe72865 VS |
262 | |
263 | if (fw_engine & FORCEWAKE_RENDER && | |
264 | dev_priv->uncore.fw_rendercount++ != 0) | |
265 | fw_engine &= ~FORCEWAKE_RENDER; | |
266 | if (fw_engine & FORCEWAKE_MEDIA && | |
267 | dev_priv->uncore.fw_mediacount++ != 0) | |
268 | fw_engine &= ~FORCEWAKE_MEDIA; | |
269 | ||
270 | if (fw_engine) | |
271 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine); | |
940aece4 D |
272 | |
273 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
274 | } | |
275 | ||
276 | void vlv_force_wake_put(struct drm_i915_private *dev_priv, | |
277 | int fw_engine) | |
278 | { | |
279 | unsigned long irqflags; | |
280 | ||
281 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
282 | ||
6fe72865 VS |
283 | if (fw_engine & FORCEWAKE_RENDER && |
284 | --dev_priv->uncore.fw_rendercount != 0) | |
285 | fw_engine &= ~FORCEWAKE_RENDER; | |
286 | if (fw_engine & FORCEWAKE_MEDIA && | |
287 | --dev_priv->uncore.fw_mediacount != 0) | |
288 | fw_engine &= ~FORCEWAKE_MEDIA; | |
940aece4 | 289 | |
6fe72865 VS |
290 | if (fw_engine) |
291 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); | |
940aece4 D |
292 | |
293 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
907b28c5 CW |
294 | } |
295 | ||
8232644c | 296 | static void gen6_force_wake_timer(unsigned long arg) |
aec347ab | 297 | { |
8232644c | 298 | struct drm_i915_private *dev_priv = (void *)arg; |
aec347ab CW |
299 | unsigned long irqflags; |
300 | ||
b2ec142c PZ |
301 | assert_device_not_suspended(dev_priv); |
302 | ||
aec347ab CW |
303 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
304 | if (--dev_priv->uncore.forcewake_count == 0) | |
c8d9a590 | 305 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
aec347ab | 306 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
6d88064e PZ |
307 | |
308 | intel_runtime_pm_put(dev_priv); | |
aec347ab CW |
309 | } |
310 | ||
0294ae7b | 311 | static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
ef46e0d2 DV |
312 | { |
313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0294ae7b CW |
314 | unsigned long irqflags; |
315 | ||
316 | del_timer_sync(&dev_priv->uncore.force_wake_timer); | |
317 | ||
318 | /* Hold uncore.lock across reset to prevent any register access | |
319 | * with forcewake not set correctly | |
320 | */ | |
321 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
ef46e0d2 | 322 | |
0a089e33 | 323 | if (IS_VALLEYVIEW(dev)) |
ef46e0d2 | 324 | vlv_force_wake_reset(dev_priv); |
0a089e33 | 325 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
ef46e0d2 | 326 | __gen6_gt_force_wake_reset(dev_priv); |
0a089e33 MK |
327 | |
328 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev)) | |
6a68735a | 329 | __gen7_gt_force_wake_mt_reset(dev_priv); |
0294ae7b CW |
330 | |
331 | if (restore) { /* If reset with a user forcewake, try to restore */ | |
332 | unsigned fw = 0; | |
333 | ||
334 | if (IS_VALLEYVIEW(dev)) { | |
335 | if (dev_priv->uncore.fw_rendercount) | |
336 | fw |= FORCEWAKE_RENDER; | |
337 | ||
338 | if (dev_priv->uncore.fw_mediacount) | |
339 | fw |= FORCEWAKE_MEDIA; | |
340 | } else { | |
341 | if (dev_priv->uncore.forcewake_count) | |
342 | fw = FORCEWAKE_ALL; | |
343 | } | |
344 | ||
345 | if (fw) | |
346 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); | |
347 | ||
348 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
349 | dev_priv->uncore.fifo_count = | |
350 | __raw_i915_read32(dev_priv, GTFIFOCTL) & | |
351 | GT_FIFO_FREE_ENTRIES_MASK; | |
352 | } else { | |
353 | dev_priv->uncore.forcewake_count = 0; | |
354 | dev_priv->uncore.fw_rendercount = 0; | |
355 | dev_priv->uncore.fw_mediacount = 0; | |
356 | } | |
357 | ||
358 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
ef46e0d2 DV |
359 | } |
360 | ||
907b28c5 CW |
361 | void intel_uncore_early_sanitize(struct drm_device *dev) |
362 | { | |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
364 | ||
365 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) | |
6af5d92f | 366 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
18ce3994 BW |
367 | |
368 | if (IS_HASWELL(dev) && | |
369 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { | |
370 | /* The docs do not explain exactly how the calculation can be | |
371 | * made. It is somewhat guessable, but for now, it's always | |
372 | * 128MB. | |
373 | * NB: We can't write IDICR yet because we do not have gt funcs | |
374 | * set up */ | |
375 | dev_priv->ellc_size = 128; | |
376 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); | |
377 | } | |
907b28c5 | 378 | |
97058870 VS |
379 | /* clear out old GT FIFO errors */ |
380 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
381 | __raw_i915_write32(dev_priv, GTFIFODBG, | |
382 | __raw_i915_read32(dev_priv, GTFIFODBG)); | |
383 | ||
0294ae7b | 384 | intel_uncore_forcewake_reset(dev, false); |
521198a2 MK |
385 | } |
386 | ||
387 | void intel_uncore_sanitize(struct drm_device *dev) | |
388 | { | |
02f4c9e0 CML |
389 | struct drm_i915_private *dev_priv = dev->dev_private; |
390 | u32 reg_val; | |
391 | ||
907b28c5 CW |
392 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
393 | intel_disable_gt_powersave(dev); | |
02f4c9e0 CML |
394 | |
395 | /* Turn off power gate, require especially for the BIOS less system */ | |
396 | if (IS_VALLEYVIEW(dev)) { | |
397 | ||
398 | mutex_lock(&dev_priv->rps.hw_lock); | |
399 | reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS); | |
400 | ||
a30180a5 ID |
401 | if (reg_val & (PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_RENDER) | |
402 | PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_MEDIA) | | |
403 | PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_DISP2D))) | |
02f4c9e0 CML |
404 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0); |
405 | ||
406 | mutex_unlock(&dev_priv->rps.hw_lock); | |
407 | ||
408 | } | |
907b28c5 CW |
409 | } |
410 | ||
411 | /* | |
412 | * Generally this is called implicitly by the register read function. However, | |
413 | * if some sequence requires the GT to not power down then this function should | |
414 | * be called at the beginning of the sequence followed by a call to | |
415 | * gen6_gt_force_wake_put() at the end of the sequence. | |
416 | */ | |
c8d9a590 | 417 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
907b28c5 CW |
418 | { |
419 | unsigned long irqflags; | |
420 | ||
ab484f8f BW |
421 | if (!dev_priv->uncore.funcs.force_wake_get) |
422 | return; | |
423 | ||
c8c8fb33 PZ |
424 | intel_runtime_pm_get(dev_priv); |
425 | ||
940aece4 D |
426 | /* Redirect to VLV specific routine */ |
427 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
428 | return vlv_force_wake_get(dev_priv, fw_engine); | |
429 | ||
907b28c5 CW |
430 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
431 | if (dev_priv->uncore.forcewake_count++ == 0) | |
c8d9a590 | 432 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
907b28c5 CW |
433 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
434 | } | |
435 | ||
436 | /* | |
437 | * see gen6_gt_force_wake_get() | |
438 | */ | |
c8d9a590 | 439 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
907b28c5 CW |
440 | { |
441 | unsigned long irqflags; | |
6d88064e | 442 | bool delayed = false; |
907b28c5 | 443 | |
ab484f8f BW |
444 | if (!dev_priv->uncore.funcs.force_wake_put) |
445 | return; | |
446 | ||
940aece4 | 447 | /* Redirect to VLV specific routine */ |
6d88064e PZ |
448 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
449 | vlv_force_wake_put(dev_priv, fw_engine); | |
450 | goto out; | |
451 | } | |
940aece4 D |
452 | |
453 | ||
907b28c5 | 454 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
aec347ab CW |
455 | if (--dev_priv->uncore.forcewake_count == 0) { |
456 | dev_priv->uncore.forcewake_count++; | |
6d88064e | 457 | delayed = true; |
8232644c CW |
458 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, |
459 | jiffies + 1); | |
aec347ab | 460 | } |
907b28c5 | 461 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
c8c8fb33 | 462 | |
6d88064e PZ |
463 | out: |
464 | if (!delayed) | |
465 | intel_runtime_pm_put(dev_priv); | |
907b28c5 CW |
466 | } |
467 | ||
e998c40f PZ |
468 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv) |
469 | { | |
470 | if (!dev_priv->uncore.funcs.force_wake_get) | |
471 | return; | |
472 | ||
473 | WARN_ON(dev_priv->uncore.forcewake_count > 0); | |
474 | } | |
475 | ||
907b28c5 CW |
476 | /* We give fast paths for the really cool registers */ |
477 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
ab484f8f | 478 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
907b28c5 CW |
479 | |
480 | static void | |
481 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
482 | { | |
483 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
484 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
485 | * hence harmless to write 0 into. */ | |
6af5d92f | 486 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
487 | } |
488 | ||
489 | static void | |
490 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) | |
491 | { | |
ab484f8f | 492 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
907b28c5 CW |
493 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
494 | reg); | |
6af5d92f | 495 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
496 | } |
497 | } | |
498 | ||
499 | static void | |
500 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) | |
501 | { | |
ab484f8f | 502 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
907b28c5 | 503 | DRM_ERROR("Unclaimed write to %x\n", reg); |
6af5d92f | 504 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
505 | } |
506 | } | |
507 | ||
5d738795 BW |
508 | #define REG_READ_HEADER(x) \ |
509 | unsigned long irqflags; \ | |
510 | u##x val = 0; \ | |
6f0ea9e2 | 511 | assert_device_not_suspended(dev_priv); \ |
5d738795 BW |
512 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
513 | ||
514 | #define REG_READ_FOOTER \ | |
515 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
516 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
517 | return val | |
518 | ||
3967018e | 519 | #define __gen4_read(x) \ |
0b274481 | 520 | static u##x \ |
3967018e BW |
521 | gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
522 | REG_READ_HEADER(x); \ | |
523 | val = __raw_i915_read##x(dev_priv, reg); \ | |
524 | REG_READ_FOOTER; \ | |
525 | } | |
526 | ||
527 | #define __gen5_read(x) \ | |
528 | static u##x \ | |
529 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
530 | REG_READ_HEADER(x); \ | |
531 | ilk_dummy_write(dev_priv); \ | |
532 | val = __raw_i915_read##x(dev_priv, reg); \ | |
533 | REG_READ_FOOTER; \ | |
534 | } | |
535 | ||
536 | #define __gen6_read(x) \ | |
537 | static u##x \ | |
538 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
5d738795 | 539 | REG_READ_HEADER(x); \ |
8232644c CW |
540 | if (dev_priv->uncore.forcewake_count == 0 && \ |
541 | NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
542 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ | |
543 | FORCEWAKE_ALL); \ | |
544 | dev_priv->uncore.forcewake_count++; \ | |
545 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \ | |
546 | jiffies + 1); \ | |
907b28c5 | 547 | } \ |
8232644c | 548 | val = __raw_i915_read##x(dev_priv, reg); \ |
5d738795 | 549 | REG_READ_FOOTER; \ |
907b28c5 CW |
550 | } |
551 | ||
940aece4 D |
552 | #define __vlv_read(x) \ |
553 | static u##x \ | |
554 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
555 | unsigned fwengine = 0; \ | |
940aece4 | 556 | REG_READ_HEADER(x); \ |
6fe72865 VS |
557 | if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ |
558 | if (dev_priv->uncore.fw_rendercount == 0) \ | |
559 | fwengine = FORCEWAKE_RENDER; \ | |
560 | } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \ | |
561 | if (dev_priv->uncore.fw_mediacount == 0) \ | |
562 | fwengine = FORCEWAKE_MEDIA; \ | |
940aece4 | 563 | } \ |
6fe72865 VS |
564 | if (fwengine) \ |
565 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ | |
566 | val = __raw_i915_read##x(dev_priv, reg); \ | |
567 | if (fwengine) \ | |
568 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ | |
940aece4 D |
569 | REG_READ_FOOTER; \ |
570 | } | |
571 | ||
572 | ||
573 | __vlv_read(8) | |
574 | __vlv_read(16) | |
575 | __vlv_read(32) | |
576 | __vlv_read(64) | |
3967018e BW |
577 | __gen6_read(8) |
578 | __gen6_read(16) | |
579 | __gen6_read(32) | |
580 | __gen6_read(64) | |
581 | __gen5_read(8) | |
582 | __gen5_read(16) | |
583 | __gen5_read(32) | |
584 | __gen5_read(64) | |
585 | __gen4_read(8) | |
586 | __gen4_read(16) | |
587 | __gen4_read(32) | |
588 | __gen4_read(64) | |
589 | ||
940aece4 | 590 | #undef __vlv_read |
3967018e BW |
591 | #undef __gen6_read |
592 | #undef __gen5_read | |
593 | #undef __gen4_read | |
5d738795 BW |
594 | #undef REG_READ_FOOTER |
595 | #undef REG_READ_HEADER | |
596 | ||
597 | #define REG_WRITE_HEADER \ | |
598 | unsigned long irqflags; \ | |
599 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
6f0ea9e2 | 600 | assert_device_not_suspended(dev_priv); \ |
5d738795 | 601 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
907b28c5 | 602 | |
0d965301 VS |
603 | #define REG_WRITE_FOOTER \ |
604 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
605 | ||
4032ef43 | 606 | #define __gen4_write(x) \ |
0b274481 | 607 | static void \ |
4032ef43 BW |
608 | gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
609 | REG_WRITE_HEADER; \ | |
610 | __raw_i915_write##x(dev_priv, reg, val); \ | |
0d965301 | 611 | REG_WRITE_FOOTER; \ |
4032ef43 BW |
612 | } |
613 | ||
614 | #define __gen5_write(x) \ | |
615 | static void \ | |
616 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
617 | REG_WRITE_HEADER; \ | |
618 | ilk_dummy_write(dev_priv); \ | |
619 | __raw_i915_write##x(dev_priv, reg, val); \ | |
0d965301 | 620 | REG_WRITE_FOOTER; \ |
4032ef43 BW |
621 | } |
622 | ||
623 | #define __gen6_write(x) \ | |
624 | static void \ | |
625 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
626 | u32 __fifo_ret = 0; \ | |
627 | REG_WRITE_HEADER; \ | |
628 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
629 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
630 | } \ | |
631 | __raw_i915_write##x(dev_priv, reg, val); \ | |
632 | if (unlikely(__fifo_ret)) { \ | |
633 | gen6_gt_check_fifodbg(dev_priv); \ | |
634 | } \ | |
0d965301 | 635 | REG_WRITE_FOOTER; \ |
4032ef43 BW |
636 | } |
637 | ||
638 | #define __hsw_write(x) \ | |
639 | static void \ | |
640 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
907b28c5 | 641 | u32 __fifo_ret = 0; \ |
5d738795 | 642 | REG_WRITE_HEADER; \ |
907b28c5 CW |
643 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
644 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
645 | } \ | |
907b28c5 | 646 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
6af5d92f | 647 | __raw_i915_write##x(dev_priv, reg, val); \ |
907b28c5 CW |
648 | if (unlikely(__fifo_ret)) { \ |
649 | gen6_gt_check_fifodbg(dev_priv); \ | |
650 | } \ | |
651 | hsw_unclaimed_reg_check(dev_priv, reg); \ | |
0d965301 | 652 | REG_WRITE_FOOTER; \ |
907b28c5 | 653 | } |
3967018e | 654 | |
ab2aa47e BW |
655 | static const u32 gen8_shadowed_regs[] = { |
656 | FORCEWAKE_MT, | |
657 | GEN6_RPNSWREQ, | |
658 | GEN6_RC_VIDEO_FREQ, | |
659 | RING_TAIL(RENDER_RING_BASE), | |
660 | RING_TAIL(GEN6_BSD_RING_BASE), | |
661 | RING_TAIL(VEBOX_RING_BASE), | |
662 | RING_TAIL(BLT_RING_BASE), | |
663 | /* TODO: Other registers are not yet used */ | |
664 | }; | |
665 | ||
666 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) | |
667 | { | |
668 | int i; | |
669 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) | |
670 | if (reg == gen8_shadowed_regs[i]) | |
671 | return true; | |
672 | ||
673 | return false; | |
674 | } | |
675 | ||
676 | #define __gen8_write(x) \ | |
677 | static void \ | |
678 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
ab2aa47e | 679 | REG_WRITE_HEADER; \ |
e9dbd2b2 MK |
680 | if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \ |
681 | if (dev_priv->uncore.forcewake_count == 0) \ | |
682 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ | |
683 | FORCEWAKE_ALL); \ | |
684 | __raw_i915_write##x(dev_priv, reg, val); \ | |
685 | if (dev_priv->uncore.forcewake_count == 0) \ | |
686 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ | |
687 | FORCEWAKE_ALL); \ | |
688 | } else { \ | |
689 | __raw_i915_write##x(dev_priv, reg, val); \ | |
ab2aa47e | 690 | } \ |
0d965301 | 691 | REG_WRITE_FOOTER; \ |
ab2aa47e BW |
692 | } |
693 | ||
694 | __gen8_write(8) | |
695 | __gen8_write(16) | |
696 | __gen8_write(32) | |
697 | __gen8_write(64) | |
4032ef43 BW |
698 | __hsw_write(8) |
699 | __hsw_write(16) | |
700 | __hsw_write(32) | |
701 | __hsw_write(64) | |
702 | __gen6_write(8) | |
703 | __gen6_write(16) | |
704 | __gen6_write(32) | |
705 | __gen6_write(64) | |
706 | __gen5_write(8) | |
707 | __gen5_write(16) | |
708 | __gen5_write(32) | |
709 | __gen5_write(64) | |
710 | __gen4_write(8) | |
711 | __gen4_write(16) | |
712 | __gen4_write(32) | |
713 | __gen4_write(64) | |
714 | ||
ab2aa47e | 715 | #undef __gen8_write |
4032ef43 BW |
716 | #undef __hsw_write |
717 | #undef __gen6_write | |
718 | #undef __gen5_write | |
719 | #undef __gen4_write | |
0d965301 | 720 | #undef REG_WRITE_FOOTER |
5d738795 | 721 | #undef REG_WRITE_HEADER |
907b28c5 | 722 | |
0b274481 BW |
723 | void intel_uncore_init(struct drm_device *dev) |
724 | { | |
725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
726 | ||
8232644c CW |
727 | setup_timer(&dev_priv->uncore.force_wake_timer, |
728 | gen6_force_wake_timer, (unsigned long)dev_priv); | |
0b274481 BW |
729 | |
730 | if (IS_VALLEYVIEW(dev)) { | |
940aece4 D |
731 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
732 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; | |
43d1b647 | 733 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
6a68735a MK |
734 | dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; |
735 | dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; | |
0b274481 BW |
736 | } else if (IS_IVYBRIDGE(dev)) { |
737 | u32 ecobus; | |
738 | ||
739 | /* IVB configs may use multi-threaded forcewake */ | |
740 | ||
741 | /* A small trick here - if the bios hasn't configured | |
742 | * MT forcewake, and if the device is in RC6, then | |
743 | * force_wake_mt_get will not wake the device and the | |
744 | * ECOBUS read will return zero. Which will be | |
745 | * (correctly) interpreted by the test below as MT | |
746 | * forcewake being disabled. | |
747 | */ | |
748 | mutex_lock(&dev->struct_mutex); | |
6a68735a | 749 | __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); |
0b274481 | 750 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
6a68735a | 751 | __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); |
0b274481 BW |
752 | mutex_unlock(&dev->struct_mutex); |
753 | ||
754 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
755 | dev_priv->uncore.funcs.force_wake_get = | |
6a68735a | 756 | __gen7_gt_force_wake_mt_get; |
0b274481 | 757 | dev_priv->uncore.funcs.force_wake_put = |
6a68735a | 758 | __gen7_gt_force_wake_mt_put; |
0b274481 BW |
759 | } else { |
760 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); | |
761 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
762 | dev_priv->uncore.funcs.force_wake_get = | |
763 | __gen6_gt_force_wake_get; | |
764 | dev_priv->uncore.funcs.force_wake_put = | |
765 | __gen6_gt_force_wake_put; | |
766 | } | |
767 | } else if (IS_GEN6(dev)) { | |
768 | dev_priv->uncore.funcs.force_wake_get = | |
769 | __gen6_gt_force_wake_get; | |
770 | dev_priv->uncore.funcs.force_wake_put = | |
771 | __gen6_gt_force_wake_put; | |
772 | } | |
773 | ||
3967018e | 774 | switch (INTEL_INFO(dev)->gen) { |
ab2aa47e BW |
775 | default: |
776 | dev_priv->uncore.funcs.mmio_writeb = gen8_write8; | |
777 | dev_priv->uncore.funcs.mmio_writew = gen8_write16; | |
778 | dev_priv->uncore.funcs.mmio_writel = gen8_write32; | |
779 | dev_priv->uncore.funcs.mmio_writeq = gen8_write64; | |
780 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; | |
781 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; | |
782 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; | |
783 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; | |
784 | break; | |
3967018e BW |
785 | case 7: |
786 | case 6: | |
4032ef43 BW |
787 | if (IS_HASWELL(dev)) { |
788 | dev_priv->uncore.funcs.mmio_writeb = hsw_write8; | |
789 | dev_priv->uncore.funcs.mmio_writew = hsw_write16; | |
790 | dev_priv->uncore.funcs.mmio_writel = hsw_write32; | |
791 | dev_priv->uncore.funcs.mmio_writeq = hsw_write64; | |
792 | } else { | |
793 | dev_priv->uncore.funcs.mmio_writeb = gen6_write8; | |
794 | dev_priv->uncore.funcs.mmio_writew = gen6_write16; | |
795 | dev_priv->uncore.funcs.mmio_writel = gen6_write32; | |
796 | dev_priv->uncore.funcs.mmio_writeq = gen6_write64; | |
797 | } | |
940aece4 D |
798 | |
799 | if (IS_VALLEYVIEW(dev)) { | |
800 | dev_priv->uncore.funcs.mmio_readb = vlv_read8; | |
801 | dev_priv->uncore.funcs.mmio_readw = vlv_read16; | |
802 | dev_priv->uncore.funcs.mmio_readl = vlv_read32; | |
803 | dev_priv->uncore.funcs.mmio_readq = vlv_read64; | |
804 | } else { | |
805 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; | |
806 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; | |
807 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; | |
808 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; | |
809 | } | |
3967018e BW |
810 | break; |
811 | case 5: | |
4032ef43 BW |
812 | dev_priv->uncore.funcs.mmio_writeb = gen5_write8; |
813 | dev_priv->uncore.funcs.mmio_writew = gen5_write16; | |
814 | dev_priv->uncore.funcs.mmio_writel = gen5_write32; | |
815 | dev_priv->uncore.funcs.mmio_writeq = gen5_write64; | |
3967018e BW |
816 | dev_priv->uncore.funcs.mmio_readb = gen5_read8; |
817 | dev_priv->uncore.funcs.mmio_readw = gen5_read16; | |
818 | dev_priv->uncore.funcs.mmio_readl = gen5_read32; | |
819 | dev_priv->uncore.funcs.mmio_readq = gen5_read64; | |
820 | break; | |
821 | case 4: | |
822 | case 3: | |
823 | case 2: | |
4032ef43 BW |
824 | dev_priv->uncore.funcs.mmio_writeb = gen4_write8; |
825 | dev_priv->uncore.funcs.mmio_writew = gen4_write16; | |
826 | dev_priv->uncore.funcs.mmio_writel = gen4_write32; | |
827 | dev_priv->uncore.funcs.mmio_writeq = gen4_write64; | |
3967018e BW |
828 | dev_priv->uncore.funcs.mmio_readb = gen4_read8; |
829 | dev_priv->uncore.funcs.mmio_readw = gen4_read16; | |
830 | dev_priv->uncore.funcs.mmio_readl = gen4_read32; | |
831 | dev_priv->uncore.funcs.mmio_readq = gen4_read64; | |
832 | break; | |
833 | } | |
0b274481 BW |
834 | } |
835 | ||
836 | void intel_uncore_fini(struct drm_device *dev) | |
837 | { | |
0b274481 BW |
838 | /* Paranoia: make sure we have disabled everything before we exit. */ |
839 | intel_uncore_sanitize(dev); | |
0294ae7b | 840 | intel_uncore_forcewake_reset(dev, false); |
0b274481 BW |
841 | } |
842 | ||
907b28c5 CW |
843 | static const struct register_whitelist { |
844 | uint64_t offset; | |
845 | uint32_t size; | |
846 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ | |
847 | } whitelist[] = { | |
43181011 | 848 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 }, |
907b28c5 CW |
849 | }; |
850 | ||
851 | int i915_reg_read_ioctl(struct drm_device *dev, | |
852 | void *data, struct drm_file *file) | |
853 | { | |
854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
855 | struct drm_i915_reg_read *reg = data; | |
856 | struct register_whitelist const *entry = whitelist; | |
857 | int i; | |
858 | ||
859 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
860 | if (entry->offset == reg->offset && | |
861 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | |
862 | break; | |
863 | } | |
864 | ||
865 | if (i == ARRAY_SIZE(whitelist)) | |
866 | return -EINVAL; | |
867 | ||
868 | switch (entry->size) { | |
869 | case 8: | |
870 | reg->val = I915_READ64(reg->offset); | |
871 | break; | |
872 | case 4: | |
873 | reg->val = I915_READ(reg->offset); | |
874 | break; | |
875 | case 2: | |
876 | reg->val = I915_READ16(reg->offset); | |
877 | break; | |
878 | case 1: | |
879 | reg->val = I915_READ8(reg->offset); | |
880 | break; | |
881 | default: | |
882 | WARN_ON(1); | |
883 | return -EINVAL; | |
884 | } | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
b6359918 MK |
889 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
890 | void *data, struct drm_file *file) | |
891 | { | |
892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
893 | struct drm_i915_reset_stats *args = data; | |
894 | struct i915_ctx_hang_stats *hs; | |
41bde553 | 895 | struct i915_hw_context *ctx; |
b6359918 MK |
896 | int ret; |
897 | ||
661df041 MK |
898 | if (args->flags || args->pad) |
899 | return -EINVAL; | |
900 | ||
b6359918 MK |
901 | if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN)) |
902 | return -EPERM; | |
903 | ||
904 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
905 | if (ret) | |
906 | return ret; | |
907 | ||
41bde553 BW |
908 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
909 | if (IS_ERR(ctx)) { | |
b6359918 | 910 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 911 | return PTR_ERR(ctx); |
b6359918 | 912 | } |
41bde553 | 913 | hs = &ctx->hang_stats; |
b6359918 MK |
914 | |
915 | if (capable(CAP_SYS_ADMIN)) | |
916 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
917 | else | |
918 | args->reset_count = 0; | |
919 | ||
920 | args->batch_active = hs->batch_active; | |
921 | args->batch_pending = hs->batch_pending; | |
922 | ||
923 | mutex_unlock(&dev->struct_mutex); | |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
907b28c5 CW |
928 | static int i965_reset_complete(struct drm_device *dev) |
929 | { | |
930 | u8 gdrst; | |
931 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | |
932 | return (gdrst & GRDOM_RESET_ENABLE) == 0; | |
933 | } | |
934 | ||
935 | static int i965_do_reset(struct drm_device *dev) | |
936 | { | |
937 | int ret; | |
938 | ||
939 | /* | |
940 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
941 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
942 | * triggers the reset; when done, the hardware will clear it. | |
943 | */ | |
944 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
945 | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
946 | ret = wait_for(i965_reset_complete(dev), 500); | |
947 | if (ret) | |
948 | return ret; | |
949 | ||
950 | /* We can't reset render&media without also resetting display ... */ | |
951 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
952 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
953 | ||
954 | ret = wait_for(i965_reset_complete(dev), 500); | |
955 | if (ret) | |
956 | return ret; | |
957 | ||
958 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
963 | static int ironlake_do_reset(struct drm_device *dev) | |
964 | { | |
965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
966 | u32 gdrst; | |
967 | int ret; | |
968 | ||
969 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
970 | gdrst &= ~GRDOM_MASK; | |
971 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
972 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
973 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
974 | if (ret) | |
975 | return ret; | |
976 | ||
977 | /* We can't reset render&media without also resetting display ... */ | |
978 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
979 | gdrst &= ~GRDOM_MASK; | |
980 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
981 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
982 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
983 | } | |
984 | ||
985 | static int gen6_do_reset(struct drm_device *dev) | |
986 | { | |
987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
988 | int ret; | |
907b28c5 CW |
989 | |
990 | /* Reset the chip */ | |
991 | ||
992 | /* GEN6_GDRST is not in the gt power well, no need to check | |
993 | * for fifo space for the write or forcewake the chip for | |
994 | * the read | |
995 | */ | |
6af5d92f | 996 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
907b28c5 CW |
997 | |
998 | /* Spin waiting for the device to ack the reset request */ | |
6af5d92f | 999 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
907b28c5 | 1000 | |
0294ae7b | 1001 | intel_uncore_forcewake_reset(dev, true); |
5babf0fc | 1002 | |
907b28c5 CW |
1003 | return ret; |
1004 | } | |
1005 | ||
1006 | int intel_gpu_reset(struct drm_device *dev) | |
1007 | { | |
1008 | switch (INTEL_INFO(dev)->gen) { | |
935e8de9 | 1009 | case 8: |
907b28c5 CW |
1010 | case 7: |
1011 | case 6: return gen6_do_reset(dev); | |
1012 | case 5: return ironlake_do_reset(dev); | |
1013 | case 4: return i965_do_reset(dev); | |
907b28c5 CW |
1014 | default: return -ENODEV; |
1015 | } | |
1016 | } | |
1017 | ||
907b28c5 CW |
1018 | void intel_uncore_check_errors(struct drm_device *dev) |
1019 | { | |
1020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1021 | ||
1022 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && | |
6af5d92f | 1023 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
907b28c5 | 1024 | DRM_ERROR("Unclaimed register before interrupt\n"); |
6af5d92f | 1025 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
1026 | } |
1027 | } |