Commit | Line | Data |
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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
cf9d2890 | 26 | #include "i915_vgpu.h" |
907b28c5 | 27 | |
6daccb0b CW |
28 | #include <linux/pm_runtime.h> |
29 | ||
83e33372 | 30 | #define FORCEWAKE_ACK_TIMEOUT_MS 50 |
907b28c5 | 31 | |
75aa3f63 | 32 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__)) |
6af5d92f | 33 | |
05a2fb15 MK |
34 | static const char * const forcewake_domain_names[] = { |
35 | "render", | |
36 | "blitter", | |
37 | "media", | |
38 | }; | |
39 | ||
40 | const char * | |
48c1026a | 41 | intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) |
05a2fb15 | 42 | { |
53abb679 | 43 | BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); |
05a2fb15 MK |
44 | |
45 | if (id >= 0 && id < FW_DOMAIN_ID_COUNT) | |
46 | return forcewake_domain_names[id]; | |
47 | ||
48 | WARN_ON(id); | |
49 | ||
50 | return "unknown"; | |
51 | } | |
52 | ||
b2ec142c PZ |
53 | static void |
54 | assert_device_not_suspended(struct drm_i915_private *dev_priv) | |
55 | { | |
2b387059 CW |
56 | WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, |
57 | "Device suspended\n"); | |
b2ec142c | 58 | } |
6af5d92f | 59 | |
05a2fb15 MK |
60 | static inline void |
61 | fw_domain_reset(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 62 | { |
f9b3927a | 63 | WARN_ON(d->reg_set == 0); |
05a2fb15 | 64 | __raw_i915_write32(d->i915, d->reg_set, d->val_reset); |
907b28c5 CW |
65 | } |
66 | ||
05a2fb15 MK |
67 | static inline void |
68 | fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 69 | { |
05a2fb15 | 70 | mod_timer_pinned(&d->timer, jiffies + 1); |
907b28c5 CW |
71 | } |
72 | ||
05a2fb15 MK |
73 | static inline void |
74 | fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 75 | { |
05a2fb15 MK |
76 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & |
77 | FORCEWAKE_KERNEL) == 0, | |
907b28c5 | 78 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
79 | DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", |
80 | intel_uncore_forcewake_domain_to_str(d->id)); | |
81 | } | |
907b28c5 | 82 | |
05a2fb15 MK |
83 | static inline void |
84 | fw_domain_get(const struct intel_uncore_forcewake_domain *d) | |
85 | { | |
86 | __raw_i915_write32(d->i915, d->reg_set, d->val_set); | |
87 | } | |
907b28c5 | 88 | |
05a2fb15 MK |
89 | static inline void |
90 | fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d) | |
91 | { | |
92 | if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) & | |
93 | FORCEWAKE_KERNEL), | |
907b28c5 | 94 | FORCEWAKE_ACK_TIMEOUT_MS)) |
05a2fb15 MK |
95 | DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", |
96 | intel_uncore_forcewake_domain_to_str(d->id)); | |
97 | } | |
907b28c5 | 98 | |
05a2fb15 MK |
99 | static inline void |
100 | fw_domain_put(const struct intel_uncore_forcewake_domain *d) | |
101 | { | |
102 | __raw_i915_write32(d->i915, d->reg_set, d->val_clear); | |
907b28c5 CW |
103 | } |
104 | ||
05a2fb15 MK |
105 | static inline void |
106 | fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d) | |
907b28c5 | 107 | { |
05a2fb15 MK |
108 | /* something from same cacheline, but not from the set register */ |
109 | if (d->reg_post) | |
110 | __raw_posting_read(d->i915, d->reg_post); | |
907b28c5 CW |
111 | } |
112 | ||
05a2fb15 | 113 | static void |
48c1026a | 114 | fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
907b28c5 | 115 | { |
05a2fb15 | 116 | struct intel_uncore_forcewake_domain *d; |
48c1026a | 117 | enum forcewake_domain_id id; |
907b28c5 | 118 | |
05a2fb15 MK |
119 | for_each_fw_domain_mask(d, fw_domains, dev_priv, id) { |
120 | fw_domain_wait_ack_clear(d); | |
121 | fw_domain_get(d); | |
05a2fb15 MK |
122 | fw_domain_wait_ack(d); |
123 | } | |
124 | } | |
907b28c5 | 125 | |
05a2fb15 | 126 | static void |
48c1026a | 127 | fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
128 | { |
129 | struct intel_uncore_forcewake_domain *d; | |
48c1026a | 130 | enum forcewake_domain_id id; |
907b28c5 | 131 | |
05a2fb15 MK |
132 | for_each_fw_domain_mask(d, fw_domains, dev_priv, id) { |
133 | fw_domain_put(d); | |
134 | fw_domain_posting_read(d); | |
135 | } | |
136 | } | |
907b28c5 | 137 | |
05a2fb15 MK |
138 | static void |
139 | fw_domains_posting_read(struct drm_i915_private *dev_priv) | |
140 | { | |
141 | struct intel_uncore_forcewake_domain *d; | |
48c1026a | 142 | enum forcewake_domain_id id; |
05a2fb15 MK |
143 | |
144 | /* No need to do for all, just do for first found */ | |
145 | for_each_fw_domain(d, dev_priv, id) { | |
146 | fw_domain_posting_read(d); | |
147 | break; | |
148 | } | |
149 | } | |
150 | ||
151 | static void | |
48c1026a | 152 | fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains) |
05a2fb15 MK |
153 | { |
154 | struct intel_uncore_forcewake_domain *d; | |
48c1026a | 155 | enum forcewake_domain_id id; |
05a2fb15 | 156 | |
3225b2f9 MK |
157 | if (dev_priv->uncore.fw_domains == 0) |
158 | return; | |
f9b3927a | 159 | |
05a2fb15 MK |
160 | for_each_fw_domain_mask(d, fw_domains, dev_priv, id) |
161 | fw_domain_reset(d); | |
162 | ||
163 | fw_domains_posting_read(dev_priv); | |
164 | } | |
165 | ||
166 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) | |
167 | { | |
168 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
169 | * thread to wake up. | |
170 | */ | |
171 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & | |
172 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) | |
173 | DRM_ERROR("GT thread status wait timed out\n"); | |
174 | } | |
175 | ||
176 | static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv, | |
48c1026a | 177 | enum forcewake_domains fw_domains) |
05a2fb15 MK |
178 | { |
179 | fw_domains_get(dev_priv, fw_domains); | |
907b28c5 | 180 | |
05a2fb15 | 181 | /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ |
c549f738 | 182 | __gen6_gt_wait_for_thread_c0(dev_priv); |
907b28c5 CW |
183 | } |
184 | ||
185 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
186 | { | |
187 | u32 gtfifodbg; | |
6af5d92f CW |
188 | |
189 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
90f256b5 VS |
190 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
191 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); | |
907b28c5 CW |
192 | } |
193 | ||
05a2fb15 | 194 | static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv, |
48c1026a | 195 | enum forcewake_domains fw_domains) |
907b28c5 | 196 | { |
05a2fb15 | 197 | fw_domains_put(dev_priv, fw_domains); |
907b28c5 CW |
198 | gen6_gt_check_fifodbg(dev_priv); |
199 | } | |
200 | ||
c32e3788 DG |
201 | static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) |
202 | { | |
203 | u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); | |
204 | ||
205 | return count & GT_FIFO_FREE_ENTRIES_MASK; | |
206 | } | |
207 | ||
907b28c5 CW |
208 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
209 | { | |
210 | int ret = 0; | |
211 | ||
5135d64b D |
212 | /* On VLV, FIFO will be shared by both SW and HW. |
213 | * So, we need to read the FREE_ENTRIES everytime */ | |
214 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
c32e3788 | 215 | dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); |
5135d64b | 216 | |
907b28c5 CW |
217 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
218 | int loop = 500; | |
c32e3788 DG |
219 | u32 fifo = fifo_free_entries(dev_priv); |
220 | ||
907b28c5 CW |
221 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
222 | udelay(10); | |
c32e3788 | 223 | fifo = fifo_free_entries(dev_priv); |
907b28c5 CW |
224 | } |
225 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
226 | ++ret; | |
227 | dev_priv->uncore.fifo_count = fifo; | |
228 | } | |
229 | dev_priv->uncore.fifo_count--; | |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
59bad947 | 234 | static void intel_uncore_fw_release_timer(unsigned long arg) |
38cff0b1 | 235 | { |
b2cff0db CW |
236 | struct intel_uncore_forcewake_domain *domain = (void *)arg; |
237 | unsigned long irqflags; | |
38cff0b1 | 238 | |
b2cff0db | 239 | assert_device_not_suspended(domain->i915); |
38cff0b1 | 240 | |
b2cff0db CW |
241 | spin_lock_irqsave(&domain->i915->uncore.lock, irqflags); |
242 | if (WARN_ON(domain->wake_count == 0)) | |
243 | domain->wake_count++; | |
244 | ||
245 | if (--domain->wake_count == 0) | |
246 | domain->i915->uncore.funcs.force_wake_put(domain->i915, | |
247 | 1 << domain->id); | |
248 | ||
249 | spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags); | |
38cff0b1 ZW |
250 | } |
251 | ||
b2cff0db | 252 | void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
38cff0b1 | 253 | { |
b2cff0db | 254 | struct drm_i915_private *dev_priv = dev->dev_private; |
48c1026a | 255 | unsigned long irqflags; |
b2cff0db | 256 | struct intel_uncore_forcewake_domain *domain; |
48c1026a MK |
257 | int retry_count = 100; |
258 | enum forcewake_domain_id id; | |
259 | enum forcewake_domains fw = 0, active_domains; | |
38cff0b1 | 260 | |
b2cff0db CW |
261 | /* Hold uncore.lock across reset to prevent any register access |
262 | * with forcewake not set correctly. Wait until all pending | |
263 | * timers are run before holding. | |
264 | */ | |
265 | while (1) { | |
266 | active_domains = 0; | |
38cff0b1 | 267 | |
b2cff0db CW |
268 | for_each_fw_domain(domain, dev_priv, id) { |
269 | if (del_timer_sync(&domain->timer) == 0) | |
270 | continue; | |
38cff0b1 | 271 | |
59bad947 | 272 | intel_uncore_fw_release_timer((unsigned long)domain); |
b2cff0db | 273 | } |
aec347ab | 274 | |
b2cff0db | 275 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
b2ec142c | 276 | |
b2cff0db CW |
277 | for_each_fw_domain(domain, dev_priv, id) { |
278 | if (timer_pending(&domain->timer)) | |
279 | active_domains |= (1 << id); | |
280 | } | |
3123fcaf | 281 | |
b2cff0db CW |
282 | if (active_domains == 0) |
283 | break; | |
aec347ab | 284 | |
b2cff0db CW |
285 | if (--retry_count == 0) { |
286 | DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); | |
287 | break; | |
288 | } | |
0294ae7b | 289 | |
b2cff0db CW |
290 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
291 | cond_resched(); | |
292 | } | |
0294ae7b | 293 | |
b2cff0db CW |
294 | WARN_ON(active_domains); |
295 | ||
296 | for_each_fw_domain(domain, dev_priv, id) | |
297 | if (domain->wake_count) | |
298 | fw |= 1 << id; | |
299 | ||
300 | if (fw) | |
301 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); | |
ef46e0d2 | 302 | |
05a2fb15 | 303 | fw_domains_reset(dev_priv, FORCEWAKE_ALL); |
38cff0b1 | 304 | |
0294ae7b | 305 | if (restore) { /* If reset with a user forcewake, try to restore */ |
0294ae7b CW |
306 | if (fw) |
307 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); | |
308 | ||
309 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
310 | dev_priv->uncore.fifo_count = | |
c32e3788 | 311 | fifo_free_entries(dev_priv); |
0294ae7b CW |
312 | } |
313 | ||
b2cff0db | 314 | if (!restore) |
59bad947 | 315 | assert_forcewakes_inactive(dev_priv); |
b2cff0db | 316 | |
0294ae7b | 317 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
ef46e0d2 DV |
318 | } |
319 | ||
f9b3927a | 320 | static void intel_uncore_ellc_detect(struct drm_device *dev) |
907b28c5 CW |
321 | { |
322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
323 | ||
e25dca86 DL |
324 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev) || |
325 | INTEL_INFO(dev)->gen >= 9) && | |
2db59d53 | 326 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) { |
18ce3994 BW |
327 | /* The docs do not explain exactly how the calculation can be |
328 | * made. It is somewhat guessable, but for now, it's always | |
329 | * 128MB. | |
330 | * NB: We can't write IDICR yet because we do not have gt funcs | |
331 | * set up */ | |
332 | dev_priv->ellc_size = 128; | |
333 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); | |
334 | } | |
f9b3927a MK |
335 | } |
336 | ||
337 | static void __intel_uncore_early_sanitize(struct drm_device *dev, | |
338 | bool restore_forcewake) | |
339 | { | |
340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
341 | ||
342 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) | |
343 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
907b28c5 | 344 | |
97058870 VS |
345 | /* clear out old GT FIFO errors */ |
346 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
347 | __raw_i915_write32(dev_priv, GTFIFODBG, | |
348 | __raw_i915_read32(dev_priv, GTFIFODBG)); | |
349 | ||
a04f90a3 D |
350 | /* WaDisableShadowRegForCpd:chv */ |
351 | if (IS_CHERRYVIEW(dev)) { | |
352 | __raw_i915_write32(dev_priv, GTFIFOCTL, | |
353 | __raw_i915_read32(dev_priv, GTFIFOCTL) | | |
354 | GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | | |
355 | GT_FIFO_CTL_RC6_POLICY_STALL); | |
356 | } | |
357 | ||
10018603 | 358 | intel_uncore_forcewake_reset(dev, restore_forcewake); |
521198a2 MK |
359 | } |
360 | ||
ed493883 ID |
361 | void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) |
362 | { | |
363 | __intel_uncore_early_sanitize(dev, restore_forcewake); | |
364 | i915_check_and_clear_faults(dev); | |
365 | } | |
366 | ||
521198a2 MK |
367 | void intel_uncore_sanitize(struct drm_device *dev) |
368 | { | |
907b28c5 CW |
369 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
370 | intel_disable_gt_powersave(dev); | |
371 | } | |
372 | ||
a6111f7b CW |
373 | static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
374 | enum forcewake_domains fw_domains) | |
375 | { | |
376 | struct intel_uncore_forcewake_domain *domain; | |
377 | enum forcewake_domain_id id; | |
378 | ||
379 | if (!dev_priv->uncore.funcs.force_wake_get) | |
380 | return; | |
381 | ||
382 | fw_domains &= dev_priv->uncore.fw_domains; | |
383 | ||
384 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { | |
385 | if (domain->wake_count++) | |
386 | fw_domains &= ~(1 << id); | |
387 | } | |
388 | ||
389 | if (fw_domains) | |
390 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
391 | } | |
392 | ||
59bad947 MK |
393 | /** |
394 | * intel_uncore_forcewake_get - grab forcewake domain references | |
395 | * @dev_priv: i915 device instance | |
396 | * @fw_domains: forcewake domains to get reference on | |
397 | * | |
398 | * This function can be used get GT's forcewake domain references. | |
399 | * Normal register access will handle the forcewake domains automatically. | |
400 | * However if some sequence requires the GT to not power down a particular | |
401 | * forcewake domains this function should be called at the beginning of the | |
402 | * sequence. And subsequently the reference should be dropped by symmetric | |
403 | * call to intel_unforce_forcewake_put(). Usually caller wants all the domains | |
404 | * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. | |
907b28c5 | 405 | */ |
59bad947 | 406 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 407 | enum forcewake_domains fw_domains) |
907b28c5 CW |
408 | { |
409 | unsigned long irqflags; | |
410 | ||
ab484f8f BW |
411 | if (!dev_priv->uncore.funcs.force_wake_get) |
412 | return; | |
413 | ||
6daccb0b | 414 | WARN_ON(dev_priv->pm.suspended); |
c8c8fb33 | 415 | |
6daccb0b | 416 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
a6111f7b | 417 | __intel_uncore_forcewake_get(dev_priv, fw_domains); |
907b28c5 CW |
418 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
419 | } | |
420 | ||
59bad947 | 421 | /** |
a6111f7b | 422 | * intel_uncore_forcewake_get__locked - grab forcewake domain references |
59bad947 | 423 | * @dev_priv: i915 device instance |
a6111f7b | 424 | * @fw_domains: forcewake domains to get reference on |
59bad947 | 425 | * |
a6111f7b CW |
426 | * See intel_uncore_forcewake_get(). This variant places the onus |
427 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
907b28c5 | 428 | */ |
a6111f7b CW |
429 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, |
430 | enum forcewake_domains fw_domains) | |
431 | { | |
432 | assert_spin_locked(&dev_priv->uncore.lock); | |
433 | ||
434 | if (!dev_priv->uncore.funcs.force_wake_get) | |
435 | return; | |
436 | ||
437 | __intel_uncore_forcewake_get(dev_priv, fw_domains); | |
438 | } | |
439 | ||
440 | static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
441 | enum forcewake_domains fw_domains) | |
907b28c5 | 442 | { |
b2cff0db | 443 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 444 | enum forcewake_domain_id id; |
907b28c5 | 445 | |
ab484f8f BW |
446 | if (!dev_priv->uncore.funcs.force_wake_put) |
447 | return; | |
448 | ||
b2cff0db CW |
449 | fw_domains &= dev_priv->uncore.fw_domains; |
450 | ||
b2cff0db CW |
451 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { |
452 | if (WARN_ON(domain->wake_count == 0)) | |
453 | continue; | |
454 | ||
455 | if (--domain->wake_count) | |
456 | continue; | |
457 | ||
458 | domain->wake_count++; | |
05a2fb15 | 459 | fw_domain_arm_timer(domain); |
aec347ab | 460 | } |
a6111f7b | 461 | } |
dc9fb09c | 462 | |
a6111f7b CW |
463 | /** |
464 | * intel_uncore_forcewake_put - release a forcewake domain reference | |
465 | * @dev_priv: i915 device instance | |
466 | * @fw_domains: forcewake domains to put references | |
467 | * | |
468 | * This function drops the device-level forcewakes for specified | |
469 | * domains obtained by intel_uncore_forcewake_get(). | |
470 | */ | |
471 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, | |
472 | enum forcewake_domains fw_domains) | |
473 | { | |
474 | unsigned long irqflags; | |
475 | ||
476 | if (!dev_priv->uncore.funcs.force_wake_put) | |
477 | return; | |
478 | ||
479 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
480 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
907b28c5 CW |
481 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
482 | } | |
483 | ||
a6111f7b CW |
484 | /** |
485 | * intel_uncore_forcewake_put__locked - grab forcewake domain references | |
486 | * @dev_priv: i915 device instance | |
487 | * @fw_domains: forcewake domains to get reference on | |
488 | * | |
489 | * See intel_uncore_forcewake_put(). This variant places the onus | |
490 | * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. | |
491 | */ | |
492 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
493 | enum forcewake_domains fw_domains) | |
494 | { | |
495 | assert_spin_locked(&dev_priv->uncore.lock); | |
496 | ||
497 | if (!dev_priv->uncore.funcs.force_wake_put) | |
498 | return; | |
499 | ||
500 | __intel_uncore_forcewake_put(dev_priv, fw_domains); | |
501 | } | |
502 | ||
59bad947 | 503 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) |
e998c40f | 504 | { |
b2cff0db | 505 | struct intel_uncore_forcewake_domain *domain; |
48c1026a | 506 | enum forcewake_domain_id id; |
b2cff0db | 507 | |
e998c40f PZ |
508 | if (!dev_priv->uncore.funcs.force_wake_get) |
509 | return; | |
510 | ||
05a2fb15 | 511 | for_each_fw_domain(domain, dev_priv, id) |
b2cff0db | 512 | WARN_ON(domain->wake_count); |
e998c40f PZ |
513 | } |
514 | ||
907b28c5 | 515 | /* We give fast paths for the really cool registers */ |
40181697 | 516 | #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) |
907b28c5 | 517 | |
1938e59a | 518 | #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) |
38fb6a40 | 519 | |
1938e59a D |
520 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
521 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
522 | REG_RANGE((reg), 0x5000, 0x8000) || \ | |
523 | REG_RANGE((reg), 0xB000, 0x12000) || \ | |
524 | REG_RANGE((reg), 0x2E000, 0x30000)) | |
525 | ||
526 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ | |
527 | (REG_RANGE((reg), 0x12000, 0x14000) || \ | |
528 | REG_RANGE((reg), 0x22000, 0x24000) || \ | |
529 | REG_RANGE((reg), 0x30000, 0x40000)) | |
530 | ||
531 | #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ | |
532 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
db5ff4ac | 533 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
1938e59a | 534 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
db5ff4ac | 535 | REG_RANGE((reg), 0xB000, 0xB480) || \ |
1938e59a D |
536 | REG_RANGE((reg), 0xE000, 0xE800)) |
537 | ||
538 | #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ | |
539 | (REG_RANGE((reg), 0x8800, 0x8900) || \ | |
540 | REG_RANGE((reg), 0xD000, 0xD800) || \ | |
541 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
542 | REG_RANGE((reg), 0x1A000, 0x1C000) || \ | |
543 | REG_RANGE((reg), 0x1E800, 0x1EA00) || \ | |
db5ff4ac | 544 | REG_RANGE((reg), 0x30000, 0x38000)) |
1938e59a D |
545 | |
546 | #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ | |
547 | (REG_RANGE((reg), 0x4000, 0x5000) || \ | |
548 | REG_RANGE((reg), 0x8000, 0x8300) || \ | |
549 | REG_RANGE((reg), 0x8500, 0x8600) || \ | |
550 | REG_RANGE((reg), 0x9000, 0xB000) || \ | |
db5ff4ac | 551 | REG_RANGE((reg), 0xF000, 0x10000)) |
38fb6a40 | 552 | |
4597a88a | 553 | #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ |
8ee558d8 | 554 | REG_RANGE((reg), 0xB00, 0x2000) |
4597a88a ZW |
555 | |
556 | #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
557 | (REG_RANGE((reg), 0x2000, 0x2700) || \ |
558 | REG_RANGE((reg), 0x3000, 0x4000) || \ | |
4597a88a | 559 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
8ee558d8 | 560 | REG_RANGE((reg), 0x8140, 0x8160) || \ |
4597a88a ZW |
561 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
562 | REG_RANGE((reg), 0x8C00, 0x8D00) || \ | |
563 | REG_RANGE((reg), 0xB000, 0xB480) || \ | |
8ee558d8 AG |
564 | REG_RANGE((reg), 0xE000, 0xE900) || \ |
565 | REG_RANGE((reg), 0x24400, 0x24800)) | |
4597a88a ZW |
566 | |
567 | #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
568 | (REG_RANGE((reg), 0x8130, 0x8140) || \ |
569 | REG_RANGE((reg), 0x8800, 0x8A00) || \ | |
4597a88a ZW |
570 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
571 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
572 | REG_RANGE((reg), 0x1A000, 0x1EA00) || \ | |
573 | REG_RANGE((reg), 0x30000, 0x40000)) | |
574 | ||
575 | #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ | |
576 | REG_RANGE((reg), 0x9400, 0x9800) | |
577 | ||
578 | #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ | |
0c8bfe52 | 579 | ((reg) < 0x40000 && \ |
4597a88a ZW |
580 | !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ |
581 | !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ | |
582 | !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ | |
583 | !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) | |
584 | ||
907b28c5 CW |
585 | static void |
586 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
587 | { | |
588 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
589 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
590 | * hence harmless to write 0 into. */ | |
6af5d92f | 591 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
592 | } |
593 | ||
594 | static void | |
5978118c PZ |
595 | hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, |
596 | bool before) | |
907b28c5 | 597 | { |
5978118c PZ |
598 | const char *op = read ? "reading" : "writing to"; |
599 | const char *when = before ? "before" : "after"; | |
600 | ||
601 | if (!i915.mmio_debug) | |
602 | return; | |
603 | ||
ab484f8f | 604 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
5978118c PZ |
605 | WARN(1, "Unclaimed register detected %s %s register 0x%x\n", |
606 | when, op, reg); | |
6af5d92f | 607 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
48572edd | 608 | i915.mmio_debug--; /* Only report the first N failures */ |
907b28c5 CW |
609 | } |
610 | } | |
611 | ||
612 | static void | |
5978118c | 613 | hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv) |
907b28c5 | 614 | { |
48572edd CW |
615 | static bool mmio_debug_once = true; |
616 | ||
617 | if (i915.mmio_debug || !mmio_debug_once) | |
5978118c PZ |
618 | return; |
619 | ||
ab484f8f | 620 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
48572edd CW |
621 | DRM_DEBUG("Unclaimed register detected, " |
622 | "enabling oneshot unclaimed register reporting. " | |
623 | "Please use i915.mmio_debug=N for more information.\n"); | |
6af5d92f | 624 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
48572edd | 625 | i915.mmio_debug = mmio_debug_once--; |
907b28c5 CW |
626 | } |
627 | } | |
628 | ||
51f67885 | 629 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 630 | u##x val = 0; \ |
51f67885 | 631 | assert_device_not_suspended(dev_priv); |
5d738795 | 632 | |
51f67885 | 633 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
634 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
635 | return val | |
636 | ||
51f67885 | 637 | #define __gen2_read(x) \ |
0b274481 | 638 | static u##x \ |
51f67885 CW |
639 | gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
640 | GEN2_READ_HEADER(x); \ | |
3967018e | 641 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 642 | GEN2_READ_FOOTER; \ |
3967018e BW |
643 | } |
644 | ||
645 | #define __gen5_read(x) \ | |
646 | static u##x \ | |
647 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
51f67885 | 648 | GEN2_READ_HEADER(x); \ |
3967018e BW |
649 | ilk_dummy_write(dev_priv); \ |
650 | val = __raw_i915_read##x(dev_priv, reg); \ | |
51f67885 | 651 | GEN2_READ_FOOTER; \ |
3967018e BW |
652 | } |
653 | ||
51f67885 CW |
654 | __gen5_read(8) |
655 | __gen5_read(16) | |
656 | __gen5_read(32) | |
657 | __gen5_read(64) | |
658 | __gen2_read(8) | |
659 | __gen2_read(16) | |
660 | __gen2_read(32) | |
661 | __gen2_read(64) | |
662 | ||
663 | #undef __gen5_read | |
664 | #undef __gen2_read | |
665 | ||
666 | #undef GEN2_READ_FOOTER | |
667 | #undef GEN2_READ_HEADER | |
668 | ||
669 | #define GEN6_READ_HEADER(x) \ | |
0670c5a6 | 670 | u32 offset = reg; \ |
51f67885 CW |
671 | unsigned long irqflags; \ |
672 | u##x val = 0; \ | |
673 | assert_device_not_suspended(dev_priv); \ | |
674 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
675 | ||
676 | #define GEN6_READ_FOOTER \ | |
677 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
678 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
679 | return val | |
680 | ||
b2cff0db | 681 | static inline void __force_wake_get(struct drm_i915_private *dev_priv, |
48c1026a | 682 | enum forcewake_domains fw_domains) |
b2cff0db CW |
683 | { |
684 | struct intel_uncore_forcewake_domain *domain; | |
48c1026a | 685 | enum forcewake_domain_id id; |
b2cff0db CW |
686 | |
687 | if (WARN_ON(!fw_domains)) | |
688 | return; | |
689 | ||
690 | /* Ideally GCC would be constant-fold and eliminate this loop */ | |
05a2fb15 | 691 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { |
b2cff0db | 692 | if (domain->wake_count) { |
05a2fb15 | 693 | fw_domains &= ~(1 << id); |
b2cff0db CW |
694 | continue; |
695 | } | |
696 | ||
697 | domain->wake_count++; | |
05a2fb15 | 698 | fw_domain_arm_timer(domain); |
b2cff0db CW |
699 | } |
700 | ||
701 | if (fw_domains) | |
702 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
703 | } | |
704 | ||
3967018e BW |
705 | #define __gen6_read(x) \ |
706 | static u##x \ | |
707 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
51f67885 | 708 | GEN6_READ_HEADER(x); \ |
5978118c | 709 | hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ |
0670c5a6 | 710 | if (NEEDS_FORCE_WAKE(offset)) \ |
b2cff0db | 711 | __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ |
dc9fb09c | 712 | val = __raw_i915_read##x(dev_priv, reg); \ |
5978118c | 713 | hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ |
51f67885 | 714 | GEN6_READ_FOOTER; \ |
907b28c5 CW |
715 | } |
716 | ||
940aece4 D |
717 | #define __vlv_read(x) \ |
718 | static u##x \ | |
719 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
6a42d0f4 | 720 | enum forcewake_domains fw_engine = 0; \ |
51f67885 | 721 | GEN6_READ_HEADER(x); \ |
0670c5a6 | 722 | if (!NEEDS_FORCE_WAKE(offset)) \ |
e97d8fbe | 723 | fw_engine = 0; \ |
0670c5a6 | 724 | else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 725 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 726 | else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \ |
6a42d0f4 VS |
727 | fw_engine = FORCEWAKE_MEDIA; \ |
728 | if (fw_engine) \ | |
729 | __force_wake_get(dev_priv, fw_engine); \ | |
6fe72865 | 730 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 731 | GEN6_READ_FOOTER; \ |
940aece4 D |
732 | } |
733 | ||
1938e59a D |
734 | #define __chv_read(x) \ |
735 | static u##x \ | |
736 | chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
6a42d0f4 | 737 | enum forcewake_domains fw_engine = 0; \ |
51f67885 | 738 | GEN6_READ_HEADER(x); \ |
0670c5a6 | 739 | if (!NEEDS_FORCE_WAKE(offset)) \ |
e97d8fbe | 740 | fw_engine = 0; \ |
0670c5a6 | 741 | else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 742 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 743 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 744 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 745 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ |
6a42d0f4 VS |
746 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
747 | if (fw_engine) \ | |
748 | __force_wake_get(dev_priv, fw_engine); \ | |
1938e59a | 749 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 750 | GEN6_READ_FOOTER; \ |
1938e59a | 751 | } |
940aece4 | 752 | |
ded17493 | 753 | #define SKL_NEEDS_FORCE_WAKE(reg) \ |
0c8bfe52 | 754 | ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) |
4597a88a ZW |
755 | |
756 | #define __gen9_read(x) \ | |
757 | static u##x \ | |
758 | gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
48c1026a | 759 | enum forcewake_domains fw_engine; \ |
51f67885 | 760 | GEN6_READ_HEADER(x); \ |
6c908bf4 | 761 | hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ |
0670c5a6 | 762 | if (!SKL_NEEDS_FORCE_WAKE(offset)) \ |
b2cff0db | 763 | fw_engine = 0; \ |
0670c5a6 | 764 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ |
b2cff0db | 765 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 766 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ |
b2cff0db | 767 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 768 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ |
b2cff0db CW |
769 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
770 | else \ | |
771 | fw_engine = FORCEWAKE_BLITTER; \ | |
772 | if (fw_engine) \ | |
773 | __force_wake_get(dev_priv, fw_engine); \ | |
774 | val = __raw_i915_read##x(dev_priv, reg); \ | |
6c908bf4 | 775 | hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ |
51f67885 | 776 | GEN6_READ_FOOTER; \ |
4597a88a ZW |
777 | } |
778 | ||
779 | __gen9_read(8) | |
780 | __gen9_read(16) | |
781 | __gen9_read(32) | |
782 | __gen9_read(64) | |
1938e59a D |
783 | __chv_read(8) |
784 | __chv_read(16) | |
785 | __chv_read(32) | |
786 | __chv_read(64) | |
940aece4 D |
787 | __vlv_read(8) |
788 | __vlv_read(16) | |
789 | __vlv_read(32) | |
790 | __vlv_read(64) | |
3967018e BW |
791 | __gen6_read(8) |
792 | __gen6_read(16) | |
793 | __gen6_read(32) | |
794 | __gen6_read(64) | |
3967018e | 795 | |
4597a88a | 796 | #undef __gen9_read |
1938e59a | 797 | #undef __chv_read |
940aece4 | 798 | #undef __vlv_read |
3967018e | 799 | #undef __gen6_read |
51f67885 CW |
800 | #undef GEN6_READ_FOOTER |
801 | #undef GEN6_READ_HEADER | |
5d738795 | 802 | |
8a74db7a VS |
803 | #define VGPU_READ_HEADER(x) \ |
804 | unsigned long irqflags; \ | |
805 | u##x val = 0; \ | |
806 | assert_device_not_suspended(dev_priv); \ | |
807 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
808 | ||
809 | #define VGPU_READ_FOOTER \ | |
810 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
811 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
812 | return val | |
813 | ||
814 | #define __vgpu_read(x) \ | |
815 | static u##x \ | |
816 | vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
817 | VGPU_READ_HEADER(x); \ | |
818 | val = __raw_i915_read##x(dev_priv, reg); \ | |
819 | VGPU_READ_FOOTER; \ | |
820 | } | |
821 | ||
822 | __vgpu_read(8) | |
823 | __vgpu_read(16) | |
824 | __vgpu_read(32) | |
825 | __vgpu_read(64) | |
826 | ||
827 | #undef __vgpu_read | |
828 | #undef VGPU_READ_FOOTER | |
829 | #undef VGPU_READ_HEADER | |
830 | ||
51f67885 | 831 | #define GEN2_WRITE_HEADER \ |
5d738795 | 832 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
6f0ea9e2 | 833 | assert_device_not_suspended(dev_priv); \ |
907b28c5 | 834 | |
51f67885 | 835 | #define GEN2_WRITE_FOOTER |
0d965301 | 836 | |
51f67885 | 837 | #define __gen2_write(x) \ |
0b274481 | 838 | static void \ |
51f67885 CW |
839 | gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
840 | GEN2_WRITE_HEADER; \ | |
4032ef43 | 841 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 842 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
843 | } |
844 | ||
845 | #define __gen5_write(x) \ | |
846 | static void \ | |
847 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
51f67885 | 848 | GEN2_WRITE_HEADER; \ |
4032ef43 BW |
849 | ilk_dummy_write(dev_priv); \ |
850 | __raw_i915_write##x(dev_priv, reg, val); \ | |
51f67885 | 851 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
852 | } |
853 | ||
51f67885 CW |
854 | __gen5_write(8) |
855 | __gen5_write(16) | |
856 | __gen5_write(32) | |
857 | __gen5_write(64) | |
858 | __gen2_write(8) | |
859 | __gen2_write(16) | |
860 | __gen2_write(32) | |
861 | __gen2_write(64) | |
862 | ||
863 | #undef __gen5_write | |
864 | #undef __gen2_write | |
865 | ||
866 | #undef GEN2_WRITE_FOOTER | |
867 | #undef GEN2_WRITE_HEADER | |
868 | ||
869 | #define GEN6_WRITE_HEADER \ | |
0670c5a6 | 870 | u32 offset = reg; \ |
51f67885 CW |
871 | unsigned long irqflags; \ |
872 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
873 | assert_device_not_suspended(dev_priv); \ | |
874 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
875 | ||
876 | #define GEN6_WRITE_FOOTER \ | |
877 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
878 | ||
4032ef43 BW |
879 | #define __gen6_write(x) \ |
880 | static void \ | |
881 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
882 | u32 __fifo_ret = 0; \ | |
51f67885 | 883 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 884 | if (NEEDS_FORCE_WAKE(offset)) { \ |
4032ef43 BW |
885 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
886 | } \ | |
887 | __raw_i915_write##x(dev_priv, reg, val); \ | |
888 | if (unlikely(__fifo_ret)) { \ | |
889 | gen6_gt_check_fifodbg(dev_priv); \ | |
890 | } \ | |
51f67885 | 891 | GEN6_WRITE_FOOTER; \ |
4032ef43 BW |
892 | } |
893 | ||
894 | #define __hsw_write(x) \ | |
895 | static void \ | |
896 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
907b28c5 | 897 | u32 __fifo_ret = 0; \ |
51f67885 | 898 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 899 | if (NEEDS_FORCE_WAKE(offset)) { \ |
907b28c5 CW |
900 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
901 | } \ | |
5978118c | 902 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
6af5d92f | 903 | __raw_i915_write##x(dev_priv, reg, val); \ |
907b28c5 CW |
904 | if (unlikely(__fifo_ret)) { \ |
905 | gen6_gt_check_fifodbg(dev_priv); \ | |
906 | } \ | |
5978118c PZ |
907 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
908 | hsw_unclaimed_reg_detect(dev_priv); \ | |
51f67885 | 909 | GEN6_WRITE_FOOTER; \ |
907b28c5 | 910 | } |
3967018e | 911 | |
ab2aa47e BW |
912 | static const u32 gen8_shadowed_regs[] = { |
913 | FORCEWAKE_MT, | |
914 | GEN6_RPNSWREQ, | |
915 | GEN6_RC_VIDEO_FREQ, | |
916 | RING_TAIL(RENDER_RING_BASE), | |
917 | RING_TAIL(GEN6_BSD_RING_BASE), | |
918 | RING_TAIL(VEBOX_RING_BASE), | |
919 | RING_TAIL(BLT_RING_BASE), | |
920 | /* TODO: Other registers are not yet used */ | |
921 | }; | |
922 | ||
923 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) | |
924 | { | |
925 | int i; | |
926 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) | |
927 | if (reg == gen8_shadowed_regs[i]) | |
928 | return true; | |
929 | ||
930 | return false; | |
931 | } | |
932 | ||
933 | #define __gen8_write(x) \ | |
934 | static void \ | |
935 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
51f67885 | 936 | GEN6_WRITE_HEADER; \ |
66bc2cab | 937 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
0670c5a6 | 938 | if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \ |
b2cff0db CW |
939 | __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ |
940 | __raw_i915_write##x(dev_priv, reg, val); \ | |
66bc2cab PZ |
941 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
942 | hsw_unclaimed_reg_detect(dev_priv); \ | |
51f67885 | 943 | GEN6_WRITE_FOOTER; \ |
ab2aa47e BW |
944 | } |
945 | ||
1938e59a D |
946 | #define __chv_write(x) \ |
947 | static void \ | |
948 | chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
6a42d0f4 | 949 | enum forcewake_domains fw_engine = 0; \ |
51f67885 | 950 | GEN6_WRITE_HEADER; \ |
0670c5a6 | 951 | if (!NEEDS_FORCE_WAKE(offset) || \ |
e97d8fbe | 952 | is_gen8_shadowed(dev_priv, reg)) \ |
6a42d0f4 | 953 | fw_engine = 0; \ |
0670c5a6 | 954 | else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 955 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 956 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \ |
6a42d0f4 | 957 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 958 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \ |
6a42d0f4 VS |
959 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
960 | if (fw_engine) \ | |
961 | __force_wake_get(dev_priv, fw_engine); \ | |
1938e59a | 962 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 963 | GEN6_WRITE_FOOTER; \ |
1938e59a D |
964 | } |
965 | ||
7c859007 ZW |
966 | static const u32 gen9_shadowed_regs[] = { |
967 | RING_TAIL(RENDER_RING_BASE), | |
968 | RING_TAIL(GEN6_BSD_RING_BASE), | |
969 | RING_TAIL(VEBOX_RING_BASE), | |
970 | RING_TAIL(BLT_RING_BASE), | |
971 | FORCEWAKE_BLITTER_GEN9, | |
972 | FORCEWAKE_RENDER_GEN9, | |
973 | FORCEWAKE_MEDIA_GEN9, | |
974 | GEN6_RPNSWREQ, | |
975 | GEN6_RC_VIDEO_FREQ, | |
976 | /* TODO: Other registers are not yet used */ | |
977 | }; | |
978 | ||
979 | static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg) | |
980 | { | |
981 | int i; | |
982 | for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) | |
983 | if (reg == gen9_shadowed_regs[i]) | |
984 | return true; | |
985 | ||
986 | return false; | |
987 | } | |
988 | ||
4597a88a ZW |
989 | #define __gen9_write(x) \ |
990 | static void \ | |
991 | gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \ | |
992 | bool trace) { \ | |
48c1026a | 993 | enum forcewake_domains fw_engine; \ |
51f67885 | 994 | GEN6_WRITE_HEADER; \ |
6c908bf4 | 995 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
0670c5a6 | 996 | if (!SKL_NEEDS_FORCE_WAKE(offset) || \ |
b2cff0db CW |
997 | is_gen9_shadowed(dev_priv, reg)) \ |
998 | fw_engine = 0; \ | |
0670c5a6 | 999 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \ |
b2cff0db | 1000 | fw_engine = FORCEWAKE_RENDER; \ |
0670c5a6 | 1001 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \ |
b2cff0db | 1002 | fw_engine = FORCEWAKE_MEDIA; \ |
0670c5a6 | 1003 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \ |
b2cff0db CW |
1004 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ |
1005 | else \ | |
1006 | fw_engine = FORCEWAKE_BLITTER; \ | |
1007 | if (fw_engine) \ | |
1008 | __force_wake_get(dev_priv, fw_engine); \ | |
1009 | __raw_i915_write##x(dev_priv, reg, val); \ | |
6c908bf4 PZ |
1010 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
1011 | hsw_unclaimed_reg_detect(dev_priv); \ | |
51f67885 | 1012 | GEN6_WRITE_FOOTER; \ |
4597a88a ZW |
1013 | } |
1014 | ||
1015 | __gen9_write(8) | |
1016 | __gen9_write(16) | |
1017 | __gen9_write(32) | |
1018 | __gen9_write(64) | |
1938e59a D |
1019 | __chv_write(8) |
1020 | __chv_write(16) | |
1021 | __chv_write(32) | |
1022 | __chv_write(64) | |
ab2aa47e BW |
1023 | __gen8_write(8) |
1024 | __gen8_write(16) | |
1025 | __gen8_write(32) | |
1026 | __gen8_write(64) | |
4032ef43 BW |
1027 | __hsw_write(8) |
1028 | __hsw_write(16) | |
1029 | __hsw_write(32) | |
1030 | __hsw_write(64) | |
1031 | __gen6_write(8) | |
1032 | __gen6_write(16) | |
1033 | __gen6_write(32) | |
1034 | __gen6_write(64) | |
4032ef43 | 1035 | |
4597a88a | 1036 | #undef __gen9_write |
1938e59a | 1037 | #undef __chv_write |
ab2aa47e | 1038 | #undef __gen8_write |
4032ef43 BW |
1039 | #undef __hsw_write |
1040 | #undef __gen6_write | |
51f67885 CW |
1041 | #undef GEN6_WRITE_FOOTER |
1042 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1043 | |
8a74db7a VS |
1044 | #define VGPU_WRITE_HEADER \ |
1045 | unsigned long irqflags; \ | |
1046 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
1047 | assert_device_not_suspended(dev_priv); \ | |
1048 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
1049 | ||
1050 | #define VGPU_WRITE_FOOTER \ | |
1051 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
1052 | ||
1053 | #define __vgpu_write(x) \ | |
1054 | static void vgpu_write##x(struct drm_i915_private *dev_priv, \ | |
1055 | off_t reg, u##x val, bool trace) { \ | |
1056 | VGPU_WRITE_HEADER; \ | |
1057 | __raw_i915_write##x(dev_priv, reg, val); \ | |
1058 | VGPU_WRITE_FOOTER; \ | |
1059 | } | |
1060 | ||
1061 | __vgpu_write(8) | |
1062 | __vgpu_write(16) | |
1063 | __vgpu_write(32) | |
1064 | __vgpu_write(64) | |
1065 | ||
1066 | #undef __vgpu_write | |
1067 | #undef VGPU_WRITE_FOOTER | |
1068 | #undef VGPU_WRITE_HEADER | |
1069 | ||
43d942a7 YZ |
1070 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
1071 | do { \ | |
1072 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ | |
1073 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ | |
1074 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ | |
1075 | dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ | |
1076 | } while (0) | |
1077 | ||
1078 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ | |
1079 | do { \ | |
1080 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ | |
1081 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ | |
1082 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ | |
1083 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ | |
1084 | } while (0) | |
1085 | ||
05a2fb15 MK |
1086 | |
1087 | static void fw_domain_init(struct drm_i915_private *dev_priv, | |
48c1026a MK |
1088 | enum forcewake_domain_id domain_id, |
1089 | u32 reg_set, u32 reg_ack) | |
05a2fb15 MK |
1090 | { |
1091 | struct intel_uncore_forcewake_domain *d; | |
1092 | ||
1093 | if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)) | |
1094 | return; | |
1095 | ||
1096 | d = &dev_priv->uncore.fw_domain[domain_id]; | |
1097 | ||
1098 | WARN_ON(d->wake_count); | |
1099 | ||
1100 | d->wake_count = 0; | |
1101 | d->reg_set = reg_set; | |
1102 | d->reg_ack = reg_ack; | |
1103 | ||
1104 | if (IS_GEN6(dev_priv)) { | |
1105 | d->val_reset = 0; | |
1106 | d->val_set = FORCEWAKE_KERNEL; | |
1107 | d->val_clear = 0; | |
1108 | } else { | |
8543747c | 1109 | /* WaRsClearFWBitsAtReset:bdw,skl */ |
05a2fb15 MK |
1110 | d->val_reset = _MASKED_BIT_DISABLE(0xffff); |
1111 | d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); | |
1112 | d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); | |
1113 | } | |
1114 | ||
1115 | if (IS_VALLEYVIEW(dev_priv)) | |
1116 | d->reg_post = FORCEWAKE_ACK_VLV; | |
1117 | else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) | |
1118 | d->reg_post = ECOBUS; | |
1119 | else | |
1120 | d->reg_post = 0; | |
1121 | ||
1122 | d->i915 = dev_priv; | |
1123 | d->id = domain_id; | |
1124 | ||
59bad947 | 1125 | setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d); |
05a2fb15 MK |
1126 | |
1127 | dev_priv->uncore.fw_domains |= (1 << domain_id); | |
f9b3927a MK |
1128 | |
1129 | fw_domain_reset(d); | |
05a2fb15 MK |
1130 | } |
1131 | ||
f9b3927a | 1132 | static void intel_uncore_fw_domains_init(struct drm_device *dev) |
0b274481 BW |
1133 | { |
1134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b274481 | 1135 | |
3225b2f9 MK |
1136 | if (INTEL_INFO(dev_priv->dev)->gen <= 5) |
1137 | return; | |
1138 | ||
38cff0b1 | 1139 | if (IS_GEN9(dev)) { |
05a2fb15 MK |
1140 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
1141 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
1142 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1143 | FORCEWAKE_RENDER_GEN9, | |
1144 | FORCEWAKE_ACK_RENDER_GEN9); | |
1145 | fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER, | |
1146 | FORCEWAKE_BLITTER_GEN9, | |
1147 | FORCEWAKE_ACK_BLITTER_GEN9); | |
1148 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1149 | FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); | |
38cff0b1 | 1150 | } else if (IS_VALLEYVIEW(dev)) { |
05a2fb15 | 1151 | dev_priv->uncore.funcs.force_wake_get = fw_domains_get; |
756c349d MK |
1152 | if (!IS_CHERRYVIEW(dev)) |
1153 | dev_priv->uncore.funcs.force_wake_put = | |
1154 | fw_domains_put_with_fifo; | |
1155 | else | |
1156 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
05a2fb15 MK |
1157 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1158 | FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); | |
1159 | fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA, | |
1160 | FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); | |
f98cd096 | 1161 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
05a2fb15 MK |
1162 | dev_priv->uncore.funcs.force_wake_get = |
1163 | fw_domains_get_with_thread_status; | |
1164 | dev_priv->uncore.funcs.force_wake_put = fw_domains_put; | |
1165 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1166 | FORCEWAKE_MT, FORCEWAKE_ACK_HSW); | |
0b274481 BW |
1167 | } else if (IS_IVYBRIDGE(dev)) { |
1168 | u32 ecobus; | |
1169 | ||
1170 | /* IVB configs may use multi-threaded forcewake */ | |
1171 | ||
1172 | /* A small trick here - if the bios hasn't configured | |
1173 | * MT forcewake, and if the device is in RC6, then | |
1174 | * force_wake_mt_get will not wake the device and the | |
1175 | * ECOBUS read will return zero. Which will be | |
1176 | * (correctly) interpreted by the test below as MT | |
1177 | * forcewake being disabled. | |
1178 | */ | |
05a2fb15 MK |
1179 | dev_priv->uncore.funcs.force_wake_get = |
1180 | fw_domains_get_with_thread_status; | |
1181 | dev_priv->uncore.funcs.force_wake_put = | |
1182 | fw_domains_put_with_fifo; | |
1183 | ||
f9b3927a MK |
1184 | /* We need to init first for ECOBUS access and then |
1185 | * determine later if we want to reinit, in case of MT access is | |
6ea2556f MK |
1186 | * not working. In this stage we don't know which flavour this |
1187 | * ivb is, so it is better to reset also the gen6 fw registers | |
1188 | * before the ecobus check. | |
f9b3927a | 1189 | */ |
6ea2556f MK |
1190 | |
1191 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); | |
1192 | __raw_posting_read(dev_priv, ECOBUS); | |
1193 | ||
05a2fb15 MK |
1194 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1195 | FORCEWAKE_MT, FORCEWAKE_MT_ACK); | |
f9b3927a | 1196 | |
0b274481 | 1197 | mutex_lock(&dev->struct_mutex); |
05a2fb15 | 1198 | fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL); |
0b274481 | 1199 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
05a2fb15 | 1200 | fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL); |
0b274481 BW |
1201 | mutex_unlock(&dev->struct_mutex); |
1202 | ||
05a2fb15 | 1203 | if (!(ecobus & FORCEWAKE_MT_ENABLE)) { |
0b274481 BW |
1204 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
1205 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
05a2fb15 MK |
1206 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, |
1207 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 BW |
1208 | } |
1209 | } else if (IS_GEN6(dev)) { | |
1210 | dev_priv->uncore.funcs.force_wake_get = | |
05a2fb15 | 1211 | fw_domains_get_with_thread_status; |
0b274481 | 1212 | dev_priv->uncore.funcs.force_wake_put = |
05a2fb15 MK |
1213 | fw_domains_put_with_fifo; |
1214 | fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, | |
1215 | FORCEWAKE, FORCEWAKE_ACK); | |
0b274481 | 1216 | } |
3225b2f9 MK |
1217 | |
1218 | /* All future platforms are expected to require complex power gating */ | |
1219 | WARN_ON(dev_priv->uncore.fw_domains == 0); | |
f9b3927a MK |
1220 | } |
1221 | ||
1222 | void intel_uncore_init(struct drm_device *dev) | |
1223 | { | |
1224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1225 | ||
cf9d2890 YZ |
1226 | i915_check_vgpu(dev); |
1227 | ||
f9b3927a MK |
1228 | intel_uncore_ellc_detect(dev); |
1229 | intel_uncore_fw_domains_init(dev); | |
1230 | __intel_uncore_early_sanitize(dev, false); | |
0b274481 | 1231 | |
3967018e | 1232 | switch (INTEL_INFO(dev)->gen) { |
ab2aa47e | 1233 | default: |
4597a88a ZW |
1234 | case 9: |
1235 | ASSIGN_WRITE_MMIO_VFUNCS(gen9); | |
1236 | ASSIGN_READ_MMIO_VFUNCS(gen9); | |
1237 | break; | |
1238 | case 8: | |
1938e59a | 1239 | if (IS_CHERRYVIEW(dev)) { |
43d942a7 YZ |
1240 | ASSIGN_WRITE_MMIO_VFUNCS(chv); |
1241 | ASSIGN_READ_MMIO_VFUNCS(chv); | |
1938e59a D |
1242 | |
1243 | } else { | |
43d942a7 YZ |
1244 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
1245 | ASSIGN_READ_MMIO_VFUNCS(gen6); | |
1938e59a | 1246 | } |
ab2aa47e | 1247 | break; |
3967018e BW |
1248 | case 7: |
1249 | case 6: | |
4032ef43 | 1250 | if (IS_HASWELL(dev)) { |
43d942a7 | 1251 | ASSIGN_WRITE_MMIO_VFUNCS(hsw); |
4032ef43 | 1252 | } else { |
43d942a7 | 1253 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
4032ef43 | 1254 | } |
940aece4 D |
1255 | |
1256 | if (IS_VALLEYVIEW(dev)) { | |
43d942a7 | 1257 | ASSIGN_READ_MMIO_VFUNCS(vlv); |
940aece4 | 1258 | } else { |
43d942a7 | 1259 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
940aece4 | 1260 | } |
3967018e BW |
1261 | break; |
1262 | case 5: | |
43d942a7 YZ |
1263 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
1264 | ASSIGN_READ_MMIO_VFUNCS(gen5); | |
3967018e BW |
1265 | break; |
1266 | case 4: | |
1267 | case 3: | |
1268 | case 2: | |
51f67885 CW |
1269 | ASSIGN_WRITE_MMIO_VFUNCS(gen2); |
1270 | ASSIGN_READ_MMIO_VFUNCS(gen2); | |
3967018e BW |
1271 | break; |
1272 | } | |
ed493883 | 1273 | |
3be0bf5a YZ |
1274 | if (intel_vgpu_active(dev)) { |
1275 | ASSIGN_WRITE_MMIO_VFUNCS(vgpu); | |
1276 | ASSIGN_READ_MMIO_VFUNCS(vgpu); | |
1277 | } | |
1278 | ||
ed493883 | 1279 | i915_check_and_clear_faults(dev); |
0b274481 | 1280 | } |
43d942a7 YZ |
1281 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
1282 | #undef ASSIGN_READ_MMIO_VFUNCS | |
0b274481 BW |
1283 | |
1284 | void intel_uncore_fini(struct drm_device *dev) | |
1285 | { | |
0b274481 BW |
1286 | /* Paranoia: make sure we have disabled everything before we exit. */ |
1287 | intel_uncore_sanitize(dev); | |
0294ae7b | 1288 | intel_uncore_forcewake_reset(dev, false); |
0b274481 BW |
1289 | } |
1290 | ||
af76ae44 DL |
1291 | #define GEN_RANGE(l, h) GENMASK(h, l) |
1292 | ||
907b28c5 | 1293 | static const struct register_whitelist { |
8697600b | 1294 | uint32_t offset_ldw, offset_udw; |
907b28c5 | 1295 | uint32_t size; |
af76ae44 DL |
1296 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
1297 | uint32_t gen_bitmask; | |
907b28c5 | 1298 | } whitelist[] = { |
8697600b VS |
1299 | { .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), |
1300 | .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), | |
1301 | .size = 8, .gen_bitmask = GEN_RANGE(4, 9) }, | |
907b28c5 CW |
1302 | }; |
1303 | ||
1304 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1305 | void *data, struct drm_file *file) | |
1306 | { | |
1307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1308 | struct drm_i915_reg_read *reg = data; | |
1309 | struct register_whitelist const *entry = whitelist; | |
648a9bc5 | 1310 | unsigned size; |
8697600b | 1311 | uint32_t offset_ldw, offset_udw; |
cf67c70f | 1312 | int i, ret = 0; |
907b28c5 CW |
1313 | |
1314 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
8697600b | 1315 | if (entry->offset_ldw == (reg->offset & -entry->size) && |
907b28c5 CW |
1316 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
1317 | break; | |
1318 | } | |
1319 | ||
1320 | if (i == ARRAY_SIZE(whitelist)) | |
1321 | return -EINVAL; | |
1322 | ||
648a9bc5 CW |
1323 | /* We use the low bits to encode extra flags as the register should |
1324 | * be naturally aligned (and those that are not so aligned merely | |
1325 | * limit the available flags for that register). | |
1326 | */ | |
8697600b VS |
1327 | offset_ldw = entry->offset_ldw; |
1328 | offset_udw = entry->offset_udw; | |
648a9bc5 | 1329 | size = entry->size; |
8697600b | 1330 | size |= reg->offset ^ offset_ldw; |
648a9bc5 | 1331 | |
cf67c70f PZ |
1332 | intel_runtime_pm_get(dev_priv); |
1333 | ||
648a9bc5 CW |
1334 | switch (size) { |
1335 | case 8 | 1: | |
8697600b | 1336 | reg->val = I915_READ64_2x32(offset_ldw, offset_udw); |
648a9bc5 | 1337 | break; |
907b28c5 | 1338 | case 8: |
8697600b | 1339 | reg->val = I915_READ64(offset_ldw); |
907b28c5 CW |
1340 | break; |
1341 | case 4: | |
8697600b | 1342 | reg->val = I915_READ(offset_ldw); |
907b28c5 CW |
1343 | break; |
1344 | case 2: | |
8697600b | 1345 | reg->val = I915_READ16(offset_ldw); |
907b28c5 CW |
1346 | break; |
1347 | case 1: | |
8697600b | 1348 | reg->val = I915_READ8(offset_ldw); |
907b28c5 CW |
1349 | break; |
1350 | default: | |
cf67c70f PZ |
1351 | ret = -EINVAL; |
1352 | goto out; | |
907b28c5 CW |
1353 | } |
1354 | ||
cf67c70f PZ |
1355 | out: |
1356 | intel_runtime_pm_put(dev_priv); | |
1357 | return ret; | |
907b28c5 CW |
1358 | } |
1359 | ||
b6359918 MK |
1360 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
1361 | void *data, struct drm_file *file) | |
1362 | { | |
1363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1364 | struct drm_i915_reset_stats *args = data; | |
1365 | struct i915_ctx_hang_stats *hs; | |
273497e5 | 1366 | struct intel_context *ctx; |
b6359918 MK |
1367 | int ret; |
1368 | ||
661df041 MK |
1369 | if (args->flags || args->pad) |
1370 | return -EINVAL; | |
1371 | ||
821d66dd | 1372 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) |
b6359918 MK |
1373 | return -EPERM; |
1374 | ||
1375 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1376 | if (ret) | |
1377 | return ret; | |
1378 | ||
41bde553 BW |
1379 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
1380 | if (IS_ERR(ctx)) { | |
b6359918 | 1381 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1382 | return PTR_ERR(ctx); |
b6359918 | 1383 | } |
41bde553 | 1384 | hs = &ctx->hang_stats; |
b6359918 MK |
1385 | |
1386 | if (capable(CAP_SYS_ADMIN)) | |
1387 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1388 | else | |
1389 | args->reset_count = 0; | |
1390 | ||
1391 | args->batch_active = hs->batch_active; | |
1392 | args->batch_pending = hs->batch_pending; | |
1393 | ||
1394 | mutex_unlock(&dev->struct_mutex); | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
59ea9054 | 1399 | static int i915_reset_complete(struct drm_device *dev) |
907b28c5 CW |
1400 | { |
1401 | u8 gdrst; | |
59ea9054 | 1402 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1403 | return (gdrst & GRDOM_RESET_STATUS) == 0; |
907b28c5 CW |
1404 | } |
1405 | ||
59ea9054 | 1406 | static int i915_do_reset(struct drm_device *dev) |
907b28c5 | 1407 | { |
73bbf6bd | 1408 | /* assert reset for at least 20 usec */ |
59ea9054 | 1409 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
73bbf6bd | 1410 | udelay(20); |
59ea9054 | 1411 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
907b28c5 | 1412 | |
59ea9054 | 1413 | return wait_for(i915_reset_complete(dev), 500); |
73bbf6bd VS |
1414 | } |
1415 | ||
1416 | static int g4x_reset_complete(struct drm_device *dev) | |
1417 | { | |
1418 | u8 gdrst; | |
59ea9054 | 1419 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1420 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
907b28c5 CW |
1421 | } |
1422 | ||
408d4b9e VS |
1423 | static int g33_do_reset(struct drm_device *dev) |
1424 | { | |
408d4b9e VS |
1425 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
1426 | return wait_for(g4x_reset_complete(dev), 500); | |
1427 | } | |
1428 | ||
fa4f53c4 VS |
1429 | static int g4x_do_reset(struct drm_device *dev) |
1430 | { | |
1431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1432 | int ret; | |
1433 | ||
59ea9054 | 1434 | pci_write_config_byte(dev->pdev, I915_GDRST, |
fa4f53c4 | 1435 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
73bbf6bd | 1436 | ret = wait_for(g4x_reset_complete(dev), 500); |
fa4f53c4 VS |
1437 | if (ret) |
1438 | return ret; | |
1439 | ||
1440 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1441 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); | |
1442 | POSTING_READ(VDECCLK_GATE_D); | |
1443 | ||
59ea9054 | 1444 | pci_write_config_byte(dev->pdev, I915_GDRST, |
fa4f53c4 | 1445 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
73bbf6bd | 1446 | ret = wait_for(g4x_reset_complete(dev), 500); |
fa4f53c4 VS |
1447 | if (ret) |
1448 | return ret; | |
1449 | ||
1450 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1451 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); | |
1452 | POSTING_READ(VDECCLK_GATE_D); | |
1453 | ||
59ea9054 | 1454 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
fa4f53c4 VS |
1455 | |
1456 | return 0; | |
1457 | } | |
1458 | ||
907b28c5 CW |
1459 | static int ironlake_do_reset(struct drm_device *dev) |
1460 | { | |
1461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
907b28c5 CW |
1462 | int ret; |
1463 | ||
c039b7f2 | 1464 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1465 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
c039b7f2 | 1466 | ret = wait_for((I915_READ(ILK_GDSR) & |
b3a3f03d | 1467 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
907b28c5 CW |
1468 | if (ret) |
1469 | return ret; | |
1470 | ||
c039b7f2 | 1471 | I915_WRITE(ILK_GDSR, |
0f08ffd6 | 1472 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
c039b7f2 | 1473 | ret = wait_for((I915_READ(ILK_GDSR) & |
9aa7250f VS |
1474 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
1475 | if (ret) | |
1476 | return ret; | |
1477 | ||
c039b7f2 | 1478 | I915_WRITE(ILK_GDSR, 0); |
9aa7250f VS |
1479 | |
1480 | return 0; | |
907b28c5 CW |
1481 | } |
1482 | ||
1483 | static int gen6_do_reset(struct drm_device *dev) | |
1484 | { | |
1485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1486 | int ret; | |
907b28c5 CW |
1487 | |
1488 | /* Reset the chip */ | |
1489 | ||
1490 | /* GEN6_GDRST is not in the gt power well, no need to check | |
1491 | * for fifo space for the write or forcewake the chip for | |
1492 | * the read | |
1493 | */ | |
6af5d92f | 1494 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
907b28c5 CW |
1495 | |
1496 | /* Spin waiting for the device to ack the reset request */ | |
6af5d92f | 1497 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
907b28c5 | 1498 | |
0294ae7b | 1499 | intel_uncore_forcewake_reset(dev, true); |
5babf0fc | 1500 | |
907b28c5 CW |
1501 | return ret; |
1502 | } | |
1503 | ||
7fd2d269 MK |
1504 | static int wait_for_register(struct drm_i915_private *dev_priv, |
1505 | const u32 reg, | |
1506 | const u32 mask, | |
1507 | const u32 value, | |
1508 | const unsigned long timeout_ms) | |
1509 | { | |
1510 | return wait_for((I915_READ(reg) & mask) == value, timeout_ms); | |
1511 | } | |
1512 | ||
1513 | static int gen8_do_reset(struct drm_device *dev) | |
1514 | { | |
1515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1516 | struct intel_engine_cs *engine; | |
1517 | int i; | |
1518 | ||
1519 | for_each_ring(engine, dev_priv, i) { | |
1520 | I915_WRITE(RING_RESET_CTL(engine->mmio_base), | |
1521 | _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)); | |
1522 | ||
1523 | if (wait_for_register(dev_priv, | |
1524 | RING_RESET_CTL(engine->mmio_base), | |
1525 | RESET_CTL_READY_TO_RESET, | |
1526 | RESET_CTL_READY_TO_RESET, | |
1527 | 700)) { | |
1528 | DRM_ERROR("%s: reset request timeout\n", engine->name); | |
1529 | goto not_ready; | |
1530 | } | |
1531 | } | |
1532 | ||
1533 | return gen6_do_reset(dev); | |
1534 | ||
1535 | not_ready: | |
1536 | for_each_ring(engine, dev_priv, i) | |
1537 | I915_WRITE(RING_RESET_CTL(engine->mmio_base), | |
1538 | _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); | |
1539 | ||
1540 | return -EIO; | |
1541 | } | |
1542 | ||
49e4d842 | 1543 | static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *) |
907b28c5 | 1544 | { |
b1330fbb CW |
1545 | if (!i915.reset) |
1546 | return NULL; | |
1547 | ||
7fd2d269 MK |
1548 | if (INTEL_INFO(dev)->gen >= 8) |
1549 | return gen8_do_reset; | |
1550 | else if (INTEL_INFO(dev)->gen >= 6) | |
49e4d842 | 1551 | return gen6_do_reset; |
542c184f | 1552 | else if (IS_GEN5(dev)) |
49e4d842 | 1553 | return ironlake_do_reset; |
542c184f | 1554 | else if (IS_G4X(dev)) |
49e4d842 | 1555 | return g4x_do_reset; |
408d4b9e | 1556 | else if (IS_G33(dev)) |
49e4d842 | 1557 | return g33_do_reset; |
408d4b9e | 1558 | else if (INTEL_INFO(dev)->gen >= 3) |
49e4d842 | 1559 | return i915_do_reset; |
542c184f | 1560 | else |
49e4d842 CW |
1561 | return NULL; |
1562 | } | |
1563 | ||
1564 | int intel_gpu_reset(struct drm_device *dev) | |
1565 | { | |
1566 | int (*reset)(struct drm_device *); | |
1567 | ||
1568 | reset = intel_get_gpu_reset(dev); | |
1569 | if (reset == NULL) | |
542c184f | 1570 | return -ENODEV; |
49e4d842 CW |
1571 | |
1572 | return reset(dev); | |
1573 | } | |
1574 | ||
1575 | bool intel_has_gpu_reset(struct drm_device *dev) | |
1576 | { | |
1577 | return intel_get_gpu_reset(dev) != NULL; | |
907b28c5 CW |
1578 | } |
1579 | ||
907b28c5 CW |
1580 | void intel_uncore_check_errors(struct drm_device *dev) |
1581 | { | |
1582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1583 | ||
1584 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && | |
6af5d92f | 1585 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
907b28c5 | 1586 | DRM_ERROR("Unclaimed register before interrupt\n"); |
6af5d92f | 1587 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
1588 | } |
1589 | } |