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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
26 | ||
27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 | |
28 | ||
6af5d92f CW |
29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) | |
31 | ||
32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) | |
33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) | |
34 | ||
35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) | |
37 | ||
38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) | |
39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) | |
40 | ||
41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) | |
42 | ||
43 | ||
907b28c5 CW |
44 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
45 | { | |
46 | u32 gt_thread_status_mask; | |
47 | ||
48 | if (IS_HASWELL(dev_priv->dev)) | |
49 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; | |
50 | else | |
51 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; | |
52 | ||
53 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
54 | * thread to wake up. | |
55 | */ | |
6af5d92f | 56 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
907b28c5 CW |
57 | DRM_ERROR("GT thread status wait timed out\n"); |
58 | } | |
59 | ||
60 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) | |
61 | { | |
6af5d92f CW |
62 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
63 | /* something from same cacheline, but !FORCEWAKE */ | |
64 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 CW |
65 | } |
66 | ||
c8d9a590 D |
67 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
68 | int fw_engine) | |
907b28c5 | 69 | { |
6af5d92f | 70 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
907b28c5 CW |
71 | FORCEWAKE_ACK_TIMEOUT_MS)) |
72 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
73 | ||
6af5d92f CW |
74 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
75 | /* something from same cacheline, but !FORCEWAKE */ | |
76 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 | 77 | |
6af5d92f | 78 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
907b28c5 CW |
79 | FORCEWAKE_ACK_TIMEOUT_MS)) |
80 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
81 | ||
82 | /* WaRsForcewakeWaitTC0:snb */ | |
83 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
84 | } | |
85 | ||
86 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) | |
87 | { | |
6af5d92f | 88 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
907b28c5 | 89 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 90 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
91 | } |
92 | ||
c8d9a590 D |
93 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
94 | int fw_engine) | |
907b28c5 CW |
95 | { |
96 | u32 forcewake_ack; | |
97 | ||
ab2aa47e | 98 | if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) |
907b28c5 CW |
99 | forcewake_ack = FORCEWAKE_ACK_HSW; |
100 | else | |
101 | forcewake_ack = FORCEWAKE_MT_ACK; | |
102 | ||
6af5d92f | 103 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
907b28c5 CW |
104 | FORCEWAKE_ACK_TIMEOUT_MS)) |
105 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
106 | ||
6af5d92f CW |
107 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
108 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 109 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 110 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 | 111 | |
6af5d92f | 112 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
907b28c5 CW |
113 | FORCEWAKE_ACK_TIMEOUT_MS)) |
114 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
115 | ||
116 | /* WaRsForcewakeWaitTC0:ivb,hsw */ | |
0f161f70 BW |
117 | if (INTEL_INFO(dev_priv->dev)->gen < 8) |
118 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
907b28c5 CW |
119 | } |
120 | ||
121 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
122 | { | |
123 | u32 gtfifodbg; | |
6af5d92f CW |
124 | |
125 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
907b28c5 CW |
126 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, |
127 | "MMIO read or write has been dropped %x\n", gtfifodbg)) | |
6af5d92f | 128 | __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); |
907b28c5 CW |
129 | } |
130 | ||
c8d9a590 D |
131 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
132 | int fw_engine) | |
907b28c5 | 133 | { |
6af5d92f | 134 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
907b28c5 | 135 | /* something from same cacheline, but !FORCEWAKE */ |
6af5d92f | 136 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
137 | gen6_gt_check_fifodbg(dev_priv); |
138 | } | |
139 | ||
c8d9a590 D |
140 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, |
141 | int fw_engine) | |
907b28c5 | 142 | { |
6af5d92f CW |
143 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
144 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 145 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 146 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
147 | gen6_gt_check_fifodbg(dev_priv); |
148 | } | |
149 | ||
150 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) | |
151 | { | |
152 | int ret = 0; | |
153 | ||
154 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { | |
155 | int loop = 500; | |
6af5d92f | 156 | u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
907b28c5 CW |
157 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
158 | udelay(10); | |
6af5d92f | 159 | fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
907b28c5 CW |
160 | } |
161 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
162 | ++ret; | |
163 | dev_priv->uncore.fifo_count = fifo; | |
164 | } | |
165 | dev_priv->uncore.fifo_count--; | |
166 | ||
167 | return ret; | |
168 | } | |
169 | ||
170 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) | |
171 | { | |
6af5d92f CW |
172 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
173 | _MASKED_BIT_DISABLE(0xffff)); | |
907b28c5 | 174 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
6af5d92f | 175 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
907b28c5 CW |
176 | } |
177 | ||
940aece4 D |
178 | static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, |
179 | int fw_engine) | |
907b28c5 | 180 | { |
940aece4 D |
181 | /* Check for Render Engine */ |
182 | if (FORCEWAKE_RENDER & fw_engine) { | |
183 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
184 | FORCEWAKE_ACK_VLV) & | |
185 | FORCEWAKE_KERNEL) == 0, | |
186 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
187 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); | |
188 | ||
189 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, | |
190 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
191 | ||
192 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
193 | FORCEWAKE_ACK_VLV) & | |
194 | FORCEWAKE_KERNEL), | |
195 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
196 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); | |
197 | } | |
907b28c5 | 198 | |
940aece4 D |
199 | /* Check for Media Engine */ |
200 | if (FORCEWAKE_MEDIA & fw_engine) { | |
201 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
202 | FORCEWAKE_ACK_MEDIA_VLV) & | |
203 | FORCEWAKE_KERNEL) == 0, | |
204 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
205 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); | |
206 | ||
207 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
208 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
209 | ||
210 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
211 | FORCEWAKE_ACK_MEDIA_VLV) & | |
212 | FORCEWAKE_KERNEL), | |
213 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
214 | DRM_ERROR("Timed out: waiting for media to ack.\n"); | |
215 | } | |
907b28c5 CW |
216 | |
217 | /* WaRsForcewakeWaitTC0:vlv */ | |
218 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
940aece4 | 219 | |
907b28c5 CW |
220 | } |
221 | ||
940aece4 D |
222 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
223 | int fw_engine) | |
907b28c5 | 224 | { |
940aece4 D |
225 | |
226 | /* Check for Render Engine */ | |
227 | if (FORCEWAKE_RENDER & fw_engine) | |
228 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, | |
229 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
230 | ||
231 | ||
232 | /* Check for Media Engine */ | |
233 | if (FORCEWAKE_MEDIA & fw_engine) | |
234 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
235 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
236 | ||
907b28c5 CW |
237 | /* The below doubles as a POSTING_READ */ |
238 | gen6_gt_check_fifodbg(dev_priv); | |
940aece4 D |
239 | |
240 | } | |
241 | ||
242 | void vlv_force_wake_get(struct drm_i915_private *dev_priv, | |
243 | int fw_engine) | |
244 | { | |
245 | unsigned long irqflags; | |
246 | ||
247 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
248 | if (FORCEWAKE_RENDER & fw_engine) { | |
249 | if (dev_priv->uncore.fw_rendercount++ == 0) | |
250 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
251 | FORCEWAKE_RENDER); | |
252 | } | |
253 | if (FORCEWAKE_MEDIA & fw_engine) { | |
254 | if (dev_priv->uncore.fw_mediacount++ == 0) | |
255 | dev_priv->uncore.funcs.force_wake_get(dev_priv, | |
256 | FORCEWAKE_MEDIA); | |
257 | } | |
258 | ||
259 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
260 | } | |
261 | ||
262 | void vlv_force_wake_put(struct drm_i915_private *dev_priv, | |
263 | int fw_engine) | |
264 | { | |
265 | unsigned long irqflags; | |
266 | ||
267 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
268 | ||
269 | if (FORCEWAKE_RENDER & fw_engine) { | |
270 | WARN_ON(dev_priv->uncore.fw_rendercount == 0); | |
271 | if (--dev_priv->uncore.fw_rendercount == 0) | |
272 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
273 | FORCEWAKE_RENDER); | |
274 | } | |
275 | ||
276 | if (FORCEWAKE_MEDIA & fw_engine) { | |
277 | WARN_ON(dev_priv->uncore.fw_mediacount == 0); | |
278 | if (--dev_priv->uncore.fw_mediacount == 0) | |
279 | dev_priv->uncore.funcs.force_wake_put(dev_priv, | |
280 | FORCEWAKE_MEDIA); | |
281 | } | |
282 | ||
283 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
907b28c5 CW |
284 | } |
285 | ||
aec347ab CW |
286 | static void gen6_force_wake_work(struct work_struct *work) |
287 | { | |
288 | struct drm_i915_private *dev_priv = | |
289 | container_of(work, typeof(*dev_priv), uncore.force_wake_work.work); | |
290 | unsigned long irqflags; | |
291 | ||
292 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
293 | if (--dev_priv->uncore.forcewake_count == 0) | |
c8d9a590 | 294 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
aec347ab CW |
295 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
296 | } | |
297 | ||
907b28c5 CW |
298 | void intel_uncore_early_sanitize(struct drm_device *dev) |
299 | { | |
300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
301 | ||
302 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) | |
6af5d92f | 303 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
18ce3994 BW |
304 | |
305 | if (IS_HASWELL(dev) && | |
306 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { | |
307 | /* The docs do not explain exactly how the calculation can be | |
308 | * made. It is somewhat guessable, but for now, it's always | |
309 | * 128MB. | |
310 | * NB: We can't write IDICR yet because we do not have gt funcs | |
311 | * set up */ | |
312 | dev_priv->ellc_size = 128; | |
313 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); | |
314 | } | |
907b28c5 CW |
315 | } |
316 | ||
521198a2 | 317 | static void intel_uncore_forcewake_reset(struct drm_device *dev) |
907b28c5 CW |
318 | { |
319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
320 | ||
321 | if (IS_VALLEYVIEW(dev)) { | |
322 | vlv_force_wake_reset(dev_priv); | |
323 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
324 | __gen6_gt_force_wake_reset(dev_priv); | |
325 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
326 | __gen6_gt_force_wake_mt_reset(dev_priv); | |
327 | } | |
521198a2 MK |
328 | } |
329 | ||
330 | void intel_uncore_sanitize(struct drm_device *dev) | |
331 | { | |
02f4c9e0 CML |
332 | struct drm_i915_private *dev_priv = dev->dev_private; |
333 | u32 reg_val; | |
334 | ||
521198a2 | 335 | intel_uncore_forcewake_reset(dev); |
907b28c5 CW |
336 | |
337 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ | |
338 | intel_disable_gt_powersave(dev); | |
02f4c9e0 CML |
339 | |
340 | /* Turn off power gate, require especially for the BIOS less system */ | |
341 | if (IS_VALLEYVIEW(dev)) { | |
342 | ||
343 | mutex_lock(&dev_priv->rps.hw_lock); | |
344 | reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS); | |
345 | ||
346 | if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT)) | |
347 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0); | |
348 | ||
349 | mutex_unlock(&dev_priv->rps.hw_lock); | |
350 | ||
351 | } | |
907b28c5 CW |
352 | } |
353 | ||
354 | /* | |
355 | * Generally this is called implicitly by the register read function. However, | |
356 | * if some sequence requires the GT to not power down then this function should | |
357 | * be called at the beginning of the sequence followed by a call to | |
358 | * gen6_gt_force_wake_put() at the end of the sequence. | |
359 | */ | |
c8d9a590 | 360 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
907b28c5 CW |
361 | { |
362 | unsigned long irqflags; | |
363 | ||
ab484f8f BW |
364 | if (!dev_priv->uncore.funcs.force_wake_get) |
365 | return; | |
366 | ||
940aece4 D |
367 | /* Redirect to VLV specific routine */ |
368 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
369 | return vlv_force_wake_get(dev_priv, fw_engine); | |
370 | ||
907b28c5 CW |
371 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
372 | if (dev_priv->uncore.forcewake_count++ == 0) | |
c8d9a590 | 373 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
907b28c5 CW |
374 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
375 | } | |
376 | ||
377 | /* | |
378 | * see gen6_gt_force_wake_get() | |
379 | */ | |
c8d9a590 | 380 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
907b28c5 CW |
381 | { |
382 | unsigned long irqflags; | |
383 | ||
ab484f8f BW |
384 | if (!dev_priv->uncore.funcs.force_wake_put) |
385 | return; | |
386 | ||
940aece4 D |
387 | /* Redirect to VLV specific routine */ |
388 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
389 | return vlv_force_wake_put(dev_priv, fw_engine); | |
390 | ||
391 | ||
907b28c5 | 392 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
aec347ab CW |
393 | if (--dev_priv->uncore.forcewake_count == 0) { |
394 | dev_priv->uncore.forcewake_count++; | |
395 | mod_delayed_work(dev_priv->wq, | |
396 | &dev_priv->uncore.force_wake_work, | |
397 | 1); | |
398 | } | |
907b28c5 CW |
399 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
400 | } | |
401 | ||
402 | /* We give fast paths for the really cool registers */ | |
403 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
ab484f8f | 404 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
907b28c5 CW |
405 | |
406 | static void | |
407 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
408 | { | |
409 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
410 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
411 | * hence harmless to write 0 into. */ | |
6af5d92f | 412 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
413 | } |
414 | ||
415 | static void | |
416 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) | |
417 | { | |
ab484f8f | 418 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
907b28c5 CW |
419 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
420 | reg); | |
6af5d92f | 421 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
422 | } |
423 | } | |
424 | ||
425 | static void | |
426 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) | |
427 | { | |
ab484f8f | 428 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
907b28c5 | 429 | DRM_ERROR("Unclaimed write to %x\n", reg); |
6af5d92f | 430 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
431 | } |
432 | } | |
433 | ||
5d738795 BW |
434 | #define REG_READ_HEADER(x) \ |
435 | unsigned long irqflags; \ | |
436 | u##x val = 0; \ | |
437 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
438 | ||
439 | #define REG_READ_FOOTER \ | |
440 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
441 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
442 | return val | |
443 | ||
3967018e | 444 | #define __gen4_read(x) \ |
0b274481 | 445 | static u##x \ |
3967018e BW |
446 | gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
447 | REG_READ_HEADER(x); \ | |
448 | val = __raw_i915_read##x(dev_priv, reg); \ | |
449 | REG_READ_FOOTER; \ | |
450 | } | |
451 | ||
452 | #define __gen5_read(x) \ | |
453 | static u##x \ | |
454 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
455 | REG_READ_HEADER(x); \ | |
456 | ilk_dummy_write(dev_priv); \ | |
457 | val = __raw_i915_read##x(dev_priv, reg); \ | |
458 | REG_READ_FOOTER; \ | |
459 | } | |
460 | ||
461 | #define __gen6_read(x) \ | |
462 | static u##x \ | |
463 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
5d738795 | 464 | REG_READ_HEADER(x); \ |
907b28c5 CW |
465 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
466 | if (dev_priv->uncore.forcewake_count == 0) \ | |
c8d9a590 D |
467 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
468 | FORCEWAKE_ALL); \ | |
6af5d92f | 469 | val = __raw_i915_read##x(dev_priv, reg); \ |
907b28c5 | 470 | if (dev_priv->uncore.forcewake_count == 0) \ |
c8d9a590 D |
471 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
472 | FORCEWAKE_ALL); \ | |
907b28c5 | 473 | } else { \ |
6af5d92f | 474 | val = __raw_i915_read##x(dev_priv, reg); \ |
907b28c5 | 475 | } \ |
5d738795 | 476 | REG_READ_FOOTER; \ |
907b28c5 CW |
477 | } |
478 | ||
940aece4 D |
479 | #define __vlv_read(x) \ |
480 | static u##x \ | |
481 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
482 | unsigned fwengine = 0; \ | |
483 | unsigned *fwcount = 0; \ | |
484 | REG_READ_HEADER(x); \ | |
485 | if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ | |
486 | fwengine = FORCEWAKE_RENDER; \ | |
487 | fwcount = &dev_priv->uncore.fw_rendercount; \ | |
488 | } \ | |
489 | else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \ | |
490 | fwengine = FORCEWAKE_MEDIA; \ | |
491 | fwcount = &dev_priv->uncore.fw_mediacount; \ | |
492 | } \ | |
493 | if (fwengine != 0) { \ | |
494 | if ((*fwcount)++ == 0) \ | |
495 | (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \ | |
496 | fwengine); \ | |
497 | val = __raw_i915_read##x(dev_priv, reg); \ | |
498 | if (--(*fwcount) == 0) \ | |
499 | (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \ | |
500 | FORCEWAKE_ALL); \ | |
501 | } else { \ | |
502 | val = __raw_i915_read##x(dev_priv, reg); \ | |
503 | } \ | |
504 | REG_READ_FOOTER; \ | |
505 | } | |
506 | ||
507 | ||
508 | __vlv_read(8) | |
509 | __vlv_read(16) | |
510 | __vlv_read(32) | |
511 | __vlv_read(64) | |
3967018e BW |
512 | __gen6_read(8) |
513 | __gen6_read(16) | |
514 | __gen6_read(32) | |
515 | __gen6_read(64) | |
516 | __gen5_read(8) | |
517 | __gen5_read(16) | |
518 | __gen5_read(32) | |
519 | __gen5_read(64) | |
520 | __gen4_read(8) | |
521 | __gen4_read(16) | |
522 | __gen4_read(32) | |
523 | __gen4_read(64) | |
524 | ||
940aece4 | 525 | #undef __vlv_read |
3967018e BW |
526 | #undef __gen6_read |
527 | #undef __gen5_read | |
528 | #undef __gen4_read | |
5d738795 BW |
529 | #undef REG_READ_FOOTER |
530 | #undef REG_READ_HEADER | |
531 | ||
532 | #define REG_WRITE_HEADER \ | |
533 | unsigned long irqflags; \ | |
534 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
535 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
907b28c5 | 536 | |
4032ef43 | 537 | #define __gen4_write(x) \ |
0b274481 | 538 | static void \ |
4032ef43 BW |
539 | gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
540 | REG_WRITE_HEADER; \ | |
541 | __raw_i915_write##x(dev_priv, reg, val); \ | |
542 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
543 | } | |
544 | ||
545 | #define __gen5_write(x) \ | |
546 | static void \ | |
547 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
548 | REG_WRITE_HEADER; \ | |
549 | ilk_dummy_write(dev_priv); \ | |
550 | __raw_i915_write##x(dev_priv, reg, val); \ | |
551 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
552 | } | |
553 | ||
554 | #define __gen6_write(x) \ | |
555 | static void \ | |
556 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
557 | u32 __fifo_ret = 0; \ | |
558 | REG_WRITE_HEADER; \ | |
559 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
560 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
561 | } \ | |
562 | __raw_i915_write##x(dev_priv, reg, val); \ | |
563 | if (unlikely(__fifo_ret)) { \ | |
564 | gen6_gt_check_fifodbg(dev_priv); \ | |
565 | } \ | |
566 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
567 | } | |
568 | ||
569 | #define __hsw_write(x) \ | |
570 | static void \ | |
571 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
907b28c5 | 572 | u32 __fifo_ret = 0; \ |
5d738795 | 573 | REG_WRITE_HEADER; \ |
907b28c5 CW |
574 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
575 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
576 | } \ | |
907b28c5 | 577 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
6af5d92f | 578 | __raw_i915_write##x(dev_priv, reg, val); \ |
907b28c5 CW |
579 | if (unlikely(__fifo_ret)) { \ |
580 | gen6_gt_check_fifodbg(dev_priv); \ | |
581 | } \ | |
582 | hsw_unclaimed_reg_check(dev_priv, reg); \ | |
583 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
584 | } | |
3967018e | 585 | |
ab2aa47e BW |
586 | static const u32 gen8_shadowed_regs[] = { |
587 | FORCEWAKE_MT, | |
588 | GEN6_RPNSWREQ, | |
589 | GEN6_RC_VIDEO_FREQ, | |
590 | RING_TAIL(RENDER_RING_BASE), | |
591 | RING_TAIL(GEN6_BSD_RING_BASE), | |
592 | RING_TAIL(VEBOX_RING_BASE), | |
593 | RING_TAIL(BLT_RING_BASE), | |
594 | /* TODO: Other registers are not yet used */ | |
595 | }; | |
596 | ||
597 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) | |
598 | { | |
599 | int i; | |
600 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) | |
601 | if (reg == gen8_shadowed_regs[i]) | |
602 | return true; | |
603 | ||
604 | return false; | |
605 | } | |
606 | ||
607 | #define __gen8_write(x) \ | |
608 | static void \ | |
609 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
610 | bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \ | |
611 | REG_WRITE_HEADER; \ | |
612 | if (__needs_put) { \ | |
c8d9a590 D |
613 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
614 | FORCEWAKE_ALL); \ | |
ab2aa47e BW |
615 | } \ |
616 | __raw_i915_write##x(dev_priv, reg, val); \ | |
617 | if (__needs_put) { \ | |
c8d9a590 D |
618 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
619 | FORCEWAKE_ALL); \ | |
ab2aa47e BW |
620 | } \ |
621 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
622 | } | |
623 | ||
624 | __gen8_write(8) | |
625 | __gen8_write(16) | |
626 | __gen8_write(32) | |
627 | __gen8_write(64) | |
4032ef43 BW |
628 | __hsw_write(8) |
629 | __hsw_write(16) | |
630 | __hsw_write(32) | |
631 | __hsw_write(64) | |
632 | __gen6_write(8) | |
633 | __gen6_write(16) | |
634 | __gen6_write(32) | |
635 | __gen6_write(64) | |
636 | __gen5_write(8) | |
637 | __gen5_write(16) | |
638 | __gen5_write(32) | |
639 | __gen5_write(64) | |
640 | __gen4_write(8) | |
641 | __gen4_write(16) | |
642 | __gen4_write(32) | |
643 | __gen4_write(64) | |
644 | ||
ab2aa47e | 645 | #undef __gen8_write |
4032ef43 BW |
646 | #undef __hsw_write |
647 | #undef __gen6_write | |
648 | #undef __gen5_write | |
649 | #undef __gen4_write | |
5d738795 | 650 | #undef REG_WRITE_HEADER |
907b28c5 | 651 | |
0b274481 BW |
652 | void intel_uncore_init(struct drm_device *dev) |
653 | { | |
654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
655 | ||
656 | INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work, | |
657 | gen6_force_wake_work); | |
658 | ||
659 | if (IS_VALLEYVIEW(dev)) { | |
940aece4 D |
660 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
661 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; | |
43d1b647 | 662 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
0b274481 BW |
663 | dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get; |
664 | dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put; | |
665 | } else if (IS_IVYBRIDGE(dev)) { | |
666 | u32 ecobus; | |
667 | ||
668 | /* IVB configs may use multi-threaded forcewake */ | |
669 | ||
670 | /* A small trick here - if the bios hasn't configured | |
671 | * MT forcewake, and if the device is in RC6, then | |
672 | * force_wake_mt_get will not wake the device and the | |
673 | * ECOBUS read will return zero. Which will be | |
674 | * (correctly) interpreted by the test below as MT | |
675 | * forcewake being disabled. | |
676 | */ | |
677 | mutex_lock(&dev->struct_mutex); | |
c8d9a590 | 678 | __gen6_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); |
0b274481 | 679 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
c8d9a590 | 680 | __gen6_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); |
0b274481 BW |
681 | mutex_unlock(&dev->struct_mutex); |
682 | ||
683 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
684 | dev_priv->uncore.funcs.force_wake_get = | |
685 | __gen6_gt_force_wake_mt_get; | |
686 | dev_priv->uncore.funcs.force_wake_put = | |
687 | __gen6_gt_force_wake_mt_put; | |
688 | } else { | |
689 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); | |
690 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
691 | dev_priv->uncore.funcs.force_wake_get = | |
692 | __gen6_gt_force_wake_get; | |
693 | dev_priv->uncore.funcs.force_wake_put = | |
694 | __gen6_gt_force_wake_put; | |
695 | } | |
696 | } else if (IS_GEN6(dev)) { | |
697 | dev_priv->uncore.funcs.force_wake_get = | |
698 | __gen6_gt_force_wake_get; | |
699 | dev_priv->uncore.funcs.force_wake_put = | |
700 | __gen6_gt_force_wake_put; | |
701 | } | |
702 | ||
3967018e | 703 | switch (INTEL_INFO(dev)->gen) { |
ab2aa47e BW |
704 | default: |
705 | dev_priv->uncore.funcs.mmio_writeb = gen8_write8; | |
706 | dev_priv->uncore.funcs.mmio_writew = gen8_write16; | |
707 | dev_priv->uncore.funcs.mmio_writel = gen8_write32; | |
708 | dev_priv->uncore.funcs.mmio_writeq = gen8_write64; | |
709 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; | |
710 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; | |
711 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; | |
712 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; | |
713 | break; | |
3967018e BW |
714 | case 7: |
715 | case 6: | |
4032ef43 BW |
716 | if (IS_HASWELL(dev)) { |
717 | dev_priv->uncore.funcs.mmio_writeb = hsw_write8; | |
718 | dev_priv->uncore.funcs.mmio_writew = hsw_write16; | |
719 | dev_priv->uncore.funcs.mmio_writel = hsw_write32; | |
720 | dev_priv->uncore.funcs.mmio_writeq = hsw_write64; | |
721 | } else { | |
722 | dev_priv->uncore.funcs.mmio_writeb = gen6_write8; | |
723 | dev_priv->uncore.funcs.mmio_writew = gen6_write16; | |
724 | dev_priv->uncore.funcs.mmio_writel = gen6_write32; | |
725 | dev_priv->uncore.funcs.mmio_writeq = gen6_write64; | |
726 | } | |
940aece4 D |
727 | |
728 | if (IS_VALLEYVIEW(dev)) { | |
729 | dev_priv->uncore.funcs.mmio_readb = vlv_read8; | |
730 | dev_priv->uncore.funcs.mmio_readw = vlv_read16; | |
731 | dev_priv->uncore.funcs.mmio_readl = vlv_read32; | |
732 | dev_priv->uncore.funcs.mmio_readq = vlv_read64; | |
733 | } else { | |
734 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; | |
735 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; | |
736 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; | |
737 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; | |
738 | } | |
3967018e BW |
739 | break; |
740 | case 5: | |
4032ef43 BW |
741 | dev_priv->uncore.funcs.mmio_writeb = gen5_write8; |
742 | dev_priv->uncore.funcs.mmio_writew = gen5_write16; | |
743 | dev_priv->uncore.funcs.mmio_writel = gen5_write32; | |
744 | dev_priv->uncore.funcs.mmio_writeq = gen5_write64; | |
3967018e BW |
745 | dev_priv->uncore.funcs.mmio_readb = gen5_read8; |
746 | dev_priv->uncore.funcs.mmio_readw = gen5_read16; | |
747 | dev_priv->uncore.funcs.mmio_readl = gen5_read32; | |
748 | dev_priv->uncore.funcs.mmio_readq = gen5_read64; | |
749 | break; | |
750 | case 4: | |
751 | case 3: | |
752 | case 2: | |
4032ef43 BW |
753 | dev_priv->uncore.funcs.mmio_writeb = gen4_write8; |
754 | dev_priv->uncore.funcs.mmio_writew = gen4_write16; | |
755 | dev_priv->uncore.funcs.mmio_writel = gen4_write32; | |
756 | dev_priv->uncore.funcs.mmio_writeq = gen4_write64; | |
3967018e BW |
757 | dev_priv->uncore.funcs.mmio_readb = gen4_read8; |
758 | dev_priv->uncore.funcs.mmio_readw = gen4_read16; | |
759 | dev_priv->uncore.funcs.mmio_readl = gen4_read32; | |
760 | dev_priv->uncore.funcs.mmio_readq = gen4_read64; | |
761 | break; | |
762 | } | |
0b274481 BW |
763 | } |
764 | ||
765 | void intel_uncore_fini(struct drm_device *dev) | |
766 | { | |
767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768 | ||
769 | flush_delayed_work(&dev_priv->uncore.force_wake_work); | |
770 | ||
771 | /* Paranoia: make sure we have disabled everything before we exit. */ | |
772 | intel_uncore_sanitize(dev); | |
773 | } | |
774 | ||
907b28c5 CW |
775 | static const struct register_whitelist { |
776 | uint64_t offset; | |
777 | uint32_t size; | |
778 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ | |
779 | } whitelist[] = { | |
780 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, | |
781 | }; | |
782 | ||
783 | int i915_reg_read_ioctl(struct drm_device *dev, | |
784 | void *data, struct drm_file *file) | |
785 | { | |
786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
787 | struct drm_i915_reg_read *reg = data; | |
788 | struct register_whitelist const *entry = whitelist; | |
789 | int i; | |
790 | ||
791 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
792 | if (entry->offset == reg->offset && | |
793 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | |
794 | break; | |
795 | } | |
796 | ||
797 | if (i == ARRAY_SIZE(whitelist)) | |
798 | return -EINVAL; | |
799 | ||
800 | switch (entry->size) { | |
801 | case 8: | |
802 | reg->val = I915_READ64(reg->offset); | |
803 | break; | |
804 | case 4: | |
805 | reg->val = I915_READ(reg->offset); | |
806 | break; | |
807 | case 2: | |
808 | reg->val = I915_READ16(reg->offset); | |
809 | break; | |
810 | case 1: | |
811 | reg->val = I915_READ8(reg->offset); | |
812 | break; | |
813 | default: | |
814 | WARN_ON(1); | |
815 | return -EINVAL; | |
816 | } | |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
b6359918 MK |
821 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
822 | void *data, struct drm_file *file) | |
823 | { | |
824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
825 | struct drm_i915_reset_stats *args = data; | |
826 | struct i915_ctx_hang_stats *hs; | |
827 | int ret; | |
828 | ||
661df041 MK |
829 | if (args->flags || args->pad) |
830 | return -EINVAL; | |
831 | ||
b6359918 MK |
832 | if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN)) |
833 | return -EPERM; | |
834 | ||
835 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
836 | if (ret) | |
837 | return ret; | |
838 | ||
839 | hs = i915_gem_context_get_hang_stats(dev, file, args->ctx_id); | |
840 | if (IS_ERR(hs)) { | |
841 | mutex_unlock(&dev->struct_mutex); | |
842 | return PTR_ERR(hs); | |
843 | } | |
844 | ||
845 | if (capable(CAP_SYS_ADMIN)) | |
846 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
847 | else | |
848 | args->reset_count = 0; | |
849 | ||
850 | args->batch_active = hs->batch_active; | |
851 | args->batch_pending = hs->batch_pending; | |
852 | ||
853 | mutex_unlock(&dev->struct_mutex); | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
907b28c5 CW |
858 | static int i965_reset_complete(struct drm_device *dev) |
859 | { | |
860 | u8 gdrst; | |
861 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | |
862 | return (gdrst & GRDOM_RESET_ENABLE) == 0; | |
863 | } | |
864 | ||
865 | static int i965_do_reset(struct drm_device *dev) | |
866 | { | |
867 | int ret; | |
868 | ||
869 | /* | |
870 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
871 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
872 | * triggers the reset; when done, the hardware will clear it. | |
873 | */ | |
874 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
875 | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
876 | ret = wait_for(i965_reset_complete(dev), 500); | |
877 | if (ret) | |
878 | return ret; | |
879 | ||
880 | /* We can't reset render&media without also resetting display ... */ | |
881 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
882 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
883 | ||
884 | ret = wait_for(i965_reset_complete(dev), 500); | |
885 | if (ret) | |
886 | return ret; | |
887 | ||
888 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
893 | static int ironlake_do_reset(struct drm_device *dev) | |
894 | { | |
895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
896 | u32 gdrst; | |
897 | int ret; | |
898 | ||
899 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
900 | gdrst &= ~GRDOM_MASK; | |
901 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
902 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
903 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
904 | if (ret) | |
905 | return ret; | |
906 | ||
907 | /* We can't reset render&media without also resetting display ... */ | |
908 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
909 | gdrst &= ~GRDOM_MASK; | |
910 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
911 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
912 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
913 | } | |
914 | ||
915 | static int gen6_do_reset(struct drm_device *dev) | |
916 | { | |
917 | struct drm_i915_private *dev_priv = dev->dev_private; | |
918 | int ret; | |
919 | unsigned long irqflags; | |
920 | ||
921 | /* Hold uncore.lock across reset to prevent any register access | |
922 | * with forcewake not set correctly | |
923 | */ | |
924 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
925 | ||
926 | /* Reset the chip */ | |
927 | ||
928 | /* GEN6_GDRST is not in the gt power well, no need to check | |
929 | * for fifo space for the write or forcewake the chip for | |
930 | * the read | |
931 | */ | |
6af5d92f | 932 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
907b28c5 CW |
933 | |
934 | /* Spin waiting for the device to ack the reset request */ | |
6af5d92f | 935 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
907b28c5 | 936 | |
521198a2 MK |
937 | intel_uncore_forcewake_reset(dev); |
938 | ||
907b28c5 CW |
939 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ |
940 | if (dev_priv->uncore.forcewake_count) | |
c8d9a590 | 941 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
907b28c5 | 942 | else |
c8d9a590 | 943 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
907b28c5 CW |
944 | |
945 | /* Restore fifo count */ | |
6af5d92f | 946 | dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); |
907b28c5 CW |
947 | |
948 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
949 | return ret; | |
950 | } | |
951 | ||
952 | int intel_gpu_reset(struct drm_device *dev) | |
953 | { | |
954 | switch (INTEL_INFO(dev)->gen) { | |
935e8de9 | 955 | case 8: |
907b28c5 CW |
956 | case 7: |
957 | case 6: return gen6_do_reset(dev); | |
958 | case 5: return ironlake_do_reset(dev); | |
959 | case 4: return i965_do_reset(dev); | |
907b28c5 CW |
960 | default: return -ENODEV; |
961 | } | |
962 | } | |
963 | ||
907b28c5 CW |
964 | void intel_uncore_check_errors(struct drm_device *dev) |
965 | { | |
966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
967 | ||
968 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && | |
6af5d92f | 969 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
907b28c5 | 970 | DRM_ERROR("Unclaimed register before interrupt\n"); |
6af5d92f | 971 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
972 | } |
973 | } |