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drm/i915: put runtime PM only at the end of intel_mark_idle
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_uncore.c
CommitLineData
907b28c5
CW		 1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "i915_drv.h"
25#include "intel_drv.h"
26
27#define FORCEWAKE_ACK_TIMEOUT_MS 2
28
6af5d92f
CW		 29#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
43
907b28c5
CW		 44static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
45{
46 u32 gt_thread_status_mask;
47
48 if (IS_HASWELL(dev_priv->dev))
49 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
50 else
51 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
52
53 /* w/a for a sporadic read returning 0 by waiting for the GT
54 * thread to wake up.
55 */
6af5d92f 56 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
907b28c5
CW		 57 DRM_ERROR("GT thread status wait timed out\n");
58}
59
60static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
61{
6af5d92f
CW		 62 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
63 /* something from same cacheline, but !FORCEWAKE */
64 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 65}
66
c8d9a590
D		 67static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
68 int fw_engine)
907b28c5 69{
6af5d92f 70 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
907b28c5
CW		 71 FORCEWAKE_ACK_TIMEOUT_MS))
72 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
73
6af5d92f
CW		 74 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
75 /* something from same cacheline, but !FORCEWAKE */
76 __raw_posting_read(dev_priv, ECOBUS);
907b28c5 77
6af5d92f 78 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
907b28c5
CW		 79 FORCEWAKE_ACK_TIMEOUT_MS))
80 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
81
82 /* WaRsForcewakeWaitTC0:snb */
83 __gen6_gt_wait_for_thread_c0(dev_priv);
84}
85
86static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
87{
6af5d92f 88 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
907b28c5 89 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 90 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 91}
92
c8d9a590
D		 93static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
94 int fw_engine)
907b28c5
CW		 95{
96 u32 forcewake_ack;
97
ab2aa47e 98 if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
907b28c5
CW		 99 forcewake_ack = FORCEWAKE_ACK_HSW;
100 else
101 forcewake_ack = FORCEWAKE_MT_ACK;
102
6af5d92f 103 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
907b28c5
CW		 104 FORCEWAKE_ACK_TIMEOUT_MS))
105 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
106
6af5d92f
CW		 107 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
108 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
907b28c5 109 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 110 __raw_posting_read(dev_priv, ECOBUS);
907b28c5 111
6af5d92f 112 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
907b28c5
CW		 113 FORCEWAKE_ACK_TIMEOUT_MS))
114 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
115
116 /* WaRsForcewakeWaitTC0:ivb,hsw */
0f161f70
BW		 117 if (INTEL_INFO(dev_priv->dev)->gen < 8)
118 __gen6_gt_wait_for_thread_c0(dev_priv);
907b28c5
CW		 119}
120
121static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
122{
123 u32 gtfifodbg;
6af5d92f
CW		 124
125 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
90f256b5
VS		 126 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
127 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
907b28c5
CW		 128}
129
c8d9a590
D		 130static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
131 int fw_engine)
907b28c5 132{
6af5d92f 133 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
907b28c5 134 /* something from same cacheline, but !FORCEWAKE */
6af5d92f 135 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 136 gen6_gt_check_fifodbg(dev_priv);
137}
138
c8d9a590
D		 139static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
140 int fw_engine)
907b28c5 141{
6af5d92f
CW		 142 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
143 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
907b28c5 144 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 145 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 146 gen6_gt_check_fifodbg(dev_priv);
147}
148
149static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
150{
151 int ret = 0;
152
5135d64b
D		 153 /* On VLV, FIFO will be shared by both SW and HW.
154 * So, we need to read the FREE_ENTRIES everytime */
155 if (IS_VALLEYVIEW(dev_priv->dev))
156 dev_priv->uncore.fifo_count =
157 __raw_i915_read32(dev_priv, GTFIFOCTL) &
158 GT_FIFO_FREE_ENTRIES_MASK;
159
907b28c5
CW		 160 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
161 int loop = 500;
46520e2b 162 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
907b28c5
CW		 163 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
164 udelay(10);
46520e2b 165 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
907b28c5
CW		 166 }
167 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
168 ++ret;
169 dev_priv->uncore.fifo_count = fifo;
170 }
171 dev_priv->uncore.fifo_count--;
172
173 return ret;
174}
175
176static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
177{
6af5d92f
CW		 178 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
179 _MASKED_BIT_DISABLE(0xffff));
907b28c5 180 /* something from same cacheline, but !FORCEWAKE_VLV */
6af5d92f 181 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
907b28c5
CW		 182}
183
940aece4
D		 184static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
185 int fw_engine)
907b28c5 186{
940aece4
D		 187 /* Check for Render Engine */
188 if (FORCEWAKE_RENDER & fw_engine) {
189 if (wait_for_atomic((__raw_i915_read32(dev_priv,
190 FORCEWAKE_ACK_VLV) &
191 FORCEWAKE_KERNEL) == 0,
192 FORCEWAKE_ACK_TIMEOUT_MS))
193 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
194
195 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
196 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
197
198 if (wait_for_atomic((__raw_i915_read32(dev_priv,
199 FORCEWAKE_ACK_VLV) &
200 FORCEWAKE_KERNEL),
201 FORCEWAKE_ACK_TIMEOUT_MS))
202 DRM_ERROR("Timed out: waiting for Render to ack.\n");
203 }
907b28c5 204
940aece4
D		 205 /* Check for Media Engine */
206 if (FORCEWAKE_MEDIA & fw_engine) {
207 if (wait_for_atomic((__raw_i915_read32(dev_priv,
208 FORCEWAKE_ACK_MEDIA_VLV) &
209 FORCEWAKE_KERNEL) == 0,
210 FORCEWAKE_ACK_TIMEOUT_MS))
211 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
212
213 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
214 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
215
216 if (wait_for_atomic((__raw_i915_read32(dev_priv,
217 FORCEWAKE_ACK_MEDIA_VLV) &
218 FORCEWAKE_KERNEL),
219 FORCEWAKE_ACK_TIMEOUT_MS))
220 DRM_ERROR("Timed out: waiting for media to ack.\n");
221 }
907b28c5
CW		 222
223 /* WaRsForcewakeWaitTC0:vlv */
224 __gen6_gt_wait_for_thread_c0(dev_priv);
940aece4 225
907b28c5
CW		 226}
227
940aece4
D		 228static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
229 int fw_engine)
907b28c5 230{
940aece4
D		 231
232 /* Check for Render Engine */
233 if (FORCEWAKE_RENDER & fw_engine)
234 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
235 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
236
237
238 /* Check for Media Engine */
239 if (FORCEWAKE_MEDIA & fw_engine)
240 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
241 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
242
907b28c5
CW		 243 /* The below doubles as a POSTING_READ */
244 gen6_gt_check_fifodbg(dev_priv);
940aece4
D		 245
246}
247
248void vlv_force_wake_get(struct drm_i915_private *dev_priv,
249 int fw_engine)
250{
251 unsigned long irqflags;
252
253 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
254 if (FORCEWAKE_RENDER & fw_engine) {
255 if (dev_priv->uncore.fw_rendercount++ == 0)
256 dev_priv->uncore.funcs.force_wake_get(dev_priv,
257 FORCEWAKE_RENDER);
258 }
259 if (FORCEWAKE_MEDIA & fw_engine) {
260 if (dev_priv->uncore.fw_mediacount++ == 0)
261 dev_priv->uncore.funcs.force_wake_get(dev_priv,
262 FORCEWAKE_MEDIA);
263 }
264
265 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
266}
267
268void vlv_force_wake_put(struct drm_i915_private *dev_priv,
269 int fw_engine)
270{
271 unsigned long irqflags;
272
273 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
274
275 if (FORCEWAKE_RENDER & fw_engine) {
276 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
277 if (--dev_priv->uncore.fw_rendercount == 0)
278 dev_priv->uncore.funcs.force_wake_put(dev_priv,
279 FORCEWAKE_RENDER);
280 }
281
282 if (FORCEWAKE_MEDIA & fw_engine) {
283 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
284 if (--dev_priv->uncore.fw_mediacount == 0)
285 dev_priv->uncore.funcs.force_wake_put(dev_priv,
286 FORCEWAKE_MEDIA);
287 }
288
289 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
907b28c5
CW		 290}
291
8232644c 292static void gen6_force_wake_timer(unsigned long arg)
aec347ab 293{
8232644c 294 struct drm_i915_private *dev_priv = (void *)arg;
aec347ab
CW		 295 unsigned long irqflags;
296
297 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
298 if (--dev_priv->uncore.forcewake_count == 0)
c8d9a590 299 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
aec347ab
CW		 300 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
301}
302
ef46e0d2
DV		 303static void intel_uncore_forcewake_reset(struct drm_device *dev)
304{
305 struct drm_i915_private *dev_priv = dev->dev_private;
306
307 if (IS_VALLEYVIEW(dev)) {
308 vlv_force_wake_reset(dev_priv);
309 } else if (INTEL_INFO(dev)->gen >= 6) {
310 __gen6_gt_force_wake_reset(dev_priv);
311 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
312 __gen6_gt_force_wake_mt_reset(dev_priv);
313 }
314}
315
907b28c5
CW		 316void intel_uncore_early_sanitize(struct drm_device *dev)
317{
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
320 if (HAS_FPGA_DBG_UNCLAIMED(dev))
6af5d92f 321 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
18ce3994
BW		 322
323 if (IS_HASWELL(dev) &&
324 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
325 /* The docs do not explain exactly how the calculation can be
326 * made. It is somewhat guessable, but for now, it's always
327 * 128MB.
328 * NB: We can't write IDICR yet because we do not have gt funcs
329 * set up */
330 dev_priv->ellc_size = 128;
331 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
332 }
907b28c5 333
97058870
VS		 334 /* clear out old GT FIFO errors */
335 if (IS_GEN6(dev) || IS_GEN7(dev))
336 __raw_i915_write32(dev_priv, GTFIFODBG,
337 __raw_i915_read32(dev_priv, GTFIFODBG));
338
ef46e0d2 339 intel_uncore_forcewake_reset(dev);
521198a2
MK		 340}
341
342void intel_uncore_sanitize(struct drm_device *dev)
343{
02f4c9e0
CML		 344 struct drm_i915_private *dev_priv = dev->dev_private;
345 u32 reg_val;
346
907b28c5
CW		 347 /* BIOS often leaves RC6 enabled, but disable it for hw init */
348 intel_disable_gt_powersave(dev);
02f4c9e0
CML		 349
350 /* Turn off power gate, require especially for the BIOS less system */
351 if (IS_VALLEYVIEW(dev)) {
352
353 mutex_lock(&dev_priv->rps.hw_lock);
354 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
355
356 if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
357 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
358
359 mutex_unlock(&dev_priv->rps.hw_lock);
360
361 }
907b28c5
CW		 362}
363
364/*
365 * Generally this is called implicitly by the register read function. However,
366 * if some sequence requires the GT to not power down then this function should
367 * be called at the beginning of the sequence followed by a call to
368 * gen6_gt_force_wake_put() at the end of the sequence.
369 */
c8d9a590 370void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
907b28c5
CW		 371{
372 unsigned long irqflags;
373
ab484f8f
BW		 374 if (!dev_priv->uncore.funcs.force_wake_get)
375 return;
376
c8c8fb33
PZ		 377 intel_runtime_pm_get(dev_priv);
378
940aece4
D		 379 /* Redirect to VLV specific routine */
380 if (IS_VALLEYVIEW(dev_priv->dev))
381 return vlv_force_wake_get(dev_priv, fw_engine);
382
907b28c5
CW		 383 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
384 if (dev_priv->uncore.forcewake_count++ == 0)
c8d9a590 385 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
907b28c5
CW		 386 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
387}
388
389/*
390 * see gen6_gt_force_wake_get()
391 */
c8d9a590 392void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
907b28c5
CW		 393{
394 unsigned long irqflags;
395
ab484f8f
BW		 396 if (!dev_priv->uncore.funcs.force_wake_put)
397 return;
398
940aece4
D		 399 /* Redirect to VLV specific routine */
400 if (IS_VALLEYVIEW(dev_priv->dev))
401 return vlv_force_wake_put(dev_priv, fw_engine);
402
403
907b28c5 404 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
aec347ab
CW		 405 if (--dev_priv->uncore.forcewake_count == 0) {
406 dev_priv->uncore.forcewake_count++;
8232644c
CW		 407 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
408 jiffies + 1);
aec347ab 409 }
907b28c5 410 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
c8c8fb33
PZ		 411
412 intel_runtime_pm_put(dev_priv);
907b28c5
CW		 413}
414
415/* We give fast paths for the really cool registers */
416#define NEEDS_FORCE_WAKE(dev_priv, reg) \
ab484f8f 417 ((reg) < 0x40000 && (reg) != FORCEWAKE)
907b28c5
CW		 418
419static void
420ilk_dummy_write(struct drm_i915_private *dev_priv)
421{
422 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
423 * the chip from rc6 before touching it for real. MI_MODE is masked,
424 * hence harmless to write 0 into. */
6af5d92f 425 __raw_i915_write32(dev_priv, MI_MODE, 0);
907b28c5
CW		 426}
427
428static void
429hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
430{
ab484f8f 431 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
907b28c5
CW		 432 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
433 reg);
6af5d92f 434 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 435 }
436}
437
438static void
439hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
440{
ab484f8f 441 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
907b28c5 442 DRM_ERROR("Unclaimed write to %x\n", reg);
6af5d92f 443 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 444 }
445}
446
8a187455
PZ		 447static void
448assert_device_not_suspended(struct drm_i915_private *dev_priv)
449{
450 WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
451 "Device suspended\n");
452}
453
5d738795
BW		 454#define REG_READ_HEADER(x) \
455 unsigned long irqflags; \
456 u##x val = 0; \
457 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
458
459#define REG_READ_FOOTER \
460 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
461 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
462 return val
463
3967018e 464#define __gen4_read(x) \
0b274481 465static u##x \
3967018e
BW		 466gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
467 REG_READ_HEADER(x); \
468 val = __raw_i915_read##x(dev_priv, reg); \
469 REG_READ_FOOTER; \
470}
471
472#define __gen5_read(x) \
473static u##x \
474gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
475 REG_READ_HEADER(x); \
476 ilk_dummy_write(dev_priv); \
477 val = __raw_i915_read##x(dev_priv, reg); \
478 REG_READ_FOOTER; \
479}
480
481#define __gen6_read(x) \
482static u##x \
483gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
5d738795 484 REG_READ_HEADER(x); \
8232644c
CW		 485 if (dev_priv->uncore.forcewake_count == 0 && \
486 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
487 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
488 FORCEWAKE_ALL); \
489 dev_priv->uncore.forcewake_count++; \
490 mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \
491 jiffies + 1); \
907b28c5 492 } \
8232644c 493 val = __raw_i915_read##x(dev_priv, reg); \
5d738795 494 REG_READ_FOOTER; \
907b28c5
CW		 495}
496
940aece4
D		 497#define __vlv_read(x) \
498static u##x \
499vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
500 unsigned fwengine = 0; \
5bc0e85c 501 unsigned *fwcount; \
940aece4
D		 502 REG_READ_HEADER(x); \
503 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
504 fwengine = FORCEWAKE_RENDER; \
505 fwcount = &dev_priv->uncore.fw_rendercount; \
506 } \
507 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
508 fwengine = FORCEWAKE_MEDIA; \
509 fwcount = &dev_priv->uncore.fw_mediacount; \
510 } \
511 if (fwengine != 0) { \
512 if ((*fwcount)++ == 0) \
513 (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
514 fwengine); \
515 val = __raw_i915_read##x(dev_priv, reg); \
516 if (--(*fwcount) == 0) \
517 (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
084054fc 518 fwengine); \
940aece4
D		 519 } else { \
520 val = __raw_i915_read##x(dev_priv, reg); \
521 } \
522 REG_READ_FOOTER; \
523}
524
525
526__vlv_read(8)
527__vlv_read(16)
528__vlv_read(32)
529__vlv_read(64)
3967018e
BW		 530__gen6_read(8)
531__gen6_read(16)
532__gen6_read(32)
533__gen6_read(64)
534__gen5_read(8)
535__gen5_read(16)
536__gen5_read(32)
537__gen5_read(64)
538__gen4_read(8)
539__gen4_read(16)
540__gen4_read(32)
541__gen4_read(64)
542
940aece4 543#undef __vlv_read
3967018e
BW		 544#undef __gen6_read
545#undef __gen5_read
546#undef __gen4_read
5d738795
BW		 547#undef REG_READ_FOOTER
548#undef REG_READ_HEADER
549
550#define REG_WRITE_HEADER \
551 unsigned long irqflags; \
552 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
553 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
907b28c5 554
0d965301
VS		 555#define REG_WRITE_FOOTER \
556 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
557
4032ef43 558#define __gen4_write(x) \
0b274481 559static void \
4032ef43
BW		 560gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
561 REG_WRITE_HEADER; \
562 __raw_i915_write##x(dev_priv, reg, val); \
0d965301 563 REG_WRITE_FOOTER; \
4032ef43
BW		 564}
565
566#define __gen5_write(x) \
567static void \
568gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
569 REG_WRITE_HEADER; \
570 ilk_dummy_write(dev_priv); \
571 __raw_i915_write##x(dev_priv, reg, val); \
0d965301 572 REG_WRITE_FOOTER; \
4032ef43
BW		 573}
574
575#define __gen6_write(x) \
576static void \
577gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
578 u32 __fifo_ret = 0; \
579 REG_WRITE_HEADER; \
580 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
581 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
582 } \
8a187455 583 assert_device_not_suspended(dev_priv); \
4032ef43
BW		 584 __raw_i915_write##x(dev_priv, reg, val); \
585 if (unlikely(__fifo_ret)) { \
586 gen6_gt_check_fifodbg(dev_priv); \
587 } \
0d965301 588 REG_WRITE_FOOTER; \
4032ef43
BW		 589}
590
591#define __hsw_write(x) \
592static void \
593hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
907b28c5 594 u32 __fifo_ret = 0; \
5d738795 595 REG_WRITE_HEADER; \
907b28c5
CW		 596 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
597 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
598 } \
8a187455 599 assert_device_not_suspended(dev_priv); \
907b28c5 600 hsw_unclaimed_reg_clear(dev_priv, reg); \
6af5d92f 601 __raw_i915_write##x(dev_priv, reg, val); \
907b28c5
CW		 602 if (unlikely(__fifo_ret)) { \
603 gen6_gt_check_fifodbg(dev_priv); \
604 } \
605 hsw_unclaimed_reg_check(dev_priv, reg); \
0d965301 606 REG_WRITE_FOOTER; \
907b28c5 607}
3967018e 608
ab2aa47e
BW		 609static const u32 gen8_shadowed_regs[] = {
610 FORCEWAKE_MT,
611 GEN6_RPNSWREQ,
612 GEN6_RC_VIDEO_FREQ,
613 RING_TAIL(RENDER_RING_BASE),
614 RING_TAIL(GEN6_BSD_RING_BASE),
615 RING_TAIL(VEBOX_RING_BASE),
616 RING_TAIL(BLT_RING_BASE),
617 /* TODO: Other registers are not yet used */
618};
619
620static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
621{
622 int i;
623 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
624 if (reg == gen8_shadowed_regs[i])
625 return true;
626
627 return false;
628}
629
630#define __gen8_write(x) \
631static void \
632gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
ab2aa47e 633 REG_WRITE_HEADER; \
e9dbd2b2
MK		 634 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
635 if (dev_priv->uncore.forcewake_count == 0) \
636 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
637 FORCEWAKE_ALL); \
638 __raw_i915_write##x(dev_priv, reg, val); \
639 if (dev_priv->uncore.forcewake_count == 0) \
640 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
641 FORCEWAKE_ALL); \
642 } else { \
643 __raw_i915_write##x(dev_priv, reg, val); \
ab2aa47e 644 } \
0d965301 645 REG_WRITE_FOOTER; \
ab2aa47e
BW		 646}
647
648__gen8_write(8)
649__gen8_write(16)
650__gen8_write(32)
651__gen8_write(64)
4032ef43
BW		 652__hsw_write(8)
653__hsw_write(16)
654__hsw_write(32)
655__hsw_write(64)
656__gen6_write(8)
657__gen6_write(16)
658__gen6_write(32)
659__gen6_write(64)
660__gen5_write(8)
661__gen5_write(16)
662__gen5_write(32)
663__gen5_write(64)
664__gen4_write(8)
665__gen4_write(16)
666__gen4_write(32)
667__gen4_write(64)
668
ab2aa47e 669#undef __gen8_write
4032ef43
BW		 670#undef __hsw_write
671#undef __gen6_write
672#undef __gen5_write
673#undef __gen4_write
0d965301 674#undef REG_WRITE_FOOTER
5d738795 675#undef REG_WRITE_HEADER
907b28c5 676
0b274481
BW		 677void intel_uncore_init(struct drm_device *dev)
678{
679 struct drm_i915_private *dev_priv = dev->dev_private;
680
8232644c
CW		 681 setup_timer(&dev_priv->uncore.force_wake_timer,
682 gen6_force_wake_timer, (unsigned long)dev_priv);
0b274481
BW		 683
684 if (IS_VALLEYVIEW(dev)) {
940aece4
D		 685 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
686 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
43d1b647 687 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
0b274481
BW		 688 dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
689 dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
690 } else if (IS_IVYBRIDGE(dev)) {
691 u32 ecobus;
692
693 /* IVB configs may use multi-threaded forcewake */
694
695 /* A small trick here - if the bios hasn't configured
696 * MT forcewake, and if the device is in RC6, then
697 * force_wake_mt_get will not wake the device and the
698 * ECOBUS read will return zero. Which will be
699 * (correctly) interpreted by the test below as MT
700 * forcewake being disabled.
701 */
702 mutex_lock(&dev->struct_mutex);
c8d9a590 703 __gen6_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
0b274481 704 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
c8d9a590 705 __gen6_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
0b274481
BW		 706 mutex_unlock(&dev->struct_mutex);
707
708 if (ecobus & FORCEWAKE_MT_ENABLE) {
709 dev_priv->uncore.funcs.force_wake_get =
710 __gen6_gt_force_wake_mt_get;
711 dev_priv->uncore.funcs.force_wake_put =
712 __gen6_gt_force_wake_mt_put;
713 } else {
714 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
715 DRM_INFO("when using vblank-synced partial screen updates.\n");
716 dev_priv->uncore.funcs.force_wake_get =
717 __gen6_gt_force_wake_get;
718 dev_priv->uncore.funcs.force_wake_put =
719 __gen6_gt_force_wake_put;
720 }
721 } else if (IS_GEN6(dev)) {
722 dev_priv->uncore.funcs.force_wake_get =
723 __gen6_gt_force_wake_get;
724 dev_priv->uncore.funcs.force_wake_put =
725 __gen6_gt_force_wake_put;
726 }
727
3967018e 728 switch (INTEL_INFO(dev)->gen) {
ab2aa47e
BW		 729 default:
730 dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
731 dev_priv->uncore.funcs.mmio_writew = gen8_write16;
732 dev_priv->uncore.funcs.mmio_writel = gen8_write32;
733 dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
734 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
735 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
736 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
737 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
738 break;
3967018e
BW		 739 case 7:
740 case 6:
4032ef43
BW		 741 if (IS_HASWELL(dev)) {
742 dev_priv->uncore.funcs.mmio_writeb = hsw_write8;
743 dev_priv->uncore.funcs.mmio_writew = hsw_write16;
744 dev_priv->uncore.funcs.mmio_writel = hsw_write32;
745 dev_priv->uncore.funcs.mmio_writeq = hsw_write64;
746 } else {
747 dev_priv->uncore.funcs.mmio_writeb = gen6_write8;
748 dev_priv->uncore.funcs.mmio_writew = gen6_write16;
749 dev_priv->uncore.funcs.mmio_writel = gen6_write32;
750 dev_priv->uncore.funcs.mmio_writeq = gen6_write64;
751 }
940aece4
D		 752
753 if (IS_VALLEYVIEW(dev)) {
754 dev_priv->uncore.funcs.mmio_readb = vlv_read8;
755 dev_priv->uncore.funcs.mmio_readw = vlv_read16;
756 dev_priv->uncore.funcs.mmio_readl = vlv_read32;
757 dev_priv->uncore.funcs.mmio_readq = vlv_read64;
758 } else {
759 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
760 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
761 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
762 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
763 }
3967018e
BW		 764 break;
765 case 5:
4032ef43
BW		 766 dev_priv->uncore.funcs.mmio_writeb = gen5_write8;
767 dev_priv->uncore.funcs.mmio_writew = gen5_write16;
768 dev_priv->uncore.funcs.mmio_writel = gen5_write32;
769 dev_priv->uncore.funcs.mmio_writeq = gen5_write64;
3967018e
BW		 770 dev_priv->uncore.funcs.mmio_readb = gen5_read8;
771 dev_priv->uncore.funcs.mmio_readw = gen5_read16;
772 dev_priv->uncore.funcs.mmio_readl = gen5_read32;
773 dev_priv->uncore.funcs.mmio_readq = gen5_read64;
774 break;
775 case 4:
776 case 3:
777 case 2:
4032ef43
BW		 778 dev_priv->uncore.funcs.mmio_writeb = gen4_write8;
779 dev_priv->uncore.funcs.mmio_writew = gen4_write16;
780 dev_priv->uncore.funcs.mmio_writel = gen4_write32;
781 dev_priv->uncore.funcs.mmio_writeq = gen4_write64;
3967018e
BW		 782 dev_priv->uncore.funcs.mmio_readb = gen4_read8;
783 dev_priv->uncore.funcs.mmio_readw = gen4_read16;
784 dev_priv->uncore.funcs.mmio_readl = gen4_read32;
785 dev_priv->uncore.funcs.mmio_readq = gen4_read64;
786 break;
787 }
0b274481
BW		 788}
789
790void intel_uncore_fini(struct drm_device *dev)
791{
792 struct drm_i915_private *dev_priv = dev->dev_private;
793
8232644c 794 del_timer_sync(&dev_priv->uncore.force_wake_timer);
0b274481
BW		 795
796 /* Paranoia: make sure we have disabled everything before we exit. */
797 intel_uncore_sanitize(dev);
8232644c 798 intel_uncore_forcewake_reset(dev);
0b274481
BW		 799}
800
907b28c5
CW		 801static const struct register_whitelist {
802 uint64_t offset;
803 uint32_t size;
804 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
805} whitelist[] = {
43181011 806 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 },
907b28c5
CW		 807};
808
809int i915_reg_read_ioctl(struct drm_device *dev,
810 void *data, struct drm_file *file)
811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 struct drm_i915_reg_read *reg = data;
814 struct register_whitelist const *entry = whitelist;
815 int i;
816
817 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
818 if (entry->offset == reg->offset &&
819 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
820 break;
821 }
822
823 if (i == ARRAY_SIZE(whitelist))
824 return -EINVAL;
825
826 switch (entry->size) {
827 case 8:
828 reg->val = I915_READ64(reg->offset);
829 break;
830 case 4:
831 reg->val = I915_READ(reg->offset);
832 break;
833 case 2:
834 reg->val = I915_READ16(reg->offset);
835 break;
836 case 1:
837 reg->val = I915_READ8(reg->offset);
838 break;
839 default:
840 WARN_ON(1);
841 return -EINVAL;
842 }
843
844 return 0;
845}
846
b6359918
MK		 847int i915_get_reset_stats_ioctl(struct drm_device *dev,
848 void *data, struct drm_file *file)
849{
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 struct drm_i915_reset_stats *args = data;
852 struct i915_ctx_hang_stats *hs;
41bde553 853 struct i915_hw_context *ctx;
b6359918
MK		 854 int ret;
855
661df041
MK		 856 if (args->flags || args->pad)
857 return -EINVAL;
858
b6359918
MK		 859 if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
860 return -EPERM;
861
862 ret = mutex_lock_interruptible(&dev->struct_mutex);
863 if (ret)
864 return ret;
865
41bde553
BW		 866 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
867 if (IS_ERR(ctx)) {
b6359918 868 mutex_unlock(&dev->struct_mutex);
41bde553 869 return PTR_ERR(ctx);
b6359918 870 }
41bde553 871 hs = &ctx->hang_stats;
b6359918
MK		 872
873 if (capable(CAP_SYS_ADMIN))
874 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
875 else
876 args->reset_count = 0;
877
878 args->batch_active = hs->batch_active;
879 args->batch_pending = hs->batch_pending;
880
881 mutex_unlock(&dev->struct_mutex);
882
883 return 0;
884}
885
907b28c5
CW		 886static int i965_reset_complete(struct drm_device *dev)
887{
888 u8 gdrst;
889 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
890 return (gdrst & GRDOM_RESET_ENABLE) == 0;
891}
892
893static int i965_do_reset(struct drm_device *dev)
894{
895 int ret;
896
897 /*
898 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
899 * well as the reset bit (GR/bit 0). Setting the GR bit
900 * triggers the reset; when done, the hardware will clear it.
901 */
902 pci_write_config_byte(dev->pdev, I965_GDRST,
903 GRDOM_RENDER | GRDOM_RESET_ENABLE);
904 ret = wait_for(i965_reset_complete(dev), 500);
905 if (ret)
906 return ret;
907
908 /* We can't reset render&media without also resetting display ... */
909 pci_write_config_byte(dev->pdev, I965_GDRST,
910 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
911
912 ret = wait_for(i965_reset_complete(dev), 500);
913 if (ret)
914 return ret;
915
916 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
917
918 return 0;
919}
920
921static int ironlake_do_reset(struct drm_device *dev)
922{
923 struct drm_i915_private *dev_priv = dev->dev_private;
924 u32 gdrst;
925 int ret;
926
927 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
928 gdrst &= ~GRDOM_MASK;
929 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
930 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
931 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
932 if (ret)
933 return ret;
934
935 /* We can't reset render&media without also resetting display ... */
936 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
937 gdrst &= ~GRDOM_MASK;
938 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
939 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
940 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
941}
942
943static int gen6_do_reset(struct drm_device *dev)
944{
945 struct drm_i915_private *dev_priv = dev->dev_private;
946 int ret;
947 unsigned long irqflags;
948
949 /* Hold uncore.lock across reset to prevent any register access
950 * with forcewake not set correctly
951 */
952 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
953
954 /* Reset the chip */
955
956 /* GEN6_GDRST is not in the gt power well, no need to check
957 * for fifo space for the write or forcewake the chip for
958 * the read
959 */
6af5d92f 960 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
907b28c5
CW		 961
962 /* Spin waiting for the device to ack the reset request */
6af5d92f 963 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
907b28c5 964
521198a2
MK		 965 intel_uncore_forcewake_reset(dev);
966
907b28c5
CW		 967 /* If reset with a user forcewake, try to restore, otherwise turn it off */
968 if (dev_priv->uncore.forcewake_count)
c8d9a590 969 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
907b28c5 970 else
c8d9a590 971 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
907b28c5
CW		 972
973 /* Restore fifo count */
46520e2b 974 dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
907b28c5
CW		 975
976 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
977 return ret;
978}
979
980int intel_gpu_reset(struct drm_device *dev)
981{
982 switch (INTEL_INFO(dev)->gen) {
935e8de9 983 case 8:
907b28c5
CW		 984 case 7:
985 case 6: return gen6_do_reset(dev);
986 case 5: return ironlake_do_reset(dev);
987 case 4: return i965_do_reset(dev);
907b28c5
CW		 988 default: return -ENODEV;
989 }
990}
991
907b28c5
CW		 992void intel_uncore_check_errors(struct drm_device *dev)
993{
994 struct drm_i915_private *dev_priv = dev->dev_private;
995
996 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
6af5d92f 997 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
907b28c5 998 DRM_ERROR("Unclaimed register before interrupt\n");
6af5d92f 999 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 1000 }
1001}
Linux kernel - Deliverables
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